Electronic device and method for reducing number of commands thereof

Abstract

An electronic device and a command quantity reduction method thereof are provided. The electronic device includes a central processor and a co-processor. The central processor generates a plurality of original register set commands to set at least one bit of at least one register of the co-processor. The plurality of original register set commands includes a plurality of first original register set commands, wherein a plurality of set targets of the plurality of first original register set commands have address continuity. The central processor fuses the plurality of first original register set commands to generate at least one fused register set command. The central processor transmits the at least one fused register set command to the co-processor. Accordingly, the quantity of register set commands transmitted by the central processor to the co-processor can be effectively reduced.

Description

[0001] This application is a divisional application of the application filed on August 28, 2020, with application number 202010887217.4 and entitled "Electronic Device and Method for Reducing the Number of Commands Thereto". Technical Field

[0002] The present invention relates to an electronic device, and more particularly to a method for reducing the number of commands for said electronic device. Background Technology

[0003] In electronic devices, the central processing unit (CPU) issues multiple commands to the coprocessor. For example, the CPU, which runs the operating system (OS) and application programs, issues multiple commands to the graphics processing unit (GPU). Generally, these commands sent to the GPU include register setting commands, drawing commands, and other commands.

[0004] A coprocessor is composed of different hardware modules. Generally, each hardware module contains several hardware registers. Each register stores / records one (or more) operational parameters required for the coprocessor to function. By setting (or changing) the contents of these registers, the central processing unit (CPU) can control the coprocessor's operation. For example, by setting (or changing) the contents of one (or more) registers of the GPU, the CPU can control the GPU's graphics operations.

[0005] The size (number of bits) of each register in a coprocessor can be defined according to design requirements. For example, a register can be 32 bits. The function of these 32 bits can be defined according to design requirements. In a register's 32 bits, a single bit may be used to represent (store) an operation parameter of the coprocessor, or multiple bits may be used to represent (store) an operation parameter of the coprocessor. That is, a register can store multiple operation parameters of the coprocessor. Furthermore, all bits of a register (e.g., 32 bits) may be used to represent (store) an operation parameter of the coprocessor.

[0006] For ease of addressing, register addresses are typically assigned to these registers in the coprocessor. For example, these registers may be divided into multiple register groups according to hardware modules, with each register group assigned a group ID. Each register within a register group can be addressed using an internal offset.

[0007] The operating system and / or applications typically set (update) these operational parameters of the coprocessor based on its runtime state. Generally, a coprocessor has a large number of operational parameters. A coprocessor may perform an operation based on multiple operational parameters. For example, the CPU may need to set (change) multiple operational parameters of the GPU before issuing a drawing command to the GPU to perform a drawing operation. To set (update) these operational parameters to the coprocessor's registers, the CPU (i.e., the operating system and / or applications) needs to issue numerous register setting commands to the coprocessor via the system bus. The more operational parameters that need to be set (updated), the more register setting commands the CPU generates. These numerous register setting commands consume system bus bandwidth. Furthermore, parsing these numerous register setting commands can negatively impact (degrade) the coprocessor's command processing speed and performance.

[0008] It should be noted that the content of the "Background Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Background Art" paragraph may not be known to those skilled in the art. The content disclosed in the "Background Art" paragraph does not imply that such content was known to those skilled in the art prior to this application. Summary of the Invention

[0009] The present invention provides an electronic device and a method for reducing the number of commands thereto, which merges multiple original register setting commands to generate at least one merged register setting command, thereby reducing the number of register setting commands.

[0010] In one embodiment of the present invention, the above-described command reduction method is adapted to reduce the number of multiple register set commands. The command reduction method includes: generating multiple raw register set commands by a central processing unit (CPU), wherein each of the multiple raw register set commands is adapted to set at least one bit of at least one register of a coprocessor, the multiple raw register set commands including multiple first raw register set commands, and the multiple set targets of the multiple first raw register set commands having address contiguousness; fusing the multiple first raw register set commands by the CPU to generate at least one fused register set command; and transmitting the at least one fused register set command to the coprocessor by the CPU.

[0011] In one embodiment of the present invention, the electronic device includes a central processing unit (CPU) and a coprocessor. The coprocessor includes at least one register. The CPU is coupled to the coprocessor. The CPU is configured to generate a plurality of raw register set commands, each of which is adapted to set at least one bit of the at least one register of the coprocessor. The plurality of raw register set commands includes a plurality of first raw register set commands, wherein the plurality of set targets of the plurality of first raw register set commands have address contiguousness. The CPU merges the plurality of first raw register set commands to generate at least one merged register set command. The CPU transmits the at least one merged register set command to the coprocessor.

[0012] Based on the above, in the embodiments of the present invention, the central processing unit (CPU) merges multiple first original register setting commands with address contiguousness of the target into at least one merged register setting command, and then transmits the at least one merged register setting command to the coprocessor. Therefore, the number of register setting commands transmitted by the CPU to the coprocessor can be effectively reduced.

[0013] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a circuit block of an electronic device according to an embodiment of the present invention.

[0015] Figure 2 This is a flowchart illustrating a method for reducing the number of commands according to an embodiment of the present invention.

[0016] The symbols in the attached diagram are briefly explained as follows:

[0017] 100: Electronic device; 110: Central processing unit; 120: Memory; 130: Coprocessor; S210~S230: Steps. Detailed Implementation

[0018] The term "coupled (or connected)" as used throughout this application (including the claims) can refer to any direct or indirect connection means. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some connection means. The terms "first," "second," etc., used throughout this application (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments can be referred to mutually in the relevant descriptions.

[0019] Figure 1 This is a schematic diagram of a circuit block of an electronic device 100 according to an embodiment of the present invention. Figure 1 The electronic device 100 shown includes a central processing unit 110, a memory 120, and a coprocessor 130. In the following description, depending on different design requirements, the central processing unit 110 and / or the coprocessor 130 may be implemented in hardware, firmware, software (i.e., programs), or a combination of the foregoing.

[0020] Central processing unit 110 is coupled to memory 120. Depending on design requirements, central processing unit 110 may include a central processing unit (CPU), a controller, a microcontroller, a microprocessor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), or other central processing circuitry. Memory 120 may include read-only memory (ROM), random access memory (RAM), flash memory, and / or storage devices. The storage devices may include hard disk drives (HDDs), solid-state drives (SSDs), or other storage devices. In other embodiments, the recording medium may include a non-transitory computer-readable medium, such as a tape, disk, card, semiconductor memory, programmable logic circuitry, etc. The memory 120 is adapted to store some (or all) of the programming codes for the operating system (OS) and / or application program. The central processing unit (CPU) 110 can read from and execute the programming codes from the memory 120 to implement the relevant functions of the CPU 110 described in the following embodiments. Furthermore, the programming codes can also be provided to the electronic device 100 (or CPU 110) via any transmission medium (communication network or radio waves, etc.). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

[0021] Depending on design requirements, the coprocessor 130 may include a controller, microcontroller, microprocessor, ASIC, DSP, FPGA, or other processing circuitry. The coprocessor 130 is coupled to the central processing unit 110 via a bus. The central processing unit 110 may issue one or more commands to the coprocessor 130. Based on the commands from the central processing unit 110, the coprocessor 130 may perform functional operations. For example, in some embodiments, the coprocessor 130 may include a graphics processing unit (GPU) and / or other coprocessing circuitry. In some application scenarios, these commands sent from the central processing unit 110 to the coprocessor 130 may include register setting commands, drawing commands, and / or other commands. Based on the commands from the central processing unit 110, the GPU (coprocessor 130) may perform drawing operations.

[0022] According to design requirements, Figure 1 In the illustrated embodiment, the coprocessor 130 may include at least one command processing unit and at least one register. Based on the contents of this (or these) registers of the coprocessor 130, the command processing unit may execute (or control) functional operations of the coprocessor 130. For example, the register may be configured to store at least one drawing parameter. Based on the drawing parameters in this (or these) registers of the coprocessor 130, the command processing unit may execute (or control) drawing operations of the coprocessor 130.

[0023] The size (number of bits) of each register in the coprocessor 130 can be defined according to design requirements. For example, a register can be 32 bits in size. The function of these 32 bits can be defined according to design requirements. In a register's 32 bits, a single bit may be used to represent (store) an operation parameter of the coprocessor 130, or multiple bits may be used to represent (store) an operation parameter of the coprocessor 130. That is, a register can store multiple operation parameters of the coprocessor 130. Furthermore, all bits of a register (e.g., 32 bits) may be used to represent (store) an operation parameter of the coprocessor 130.

[0024] The central processing unit 110 can issue register setting commands to the coprocessor 130 to set (change) part or all of the contents of any register of the coprocessor 130 (i.e., one or more operating parameters, such as drawing parameters). By setting (changing) the contents (operating parameters) of these registers of the coprocessor 130, the central processing unit 110 can control the functional operation of the coprocessor 130 (e.g., drawing operations).

[0025] Figure 2 This is a flowchart illustrating a method for reducing the number of commands according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In step S210, the central processing unit 110 may execute programming code for an operating system (OS) and / or an application, and / or execute other programming code. During the execution of the programming code, the central processing unit 110 may generate a plurality of raw register setting commands. Each of the plurality of raw register setting commands is adapted to set at least one bit of at least one register of the coprocessor 130. These raw register setting commands may be temporarily stored in memory 120 and / or in cache memory (not shown) of the central processing unit 110.

[0026] Generally, some of the multiple original register set commands (referred to herein as first original register set commands) may have address contiguousness. That is, multiple set targets of these first original register set commands have address contiguousness. In step S220, the central processing unit 110 can fuse these first original register set commands (i.e., original register set commands with address contiguousness) to generate at least one fused register set command. After fusion, in step S230, the central processing unit 110 can transmit the at least one fused register set command to the coprocessor 130. Therefore, the electronic device 100 can execute... Figure 2 The method shown reduces the number of command reductions to decrease the number of register setting commands transmitted from the CPU 110 to the coprocessor 130. Because the number of register setting commands transmitted from the CPU 110 to the coprocessor 130 can be effectively reduced, the bandwidth of the bus between the CPU 110 and the coprocessor 130 can be made more efficient. Furthermore, because the number of these register setting commands is reduced, the burden on the coprocessor 130 to parse these commands can be effectively alleviated, thereby improving the command processing speed and performance of the coprocessor 130.

[0027] The following will illustrate different implementations of step S220 using several examples. It should be noted that the addressing method of the coprocessor 130's registers may differ depending on the application environment and conditions, and the format (syntax) of the original register setting command may also differ. For example, for addressing convenience, these registers of the coprocessor 130 can be divided into multiple register groups, each of which is assigned a group number GID. Each register within a register group can be addressed according to an internal offset.

[0028] The first embodiment will be described here. The first embodiment will employ a "sorting and merging method". In the first embodiment, the masked register setting command "SetRMask" will be used as an example of the original register setting command. It is assumed that the syntax of this masked register setting command is SetRMask(GID,O,M,V), where GID represents the register group number, O represents the offset within a register group, M represents the mask, and V represents the value. It is also assumed that during the execution of the programming code, the central processing unit 110 can generate multiple original commands as shown in Table 1. In Table 1, Draw_command represents the drawing command.

[0029] Table 1: Raw commands generated by the central processing unit 110 and their generation order

[0030]

[0031]

[0032] In the first embodiment, the central processing unit 110 can sort the original register setting commands according to the address of the setting target of the plurality of original register setting commands shown in Table 1. For example, the central processing unit 110 can sort the original register setting commands shown in Table 1 in ascending order. The sorted original commands are shown in Table 2.

[0033] Table 2: New order of the original commands after sorting

[0034]

[0035]

[0036] After sorting, the CPU 110 can merge multiple "first raw register set commands" (i.e., raw register set commands with address contiguousness) that target the same register into a single fused register set command. For example, the raw register set commands in the new sequence 1 to 7 shown in Table 2 all target "offset 2 within register group 1". Since the raw register set commands in the new sequence 1 to 7 target the same register, the CPU 110 can merge these raw register set commands into a single fused register set command "SetRMask(1,2,0xF3FFFFFF,0x12345678)". The remaining raw register set commands shown in Table 2 can be processed similarly.

[0037] The merged commands are shown in Table 3. As can be seen from Table 3, the number of register setting commands transmitted from the CPU 110 to the coprocessor 130 can be effectively reduced. Therefore, the bus bandwidth between the CPU 110 and the coprocessor 130 can be more efficient. On the other hand, because the number of these register setting commands is reduced, the burden on the coprocessor 130 to parse these register setting commands can be effectively reduced, thereby improving the command processing speed and performance of the coprocessor 130.

[0038] Table 3: Original Commands and Commands Set via Fusion Register

[0039]

[0040]

[0041] The second embodiment will be described next. The second embodiment also employs the "sorting and merging method". In the second embodiment, the register setting command "SetR" without a mask will be used as an example of the original register setting command. This register setting command "SetR" can set one or more registers consecutively. It is assumed here that the syntax of this register setting command is SetR(GID,O,N,V1,…,VN), where GID represents the register group number, O represents the offset within a register group, N represents the number of registers, and V1,…,VN represent the values ​​of these N registers respectively. It is also assumed that during the execution of the programming code, the central processing unit 110 can generate multiple original commands as shown in Table 4. In Table 4, Draw_command represents the drawing command.

[0042] Table 4: Original commands generated by the central processing unit 110 and their generation order

[0043]

[0044]

[0045] In the second embodiment, the central processing unit 110 can sort the original register setting commands according to the address of the setting target of the multiple original register setting commands shown in Table 4. For example, the central processing unit 110 can sort the original register setting commands shown in Table 4 in ascending order. The sorted original commands are shown in Table 5.

[0046] Table 5: New order of the original commands after sorting

[0047] Original order New order Original command 1 1 SetR(2,3,2,0x22221111,0x22222222) 3 2 SetR(3,1,1,0x33331111) 2 3 SetR(3,3,2,0x33333333,0x33334444) 4 4 SetR(3,5,1,0x33335555) 5 5 Draw_command

[0048] After sorting, the CPU 110 can merge multiple "first raw register set commands" (i.e., raw register set commands with consecutive address addresses) targeting multiple registers into a single fused register set command. For example, the raw register set commands in the new sequence 3 to 4 shown in Table 5 target three registers with consecutive address addresses (i.e., "three registers offset 3, 4, and 5 within register group 3"). Since the raw register set commands in the new sequence 3 to 4 shown in Table 5 target three registers with consecutive address addresses, the CPU 110 can merge these raw register set commands in the new sequence 3 to 4 shown in Table 5 into a single fused register set command "SetR(3,3,3,0x33333333,0x33334444,0x33335555)".

[0049] The merged commands are shown in Table 6. As can be seen from Table 6, the number of register setting commands transmitted from the CPU 110 to the coprocessor 130 can be effectively reduced. Therefore, the bandwidth of the bus between the CPU 110 and the coprocessor 130 can be made more efficient. On the other hand, because the number of these register setting commands is reduced, the burden on the coprocessor 130 to parse these register setting commands can be effectively reduced, thereby improving the command processing speed and performance of the coprocessor 130.

[0050] Table 6: Original Commands and Commands Set via Fusion Register

[0051]

[0052] The third embodiment will be described below. The third embodiment also employs the "sorting and merging method". In the third embodiment, the masked register setting command "SetRMask" and the unmasked register setting command "SetR" will be used as examples of the original register setting commands. It is assumed that during the execution of the programming code, the central processing unit 110 can generate multiple original commands as shown in Table 7. In Table 7, Draw_command represents the drawing command.

[0053] Table 7: Raw commands generated by the central processing unit 110 and their generation order

[0054]

[0055]

[0056] In the third embodiment, the central processing unit 110 can sort the original register setting commands according to the address of the setting target of the multiple original register setting commands shown in Table 7. For example, the central processing unit 110 can sort the original register setting commands shown in Table 7 in ascending order. The sorted original commands are shown in Table 8.

[0057] Table 8: New order of the original commands after sorting

[0058]

[0059]

[0060] After sorting, the CPU 110 can perform a "first merging operation" to organize the original register setting commands shown in Table 8 into an intermediate command group (as shown in Table 9 below). The "first merging operation" includes: the CPU 110 merging multiple setting commands whose target address is the same register in the original register setting commands shown in Table 8 into a single merged register setting command. The details of the first merging operation can be deduced by referring to the relevant descriptions in Tables 2 and 3, and will not be repeated here. The commands merged by the "first merging operation" are shown in Table 9. As can be seen from Table 9, the number of register setting commands can be effectively reduced.

[0061] Table 9: Original Commands and Merged Register Setting Commands

[0062]

[0063]

[0064] After completing the "first merging operation," the CPU 110 can perform a "second merging operation" to reorganize the intermediate command group shown in Table 9 into a fused command group (as shown in Table 10 below). The "second merging operation" includes: the CPU 110 merging multiple register setting commands (if the command is a masked register setting command "SetRMask", then its mask must be "0xFFFFFFFF") from the intermediate command group shown in Table 9, where the target address is a consecutive address, into a single fused register setting command. The "second merging operation" can be deduced by referring to the relevant descriptions in Tables 5 and 6, and will not be elaborated further.

[0065] Table 10: Original Commands and Commands Set via Fusion Register

[0066]

[0067]

[0068] The commands merged by the "second merging operation" are shown in Table 10. As can be seen from Table 10, the number of register setting commands transmitted from the CPU 110 to the coprocessor 130 can be effectively reduced (from 29 commands to 5 commands). Therefore, the bus bandwidth between the CPU 110 and the coprocessor 130 can be more efficient. On the other hand, because the number of these register setting commands is reduced, the burden on the coprocessor 130 to parse these register setting commands can be effectively reduced, thereby improving the command processing speed and performance of the coprocessor 130.

[0069] The fourth embodiment will be described below. The fourth embodiment employs a "register buffer method." The central processing unit 110 can initialize at least one buffer, wherein the at least one buffer corresponds one-to-one with a register of the coprocessor 130. For example, if the coprocessor 130 has 10 registers, the central processing unit 110 can initialize 10 buffers. These buffers can be located in memory 120 and / or in the cache memory (not shown) of the central processing unit 110.

[0070] In the fourth embodiment, the masked register setting command "SetRMask" and the unmasked register setting command "SetR" will be used as examples of the raw register setting commands. It is assumed that during the execution of the programming code, the CPU 110 can generate multiple raw commands as shown in Table 7. For ease of explanation, it is assumed that these registers of the coprocessor 130 can be divided into three register groups (group numbers 1, 2, and 3), with each register group having 7 registers. Therefore, the CPU 110 can initialize 3 * 7 = 21 buffers, as shown in Table 11. Each buffer has a mask field and a value field.

[0071] Table 11: Initialized buffers of the central processing unit 110

[0072]

[0073] The CPU 110 can pseudo-execute the raw register setting commands shown in Table 7 to fill the corresponding set values ​​of these raw register setting commands into the buffers shown in Table 11. For example, the CPU 110 can pseudo-execute the raw register setting command SetRMask(1,2,0x000000FF,0x00000078) shown in sequence "1" of Table 7 to merge "0x000000FF" and "0x00000078" into the mask field and value field of the buffer in group number 1 and offset 2, respectively. Then, the CPU 110 can pseudo-execute the raw register setting command SetRMask(2,0,0xFFF00000,0x87600000) shown in sequence "2" of Table 7 to merge "0xFFF00000" and "0x87600000" into the mask field and value field of the buffer in group number 2 and offset 0, respectively. Similarly, the CPU 110 can pseudo-execute the raw register setting commands in the order "3", "4" and "5" shown in Table 7, so as to incorporate the masks and values ​​of these raw register setting commands into the mask and value fields of these buffers shown in Table 11, respectively. After the CPU 110 pseudo-executes the orders "1" to "5" shown in Table 7, the contents of the 21 buffers of the CPU 110 are as shown in Table 12.

[0074] Table 12: Buffers following the sequence "1" to "5" shown in Table 7 of the pseudo-execution table of the central processing unit 110

[0075]

[0076] Similarly, the CPU 110 can pseudo-execute the raw register setting commands in the order "1" to "28" shown in Table 7, so as to incorporate the masks and values ​​of these raw register setting commands into the mask and value fields of the buffers shown in Table 11, respectively. After the CPU 110 pseudo-executes the order "1" to "28" shown in Table 7, the contents of the 21 buffers of the CPU 110 are shown in Table 13.

[0077] Table 13: Buffers following the sequence "1" to "28" shown in Table 7 of the pseudo-execution table of the central processing unit 110

[0078]

[0079] After completing the pseudo-execution of all the raw register set commands shown in Table 7, the CPU 110 may scan the 21 buffers of the CPU 110 (as shown in Table 13) to convert the same buffer filled with set values ​​in these buffers into a fused register set command (“SetRMask” or “SetR”), and / or convert multiple buffers filled with set values ​​and with consecutive addresses into the at least one fused register set command (“SetRMask” or “SetR”).

[0080] For example, the buffer in group number 1 and offset 2 shown in Table 13 is filled with a setting value, so the CPU 110 can convert the mask field and value field of this same buffer into a fusion register setting command SetRMask(1,2,0xF3FFFFFF,0x12345678). The buffer in group number 1 and offset 5 shown in Table 13 is filled with a setting value, so the CPU 110 can convert the mask field and value field of this same buffer into a fusion register setting command SetRMask(1,5,0xFF07F0F8,0x12045078).

[0081] The five buffers in group 2 and offsets 0 to 4 shown in Table 13 are filled with setting values, and the addresses of these five buffers are consecutive. The mask fields of these five buffers are all "0xFFFFFFFF" (that is, all bits of this buffer are set). Therefore, the central processing unit 110 can convert these five buffers into a fused register setting command SetR(2,0,5,0x87654321,0x12345678,0xAABBBCCC,0x22221111,0x22222222). The five buffers in group 3 and offset 1 to 5 shown in Table 13 are filled with setting values, and the addresses of these five buffers are consecutive, and the mask field of these five buffers is "0xFFFFFFFF". Therefore, the central processing unit 110 can convert these five buffers into a fused register setting command SetR(3,1,5,0x33331111,0x22555551,0x33333333,0x33334444,0x33335555).

[0082] Therefore, the CPU 110 can convert the 21 buffers shown in Table 13 into 4 fused register set commands. That is, the CPU 110 can convert the 29 raw register set commands shown in Table 7 into 4 fused register set commands. Thus, the number of register set commands transmitted from the CPU 110 to the coprocessor 130 can be effectively reduced, making the bus bandwidth between the CPU 110 and the coprocessor 130 more efficient. On the other hand, because the number of these register set commands transmitted to the coprocessor 130 is reduced, the burden on the coprocessor 130 to parse these register set commands can be effectively reduced, thereby improving the command processing speed and performance of the coprocessor 130.

[0083] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. A method for reducing the number of commands, suitable for reducing the number of multiple register setting commands, characterized in that, include: The central processing unit generates a plurality of raw register setting commands, each of which is adapted to set at least one bit of at least one register of the coprocessor, the plurality of raw register setting commands including a plurality of first raw register setting commands, and the plurality of setting targets of the plurality of first raw register setting commands having address contiguousness; The central processing unit fuses the plurality of first raw register setting commands to generate at least one fused register setting command; as well as The central processing unit transmits the at least one fusion register set command to the coprocessor. The operation of fusing the multiple first original register setting commands includes: The multiple original register setting commands are sorted according to the addresses of the multiple setting targets of the multiple original register setting commands; After sorting, a first merging operation is performed to organize the multiple original register setting commands into an intermediate command group. This first merging operation includes: merging multiple setting commands whose target address is the same register from the multiple original register setting commands into a single merged register setting command; and A second merging operation is performed to organize the intermediate command group into a fused command group, wherein the second merging operation includes merging multiple register setting commands of multiple registers whose addresses are consecutive in the intermediate command group into the at least one fused register setting command.

2. The method for reducing the number of commands according to claim 1, wherein, The coprocessor includes a graphics processor, and the at least one register is configured to store at least one drawing parameter.

3. An electronic device, characterized in that, include: A coprocessor, including at least one register; as well as A central processing unit (CPU), coupled to the coprocessor, is configured to generate a plurality of raw register set commands, each of which is adapted to set at least one bit of the at least one register of the coprocessor. The plurality of raw register set commands include a plurality of first raw register set commands, the plurality of set targets of which have address contiguousness. The CPU merges the plurality of first raw register set commands to generate at least one merged register set command, and the CPU transmits the at least one merged register set command to the coprocessor. The central processing unit sorts the multiple original register setting commands according to the addresses of the multiple setting targets of the multiple original register setting commands; After sorting, the central processing unit performs a first merging operation to organize the multiple original register setting commands into an intermediate command group. The first merging operation includes: merging multiple setting commands whose target address is the same register from the multiple original register setting commands into a single merged register setting command; and The central processing unit performs a second merging operation to organize the intermediate command group into a fused command group, wherein the second merging operation includes merging multiple register setting commands of multiple registers whose addresses are consecutive in the intermediate command group into the at least one fused register setting command.

4. The electronic device according to claim 3, wherein, The coprocessor includes a graphics processor, and the at least one register is configured to store at least one drawing parameter.

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