Qemu-based floating point calculation optimization method and system, storage medium and device

Abstract

The application relates to a QEMU-based floating point calculation optimization method, which comprises the following steps: obtaining an executable file of a target platform architecture; extracting a floating point calculation instruction in the executable file; parsing the floating point calculation instruction, reading an operand and an operation code; judging whether the operand and the operation code belong to a preset classification range; if the operand and the operation code belong to the preset classification range, selecting a floating point calculation mode according to the type of a local platform architecture to replace the floating point calculation instruction for floating point calculation; and if the operand and the operation code do not belong to the preset classification range, still adopting an ALU floating point calculation unit for floating point calculation. The application adopts a method of replacing a floating point calculation with a SIMD instruction, so as to improve the dynamic binary translation efficiency and simplify functions.

Description

Technical Field

[0001] This invention relates to the field of dynamic binary translation technology, and in particular to a floating-point calculation optimization method and system, storage medium and device based on QEMU. Background Technology

[0002] Dynamic binary translation (DBT) is a special just-in-time compilation technology that enables binary files compiled on a target platform to run on other architectures' native platforms without requiring the source code of the translated program as input to the translation system. This reduces the coupling between the application and the underlying hardware, bridging the gap between new and old processors and cross-platform software migration.

[0003] Most dynamic binary translators, regardless of the local platform architecture, use only software languages ​​to simulate floating-point calculations. When processing floating-point instructions, they perform instruction-by-instruction computations in pure software, resulting in low overall efficiency for dynamic binary translation. Among current mainstream multi-platform open-source binary translation frameworks, QEMU offers good portability and scalability. However, QEMU's floating-point instruction processing also relies on function calls to assist in instruction functionality. These functions simulate all floating-point calculations using high-level languages, requiring lengthy instructions to implement the target platform's instructions, which is time-consuming and results in high code redundancy. Furthermore, QEMU incorporates numerous special case checks. Analysis of the SPEC2006 floating-point problem revealed that over 95% of floating-point operands are conventional data, with non-numerical or infinite cases being less common. Currently, QEMU, in achieving compatibility with multiple target machines and multiple host machines, does not fully utilize the resources and advantages of the host machine architecture; the translation efficiency of an unoptimized binary translator is typically only about 10% of that of locally compiled execution.

[0004] Currently, almost every processor architecture has incorporated support for SIMD instructions. SIMD instructions can perform the same operation on a set of data simultaneously, improving processor performance through data parallelism. However, most dynamic binary translators, including QEMU, neglect the use of native SIMD instructions, instead simulating floating-point calculations only through software language implementations. Current binary translation systems that optimize themselves using SIMD instruction technology do not fully leverage the advantages of SIMD technology in new architectures, resulting in lower translation performance. Furthermore, most of these technologies focus on single technical aspects, lacking versatility and a system-wide framework approach, failing to achieve compatibility across multiple platforms and lacking universality. Summary of the Invention

[0005] Therefore, the technical problem this invention aims to solve is to overcome the shortcomings of existing technologies, such as low efficiency in dynamic binary translation, reliance on software language simulation for floating-point computation tasks without fully utilizing local platform resources, low floating-point operation efficiency, high execution overhead, lack of system framework perspective, and lack of universality. To address these problems, this invention provides a QEMU-based floating-point computation optimization method and system, storage medium, and device. Based on the QEMU framework, it fully leverages the resources and advantages of the local platform by replacing floating-point computation instructions with SIMD instructions, thereby improving floating-point computation efficiency and thus enhancing dynamic binary translation efficiency. It is also applicable to various architecture platforms that support SIMD instructions.

[0006] To achieve the above objectives, the main technical solutions adopted by the present invention include:

[0007] In a first aspect, the present invention provides a floating-point calculation optimization method based on QEMU, comprising: obtaining an executable file of a target platform architecture; extracting floating-point calculation instructions from the executable file; parsing the floating-point calculation instructions and reading operands and opcodes; determining whether the operands and opcodes belong to a preset classification range; if the operands and opcodes belong to the preset classification range, then selecting a floating-point calculation method according to the type of the local platform architecture to replace the floating-point calculation instructions for floating-point calculation; if the operands and opcodes do not belong to the preset classification range, then still using the ALU floating-point calculation unit for floating-point calculation.

[0008] In one embodiment of the present invention, the preset classification range is: the operand value type is floating point number and the operand precision does not exceed 64 bits and the opcode corresponding to the operand belongs to the four arithmetic operations; wherein, the four arithmetic operations are: addition, subtraction, multiplication and division.

[0009] In one embodiment of the present invention, the step of selecting a floating-point calculation method to replace the floating-point calculation instruction for floating-point calculation according to the type of local platform architecture includes: determining whether the local platform architecture supports SIMD instructions; if yes, then using the SIMD instructions supported by the local platform architecture to replace the floating-point calculation instruction and perform floating-point calculation; if no, then still using the ALU floating-point calculation unit for floating-point calculation.

[0010] In one embodiment of the present invention, the local platform architecture includes: x86 architecture and ARM architecture.

[0011] In one embodiment of the present invention, the step of selecting a floating-point calculation method to replace the floating-point calculation instruction for floating-point calculation according to the type of local platform architecture further includes: if the local platform architecture is an x86 architecture, then the SSE instruction is used to replace the floating-point calculation instruction and floating-point calculation is performed; if the local platform architecture is an ARM architecture, then the NEON instruction is used to replace the floating-point calculation instruction for floating-point calculation.

[0012] In one embodiment of the present invention, the Helper function is called to parse and read the operands and opcode of the floating-point calculation instruction; the utsname function is called to determine whether the local platform architecture supports SIMD instructions.

[0013] In one embodiment of the present invention, the NEON instruction includes instructions for floating-point division; the instructions for floating-point division are expressed as follows:

[0014] float32x4_t ax=vrecpeq_f32(axt)

[0015] float32x4_t bx=vmulq_f32(cxt,ax)

[0016] Where float and f both represent floating-point numbers; vrecpeq means taking the reciprocal; vmulq means taking the product; ax and bx are both parameters; axt and cxt are both floating-point operands; and float32x4_t is a 32-bit vector floating-point operand.

[0017] Secondly, the present invention provides a floating-point calculation optimization system based on QEMU, comprising: an acquisition module for acquiring an executable file of a target platform architecture; an extraction module for extracting floating-point calculation instructions from the executable file; a parsing module for parsing the floating-point calculation instructions and reading operands and opcodes; and a judgment module for judging whether the operands and opcodes belong to a preset classification range. The judgment module is configured to, if the operands and opcodes belong to the preset classification range, select a floating-point calculation method according to the type of the local platform architecture to replace the floating-point calculation instructions for floating-point calculation; if the operands and opcodes do not belong to the preset classification range, still use the ALU floating-point calculation unit for floating-point calculation.

[0018] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed, implements the QEMU-based floating-point calculation optimization method described in any of the first aspects above.

[0019] Fourthly, the present invention provides a storage device, including a storage medium and a processor, wherein the storage medium stores a computer program, and when the program is executed by the processor, it implements the QEMU-based floating-point calculation optimization method described in any of the first aspects above.

[0020] (III) Beneficial Effects

[0021] The beneficial effects of this invention are as follows: The floating-point calculation optimization method, system, storage medium, and device based on QEMU described in this invention adopt the QEMU framework, delve into the architectural characteristics of the local platform, and fully utilize the resource advantages of the local platform. It performs local SIMD instruction replacement processing on the execution of floating-point processing functions in the source program, using SIMD instructions to optimize and replace floating-point calculation instructions. It identifies opportunities for accelerating floating-point calculations in the dynamic binary translation system, enabling the processor to perform operations on multiple floating-point numbers simultaneously in a single instruction, reducing the number of instructions and execution overhead, thereby improving the efficiency and performance of floating-point operations. This application analyzes the operands and opcodes in the calculation process, classifies various operand and opcode scenarios, and achieves the goal of improving dynamic binary translation efficiency while simplifying functions by using SIMD instructions to replace floating-point calculation instructions. Simultaneously, it identifies the local architecture platform, ensuring compatibility with multiple platforms and possessing high universality and scalability. Attached Figure Description

[0022] Figure 1 A schematic diagram of the overall process of the floating-point calculation optimization method based on QEMU provided for a preferred embodiment of the present invention;

[0023] Figure 2 for Figure 1 A flowchart illustrating the process of determining the local platform architecture using the QEMU-based floating-point calculation optimization method.

[0024] Figure 3 A block diagram of a QEMU-based floating-point calculation optimization system provided in an embodiment of the present invention;

[0025] Figure 4 for Figure 1 Function call graph of the QEMU-based floating-point calculation optimization method;

[0026] Figure 5 for Figure 1 The state transition diagram of the QEMU-based floating-point calculation optimization method;

[0027] Figure 6 for Figure 1 The speedup diagram for floating-point computation optimization of the QEMU-based method on x86 architecture;

[0028] Figure 7 for Figure 1 The speedup of floating-point calculation on ARM architecture based on the QEMU-based floating-point calculation optimization method;

[0029] Figure 8 for Figure 1 The overall structure diagram of the QEMU-based floating-point calculation optimization method.

[0030] [Explanation of Markings in the Attached Images]

[0031] 600: A QEMU-based floating-point computing optimization system;

[0032] 601: Get module;

[0033] 602: Extraction module;

[0034] 603: Parsing module;

[0035] 604: Decision module. Detailed Implementation

[0036] To better explain and facilitate understanding of the present invention, it will be described in detail below with reference to the accompanying drawings and specific embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a clearer and more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0037] Firstly, referring to Figure 1 , Figure 2 As shown, a preferred embodiment of the present invention provides a floating-point calculation optimization method based on QEMU, which will be referred to as "FP-QEMU" for ease of description, and includes:

[0038] S1, obtain the executable file for the target platform architecture;

[0039] Specifically, dynamic binary translation involves both the target platform and the native platform. The binary files compiled on the target platform will run on other architecture native platforms. Therefore, it is necessary to obtain the ELF executable files of the target platform architecture during the dynamic binary translation process.

[0040] S2, extracts floating-point calculation instructions from the executable file;

[0041] Specifically, floating-point numbers are a computer's approximate representation of any real number, similar to scientific notation with a base of 10. Floating-point arithmetic refers to operations involving floating-point numbers, which are typically accompanied by approximations or rounding due to limitations in precise representation. Compared to integers of the same number of bits, floating-point numbers offer a wider range and higher precision.

[0042] In this embodiment, the SPEC2006 benchmark suite is used, which includes the SPEC integer benchmark and the SPEC floating-point benchmark. The SPEC floating-point benchmark covers a variety of intensive floating-point computing tasks. By testing the floating-point tasks in SPEC2006, the performance of a computer system in handling floating-point computing tasks can be evaluated, and performance comparisons, system optimizations, and application optimizations can be performed to meet the need to compare the performance of FP-QEMU and QEMU in floating-point computing under different application scenarios.

[0043] S3, parses floating-point calculation instructions, and reads operands and opcodes;

[0044] Specifically, the Helper function is called to parse and read the operands and opcodes of the floating-point calculation instructions;

[0045] Specifically, in the ELF executable file, when the operation falls under the category of floating-point calculation, the system calls the Helper function to process the operation and parse and read the operands and opcodes of the operation. During the dynamic binary translation process, the system also detects and analyzes the operands and opcodes in real time.

[0046] S4, determine whether the operand and opcode belong to the preset category range;

[0047] Specifically, this application categorizes different operands and opcodes, extracts operands, analyzes and determines their precision range, and analyzes the specific operation types in the opcodes.

[0048] Specifically, it includes:

[0049] S41, if the operands and opcodes belong to the preset classification range, then select the floating-point calculation method according to the type of local platform architecture to replace the floating-point calculation instruction for floating-point calculation;

[0050] Specifically, the preset classification range is: operands whose numerical type is floating point and whose precision does not exceed 64 bits, and whose corresponding opcodes belong to the four arithmetic operations; where the four arithmetic operations are: addition, subtraction, multiplication, and division.

[0051] Specifically, it determines whether the operand's value type is a floating-point number and whether the precision is double-precision (64-bit) or single-precision (32-bit). If the operand is a floating-point number and the precision does not exceed 64 bits, it further determines whether the operation type of the opcode is one of the four arithmetic operations: addition, subtraction, multiplication, and division. If the operation type is one of the four arithmetic operations, it selects the floating-point calculation method according to the type of the local platform architecture to replace the floating-point calculation instruction for floating-point calculation.

[0052] Specifically, it includes:

[0053] S411, determine whether the local platform architecture supports SIMD instructions:

[0054] Specifically, SIMD instructions are a processor instruction set architecture that allows the processor to perform the same operation on a set of data simultaneously, achieving efficient parallel computing. By performing the same operation on multiple data elements within a single clock cycle, SIMD instructions improve data parallelism and reduce instruction execution overhead. SIMD instructions are closely related to floating-point arithmetic; by using SIMD instructions, the processor can perform operations on multiple floating-point numbers simultaneously within a single instruction. For example, it can perform addition, multiplication, square root, and other operations on multiple floating-point numbers in a vector or scalar at once, thereby reducing the number of instructions and execution overhead, and thus improving the efficiency and performance of floating-point operations.

[0055] S412, if so, then use the SIMD instructions supported by the local platform architecture to replace the floating-point calculation instructions and perform floating-point calculations;

[0056] Specifically, if the currently detected floating-point calculation instruction is a simple arithmetic operation on a floating-point number with a precision of no more than 64 bits, unlike the existing technology which uses software language to perform simulated calculations, this application uses the SIMD instruction in the local platform processor to replace such operations with a data parallel processing method, thereby improving floating-point calculation efficiency and thus improving translation efficiency.

[0057] In this embodiment, the local platform selected the most representative x86 architecture and ARM architecture. When the local platform is x86 architecture, the floating-point calculation part uses the SIMD instruction - SSE instruction in the CPU of x86 architecture for processing. When the local platform is ARM architecture, the floating-point calculation part uses the SIMD instruction - NEON instruction in the CPU of ARM architecture for processing.

[0058] Since the NEON instruction set does not include instructions for floating-point division, this application uses floating-point multiplication to replace floating-point division, as shown in formulas (1) and (2):

[0059] float32x4_t ax=vrecpeq_f32(axt)(1)

[0060] float32x4_t bx=vmulq_f32(cxt,ax)(2)

[0061] Formula (1) assigns the reciprocal of axt to ax, and then formula (2) calculates the product of cx and ax to achieve the division of axt by cx. float and f both represent floating-point numbers; vrecpeq means taking the reciprocal; vmulq means taking the product; ax and bx are both parameters, axt and cxt are both floating-point operands; float32x4_t is a 32-bit vector floating-point operand, and four operands are taken at once.

[0062] It is important to note that combining research on floating-point computation and SIMD instructions involves a deep understanding of both floating-point computation algorithms and SIMD parallel computing, and requires addressing compatibility and optimization issues between the two. This application aims to replace floating-point computation instructions with SIMD instructions, thereby enabling the invocation of SIMD instructions across different native platforms, leveraging the advantages of the native platform architecture, and ultimately improving the efficiency of dynamic binary translation.

[0063] During the translation of the ELF file, the UTSNAME library function is called to obtain CPU parameters. The obtained parameter information is then compared with preset values ​​for judgment. Different SIMD instruction implementation functions have been encapsulated in different .h files. Based on different CPU information, the system jumps to the corresponding .h file to call the corresponding SIMD processing function. In this embodiment, the x86 architecture is used as an example, referring to... Figure 4 The diagram shown is a specific function call graph during the execution of the dynamic binary translation system.

[0064] S413, if not, then the ALU floating-point unit will still be used for floating-point calculations.

[0065] Specifically, if the local platform's processor does not support SIMD instructions, then the floating-point computing unit in the processor is still used for calculations.

[0066] S42, if the operand and opcode do not belong to the preset classification range, then the ALU floating-point calculation unit is still used for floating-point calculation.

[0067] Specifically, if the operand precision in floating-point operations exceeds 64 bits, or if the operation in the opcode is a complex operation such as square root extraction and trigonometric function operations, as well as applications in engineering and finance, the floating-point computing unit in the processor is still used for calculation.

[0068] Reference Figure 5 In this embodiment, a state transition flow mathematical model is used to represent the workflow of the QEMU-based floating-point calculation optimization method described in this application, specifically including:

[0069] 1) State Definition

[0070] a) ELF: Executable files for the target architecture.

[0071] b) Helper: When the operation falls under the category of floating-point calculation, the system calls the Helper function to handle the operation.

[0072] c) SIMD Exchange: Floating-point calculation instructions enter the SIMD instruction replacement floating-point calculation instruction frame for processing.

[0073] d) ALU: Floating-point calculation instructions are processed in the arithmetic logic unit.

[0074] e)Insn: Floating-point calculation instruction.

[0075] f) UTSNAME: The computer system calls the utsname function to determine the local platform (Host) architecture.

[0076] g) Final: After the instruction processing is complete, the translated instruction is stored in the local cache.

[0077] 2) Condition Definition

[0078] a) rule1: Parse and read the operand, and determine whether the operand's value type is floating-point and whether the precision is double-precision (64-bit) or single-precision (32-bit).

[0079] b) rule2: Parse and read the opcode, and determine whether the operation type belongs to the four arithmetic operations.

[0080] c) rule3: Operands are not floating-point numbers, precision exceeds the range of double precision (64-bit), and operations are complex operations that do not belong to the four arithmetic operations, such as trigonometric functions.

[0081] 3) Action definition

[0082] a) [Insn] → [SIMD Exchange] indicates that when the floating-point calculation instruction belongs to the four arithmetic operations and the precision requirement is met, the SIMD instruction is used for replacement.

[0083] b) [Insn] → [ALU] indicates that when a floating-point calculation instruction is a high-precision (more than 64-bit precision) or complex operation, it is switched to the ALU floating-point calculation unit.

[0084] c) [UTSNAME] → [SIMD Exchange] indicates that the local CPU supports SIMD instructions and jumps to the specific SIMD instruction implementation.

[0085]

UTSNAME

ALU

[0086] The overall structure of this application is as follows: Figure 8 As shown in Table 1, in this embodiment, tests are conducted in two system architectures.

[0087] Table 1 Binary Translation Local Environment

[0088]

[0089] The x86 architecture test platform uses an 8-core, 8-thread Intel i7-9700 processor, a desktop processor with a CPU clock speed of 3GHz. The ARM architecture test platform uses a Phytium D2000 processor, which integrates eight Phytium-developed high-performance FTC663 cores. The translator used in this embodiment is QEMU 6.0. The QEMU-based floating-point calculation optimization method described in this application is implemented through improved and optimized QEMU 6.0, supporting the replacement of floating-point calculation instructions with SSE and NEON instructions. The experiment uses the standard performance test suite SPEC CPU2006. Since this application mainly focuses on floating-point calculations, all SPEC CPU2006 test cases are floating-point test cases.

[0090] This embodiment uses QEMU 6.0 (translation method without SIMD instruction replacement) and FP-QEMU (translation method with SIMD instruction replacement for floating-point calculations). The translation time of the QEMU 6.0 translator is represented by Time0, and the translation time of FP-QEMU is represented by Time1. The floating-point problem in SPEC2006 was fully tested, with three rounds of testing conducted, and the average value was taken. The speedup calculation formula is shown in formula (3):

[0091] Speedup ratio = (Time0 - Time1) / Time0(3)

[0092] Reference Figure 6 As shown, after using the FP-QEMU method to handle floating-point calculations on the x86 architecture as the native platform, the translation efficiency of all tested floating-point topics was improved. The highest speedup reached 51.5%, and the average speedup reached 37.42%, significantly improving the translation efficiency of the x86 architecture as the native platform. (Refer to...) Figure 7 As shown, after using the FP-QEMU method to process floating-point calculations on the ARM architecture as a native platform, the translation efficiency of all tested floating-point topics was improved. The highest speedup reached 59.59%, and the average speedup reached 52.72%, significantly improving the translation efficiency of the ARM architecture as a native platform.

[0093] This application adopts a technical approach of replacing floating-point calculation instructions with SIMD instructions to fully utilize the SIMD technology resources of the host platform. It analyzes the operands and opcodes in the operation process, classifies various operand and opcode scenarios, and determines the local architecture platform. For the x86 local platform, SSE instructions are used for replacement operations; for the ARM platform, NEON instructions are used to replace floating-point calculation instructions; and for other architectures, corresponding SIMD instructions are used. This solves the problem of low efficiency in dynamic binary translation and fully utilizes the SIMD resources of the local platform to accelerate binary translation applications.

[0094] Secondly, such as Figure 3 As shown, this embodiment provides a QEMU-based floating-point calculation optimization system 600, including: an acquisition module 601 for acquiring an executable file of a target platform architecture; an extraction module 602 for extracting floating-point calculation instructions from the executable file; a parsing module 603 for parsing the floating-point calculation instructions and reading operands and opcodes; and a judgment module 604 for judging whether the operands and opcodes belong to a preset classification range. The judgment module 604 is configured to, if the operands and opcodes belong to the preset classification range, select a floating-point calculation method according to the type of the local platform architecture to replace the floating-point calculation instructions for floating-point calculation; if the operands and opcodes do not belong to the preset classification range, then still use the ALU floating-point calculation unit for floating-point calculation.

[0095] The floating-point calculation optimization system based on QEMU provided in this embodiment is used to implement the steps of the floating-point calculation optimization method based on QEMU provided in the first aspect embodiment of the present invention. Therefore, the floating-point calculation optimization system based on QEMU has all the technical effects of the floating-point calculation optimization method based on QEMU, which will not be repeated here.

[0096] Thirdly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed, implements the QEMU-based floating-point calculation optimization method described in any of the first aspects above.

[0097] Fourthly, embodiments of the present invention provide a storage device, including a storage medium and a processor, wherein the storage medium stores a computer program, and when the program is executed by the processor, it implements the QEMU-based floating-point calculation optimization method described in any of the first aspects above.

[0098] This application uses SIMD instructions to replace floating-point calculations, so as to give full play to the architectural advantages of the local platform. Compared with the method of pure software operation in processing floating-point calculation instructions, when the same operation needs to be performed on a set of data, using SIMD instructions can significantly improve processing performance, thereby improving the efficiency of dynamic binary translation while simplifying functions.

[0099] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0100] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, then this invention should also include these modifications and variations.

[0101] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A floating-point calculation optimization method based on QEMU, characterized in that, include: Obtain the executable file for the target platform architecture; Extract the floating-point calculation instructions from the executable file; Parse the floating-point calculation instruction and read the operands and opcode; Determine whether the operand and the opcode belong to a preset classification range; If the operand and the opcode belong to a preset classification range, then the floating-point calculation method is selected according to the type of local platform architecture to replace the floating-point calculation instruction for floating-point calculation; If the operand and the opcode do not belong to the preset classification range, then floating-point calculation is still performed using the ALU floating-point calculation unit; The preset classification range is as follows: the operand value type is floating point and the operand precision does not exceed 64 bits, and the opcode corresponding to the operand belongs to the four arithmetic operations; wherein, the four arithmetic operations are: addition, subtraction, multiplication, and division; The step of selecting a floating-point calculation method to replace the floating-point calculation instruction for floating-point calculation based on the type of local platform architecture includes: determining whether the local platform architecture supports SIMD instructions; if yes, then using the SIMD instructions supported by the local platform architecture to replace the floating-point calculation instruction and perform floating-point calculation; if no, then still using the ALU floating-point calculation unit for floating-point calculation. The local platform architecture includes: x86 architecture and ARM architecture; The step of selecting a floating-point calculation method to replace the floating-point calculation instruction according to the type of local platform architecture further includes: if the local platform architecture is an x86 architecture, then the SSE instruction is used to replace the floating-point calculation instruction and perform floating-point calculation; if the local platform architecture is an ARM architecture, then the NEON instruction is used to replace the floating-point calculation instruction and perform floating-point calculation. The Helper function is called to parse and read the operands and opcodes of the floating-point calculation instruction; the utsname function is called to determine whether the local platform architecture supports SIMD instructions.

2. The floating-point calculation optimization method based on QEMU according to claim 1, characterized in that: The NEON instruction includes instructions for floating-point division; the instructions for floating-point division are expressed as follows: float32x4_t ax = vrecpeq_f32(axt) float32x4_t bx = vmulq_f32(cxt, ax) Where float and f both represent floating-point numbers; vrecpeq means taking the reciprocal; vmulq means taking the product; ax and bx are both parameters; axt and cxt are both floating-point operands; and float32x4_t is a 32-bit vector floating-point operand.

3. A QEMU-based floating-point calculation optimization system for executing the method of claim 1 or 2, characterized in that, The system includes: The acquisition module is used to acquire the executable file for the target platform architecture; The extraction module is used to extract floating-point calculation instructions from the executable file; The parsing module is used to parse the floating-point calculation instructions and read the operands and opcodes; A judgment module is used to determine whether the operand and the opcode belong to a preset classification range. The judgment module is configured to select a floating-point calculation method to replace the floating-point calculation instruction for floating-point calculation according to the type of local platform architecture if the operand and the opcode belong to the preset classification range; if the operand and the opcode do not belong to the preset classification range, the ALU floating-point calculation unit is still used for floating-point calculation.

4. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the QEMU-based floating-point calculation optimization method as described in claim 1 or 2.

5. A storage device comprising a storage medium and a processor, wherein the storage medium stores a computer program, characterized in that, When the processor executes the computer program, it implements the QEMU-based floating-point calculation optimization method as described in claim 1 or 2.

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