A fan-out packaging structure and fan-out packaging method

Abstract

This invention provides a fan-out packaging structure and method, relating to the field of memory chips. The fan-out packaging structure includes: a chip, an inner substrate, a surface mount layer, an encapsulation layer, an insulating support layer, interconnects, package pins, a first conductive layer, and a second conductive layer. This fan-out packaging structure is fabricated using a fan-out packaging method, transmitting electrical signals through the various conductive layers. This eliminates the need for through-silicon vias (TSVs) on the chip, reducing process complexity, improving production efficiency, and lowering costs. Furthermore, since the chip is mounted on both sides of the inner substrate without the need for thermosetting bonding, manufacturing costs are reduced, heat dissipation is improved, and product performance is enhanced.

Description

Technical Field

[0001] This invention relates to the field of memory chips, and more specifically, to a fan-out packaging structure and a fan-out packaging method. Background Technology

[0002] In the current manufacturing process of memory chips, through-silicon vias and micro-copper pillars are usually arranged on the chip and fixed by thermo-press bonding process. The arrangement process is complicated, the material cost is too high, and the thermo-press equipment is expensive, which leads to low production efficiency and limited performance. Summary of the Invention

[0003] This invention provides a fan-out packaging structure and fan-out packaging method, which can reduce production costs and improve product production efficiency and performance.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] An embodiment of the present invention provides a fan-out packaging structure, comprising:

[0006] Chip, inner substrate, surface mount layer, encapsulation layer, insulating support layer, interconnect, package pins, first conductive layer and second conductive layer;

[0007] The inner substrate has a patch area formed on one side, and the patch layer and the chip are both housed in the patch area. The inner substrate has a through hole, and the through hole houses the insulating support layer. The insulating support layer covers the surface of the inner substrate and exposes the patch area. The insulating support layer is higher than the patch area. The insulating support layer has a first conductive hole through it, and the first conductive hole is filled with the first conductive layer.

[0008] The chip has a functional surface and a non-functional surface arranged opposite each other. The functional surface has chip pin pads. The surface mount layer is in contact with both the non-functional surface and one side of the inner substrate.

[0009] The encapsulation layer is used to encapsulate the chip, the insulating support layer, and the inner substrate. The encapsulation layer has a second conductive hole and exposes the chip pin pads and the first conductive layer. The second conductive hole is filled with the second conductive layer, and the second conductive layer is electrically connected to the chip pin pads and the first conductive layer.

[0010] The interconnect is disposed on the surface of the encapsulation layer, and the interconnect is electrically connected to both the second conductive layer and the package pin.

[0011] Optionally, the patch area is formed on both sides of the inner substrate, each patch area accommodating the patch layer and the chip, and the second conductive hole is formed on both sides of the encapsulation layer and the interconnect line is provided.

[0012] Optionally, the coefficient of thermal expansion of the inner substrate is less than that of the insulating support layer.

[0013] Optionally, the chip includes two sub-stackings arranged opposite each other, each of the two sub-stackings having a functional surface and a non-functional surface arranged opposite each other, the functional surfaces of the two sub-stackings being close to each other, the non-functional surfaces of the two sub-stackings being far from each other, and one of the non-functional surfaces of the sub-stackings being in contact with the patch layer.

[0014] The sub-stacking layer, located away from the surface mount layer, is embedded with a third conductive layer, which is electrically connected to the chip pin pads on the same sub-stacking layer.

[0015] Optionally, the chip includes at least three sub-stackings arranged in the same direction, each of the sub-stackings having a functional surface and a non-functional surface disposed opposite to each other, wherein the non-functional surface of one of the sub-stackings is in contact with the patch layer;

[0016] Each of the sub-lamps that is not in contact with the patch layer is embedded with a fourth conductive layer, which is simultaneously electrically connected to the chip pin pads on the two adjacent sub-lamps.

[0017] Optionally, there is a gap between the chip and the insulating support layer, and the encapsulation layer fills the gap.

[0018] Embodiments of the present invention also provide a fan-out packaging structure, which includes:

[0019] Chip, inner substrate, surface mount layer, encapsulation layer, insulating support layer, interconnect, package pins, first conductive layer and second conductive layer;

[0020] The inner substrate has a patch area formed on one side, the patch layer and the chip are both housed in the patch area, the insulating support layer covers the surface of the inner substrate and exposes the patch area, and the insulating support layer is higher than the patch area.

[0021] The chip has a functional surface and a non-functional surface arranged opposite each other. The functional surface has chip pin pads. The surface mount layer is in contact with both the non-functional surface and one side of the inner substrate.

[0022] The encapsulation layer is used to encapsulate the chip, the insulating support layer, and the inner substrate. The encapsulation layer has a second conductive hole and exposes the chip pin pads. The second conductive hole is filled with a second conductive layer, and the second conductive layer is electrically connected to the chip pin pads.

[0023] The interconnect is disposed on the surface of the encapsulation layer, and the interconnect is electrically connected to both the second conductive layer and the package pin;

[0024] The inner substrate includes two sub-heat sinks and a temporary bonding layer. The temporary bonding layer is embedded between the two sub-heat sinks, and the patch area is located on the side of the two sub-heat sinks that are far apart from each other.

[0025] Optionally, the temporary bonding layer is used to debond under external force to separate the two sub-heat sinks from each other.

[0026] Optionally, the insulating support layer is provided with a first conductive hole, the first conductive hole is filled with the first conductive layer, and the first conductive layer is electrically connected to the second conductive layer.

[0027] An embodiment of the present invention also provides a fan-out packaging method for preparing the above-mentioned fan-out packaging structure, the fan-out packaging method comprising:

[0028] Fabricate the chip;

[0029] Prepare the inner liner substrate;

[0030] The insulating support layer is coated onto the inner liner substrate;

[0031] The first conductive hole is formed in the insulating support layer and then filled to form the first conductive layer.

[0032] The patch layer is arranged in the patch area and the chip is mounted thereon.

[0033] The encapsulation layer is coated on the outer side of the chip, the insulating support layer, and the inner substrate.

[0034] The second conductive hole is formed in the encapsulation layer and filled to form the second conductive layer;

[0035] At least one layer of the interconnects and the package pins are disposed on the surface of the encapsulation layer. Optionally, the step of fabricating the inner substrate includes:

[0036] The through hole is prepared on the inner liner substrate.

[0037] Optionally, the step of coating the insulating support layer includes:

[0038] The through hole is filled with insulating material, and the surface of the inner liner substrate is covered with insulating support material.

[0039] A portion of the insulating material is removed to avoid the patch area, and the insulating support layer is formed.

[0040] Optionally, the step of fabricating the chip includes:

[0041] In the case where the chip comprises two sub-laminated wafers, the functional surfaces of the two sub-laminated wafers are made to fit together.

[0042] A through-hole is made through one of the sub-laminated wafers and filled with conductive material, so that the conductive material contacts the chip pin pads.

[0043] The beneficial effects of the fan-out packaging structure and fan-out packaging method of the present invention include, for example:

[0044] This fan-out packaging structure is fabricated using a fan-out packaging method, which transmits electrical signals through each conductive layer, reducing the need for through-silicon vias on the chip, lowering the process difficulty, and improving production efficiency. Furthermore, the chip is mounted on both sides of the inner substrate without the need for thermo-bonding, which can reduce manufacturing costs and improve heat dissipation, thereby enhancing product performance. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the fan-out packaging structure provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Figure 1 ;

[0048] Figure 3 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Figure 2 ;

[0049] Figure 4 This is a schematic diagram showing the location of the through holes on the inner substrate provided in an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of the inner liner substrate and the insulating support layer provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure of an inner substrate with a temporary bonding layer provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram showing the position of the first conductive layer provided in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram showing the positions of the chip and the patch layer provided in an embodiment of the present invention;

[0054] Figure 9 This is a schematic diagram of the structure after coating and encapsulation provided in an embodiment of the present invention;

[0055] Figure 10 This is a schematic diagram showing the location of the second conductive layer provided in an embodiment of the present invention;

[0056] Figure 11 This is a schematic flowchart of the fan-out packaging method provided in an embodiment of the present invention.

[0057] Icons: 100 - Fan-out package structure; 110 - Chip; 111 - Functional surface; 112 - Non-functional surface; 113 - Chip pin pads; 115 - Sub-stacking; 116 - Third conductive layer; 117 - Fourth conductive layer; 120 - Inner substrate; 121 - Surface mount area; 122 - Through-hole; 125 - Sub-heat sink; 126 - Temporary bonding layer; 130 - Surface mount layer; 140 - Encapsulation layer; 141 - Second conductive via; 150 - Insulating support layer; 151 - First conductive via; 160 - Interconnect; 170 - Package pins; 180 - First conductive layer; 190 - Second conductive layer. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0060] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0061] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0062] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0063] The terms “comprising,” “including,” or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] Unless otherwise explicitly specified and limited, terms such as "setup" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0065] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0066] Please refer to Figures 1-11 The fan-out packaging structure 100 and fan-out packaging method provided in the embodiments of the present invention can solve the above problems, and will be described in detail below.

[0067] refer to Figure 1 , Figure 2 , Figure 7 as well as Figure 10The fan-out package structure 100 includes a chip 110, an inner substrate 120, a surface mount layer 130, an encapsulation layer 140, an insulating support layer 150, an interconnect 160, package pins 170, a first conductive layer 180, and a second conductive layer 190.

[0068] The inner substrate 120 has a patch area 121 formed on one side. The patch layer 130 and the chip 110 are both housed in the patch area 121. The inner substrate 120 has a through hole 122. The through hole 122 houses an insulating support layer 150. The insulating support layer 150 covers the surface of the inner substrate 120 and exposes the patch area 121. The insulating support layer 150 is higher than the patch area 121. The insulating support layer 150 can be used to open a first conductive hole 151. The first conductive hole 151 is filled with a first conductive layer 180.

[0069] The chip 110 has a functional surface 111 and a non-functional surface 112 respectively. The functional surface 111 has chip pin pads 113. The surface mount layer 130 is in contact with both the non-functional surface 112 and one side of the inner substrate 120.

[0070] Encapsulation layer 140 is used to encapsulate chip 110, insulating support layer 150 and inner substrate 120. Encapsulation layer 140 has a second conductive hole 141 and exposes chip pin pad 113 and first conductive layer 180. The second conductive hole 141 is filled with a second conductive layer 190. The second conductive layer 190 is electrically connected to chip pin pad 113 and first conductive layer 180.

[0071] Interconnect 160 is disposed on one side of encapsulation layer 140, and interconnect 160 is electrically connected to the second conductive layer 190 and the package pin 170.

[0072] The fan-out packaging structure 100 is fabricated using a fan-out packaging method. Electrical signals are transmitted through each conductive layer, reducing the need for through-silicon vias on the chip 110, thus lowering the process difficulty and improving production efficiency. Furthermore, the chip 110 is mounted on both sides of the inner substrate 120 without the need for thermo-bonding, which reduces manufacturing costs and improves heat dissipation, thereby enhancing product performance.

[0073] In this embodiment, patch areas 121 are formed on both sides of the inner substrate 120, and each patch area 121 accommodates a patch layer 130 and a chip 110. Second conductive holes 141 are opened on both sides of the encapsulation layer 140 and interconnect lines 160 are provided.

[0074] It is worth noting that the coefficient of thermal expansion of the inner substrate 120 is less than that of the insulating support layer 150.

[0075] Furthermore, both the inner substrate 120 and the patch layer 130 are made of thermally conductive materials, such as copper, aluminum, ceramics, or alloys, to better dissipate heat from the chip 110 and meet the requirements for high-speed, high-bandwidth data exchange between chips 110. Of course, the inner substrate 120 can also be made of materials such as BT resin, ABF resin, carbon fiber, and graphene.

[0076] Of course, if only a single chip 110 is needed, the patch layer 130 and the chip 110 can be arranged on only one side of the inner substrate 120, while the encapsulation layer 140 still needs to encapsulate the insulating support layer 150 of the inner substrate 120 and the chip 110.

[0077] refer to Figure 2 The chip 110 may include two sub-stackings 115 arranged opposite to each other. Each sub-stacking is provided with a functional surface 111 and a non-functional surface 112. The functional surfaces 111 of the two sub-stackings are close to each other, and the non-functional surfaces 112 of the two sub-stackings are far apart from each other. One of the non-functional surfaces 112 of the sub-stacking is in contact with the patch layer 130.

[0078] Specifically, a third conductive layer 116 is embedded in the sub-laminate 115 away from the surface mount layer 130, and the third conductive layer 116 is electrically connected to the chip pin pad 113 on the same sub-laminate 115.

[0079] refer to Figure 3 The chip 110 may also include at least three sub-staples 115 arranged in the same direction. Each sub-staple 115 has a functional surface 111 and a non-functional surface 112 arranged opposite to each other. The non-functional surface 112 of one of the sub-staples 115 is in contact with the surface mount layer 130.

[0080] Specifically, each of the sub-lamps 115 that is not in contact with the patch layer 130 is provided with a fourth conductive layer 117, and the fourth conductive layer 117 is electrically connected to the chip pin pads 113 on the two adjacent sub-lamps 115.

[0081] It is worth noting that there is a gap between the chip 110 and the insulating support layer 150. The encapsulation layer 140 fills the gap, which can better separate the chip 110 and the insulating support layer 150 and ensure the relative position and the stability of the external structure.

[0082] It is worth noting that the specific encapsulation method of the encapsulation layer 140 includes, but is not limited to, plastic sealing or vacuum lamination.

[0083] refer to Figure 6In order to improve the manufacturing efficiency during the fabrication process, the inner substrate 120 may include two sub-heat sinks 125 and a temporary bonding layer 126. The temporary bonding layer 126 is embedded between the two sub-heat sinks 125, and the patch area 121 is located on the side of the two sub-heat sinks 125 that is far from each other. After the fabrication is completed, the temporary bonding layer 126 may be debonded under the action of external force to separate the two sub-heat sinks 125 from each other, thereby forming two relatively small fan-out package structures 100.

[0084] It is worth noting that the inner substrate 120 with temporary bonding layer 126 may not have through hole 122, and the corresponding insulating support layer 150 may not have first conductive hole 151, thereby allowing the inner substrate 120 to be separated by debonding, thus reducing manufacturing costs.

[0085] Of course, the inner substrate 120 with temporary bonding layer 126 may also have through hole 122, and the corresponding insulating support layer 150 may also have first conductive hole 151.

[0086] An embodiment of the present invention also provides a fan-out packaging method for preparing the above-mentioned fan-out packaging structure 100, the fan-out packaging method comprising:

[0087] S100: Fabrication of chip 110; specifically including:

[0088] S110: When the chip 110 includes two sub-laminated wafers 115, the functional surfaces 111 of the two sub-laminated wafers 115 are relatively attached.

[0089] S120: A through hole is made through one of the sub-laminated wafers 115 and filled with conductive material so that the conductive material contacts the chip pin pad 113.

[0090] Of course, in other embodiments of the present invention, the chip 110 may be a single-layer structure or a multi-layer structure. When the chip 110 is a multi-layer structure, it includes at least three sub-staples 115, and the at least three sub-staples 115 are arranged in the same direction.

[0091] S200: Prepare an inner substrate 120; which includes and has through holes 122, the inner substrate 120 has a certain extension length, and the opening direction of the through holes 122 is perpendicular to the extension direction of the inner substrate 120, and the through holes 122 can penetrate through both sides of the inner substrate 120.

[0092] S300: An insulating support layer 150 is coated on the inner substrate 120; specifically, it includes:

[0093] S310: Insulating support material is filled inside the through hole 122 and on the outside of the inner substrate 120;

[0094] S320: Part of the insulating material is removed to avoid the patch area 121, and an insulating support layer 150 is formed.

[0095] After the insulating material is coated, its surface needs to be polished. This makes the shape and structure of the formed insulating support layer 150 more regular, which is convenient for subsequent encapsulation operations and the arrangement of the conductive layer.

[0096] S400: A first conductive hole 151 is formed in the insulating support layer 150 and filled to form a first conductive layer 180.

[0097] In this embodiment, in order to reduce material usage and save manufacturing costs, the extension direction of the first conductive hole 151 can be made to be consistent with the extension direction of the through hole 122; of course, there can also be a certain angle between the extension directions of the two.

[0098] S500: A surface mount layer 130 is arranged in the surface mount area 121 and a chip 110 is mounted thereon. The surface mount layer 130 is formed by curing a material with a certain degree of adhesion and has a certain thermal conductivity. The chip 110 and the inner substrate 120 are located on both sides of the surface mount layer 130, so that while fixing the chip 110 and the inner substrate 120, it can also play a good thermal conductivity role, thereby improving the overall performance of the fan-out package structure 100.

[0099] S600: An encapsulation layer 140 is coated on the outside of the chip 110, the insulating support layer 150, and the inner substrate 120. By coating the encapsulation layer 140, the various structures located inside the encapsulation layer 140 can be encapsulated and protected, and the relative positional stability of the various structures inside can be ensured.

[0100] S700: A second conductive hole 141 is formed in the encapsulation layer 140 and filled to form a second conductive layer 190;

[0101] It is worth noting that the specific method for opening the second conductive hole 141 can be exposure and development, laser drilling, or dry etching, so that the second conductive hole 141 can contact the chip pin pad 113 of the chip 110, and facilitate the electrical connection between the filled second conductive layer 190 and the chip pin pad 113.

[0102] S800: At least one layer of interconnects 160 and package pins 170 are arranged on the surface of the encapsulation layer 140 to facilitate electrical connection between the fan-out package structure 100 and external components.

[0103] It is worth noting that, in order to protect the interconnect 160, the surface of the interconnect 160 can also be covered with a protective layer. In addition, the package pin 170 can also be embedded in the protective layer, which can improve the installation stability of the package pin 170.

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fan-out packaging structure, characterized in that, include: Chip (110), inner substrate (120), surface mount layer (130), encapsulation layer (140), insulating support layer (150), interconnect (160), package pin (170), first conductive layer (180) and second conductive layer (190). The inner substrate (120) has a patch area (121) formed on one side. The patch layer (130) and the chip (110) are both housed in the patch area (121). The inner substrate (120) has a through hole (122) which houses the insulating support layer (150). The insulating support layer (150) covers the surface of the inner substrate (120) and exposes the patch area (121). The insulating support layer (150) is higher than the patch area (121). The insulating support layer (150) has a first conductive hole (151) through it, and the first conductive hole (151) is filled with the first conductive layer (180). The chip (110) has a functional surface (111) and a non-functional surface (112) disposed opposite to each other. The functional surface (111) is provided with chip pin pads (113). The surface mount layer (130) is in contact with both the non-functional surface (112) and one side of the inner substrate (120). The encapsulation layer (140) is used to encapsulate the chip (110), the insulating support layer (150), and the inner substrate (120). The encapsulation layer (140) has a second conductive hole (141) and exposes the chip pin pad (113) and the first conductive layer (180). The second conductive hole (141) is filled with the second conductive layer (190). The second conductive layer (190) is electrically connected to the chip pin pad (113) and the first conductive layer (180). The interconnect (160) is disposed on the surface of the encapsulation layer (140), and the interconnect (160) is electrically connected to both the second conductive layer (190) and the package pin (170). The inner substrate (120) has patch areas (121) formed on both sides, each patch area (121) accommodating the patch layer (130) and the chip (110). The encapsulation layer (140) has the second conductive holes (141) on both sides and the interconnects (160) are provided. There is a gap between the chip (110) and the insulating support layer (150), and the encapsulation layer (140) fills the gap.

2. The fan-out packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the inner substrate (120) is less than that of the insulating support layer (150).

3. The fan-out packaging structure according to claim 1, characterized in that, The chip (110) includes two sub-lamps (115) arranged opposite to each other. Each of the two sub-lamps (115) is provided with a functional surface (111) and a non-functional surface (112) arranged opposite to each other. The functional surfaces (111) of the two sub-lamps (115) are close to each other, and the non-functional surfaces (112) of the two sub-lamps (115) are far apart from each other. The non-functional surface (112) of one of the sub-lamps (115) is in contact with the patch layer (130). The sub-lamps (115) away from the patch layer (130) is provided with a third conductive layer (116). The third conductive layer (116) is electrically connected to the chip pin pad (113) on the same sub-lamps (115).

4. The fan-out packaging structure according to claim 1, characterized in that, The chip (110) includes at least three sub-lamps (115) arranged in the same direction. Each sub-lamp (115) has a functional surface (111) and a non-functional surface (112) arranged opposite to each other. The non-functional surface (112) of one of the sub-lamps (115) is in contact with the patch layer (130). The sub-lamps (115) that are not in contact with the patch layer (130) are all embedded with a fourth conductive layer (117). The fourth conductive layer (117) is electrically connected to the chip pin pads (113) on the two adjacent sub-lamps (115).

5. A fan-out packaging structure, characterized in that, include: Chip (110), inner substrate (120), patch layer (130), encapsulation layer (140), insulating support layer (150), interconnect (160), package pin (170) and second conductive layer (190). The inner substrate (120) has a patch area (121) formed on one side. The patch layer (130) and the chip (110) are both housed in the patch area (121). The insulating support layer (150) covers the surface of the inner substrate (120) and exposes the patch area (121). The insulating support layer (150) is higher than the patch area (121). The chip (110) has a functional surface (111) and a non-functional surface (112) disposed opposite to each other. The functional surface (111) is provided with chip pin pads (113). The surface mount layer (130) is in contact with both the non-functional surface (112) and one side of the inner substrate (120). The encapsulation layer (140) is used to encapsulate the chip (110), the insulating support layer (150), and the inner substrate (120). The encapsulation layer (140) has a second conductive hole (141) and exposes the chip pin pad (113). The second conductive hole (141) is filled with a second conductive layer (190), and the second conductive layer (190) is electrically connected to the chip pin pad (113). The interconnect (160) is disposed on the surface of the encapsulation layer (140), and the interconnect (160) is electrically connected to both the second conductive layer (190) and the package pin (170). The inner substrate (120) includes two sub-heat sinks (125) and a temporary bonding layer (126). The temporary bonding layer (126) is embedded between the two sub-heat sinks (125), and the patch area (121) is located on the side of the two sub-heat sinks (125) that are far apart from each other. The inner substrate (120) has patch areas (121) formed on both sides, each patch area (121) accommodating the patch layer (130) and the chip (110), and the encapsulation layer (140) has the second conductive hole (141) on both sides and the interconnect line (160) provided. There is a gap between the chip (110) and the insulating support layer (150), and the encapsulation layer (140) fills the gap.

6. The fan-out packaging structure according to claim 5, characterized in that, The temporary bonding layer (126) is used to debond under external force so that the two sub-heat sinks (125) can be separated from each other.

7. The fan-out packaging structure according to claim 5, characterized in that, The insulating support layer (150) is provided with a first conductive hole (151) through it, and the first conductive hole (151) is filled with a first conductive layer (180). The first conductive layer (180) is electrically connected to the second conductive layer (190).

8. A fan-out packaging method, characterized in that, The fan-out packaging method is used to prepare the fan-out packaging structure according to any one of claims 1-7, comprising: The chip (110) is prepared. Prepare the inner substrate (120); The insulating support layer (150) is coated on the inner substrate (120). The first conductive hole (151) is formed in the insulating support layer (150), and the first conductive layer (180) is formed by filling it. The patch layer (130) is arranged in the patch area (121) and the chip (110) is mounted thereon. The encapsulation layer (140) is coated on the outside of the chip (110), the insulating support layer (150), and the inner substrate (120). The second conductive hole (141) is opened in the encapsulation layer (140) and filled to form the second conductive layer (190). At least one layer of the interconnect (160) and the package pin (170) are arranged on the surface of the encapsulation layer (140).

9. The fan-out packaging method according to claim 8, characterized in that, The step of preparing the inner substrate (120) includes: Through holes (122) are formed on the inner substrate (120).

10. The fan-out packaging method according to claim 9, characterized in that, The step of coating the insulating support layer (150) includes: The through hole (122) is filled with insulating support material, and the surface of the inner liner substrate (120) is covered with insulating support material; Part of the insulating support material is removed to avoid the patch area (121), and the insulating support layer (150) is formed.

11. The fan-out packaging method according to claim 8, characterized in that, The steps for preparing the chip (110) include: In the case where the chip (110) includes two sub-laminated sheets (115), the functional surfaces (111) of the two sub-laminated sheets (115) are made to be in relative contact; A through-hole is made in one of the sub-laminates (115) and filled with conductive material so that the conductive material contacts the chip pin pad (113).

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