Circuit path detection method, electronic device and readable storage medium

Abstract

The present application belongs to the field of circuit technology, and relates to a detection method for a circuit path, an electronic device, and a readable storage medium. The detection method for a circuit path includes: performing static timing analysis on all timing paths of the chip globally, and determining the static analysis results of all timing paths. Based on the first timing margin in the static analysis results, an object path is determined in all timing paths, and the first timing margin of the object path is less than a first preset threshold. Dynamic simulation analysis is performed on all object paths to determine the violation paths in all object paths. In this way, the present application provides a timing analysis method to efficiently and accurately complete the timing analysis of the chip globally to obtain the timing analysis results, which can not only maintain the efficiency of static timing analysis to determine the violation paths, but also accurately perform dynamic simulation on these violation paths to accurately identify the true violation paths. The timing analysis method provided by the present application is efficient, accurate, and highly versatile.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a circuit path detection method, an electronic device, and a readable storage medium. Background Art

[0002] Timing analysis is a very important part of chip design. As the chip scale continues to increase, the internal timing analysis requirements are becoming more stringent. The timing analysis results can be used to determine the timing margin of each timing path in the chip design during the timing check to determine the violation path in the chip design so as to repair the chip design. For timing analysis, there are usually two methods for timing calculation, namely dynamic timing simulation and static timing analysis.

[0003] However, in static timing analysis, the analysis of unit delay and interconnect delay is performed by table lookup and modeling, which is less accurate than dynamic simulation. In addition to the slow calculation speed, dynamic timing simulation is not perfect in searching for critical paths. Therefore, how to provide a timing analysis method to efficiently and accurately complete the timing analysis of the chip as a whole to obtain the timing analysis results and realize efficient screening of violation paths in chip design is an issue that technicians in this field need to consider urgently. Summary of the invention

[0004] In response to the above technical problems, the present application provides a circuit path detection method, an electronic device and a readable storage medium, which can provide a timing analysis method to efficiently and accurately complete the global timing analysis of the chip to obtain the timing analysis results, thereby achieving efficient screening of illegal paths in chip design for subsequent timely repairs and accelerating the chip production progress.

[0005] In order to solve the above technical problems, the first aspect of the present application provides a circuit path detection method, comprising: performing static timing analysis on all timing paths of the chip globally, and determining the static analysis results of all timing paths. Based on the first timing margin in the static analysis results, determining the object path in all timing paths, the first timing margin of the object path is less than the first preset threshold. Performing dynamic simulation analysis on all object paths, and determining the violating paths in all object paths.

[0006] Optionally, the step of performing static timing analysis on all timing paths of the chip globally and determining the static analysis results of all timing paths includes: performing a timing check on each timing path, and calculating the unit delay and interconnection delay of each timing path. Based on the unit delay and interconnection delay of each timing path, obtaining a first timing margin in the static analysis results of each timing path.

[0007] Optionally, the timing check includes a setup time check, a hold time check, a recovery time check, or a removal time check.

[0008] Optionally, the step of obtaining the first timing margin in the static analysis result of each timing path based on the unit delay and interconnection delay of each timing path includes: obtaining the data signal arrival time of each timing path and the first data requirement time that meets the setup time requirement or the second data requirement time that meets the hold time requirement based on the unit delay and interconnection delay of each timing path. When the timing check is a setup time check, the first timing margin in the static analysis result of each timing path is obtained based on the difference between the first data requirement time and the data signal arrival time; or, when the timing check is a hold time check, the first timing margin in the static analysis result of each timing path is obtained based on the difference between the data signal arrival time and the second data requirement time.

[0009] Optionally, the step of performing dynamic simulation analysis on all object paths and determining the violating paths among all object paths includes: obtaining a dynamic simulation input file for each object path in response to simulation parameter settings. Based on the dynamic simulation input file for each object path, calling a dynamic simulator to perform simulation to obtain a dynamic simulation result. Based on the second timing margin in the dynamic simulation result of each object path, determining the violating paths among all object paths, wherein the second timing margin of the violating paths is less than a second preset threshold.

[0010] Optionally, the static analysis result also includes the pin input conversion time and / or the maximum cumulative delay time. In response to the simulation parameter setting, the step of obtaining the dynamic simulation input file of each object path includes: performing excitation setting based on the pin input conversion time in the static analysis result to determine the starting point input waveform in the dynamic simulation input file. And / or determining the starting point input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file. Performing simulation time setting based on the maximum cumulative delay time in the static analysis result to determine the simulation time in the dynamic simulation input file, wherein the simulation time is greater than the maximum cumulative delay time in the static analysis result.

[0011] Optionally, the step of setting the excitation based on the pin input conversion time in the static analysis result to determine the starting point input waveform in the dynamic simulation input file, and / or the step of determining the starting point input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file includes: obtaining the initial conversion time of the starting point according to the pin input conversion time of the static analysis result, and / or obtaining the initial conversion time of the starting point according to the port input conversion time set in the timing constraint file. Based on the restriction parameters, the initial conversion time is corrected to obtain the starting point input conversion time, and the restriction parameters include the threshold and attenuation coefficient in the timing library. The starting point input waveform is determined based on the starting point input conversion time.

[0012] Optionally, the maximum cumulative delay time in the static analysis result is the larger one between the data signal arrival time and the data requirement time.

[0013] Optionally, the first preset threshold is 0 or a positive value close to 0.

[0014] A second aspect of the present application provides an electronic device, which includes: a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the circuit path detection method as described above is implemented.

[0015] A third aspect of the present application provides a readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the circuit path detection method as described in any one of the above items is implemented.

[0016] The present application provides a circuit path detection method, an electronic device, and a readable storage medium. The circuit path detection method includes: performing static timing analysis on all timing paths of the chip globally, and determining the static analysis results of all timing paths. Based on the first timing margin in the static analysis results, an object path is determined in all timing paths, and the first timing margin of the object path is less than a first preset threshold. Dynamic simulation analysis is performed on all object paths to determine the violation paths in all object paths. In this way, the present application uses static simulation to efficiently parse the global object path of the chip (i.e., the initial violation path), generates a dynamic simulation input file for the object path, and calls the dynamic simulator to complete the timing simulation, accurately identifying the true violation path in all object paths, so as to facilitate subsequent timely repairs and speed up the chip production progress; therefore, the present application provides a timing analysis method to efficiently and accurately complete the global timing analysis of the chip to obtain the timing analysis results, which can not only maintain the efficiency of static timing analysis to determine the violation path, but also can accurately perform dynamic simulation on these violation paths to accurately identify the true violation path. The timing analysis method provided by the present application is efficient, accurate, and highly versatile. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0018] Figure 1 is a flow chart of a circuit path detection method provided in the first embodiment of the present application;

[0019] Figure 2 is a schematic diagram of the circuit structure of the timing path shown in the first embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a pi-model equivalent circuit and an effective capacitance equivalent circuit shown in the first embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the calculation process of the unit delay and the unit conversion time provided in the first embodiment of the present application;

[0022] Figure 5 It is a schematic diagram comparing the results of static timing analysis and dynamic simulation analysis provided by the first embodiment of the present application;

[0023] Figure 6 It is a schematic diagram of the structure of an electronic device provided in the second embodiment of the present application.

[0024] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0025] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0026] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. Optionally, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment.

[0027] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0028] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0029] It should be noted that in this article, step codes such as S1 and S2 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the scope of protection of this application.

[0030] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0031] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0032] A timing path refers to the logical path that a data signal passes through when it propagates in a chip design. A timing path contains a startpoint and an endpoint. The startpoint of a timing path is the input port of the design or the clock pin of a timing element, and the endpoint can be the output port of the design or the data input pin of a timing unit. During design, the timing path needs to meet the constraints related to the timing unit, that is, to perform corresponding timing checks, such as setup time check, hold time check, recovery time check, and removal time check. During timing checks, each timing path in the chip design has a corresponding timing slack. When the timing slack is negative, a timing violation will occur. The timing path that has a violation is called a violation path.

[0033] Dynamic timing simulation can realize transistor-level simulation, so the analysis results are accurate.

[0034] Static timing analysis does not require calling the process library for precise simulation. It uses an interpolation calculation method based on the feature library for unit delay and a model analysis for interconnect delay. It has the characteristics of fast analysis speed and high efficiency. In addition, when using static methods to analyze the timing of paths, the chip design can be divided into a series of paths as the basic unit. It analyzes and reports whether the delay of each path meets the timing requirements, so the test coverage of the timing path is high.

[0035] First embodiment

[0036] Figure 1 is a flow chart of a circuit path detection method provided in the first embodiment of the present application; Figure 2 is a schematic diagram of the circuit structure of the timing path shown in the first embodiment of the present application; Figure 3 is a schematic diagram of a pi-model equivalent circuit and an effective capacitance equivalent circuit shown in the first embodiment of the present application; Figure 4 It is a schematic diagram of the calculation process of the unit delay and the unit conversion time provided in the first embodiment of the present application; Figure 5 It is a schematic diagram comparing the results of static timing analysis and dynamic simulation analysis provided in the first embodiment of the present application.

[0037] In order to clearly describe the circuit path detection method provided by the first embodiment of the present application, please refer to Figures 1 to 5 .

[0038] See also Figure 1 The first embodiment of the present application provides a circuit path detection method, comprising:

[0039] S1: Perform static timing analysis on all timing paths of the chip globally to determine the static analysis results of all timing paths.

[0040] In one implementation, the static analysis results include but are not limited to the first timing margin, the pin input conversion time and / or the maximum accumulated delay time, etc.

[0041] In one embodiment, S1: performing static timing analysis on all timing paths of the chip globally, and determining the static analysis results of all timing paths, includes but is not limited to: performing a timing check on each timing path, and calculating the unit delay and interconnection delay of each timing path. Based on the unit delay and interconnection delay of each timing path, obtaining a first timing margin in the static analysis results of each timing path.

[0042] In one embodiment, based on all unit delays and all interconnection line delays of each timing path, a first timing margin in the static analysis results of each timing path is obtained. For example, based on all unit delays and all interconnection line delays of each timing path, a first timing margin in the static analysis results of each timing path is obtained.

[0043] In one embodiment, the timing check includes but is not limited to a setup time check, a hold time check, a recovery time check, or a removal time check.

[0044] In one embodiment, the step of obtaining the first timing margin in the static analysis result of each timing path based on the unit delay and interconnection delay of each timing path includes, but is not limited to: obtaining the data signal arrival time of each timing path and the first data requirement time that meets the setup time requirement or the second data requirement time that meets the hold time requirement based on the unit delay and interconnection delay of each timing path. When the timing check is a setup time check, the first timing margin in the static analysis result of each timing path is obtained based on the difference between the first data requirement time and the data signal arrival time; or, when the timing check is a hold time check, the first timing margin in the static analysis result of each timing path is obtained based on the difference between the data signal arrival time and the second data requirement time.

[0045] Based on the above technical concept, the following describes the process of obtaining the first timing margin by static timing analysis, taking the establishment time check as an example:

[0046] based on Figure 2 The timing path diagram of the timing margin (slack) is as follows:

[0047] Formula 1: Tarrival=Tlaunch+Tcp2q+Tdp

[0048] Formula 2: Trequired=Tcapture+Tclk-Tsetup

[0049] Formula 3: Slack=Trequired-Tarrival

[0050] Among them, Tarrival represents the arrival time of the data signal, Trequired represents the data requirement time when the setup requirement (setup time requirement) is met (that is, the time taken for the clock to be transmitted to the capture trigger plus the clock cycle minus the setup time requirement), Tclk represents the clock cycle. Tsetup represents the setup time, which is obtained by looking up the timing library corresponding to the chip.

[0051] Among them, Tlaunch represents the clock network delay from the clock source point to the first trigger (that is, including the unit delay of this part and the interconnection line delay); Tcp2q represents the delay from the CP end to the Q end of the trigger (that is, the unit delay of this part, which is determined by the electrical characteristics of the trigger itself); Tdp represents the circuit delay of the combinational logic circuit part (that is, including the unit delay of this part and the interconnection line delay, which is the circuit delay of the combinational logic circuit part between the output end of the first trigger and the input end of the second trigger).

[0052] From the above formula, we can know that the calculation of timing margin using static timing analysis method is actually to calculate and accumulate the unit delay and interconnection delay in each timing path separately, and then subtract the data requirement time of the data path that meets the setup time requirement from the data signal arrival time. Therefore, the key to calculating timing margin using static timing analysis method lies in the calculation of unit delay, unit output conversion time, interconnection delay and interconnection output conversion time.

[0053] Optionally, when calculating the unit delay, the equivalent capacitance needs to be solved first: First, the interconnection line and the receiver are simplified into a pi-model circuit as follows Figure 3 As shown in A, the effective capacitance circuit solved is Figure 3 As shown in B, an equation is established based on the equal amount of charged charge, and the effective capacitance value is obtained by solving. After the effective capacitance value is obtained, the cell delay is obtained by looking up the table in the standard cell library file and performing interpolation calculation based on the input conversion time and the effective capacitance.

[0054] Optionally, when solving the interconnection delay, the Elmore delay calculation scheme or the interconnection delay calculation based on the circuit equation can be used to solve the interconnection delay. Among them, the Elmore delay calculation scheme has the advantage of fast calculation speed. Among them, when using the interconnection delay calculation based on the circuit equation, it is necessary to find the parasitic parameter information of the interconnection in the parasitic parameter file corresponding to the chip design (for example, including the distribution and specific values ​​of the resistance between nodes, the capacitance to ground, etc.), establish an equivalent circuit model, and establish a differential equation group for description, and finally obtain the interconnection delay and the interconnection output conversion time by solving the differential equation.

[0055] Based on the above timing margin calculation process, after calculating all timing paths of the chip globally, the timing paths whose first timing margins are negative are screened out as the target paths.

[0056] Based on the above technical concept, the following describes the process of obtaining the first timing margin by static timing analysis, taking the hold time check as an example:

[0057] based on Figure 2 The timing path diagram of the timing margin (slack) is as follows:

[0058] Formula 1: Tarrival=Tlaunch+Tcp2q+Tdp

[0059] Formula 2: Trequired=Tcapture+Thold

[0060] Formula 3: Slack=Tarrival–Trequired

[0061] Among them, Tarrival represents the arrival time of the data signal, Trequired represents the data requirement time when the hold requirement (hold time requirement) is met (that is, the time taken for the clock to be transmitted to the capture trigger plus the hold time requirement). Thold represents the hold time, which is obtained by looking up the timing library corresponding to the chip.

[0062] Among them, Tlaunch represents the clock network delay from the clock source point to the first trigger (that is, including the unit delay of this part and the interconnection line delay); Tcp2q represents the delay from the CP end to the Q end of the trigger (that is, the unit delay of this part, which is determined by the electrical characteristics of the trigger itself); Tdp represents the circuit delay of the combinational logic circuit part (that is, including the unit delay of this part and the interconnection line delay, which is the circuit delay of the combinational logic circuit part between the output end of the first trigger and the input end of the second trigger).

[0063] It can be seen from the above formula that the static timing analysis method is used to calculate the timing margin. In fact, the unit delay and interconnection delay in each timing path are calculated and accumulated separately, and then the data signal arrival time and the data required time that meets the hold time requirement are subtracted to obtain the timing margin.

[0064] Based on the above timing margin calculation process, after calculating all timing paths of the chip globally, the timing paths whose first timing margins are negative are screened out as the target paths.

[0065] Based on the above technical concept, the technical process of recovery time check and removal time check in timing check is similar to the technical process of setup time check and hold time check, and will not be elaborated in detail.

[0066] S2: Based on the first timing margin in the static analysis result, determine the object path among all the timing paths, and the first timing margin of the object path is less than a first preset threshold.

[0067] In one embodiment, the first preset threshold value may be 0, and when the first timing margin of the sequential circuit is a negative value, it is determined to be the object path (i.e., the initial violation path). Optionally, the first preset threshold value may also be a positive value close to 0, so as to appropriately expand the determination range of the object path and avoid the static timing analysis from missing the initial violation path.

[0068] S3: Perform dynamic simulation analysis on all object paths to determine the violation paths among all object paths.

[0069] In one embodiment, S3: performing dynamic simulation analysis on all object paths to determine the step of violating paths in all object paths, includes but is not limited to: in response to simulation parameter settings, obtaining a dynamic simulation input file for each object path. Based on the dynamic simulation input file of each object path, calling a dynamic simulator to perform simulation to obtain a dynamic simulation result. Based on the second timing margin in the dynamic simulation result of each object path, determining the violating paths in all object paths, the second timing margin of the violating paths being less than a second preset threshold.

[0070] In one implementation, the second preset threshold may be 0, and when the timing margin determined by the sequential circuit based on the dynamic simulation analysis is negative again, it is determined as the final violation path.

[0071] In one embodiment, it should be understood that the dynamic simulation result may include, in addition to the second timing margin, other data or information for subsequent operations (eg, repair testing, etc.) after the violation path is detected.

[0072] In one embodiment, the static analysis result also includes the pin input conversion time and / or the maximum cumulative delay time. In response to the simulation parameter setting, the step of obtaining the dynamic simulation input file of each object path includes: performing excitation setting based on the pin input conversion time in the static analysis result to determine the starting point input waveform in the dynamic simulation input file. And / or, determining the starting point input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file. And / or, performing simulation time setting based on the maximum cumulative delay time in the static analysis result to determine the simulation time in the dynamic simulation input file.

[0073] In one implementation, when both dynamic simulation analysis and static timing analysis need to use a timing constraint file, the timing constraint file used in the dynamic simulation analysis may be consistent with the timing constraint file used in the static timing analysis.

[0074] In one embodiment, the step of setting the excitation based on the pin input conversion time in the static analysis result to determine the starting point input waveform in the dynamic simulation input file, and / or determining the starting point input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file includes but is not limited to: obtaining the initial conversion time of the starting point according to the pin input conversion time of the static analysis result, or obtaining the initial conversion time of the starting point according to the port input conversion time set in the timing constraint file; based on the restriction parameters, the initial conversion time is corrected to obtain the starting point input conversion time, and the restriction parameters include the threshold and attenuation coefficient in the timing library. Determine the starting point input waveform based on the starting point input conversion time. For example, the initial conversion time t0 of the starting point is obtained according to the pin input conversion time solved by the static simulation analysis, and then t0 is corrected according to the threshold, attenuation coefficient and other parameters in the timing library. For example, when the attenuation coefficient derate=0.5 and the measurement threshold point is set to 30%-70%, the corrected starting point input conversion time t1 is: t1=0.5*t0 / (70%-30%). Accordingly, the input excitation of the starting point, that is, the voltage waveform or current waveform, is obtained. Or for example, the initial conversion time t0 of the starting point is obtained according to the port conversion time set in the timing constraint file, and then t0 is corrected according to the threshold, attenuation coefficient and other parameters in the timing library. For example, when the attenuation coefficient derate = 0.5 and the measurement threshold point is set to 30%-70%, the corrected starting input conversion time t1 is: t1 = 0.5*t0 / (70%-30%). Based on this, the input excitation of the starting point, that is, the voltage waveform or current waveform, is obtained. In one embodiment, the simulation time may be greater than the maximum cumulative delay time in the static analysis result. Optionally, the case where the simulation time is greater than the maximum cumulative delay time in the static analysis result includes: T2 = 2*T1; or, T2 = T1+20ns. Wherein, T1 represents the maximum cumulative delay time in the static analysis result. For example, when checking the establishment time, T1 is set to the maximum value obtained by comparing the data signal arrival time Tarrival with the data requirement time Trequired that meets the establishment time requirement. T2 represents the simulation time.

[0075] In one embodiment, the maximum cumulative delay time in the static analysis result is the larger one between the aforementioned data signal arrival time and the data request time.

[0076] In one implementation, the simulation parameter setting may further include defining simulation settings, unit information settings, interconnection line information settings, measurement point settings, and the like.

[0077] In one embodiment, based on the dynamic simulation input file of each object path, the step of calling a dynamic simulator for simulation to obtain a dynamic simulation result includes but is not limited to: based on the dynamic simulation input file of each object path, calling a dynamic simulator for simulation, and collecting all waveforms of each object path after the simulation to obtain waveform information; calculating the unit delay and interconnection delay of each object path based on the waveform information; calculating the timing margin based on the unit delay and interconnection delay of each object path to obtain a second timing margin in the dynamic simulation result.

[0078] Based on the above technical concept, the following example describes the process of obtaining the second timing margin through dynamic simulation analysis:

[0079] 1) Define simulation settings:

[0080] Set the chip design information such as the process library (model) and component library required for simulation, and set the simulation environment such as voltage and temperature.

[0081] 2) Unit information setting:

[0082] Select all the units involved in the object path and use them as subcircuits (the internal circuit information of these units is listed in the component library in 1)).

[0083] 3) Interconnection line information setting:

[0084] Record the names of all interconnection lines from the starting point of the object path to the end point of the object path, search out the information of these interconnection lines in the parasitic parameter file corresponding to the chip, and convert them into a parameter format recognizable by the dynamic simulator.

[0085] 4) Incentive setting:

[0086] According to the port attributes of the timing constraint file and the pin input conversion time in the static analysis results, the excitation of the starting point of the object path is obtained to obtain the starting point input conversion time; then according to the threshold, attenuation coefficient and other parameters in the timing library, the input conversion time of the starting point of the object path is converted into an input waveform as the input excitation of the entire simulation circuit. In addition, you can also set the excitation signal information for the power supply and ground and other pin input excitation information, such as the excitation at the D pin of the first trigger, which is similar to the excitation acquisition method of the starting point, or when other pin excitations do not affect the delay of the timing path, you can set reasonable excitations yourself. .

[0087] 5) Measurement point setting:

[0088] According to the unit information in 2), the input and output voltage waveforms of all units are measured and recorded; according to the interconnection line information in 3), the input waveforms at the starting points and the output waveforms at the end points of all interconnections are measured.

[0089] 6) Simulation time setting

[0090] According to the maximum cumulative delay time T1 in the previous static analysis results, set the simulation time T2. In principle, T2>T1. To ensure simulation stability, you can set T2=2*T1 or T2=T1+20ns.

[0091] The information obtained by setting the above simulation parameters is summarized in the dynamic simulation input file. The dynamic simulator is called based on the dynamic simulation input file for simulation. After the simulation is completed, all waveforms of each object path are collected to obtain waveform information; based on the waveform information, the unit delay and interconnection line delay of each object path are calculated. For example, taking the inverter as an example, see Figure 4 The cell delay of the inverter is calculated based on the waveform delays at its input and output ends, the cell output delay cell output transition is calculated based on the waveform at the inverter output end, and the net delay of the interconnection line is calculated based on the waveform delays at the input and output ends of the interconnection line, and the net output transition of the interconnection line is calculated based on the waveform at the output end of the interconnection line (not shown in the figure).

[0092] There are two solutions for solving the second timing margin:

[0093] 1) Based on the information of unit delay and interconnection delay obtained by the above dynamic simulation analysis, the total delay is accumulated using the same method as the static timing analysis, and then the timing margin is solved (for example, the process example of obtaining the first timing margin by the above static timing analysis can be referred to);

[0094] 2) Directly solve the timing margin, for example, directly analyze Figure 2 The waveform delay relationship between the data port and the clock port of the second trigger dff_out_2 is calculated, and the timing margin is obtained by considering the clock cycle and timing constraints.

[0095] In other implementations, during the dynamic simulation analysis of all object paths, a dynamic simulation input file may be automatically generated for each object path, for example, by using programming, scripting, or other methods to automatically generate the dynamic simulation input file.

[0096] After testing, taking a 28nm chip as an example, the above method was used to obtain the cell delay, net delay and stage delay of 100,000 cases. Figure 5 By comparing the results of static timing analysis (STA) and dynamic simulation analysis (DTA), it can be seen that although the static analysis results can maintain a high accuracy, there are still differences in delay calculation with the dynamic simulation results. When calculating the total delay, due to the existence of the cumulative effect, the error is gradually increased, thereby affecting the calculation accuracy of the final timing margin. It can be seen that it is very necessary to use dynamic simulation analysis again to perform accurate timing analysis on the initial violation path obtained by static timing analysis (STA).

[0097] It should be understood that when analyzing the global timing path of the chip, efficiently screening out the timing violation path is crucial to the timing analysis of the chip, especially in the sign-off stage. Fast and accurate timing analysis plays a vital role in the production and iteration of the chip. A detection method for a circuit path in this embodiment proposes a timing analysis method, that is, after the timing violation path is parsed out by static timing analysis, a dynamic simulation input file can be automatically generated, and the dynamic simulator is called to complete the timing calculation of the critical path (object path). That is, this implementation scheme maintains the efficiency of static timing analysis when estimating the timing of the chip globally; the timing violation path is screened out through static timing analysis, and these paths are accurately dynamically simulated and analyzed, which has the characteristics of high efficiency, accuracy and strong versatility. In summary, this scheme efficiently integrates the advantages of static timing analysis and dynamic simulation analysis, and effectively avoids the problems of inaccurate static timing analysis and lengthy overall circuit time of dynamic simulation analysis chip, and can provide chip designers with efficient and high-precision global timing calculation solutions.

[0098] The first embodiment of the present application provides a circuit path detection method, comprising: S1: performing static timing analysis on all timing paths of the chip globally to determine the static analysis results of all timing paths. S2: determining an object path in all timing paths based on a first timing margin in the static analysis results, wherein the first timing margin of the object path is less than a first preset threshold. S3: performing dynamic simulation analysis on all object paths to determine the violating paths in all object paths. Thus, the first embodiment of the present application provides a method for detecting a timing path. After using static simulation to efficiently parse the global object path of the chip (i.e., the initial violation path), a dynamic simulation input file is generated for the object path, and after calling the dynamic simulator to complete the timing simulation, the real violation path in all object paths is accurately identified, so as to facilitate the subsequent timely repair and speed up the chip production progress; therefore, the present embodiment provides a timing analysis method to efficiently and accurately complete the global timing analysis of the chip to obtain the timing analysis result, which can maintain the efficiency of static timing analysis to determine the violation path, and can accurately perform dynamic simulation on these violation paths to accurately identify the real violation path. The timing analysis method provided by the present embodiment has the characteristics of high efficiency, accuracy, and strong versatility. Further, the present embodiment can query all the violation paths in the chip design, so as to facilitate the subsequent repair, thereby meeting the sign-off requirements.

[0099] Second embodiment:

[0100] Figure 6 1 is a schematic diagram of the structure of the electronic device provided in the second embodiment of the present application. In order to clearly describe the electronic device 1 provided in the second embodiment of the present application, please refer to Figure 6 .

[0101] The electronic device 1 provided in the second embodiment of the present application includes: a processor A101 and a memory A201. Optionally, the processor A101 is used to execute a computer program A6 stored in the memory A201 to implement the steps of the circuit path detection method as in the first embodiment.

[0102] Optionally, the electronic device 1 provided in this embodiment may include at least one processor A101 and at least one memory A201. Optionally, the at least one processor A101 may be referred to as a processing unit A1, and the at least one memory A201 may be referred to as a storage unit A2. Optionally, the storage unit A2 stores a computer program A6, and when the computer program A6 is executed by the processing unit A1, the electronic device 1 provided in this embodiment implements the steps of the circuit path detection method of the first embodiment, for example, Figure 1The steps S1 shown in the figure: static timing analysis is performed on all timing paths of the chip globally to determine the static analysis results of all timing paths. S2: based on the first timing margin in the static analysis results, an object path is determined in all timing paths, and the first timing margin of the object path is less than a first preset threshold. S3: dynamic simulation analysis is performed on all object paths to determine the violation paths in all object paths.

[0103] Optionally, the electronic device 1 provided in this embodiment may include multiple memories A201 (referred to as storage units A2 for short).

[0104] Optionally, the storage unit A2 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Optionally, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAM bus random access memory (DRRAM, Direct Rambus Random Access Memory).The storage unit A2 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0105] Optionally, the electronic device 1 further includes a bus connecting different components (eg, the processor A101 and the memory A201, etc.).

[0106] Optionally, the electronic device 1 may further include a program calling interface A4 and a command line and / or a graphical user interface A3.

[0107] Optionally, the electronic device 1 provided in this embodiment may further include a communication device A5.

[0108] The electronic device 1 provided in the second embodiment of the present application includes a memory A101 and a processor A201, and the processor A101 is used to execute the computer program A6 stored in the memory A201 to implement the steps of the circuit path detection method of the first embodiment. Therefore, the electronic device 1 provided in this embodiment can use static simulation to efficiently parse the global object path (i.e., the initial violation path) of the target chip, generate a dynamic simulation input file for the object path, and call the dynamic simulator to complete the timing simulation, and accurately identify the real violation path in all object paths, so as to facilitate the subsequent timely repair and speed up the target chip production progress; Therefore, the electronic device 1 of this embodiment can provide a timing analysis method to efficiently and accurately complete the timing analysis of the chip global to obtain the timing analysis result, which can not only maintain the efficiency of the static timing analysis to determine the violation path, but also can accurately perform dynamic simulation on these violation paths to accurately identify the real violation path. Further, the electronic device 1 provided in this embodiment can query all the violation paths in the target chip design, so as to facilitate the subsequent repair, so as to meet the sign-off requirements.

[0109] The second embodiment of the present application further provides a computer-readable storage medium, which stores a computer program A6. When the computer program A6 is executed by the processor A101, the steps of the circuit path detection method of the first embodiment are implemented, for example: Figure 1 Follow the steps shown in .

[0110] Optionally, the computer-readable storage medium provided by this embodiment may include any entity or device, recording medium that can carry computer program code, such as ROM, RAM, magnetic disk, optical disk, flash memory, etc.

[0111] The computer program A6 stored in the computer-readable storage medium provided in the second embodiment of the present application can provide a timing analysis method when executed by the processor A101, so as to efficiently and accurately complete the global timing analysis of the chip to obtain the timing analysis results, which can not only maintain the efficiency of static timing analysis to determine the violation path, but also can accurately perform dynamic simulation on these violation paths to accurately identify the true violation paths.

[0112] Optionally, in the embodiments of the electronic device and computer-readable storage medium provided in the present application, some or all of the technical features of the above-mentioned circuit path detection method are included, and the expanded and explained contents of the specification are basically the same as those of the embodiments of the above-mentioned method, and will not be repeated here.

[0113] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.

[0114] An embodiment of the present application also provides a detection chip, including a memory and a processor, the memory is used to store computer programs, and the processor is used to call and run the computer programs from the memory, so that a device equipped with the chip executes the methods in various possible implementation modes as described above.

[0115] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0116] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0117] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0118] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0119] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0120] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0121] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as above, and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, a controlled terminal, or a network device, etc.) to execute the method of each embodiment of the present application.

[0122] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a storage disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state storage disk Solid State Disk (SSD)), etc.

[0123] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A circuit path detection method, characterized in that: include: Performing static timing analysis on all timing paths of the chip globally to determine static analysis results of all timing paths, wherein the static analysis results include a first timing margin, a pin input conversion time, and / or a maximum accumulated delay time; Based on the first timing margin in the static analysis result, determining an object path among all the timing paths, wherein the first timing margin of the object path is less than a first preset threshold; Responsive to the simulation parameter settings, a dynamic simulation input file for each object path is obtained; Performing dynamic simulation analysis based on the dynamic simulation input file of each object path to determine the violation paths among all the object paths; The step of obtaining a dynamic simulation input file for each object path in response to the simulation parameter setting includes: Perform stimulus setting based on the pin input conversion time in the static analysis result to determine the starting input waveform in the dynamic simulation input file, and / or, determine the starting input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file; and / or, The simulation time is set based on the maximum cumulative delay time in the static analysis result to determine the simulation time in the dynamic simulation input file, wherein the simulation time is greater than the maximum cumulative delay time in the static analysis result.

2. The circuit path detection method according to claim 1, characterized in that: The step of performing static timing analysis on all timing paths of the chip globally and determining the static analysis results of all timing paths includes: Perform timing check on each timing path and calculate the cell delay and interconnection delay of each timing path; Based on the cell delay and the interconnection line delay of each timing path, a first timing margin in the static analysis result of each timing path is obtained.

3. The circuit path detection method according to claim 2, characterized in that: The timing check includes a setup time check, a hold time check, a recovery time check or a removal time check.

4. The circuit path detection method according to claim 3, characterized in that: The step of obtaining the first timing margin in the static analysis result of each timing path based on the unit delay and interconnection line delay of each timing path comprises: Based on the unit delay and interconnection line delay of each timing path, the data signal arrival time of each timing path and the first data required time that meets the setup time requirement or the second data required time that meets the hold time requirement are obtained; When the timing check is the setup time check, based on the difference between the first data requirement time and the data signal arrival time, a first timing margin in the static analysis result of each timing path is obtained; or, When the timing check is the hold time check, a first timing margin in the static analysis result of each timing path is obtained based on a difference between the data signal arrival time and the second data required time.

5. The circuit path detection method according to claim 1 or 3, characterized in that: The step of performing dynamic simulation analysis based on the dynamic simulation input file of each object path to determine the illegal paths among all the object paths comprises: Based on the dynamic simulation input file of each object path, a dynamic simulator is called to perform simulation to obtain dynamic simulation results; Based on the second timing margin in the dynamic simulation result of each object path, a violating path among all the object paths is determined, and the second timing margin of the violating path is less than a second preset threshold.

6. The circuit path detection method according to claim 1, characterized in that: The step of performing stimulus setting based on the pin input conversion time in the static analysis result to determine the starting point input waveform in the dynamic simulation input file, and / or determining the starting point input waveform in the dynamic simulation input file according to the port input conversion time set in the timing constraint file, comprises: Obtaining the initial conversion time of the starting point according to the pin input conversion time of the static analysis result, or obtaining the initial conversion time of the starting point according to the port input conversion time set in the timing constraint file; Based on the restriction parameters, the initial conversion time is modified to obtain the starting input conversion time, wherein the restriction parameters include a threshold value and an attenuation coefficient in the timing library; The start point input waveform is determined based on the start point input transition time.

7. The circuit path detection method according to claim 1, characterized in that: The maximum cumulative delay time in the static analysis result is the larger one between the data signal arrival time and the data request time.

8. The circuit path detection method according to claim 1, characterized in that: The first preset threshold is 0 or a positive value close to 0.

9. An electronic device, characterized in that: The electronic device comprises: a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the circuit path detection method according to any one of claims 1 to 8 is implemented.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the circuit path detection method according to any one of claims 1 to 8 is implemented.

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