Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. A timing controller is configured to generate a first compensation signal and a second compensation signal in time. The first compensation signal is configured to control a first source driver and a second source driver to load positive polarity data voltages and negative polarity data voltages to a plurality of first sub-pixels and a plurality of second sub-pixels in a first polarity sequence, respectively. The data voltages of the two polarities respectively include corresponding polarity compensation values. The second compensation signal is configured to control the first source driver to load the positive polarity data voltages and the negative polarity data voltages to the plurality of first sub-pixels in the first polarity sequence, and control the second source driver to load the positive polarity data voltages and the negative polarity data voltages to the plurality of second sub-pixels in a second polarity sequence. The second polarity sequence is opposite to the first polarity sequence. The compensation of the data voltages of different polarities is avoided from being reversed, so that the brightness difference is enlarged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to the manufacturing of display device, and more particularly to a display panel and a driving method thereof. BACKGROUND

[0002] An LCD (Liquid Crystal Display) display device controls the deflection of liquid crystal molecules in a liquid crystal layer to make the light of a backlight pass through the liquid crystal layer at a certain transmittance to realize picture display.

[0003] In a VRR (Variable Refresh Rate) mode, due to different leakage conditions of sub-sub-pixels under the action of positive and negative data voltages, compensation values need to be set for the two cases of positive and negative polarities, which is called VDF (VRR De-Flicker) compensation. In addition, in order to improve the influence of the capacitive coupling between the data line and the common electrode, the positive and negative polarities of adjacent two source drivers are set to be opposite, that is, the corresponding positive and negative polarities of the two are symmetrically set, which is called symmetric polarity inversion function. Therefore, if the symmetric polarity inversion function is adopted for the display panel, the polarity of some sub-sub-pixels will change, which will cause the VDF compensation value set originally to no longer be applicable to the polarity, thereby causing picture abnormality.

[0004] Therefore, the existing LCD display device has the above-mentioned picture abnormality problem, which needs to be improved. SUMMARY

[0005] The present application aims to provide a display panel and a driving method thereof to solve the technical problem of mismatch between VDF compensation value and polarity under the symmetric polarity inversion function in the existing LCD display device.

[0006] The present application provides a display panel, comprising:

[0007] a panel body having adjacent first and second display areas, the panel body comprising a plurality of sub-pixels, the plurality of sub-pixels comprising a plurality of first sub-pixels located in the first display area and a plurality of second sub-pixels located in the second display area, each of the sub-pixels being loaded with a corresponding positive polarity data voltage greater than or equal to a common voltage or a negative polarity data voltage less than or equal to the common voltage at the same gray scale value;

[0008] a plurality of source drivers comprising a first source driver and a second source driver, the first source driver being electrically connected to the plurality of first sub-pixels, and the second source driver being electrically connected to the plurality of second sub-pixels;

[0009] a timing controller electrically connected to the plurality of source drivers, configured to generate a first compensation signal and a second compensation signal in time sequence;

[0010] The first compensation signal is configured to control the first source driver and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels and the plurality of second sub-pixels in a first polarity sequence respectively, wherein the positive polarity data voltage comprises a positive polarity compensation value, and the negative polarity data voltage comprises a negative polarity compensation value.

[0011] The second compensation signal is configured to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity sequence, and control the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in a second polarity sequence, wherein the second polarity sequence is opposite to the first polarity sequence.

[0012] In some embodiments, the timing controller is configured to acquire a refresh rate of the display panel, and generate the first compensation signal or the second compensation signal according to the refresh rate.

[0013] In some embodiments, the timing controller is configured to determine whether the display panel is in a variable frequency state according to the refresh rate.

[0014] If the display panel is in the variable frequency state, the timing controller is configured to generate the first compensation signal.

[0015] If the display panel is in a fixed frequency state, the timing controller is configured to generate the second compensation signal.

[0016] In some embodiments, the timing controller comprises:

[0017] a determination module configured to generate a determination signal according to the refresh rate, wherein the determination signal has a first amplitude in the variable frequency state and has a second amplitude in the fixed frequency state;

[0018] a first compensation module configured to acquire the refresh rate and generate the first compensation signal when the display panel is in the variable frequency state, or configured to acquire the determination signal and generate the first compensation signal when the value of the determination signal is equal to the first amplitude;

[0019] a second compensation module configured to acquire the determination signal and generate the second compensation signal when the value of the determination signal is equal to the second amplitude.

[0020] In some embodiments, the starting time of the second compensation signal is later than the ending time of the corresponding first compensation signal, and the starting time of the first compensation signal is later than the ending time of the corresponding second compensation signal.

[0021] In some embodiments, the display panel further comprises:

[0022] a gamma voltage generator electrically connected to the plurality of source drivers, configured to transmit a plurality of gamma voltages to the source drivers;

[0023] The timing controller is configured to transmit the gray scale value corresponding to the sub-pixel to the source driver, and the source driver is configured to generate the positive polarity data voltage or the negative polarity data voltage corresponding to the gray scale value and the plurality of gamma voltages according to one of the first compensation signal and the second compensation signal.

[0024] The present application provides a driving method of a display panel, configured to drive the display panel as described in any of the above, comprising:

[0025] controlling the timing controller to generate the first compensation signal and the second compensation signal in time;

[0026] The first compensation signal is configured to control the first source driver and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels and the plurality of second sub-pixels in a first polarity sequence respectively, and the difference between the positive polarity data voltage and the common voltage is not equal to the difference between the common voltage and the negative polarity data voltage.

[0027] The second compensation signal is configured to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity sequence, and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in a second polarity sequence, and the difference between the positive polarity data voltage and the common voltage is equal to the difference between the common voltage and the negative polarity data voltage.

[0028] In some embodiments, the step of controlling the timing controller to generate the first compensation signal and the second compensation signal in time comprises:

[0029] controlling the timing controller to obtain a refresh rate of the display panel;

[0030] controlling the timing controller to generate the first compensation signal or the second compensation signal according to the refresh rate.

[0031] In some embodiments, the step of generating the first compensation signal or the second compensation signal according to the refresh rate comprises:

[0032] controlling the timing controller to determine whether the display panel is in the variable frequency state according to the refresh rate;

[0033] if the display panel is in the variable frequency state, controlling the timing controller to generate the first compensation signal;

[0034] if the display panel is in the fixed frequency state, controlling the timing controller to generate the second compensation signal.

[0035] In some embodiments, the timing controller comprises a determination module, a first compensation module and a second compensation module;

[0036] wherein the step of controlling the timing controller to determine whether the display panel is in the variable frequency state according to the refresh rate comprises:

[0037] controlling the determination module to generate a determination signal according to the refresh rate, the determination signal having a first amplitude in the variable frequency state and a second amplitude in the fixed frequency state;

[0038] wherein the step of controlling the timing controller to generate the first compensation signal comprises:

[0039] controlling the first compensation module to acquire the determination signal and generate the first compensation signal when the value of the determination signal is equal to the first amplitude;

[0040] wherein the step of controlling the timing controller to generate the second compensation signal comprises:

[0041] controlling the second compensation module to acquire the determination signal and generate the second compensation signal when the value of the determination signal is equal to the second amplitude.

[0042] The application provides a display panel and a driving method thereof. A plurality of sub-pixels in a panel body include a plurality of first sub-pixels in a first display area and a plurality of second sub-pixels in a second display area. A timing controller is configured to generate a first compensation signal and a second compensation signal in time. The first compensation signal is configured to control the first source driver and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels and the plurality of second sub-pixels in a first polarity sequence, respectively. The positive polarity data voltage includes a positive polarity compensation value, and the negative polarity data voltage includes a negative polarity compensation value. The second compensation signal is configured to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity sequence, and control the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in a second polarity sequence. The second polarity sequence is opposite to the first polarity sequence. The first compensation signal and the second compensation signal are applied to the plurality of source drivers, respectively, so as to avoid the compensation of the data voltage of different polarities from being reversed, thereby improving the brightness difference and abnormal picture. BRIEF DESCRIPTION OF DRAWINGS

[0043] The application will be further described below with reference to the drawings. It should be noted that the drawings described below are only used to explain some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0044] Figure 1 A top view of the display panel provided by the embodiment of the application.

[0045] Figure 2 A module diagram of the source driver provided by the embodiment of the application.

[0046] Figure 3 A waveform diagram of part of signals in the display panel provided by the embodiment of the application.

[0047] Figure 4 A flowchart of the driving method of the display panel provided by the embodiment of the application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative effort fall within the protection scope of the application.

[0049] In the description of the application, the terms "first", "second", etc. are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In addition, it should be noted that the drawings provided are only relatively close to the structure of the application, and some details that are not closely related to the application are omitted, the purpose is to simplify the drawings, make the invention points clear at a glance, and not as a limitation of the actual device. Figure 1 The actual device is not limited as the same.

[0050] In this paper, the "embodiment" means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the application. The phrase appears at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is not mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0051] The application provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0052] In some embodiments, as Figure 1As shown, the display panel 100 comprises: a panel body 10 having a first display area A1 and a second display area A2 adjacent to each other, a plurality of sub-pixels and a common electrode (not shown) having a common voltage Vcom, the plurality of sub-pixels comprising a plurality of first sub-pixels 1021 located in the first display area A1 and a plurality of second sub-pixels 1022 located in the second display area A2, each of the sub-pixels loading a positive polarity data voltage Vd+ greater than or equal to the common voltage Vcom or a negative polarity data voltage Vd- less than or equal to the common voltage Vcom at the same gray scale value; a plurality of source drivers comprising a first source driver 201 and a second source driver 202, the first source driver 201 being electrically connected to the plurality of first sub-pixels 1021, and the second source driver 202 being electrically connected to the plurality of second sub-pixels 1022; a timing controller 301 electrically connected to the plurality of source drivers, for generating a first compensation signal Vb1 and a second compensation signal Vb2 in time; wherein the first compensation signal Vb1 is used to control the first source driver 201 and the second source driver 202 to load the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- to the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 respectively in a first polarity sequence, the positive polarity data voltage Vd+ comprising a positive polarity compensation value, and the negative polarity data voltage Vd- comprising a negative polarity compensation value; wherein the second compensation signal Vb2 is used to control the first source driver 201 to load the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- to the plurality of first sub-pixels 1021 in the first polarity sequence, and control the second source driver 202 to load the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- to the plurality of second sub-pixels 1022 in a second polarity sequence opposite to the first polarity sequence.

[0053] wherein, as Figure 1As shown, the panel body 10 can be divided into at least a plurality of display areas (including the first display area A1 and the second display area A2) arranged along a first direction D1, and a plurality of sub-pixels (including a plurality of first sub-pixels 1021 and a plurality of second sub-pixels 1022) arranged along the first direction D1 and a second direction D2. For ease of description, the first direction D1 and the second direction D2 are taken as the row direction and the column direction, respectively. The panel body 10 can further include a plurality of gate lines 101 and a plurality of data lines (including a plurality of first data lines 1031 and a plurality of second data lines 1032). Each gate line 101 is located in a same row of the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022. Each first data line 1031 can be electrically connected to a same column of the plurality of first sub-pixels 1021. Each second data line 1032 can be electrically connected to a same column of the plurality of second sub-pixels 1022.

[0054] Of course, the plurality of display areas can further include a third display area A3 and a fourth display area A4 along the first direction D1, and the plurality of source drivers can further include a third source driver 203 for controlling the third display area A3 to emit light and a fourth source driver 204 for controlling the fourth display area A4 to emit light. The first display area A1 and the second display area A2 in the embodiment of the present application can be replaced by any two of the plurality of display areas, and the first source driver 201 and the second source driver 202 can also be replaced accordingly.

[0055] The plurality of source drivers can be fixed to the panel body 10 by COF (Chip On Flex) technology, but are not limited thereto. The display panel 100 can further include a main board 30 electrically connected to the plurality of source drivers and the panel body 10. The main board 30 can include the timing controller 301 and the power manager 302 electrically connected thereto. The power manager 302 is configured to provide respective working voltages for the plurality of source drivers and the timing controller 301.

[0056] In the same gray scale value, each of the sub-pixels is loaded with a positive polarity data voltage Vd+ greater than or equal to the common voltage Vcom or a negative polarity data voltage Vd- less than or equal to the common voltage Vcom. This can be understood as each of the sub-pixels being loaded with a corresponding "positive polarity data voltage Vd+" (both polarities being positive) or a "negative polarity data voltage Vd-" (both polarities being negative) corresponding to the gray scale value. In this case, the first data line 1031 can be understood as being electrically connected to the sub-pixel, and the second data line 1032 can also be understood in the same way.

[0057] It should be noted that the first sub-pixel 1021 and the second sub-pixel 1022 discussed above are different in that the source driver to which they are electrically connected is different, so that they can work in different orders of polarity, and both have their own positive polarity data voltage Vd+ and negative polarity data voltage Vd-. Among them, without considering the difference in leakage between the two, etc., the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- of each of the two can theoretically not have corresponding polarity compensation values (positive polarity compensation value, negative polarity compensation value), that is, the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- of each of them must be symmetric about the common voltage; according to this understanding, when the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 are respectively loaded with the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- in different orders of polarity, the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- of each of the two at this time have corresponding polarity compensation values (positive polarity compensation value, negative polarity compensation value), that is, at this time the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- of each of them are obtained after being compensated by the respective polarity compensation values.

[0058] Among them, when the colors of the first sub-pixel 1021 and the second sub-pixel 1022 are the same, then in the above “the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 are respectively loaded with the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- in different orders of polarity”, it can be considered that the polarity compensation values (positive polarity compensation value, negative polarity compensation value) of the two are at least set according to the respective leakage differences and other reasons.

[0059] Specifically, as shown in Figure 1 At the same gray scale value, it can be considered that the main board 30 sends the gray scale value GM corresponding to each sub-pixel to each source driver, and each source driver can also receive the first compensation signal Vb1 and the second compensation signal Vb2 issued by the timing controller 301 in time. At each moment, each source driver generates the positive polarity data voltage Vd+ or the negative polarity data voltage Vd- corresponding to the gray scale value GM according to one of the first compensation signal Vb1 and the second compensation signal Vb2 and the gray scale value GM, to act on the plurality of sub-pixels, some of which are loaded with the corresponding positive polarity data voltage Vd+, and some of which are loaded with the corresponding negative polarity data voltage Vd-.

[0060] The first polarity sequence and the second polarity sequence are two opposite polarity sequences of data voltages loaded on the multiple columns of sub-pixels in the same display area from left to right, for example, the polarity sequence of the first polarity sequence can be "+, -, +, -, +, -... ", that is, the corresponding multiple columns of sub-pixels can be loaded with Vd+, Vd-, Vd+, Vd-... from left to right, and for example, the polarity sequence of the second polarity sequence can be "-, +, -, +, -, +... ", that is, the corresponding multiple columns of sub-pixels can be loaded with Vd-, Vd+, Vd-, Vd+... from left to right.

[0061] Further, the display panel 100 can be a liquid crystal display panel. The panel body 10 can include an array substrate and a color film substrate arranged opposite to each other, the multiple sub-pixels, the multiple gate lines and the multiple data lines can be located in the array substrate, and the common electrode can be located in the array substrate or the color film substrate. It can be considered that the luminous brightness of the sub-pixel is positively or negatively correlated with the absolute value of the difference between the corresponding positive polarity data voltage or negative polarity data voltage and the common voltage loaded on the common electrode. If other problems are not considered, it can be considered that the luminous brightness is the same when the sub-pixel respectively loads the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- symmetrical to the common voltage. In the present application, for the purpose of comparison, the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- are set to correspond to the same gray scale, that is, without considering other problems, the two are theoretically symmetrical to the common voltage.

[0062] However, if the difference in characteristics of the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- is considered in other problems, the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- symmetrical to the common voltage may have different luminance when acting on the same sub-pixel, at this time, it may be necessary to set the two to respectively include positive polarity compensation value and negative polarity compensation value, further, the two can be compensated by the corresponding compensation value, at this time, the two can only achieve the same luminance when acting on the same sub-pixel.

[0063] Wherein, it is not limited here whether the positive polarity compensation value and the negative polarity compensation value of the same sub-pixel at the same gray scale value are the same, for example, if the display panel 100 is only affected by a single factor, then the positive polarity compensation value and the negative polarity compensation value can be different (then the difference between the positive polarity data voltage Vd+ and the common voltage Vcom is not equal to the difference between the common voltage Vcom and the negative polarity data voltage Vd-), for another example, the display panel 100 can also be affected by multiple factors, at this time, there is a case of offsetting multiple factors, causing the positive polarity compensation value and the negative polarity compensation value can be the same (the difference between the positive polarity data voltage Vd+ and the common voltage Vcom is equal to the difference between the common voltage Vcom and the negative polarity data voltage Vd-).

[0064] In summary, it can be considered that the absolute value of the difference between the positive polarity compensation value and the negative polarity compensation value and the common voltage is related to the polarity of the two, that is, whether the positive polarity data voltage includes the positive polarity compensation value and the negative polarity data voltage includes the negative polarity compensation value is related to the polarity of the two, and the source driver generally processes the corresponding gray scale value GM according to the polarity order (which can be considered as the first polarity order described above) of the plurality of sub-pixels to generate the positive polarity compensation value or the negative polarity compensation value in the corresponding order to generate the positive polarity data voltage Vd+ or the negative polarity data voltage Vd- in the corresponding order, and loads it to the plurality of columns of sub-pixels in the preset polarity order. The above "processing" can be understood as generating Vd+ in the positive polarity direction with the positive polarity compensation value and generating Vd- in the negative polarity direction with the negative polarity compensation value based on the common voltage. The sign of the positive polarity compensation value and the sign of the negative polarity compensation value correspond to the polarity. It can be considered that the former is greater than 0 and the latter is less than 0. The difference with the common voltage is different, for example, when the gray scale value GM is 32, the corresponding positive polarity compensation value and negative polarity compensation value can be 8 and (-4) respectively. The corresponding positive polarity gray scale value (corresponding to Vd+) and negative polarity gray scale value (corresponding to Vd-) are (+40) = +(32+8) and (-28) = -(32+(-4)) respectively.

[0065] Wherein, the positive polarity compensation value and the negative polarity compensation value only represent that the two respectively generate the positive polarity gray scale value and the negative polarity gray scale value with the gray scale value GM, and do not limit the positive and negative of the two themselves. If it is positive, it means that the compensated positive / negative polarity gray scale value is farther away from the gray scale value 0. If it is negative, it means that the compensated positive / negative polarity gray scale value is closer to the gray scale value 0.

[0066] Further, as Figure 1As shown, the display panel 100 further comprises a gamma voltage generator 303 electrically connected to the plurality of source drivers, configured to transmit a plurality of gamma voltages VG to the source drivers; wherein the timing controller 301 is configured to transmit the gray scale value GM corresponding to the sub-pixel to the source driver, and the source driver is configured to generate the positive polarity data voltage Vd+ or the negative polarity data voltage Vd- according to one of the first compensation signal Vb1 and the second compensation signal Vb2, the gray scale value GM and the plurality of gamma voltages VG.

[0067] The plurality of gamma voltages VG can correspond to all values of the gray scale value GM one by one. It can be understood that the corresponding positive polarity gray scale value or negative polarity gray scale value is determined according to one of the first compensation signal Vb1 and the second compensation signal Vb2 and the gray scale value GM, and then the corresponding gamma voltage VG corresponding to the absolute value of the positive polarity gray scale value or the negative polarity gray scale value is obtained as the absolute value of the corresponding Vd+ or Vd-, and then the corresponding positive or negative sign is added to form the corresponding Vd+ or Vd-.

[0068] Specifically, in the present application, the timing controller 301 is configured to generate the first compensation signal Vb1 and the second compensation signal Vb2 in time sharing mode, and input the first compensation signal Vb1 or the second compensation signal Vb2 to each source driver (including the first source driver 201 and the second source driver 202) at the same time, so that the working of the plurality of source drivers has the following two corresponding modes:

[0069] In mode 1, the first compensation signal Vb1 is generated and can be transmitted to the first source driver 201 and the second source driver 202 at the same time to control both to drive the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 in the first polarity order respectively, that is, the plurality of columns of first sub-pixels 1021 are loaded with Vd+, Vd-, Vd+, Vd-… from left to right in turn, and the plurality of columns of second sub-pixels 1022 are also loaded with Vd+, Vd-, Vd+, Vd-… from left to right in turn. At this time, the positive polarity data voltage Vd+ includes a positive polarity compensation value, and the negative polarity data voltage Vd- includes a negative polarity compensation value. It can be understood that the positive polarity data voltage Vd+ is generated according to the corresponding positive polarity compensation value, and the negative polarity data voltage Vd- is generated according to the corresponding negative polarity compensation value. At this time, if only the influence of a single factor on the display panel 100 is considered, the Vd+, Vd- that are not symmetrical with respect to the above-mentioned common voltage (i.e., the difference between the positive polarity data voltage Vd+ and the common voltage Vcom is not equal to the difference between the common voltage Vcom and the negative polarity data voltage Vd-) can be used to act on the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 to counteract the influence of this single factor. That is, the absolute values of the differences between Vd+ and Vd- and the common voltage Vcom loaded by adjacent two first sub-pixels 1021 are not equal, and the absolute values of the differences between Vd+ and Vd- and the common voltage Vcom loaded by adjacent two second sub-pixels 1022 are also not equal.

[0070] It can be understood that in mode 1, the positive polarity compensation values and the negative polarity compensation values stored by the source driver are originally arranged in the first polarity order, which is defined for generating Vd+ and Vd- in turn, and the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022 are also driven in the first polarity order, so that the positive polarity compensation values and the negative polarity compensation values are also utilized in the first polarity order, that is, the order of utilization is consistent with the originally defined order, so that the finally generated Vd+ and Vd- are accurate.

[0071] Mode 2, the second compensation signal Vb2 is generated and can be transmitted to the first source driver 201 and the second source driver 202 at the same time, to control the former to drive the plurality of first sub-pixels 1021 to work in the first polarity sequence, and the latter to drive the plurality of second sub-pixels 1022 to work in the second polarity sequence (opposite to the first polarity sequence), that is, the plurality of columns of first sub-pixels 1021 are sequentially loaded with Vd+, Vd-, Vd+, Vd-… from left to right, and the plurality of columns of second sub-pixels 1022 are sequentially loaded with Vd-, Vd+, Vd-, Vd+… from left to right, at this time, it can be considered that the positive polarity data voltage Vd+ does not include a positive polarity compensation value, and the negative polarity data voltage Vd- also does not include a negative polarity compensation value, that is, the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- are both compensated, and it can be considered that they are symmetrical about the common voltage, that is, at this time, the Vd+ and Vd- symmetrical about the common voltage (that is, "the difference between the positive polarity data voltage Vd+ and the common voltage Vcom is equal to the difference between the common voltage Vcom and the negative polarity data voltage Vd-") are used to act on the plurality of first sub-pixels 1021 and the plurality of second sub-pixels 1022, that is, the absolute values of the differences between Vd+ and Vcom and Vd- and Vcom loaded by two adjacent first sub-pixels 1021 are equal, and the absolute values of the differences between Vd+ and Vcom and Vd- and Vcom loaded by two adjacent second sub-pixels 1022 are also equal.

[0072] It should be noted that the positive polarity compensation value and the negative polarity compensation value stored by the second source driver 202 in mode 2 are still defined as being used to sequentially generate Vd+ and Vd-, at this time, if only one-sided factors are considered to affect the display panel 100, that is, the absolute values of the differences between Vd+ and Vcom and Vd- and Vcom are not equal, then because the plurality of second sub-pixels 1022 are driven in the second polarity sequence (opposite to the preset polarity sequence), the positive polarity compensation value and the negative polarity compensation value are also used in the second polarity sequence, that is, the sequence used is opposite to the sequence defined originally, so that the finally generated Vd+ and Vd- are wrong; here, taking "gray scale value GM" as 32 as an example, the positive polarity compensation value (for example, 8) is used to generate a negative polarity gray scale value of -(32+8)=(-40), and the negative polarity compensation value (for example, (-4)) is used to generate a positive polarity gray scale value of +(32+(-4))=(+28), resulting in that the finally generated Vd+ and Vd- are both wrong, which is specifically manifested as that the compensation directions are opposite, causing the brightness difference corresponding to Vd+ and Vd- to be further expanded, and the brightness of the second display area A2 is abnormal.

[0073] Therefore, in mode 2 of the present invention, considering that the plurality of second sub-pixels 1022 operate in a second polarity order (different from the preset polarity order), Vd+ and Vd- are set to be symmetrical about the common voltage, that is, the corresponding positive polarity compensation value and negative polarity compensation value are equal (the signs and absolute values ​​are the same). Taking the "grayscale value GM" as b as an example, even if the "positive polarity compensation value originally corresponding to Vd+ (for example, a) is used to generate a negative polarity grayscale value (corresponding to Vd-), and the negative polarity compensation value originally corresponding to Vd- (for example, a) is used to generate a positive polarity grayscale value (corresponding to Vd +)", the compensated negative polarity grayscale value and positive polarity grayscale value are -(b+a)=(-ba) and +(b+a)=(b+a), respectively. That is, the absolute values ​​of the differences between the compensated negative polarity grayscale value and the positive polarity grayscale value and the grayscale value 0 are the same, so that the generated Vd+ and Vd- are symmetrical about the above-mentioned common voltage. Although this cannot improve the brightness difference caused by the "characteristic difference between the positive polarity data voltage Vd+ and the negative polarity data voltage Vd-", it will at least not cause the brightness difference corresponding to Vd+ and Vd- to be further expanded (that is, reverse compensation can be avoided).

[0074] In some embodiments, as Figure 1 As shown, the timing controller 301 is used to obtain the refresh rate of the display panel 100 and generate the first compensation signal Vb1 or the second compensation signal Vb2 based on the refresh rate. In conjunction with the above discussion of "Taking into account the characteristic differences between the positive polarity data voltage Vd+ and the negative polarity data voltage Vd- in other issues, it is possible that the positive polarity data voltage Vd+ and the negative polarity data voltage Vd-, which are symmetrical about a common voltage, may act on the same sub-pixel to produce different brightnesses," the "other issues" here can be understood as the different leakage times of the display panel 100 at different refresh rates. At least at some refresh rates, corresponding compensation values ​​need to be set to compensate for the brightness loss caused by this leakage. Furthermore, because the leakage conditions of sub-pixels under the positive and negative polarity data voltages at the same grayscale are different, separate compensation values ​​need to be set for both, that is, different positive polarity compensation values ​​and negative polarity grayscale values ​​are set to improve the brightness difference caused by the refresh rate difference and the difference between the positive and negative polarity data voltages.

[0075] Among them, the above-mentioned technology of "the leakage conditions of sub-pixels under the positive polarity and negative polarity data voltages at the same grayscale are different, and the compensation values ​​of the two need to be set separately" can be called VDF compensation function, and "the polarity order of the first source driver 201 and the second source driver 202 for their respective sub-pixels is opposite" can be called "symmetrical polarity inversion function".

[0076] According to the above description, in mode 1, the first compensation signal Vb1 controls that the absolute value of the difference between Vd+ and Vd- and the common voltage Vcom is not equal (i.e., the VDF compensation function is turned on), and controls the first source driver 201 and the second source driver 202 to drive the first sub-pixels 1021 and the second sub-pixels 1022 in the first polarity sequence respectively (i.e., the symmetric polarity inversion function is turned off); in mode 2, the second compensation signal Vb2 controls that the polarity sequence of the first source driver 201 and the second source driver 202 for driving the respective sub-pixels is opposite (i.e., the symmetric polarity inversion function is turned on), and controls that the absolute value of the difference between Vd+ and Vd- and the common voltage Vcom is equal (i.e., the VDF compensation function is turned off).

[0077] Based on this, as shown in FIG. 3, the timing controller 301 is configured to determine whether the display panel 100 is in the variable frequency state according to the refresh rate; if the display panel 100 is in the variable frequency state, the timing controller 301 is configured to generate the first compensation signal Vb1; if the display panel 100 is in the fixed frequency state, the timing controller 301 is configured to generate the second compensation signal Vb2. Figure 1

[0078] The judgment of the variable frequency state and the fixed frequency state can be based on the values of the plurality of refresh rates corresponding to the plurality of continuously arranged frames, for example, the number of frames with continuously changing refresh rates can be first determined whether it reaches a first preset value, if it reaches, the total amplitude of the refresh rate changing in the corresponding plurality of frames is further determined whether it reaches a second preset value, if it reaches, it is considered to be in the variable frequency state, otherwise it is in the fixed frequency state.

[0079] According to the above description, in the variable frequency state, the timing controller 301 generates the first compensation signal Vb1 to control the display panel 100 to work in mode 1 to improve the brightness difference caused by the difference in refresh rate and the difference in positive polarity and negative polarity data voltage; in the fixed frequency state, the timing controller 301 generates the second compensation signal Vb2 to control the display panel 100 to work in mode 2 to avoid the brightness difference in the second display area A2 caused by Vd+ and Vd- (i.e., reverse compensation can be avoided).

[0080] ​It is understandable that the human eye is generally concerned about the crosstalk problem caused by the "capacitive coupling effect between the data line and the common electrode" in the fixed frequency state. Therefore, the second compensation signal Vb2 generated in the fixed frequency state in the present invention is used to control the display panel 100 to operate in mode 2, that is, to turn on the "symmetrical polarity inversion function" and turn off the VDF compensation function; and the human eye is generally concerned about the flicker problem caused by the "different leakage conditions of sub-pixels under the action of positive and negative polarity data voltages in VRR mode" in the variable frequency state. Therefore, the first compensation signal Vb1 generated in the variable frequency state in the present invention is used to control the display panel 100 to operate in mode 1, that is, to turn on the VDF compensation function and turn off the "symmetrical polarity inversion function".

[0081] In summary, the time-sharing control of the display panel 100 in the present invention to operate in mode 1 and mode 2 can not only greatly improve the crosstalk problem and flicker problem, but also avoid the simultaneous activation of the "symmetrical polarity inversion function" and the VDF compensation function, thereby avoiding the compensation error of data voltages of different polarities, which leads to further expansion of the brightness difference.

[0082] In some embodiments, combined Figure 2 and Figure 3 As shown, the timing controller 301 includes: a judgment module 3011, configured to generate a judgment signal A according to the refresh rate f, wherein the judgment signal A has a first amplitude V1 in the variable frequency state and a second amplitude V2 in the fixed frequency state; a first compensation module 3012, configured to obtain the refresh rate f and generate the first compensation signal Vb1 ( Figure 2 This embodiment is not shown), or is used to obtain the judgment signal A and generate the first compensation signal Vb1 when the value of the judgment signal A is equal to the first amplitude V1; a second compensation module 3013 is used to obtain the judgment signal A and generate the second compensation signal Vb2 when the value of the judgment signal A is equal to the second amplitude V2.

[0083] The amplitudes of the first compensation signal Vb1 and the second compensation signal Vb2 can also be different constant values, which are transmitted to each source driver for identification and determination of whether the display panel 100 is in a variable frequency state or a fixed frequency state. The relationship between the first amplitude V1 and the second amplitude V2 in the determination signal A is also not limited. The purpose is to enable the first compensation module 3012 and the second compensation module 3013 to identify whether the display panel 100 is in a variable frequency state or a fixed frequency state, thereby determining whether to generate the first compensation signal Vb1 or the second compensation signal Vb2.

[0084] Figure 3The waveform of polc in FIG. 6 can represent the effective working period (corresponding to high amplitude) and the invalid working period (corresponding to low amplitude) of the "symmetrical polarity inversion function", and the waveform of vdf can represent the effective working period (corresponding to high amplitude) and the invalid working period (corresponding to low amplitude) of the "VDF compensation function", and does not mean that there are two corresponding signals. It can be observed from FIG. 6 that the first compensation signal Vb1 exists in the high amplitude period of the waveform of vdf, and the second compensation signal Vb2 exists in the high amplitude period of the waveform of polc, but the amplitudes of the two are not necessarily the same as the high amplitude of the waveform of vdf and the high amplitude of the waveform of polc. Figure 3 It can be observed from FIG. 6 that the first compensation signal Vb1 exists in the high amplitude period of the waveform of vdf, and the second compensation signal Vb2 exists in the high amplitude period of the waveform of polc, but the amplitudes of the two are not necessarily the same as the high amplitude of the waveform of vdf and the high amplitude of the waveform of polc.

[0085] Specifically, as shown in FIG. 6, the first compensation signal Vb1 is generated in the high amplitude period of the waveform of vdf, and the second compensation signal Vb2 is generated in the high amplitude period of the waveform of polc. Figure 2 and Figure 3 It can be observed from FIG. 6 that the first compensation signal Vb1 exists in the high amplitude period of the waveform of vdf, and the second compensation signal Vb2 exists in the high amplitude period of the waveform of polc, but the amplitudes of the two are not necessarily the same as the high amplitude of the waveform of vdf and the high amplitude of the waveform of polc.

[0086] The present application provides a driving method of a display panel, which is used for driving the display panel as described in any of the above embodiments, and can include but is not limited to the following embodiments and combinations of the following embodiments.

[0087] In some embodiments, the driving method can include but is not limited to the following steps:

[0088] S1, controlling the time sequence controller to generate the first compensation signal and the second compensation signal in time.

[0089] The first compensation signal is used to control the first source driver and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels and the plurality of second sub-pixels in a first polarity sequence respectively, and the difference between the positive polarity data voltage and the common voltage is not equal to the difference between the common voltage and the negative polarity data voltage.

[0090] The second compensation signal is used for controlling the first source driver to sequentially load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity, and the second source driver to sequentially load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in the second polarity, wherein a difference between the positive polarity data voltage and the common voltage is equal to a difference between the common voltage and the negative polarity data voltage.

[0091] Specific details can be referred to the relevant discussion above.

[0092] In some embodiments, as shown in Figure 4 The step S1 can include but is not limited to the following steps:

[0093] S11, controlling the timing controller to acquire a refresh rate of the display panel.

[0094] S12, controlling the timing controller to generate the first compensation signal or the second compensation signal according to the refresh rate.

[0095] Specific details can be referred to the relevant discussion above.

[0096] In some embodiments, the step S12 can include but is not limited to the following steps:

[0097] S121, controlling the timing controller to determine whether the display panel is in a variable frequency state according to the refresh rate.

[0098] If the display panel is in the variable frequency state, then:

[0099] S122, controlling the timing controller to generate the first compensation signal.

[0100] If the display panel is in a fixed frequency state, then:

[0101] S123, controlling the timing controller to generate the second compensation signal.

[0102] Specific details can be referred to the relevant discussion above.

[0103] In some embodiments, the timing controller includes a determination module, a first compensation module and a second compensation module.

[0104] The step S121 can include but is not limited to the following steps:

[0105] S1210, controlling the determination module to generate a determination signal according to the refresh rate, the determination signal having a first amplitude in the variable frequency state and a second amplitude in the fixed frequency state.

[0106] The step S122 can include but is not limited to the following steps:

[0107] S120, controlling the first compensation module to acquire the judgment signal and generate the first compensation signal when the value of the judgment signal is equal to the first amplitude;

[0108] The step S123 can include but is not limited to the following steps:

[0109] S1230, controlling the second compensation module to acquire the judgment signal and generate the second compensation signal when the value of the judgment signal is equal to the second amplitude.

[0110] Specific details can be referred to the relevant discussion above.

[0111] The display panel and the driving method thereof are provided, the plurality of sub-pixels in the panel body include a plurality of first sub-pixels located in a first display area and a plurality of second sub-pixels located in a second display area (the color of the second sub-pixels is different from the color of the first sub-pixels), a timing controller is used to generate a first compensation signal and a second compensation signal in time, the first compensation signal is used to control the first source driver and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels and the plurality of second sub-pixels respectively in a first polarity sequence, the positive polarity data voltage includes a positive polarity compensation value, the negative polarity data voltage includes a negative polarity compensation value, the second compensation signal is used to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity sequence, and control the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in a second polarity sequence, the second polarity sequence is opposite to the first polarity sequence, the first compensation signal and the second compensation signal are used to act on the plurality of source drivers respectively, the compensation of the data voltage of different polarities is avoided from being reversed to cause the brightness difference to expand, and the picture abnormality is improved.

[0112] The display panel and the driving method thereof provided by the embodiments of the present application are introduced in detail above, the principle and the implementation mode of the present application are described by applying specific examples in this paper, the above embodiment description is only used to help understand the technical scheme and the core idea of the present application; the person skilled in the art should understand that: the technical scheme recorded in the foregoing embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A panel body having a first display area and a second display area adjacent to each other, the panel body including a plurality of sub-pixels, the plurality of sub-pixels including a plurality of first sub-pixels located in the first display area and a plurality of second sub-pixels located in the second display area, wherein at the same grayscale value, each of the sub-pixels is respectively loaded with a corresponding positive polarity data voltage greater than or equal to a common voltage, or a negative polarity data voltage less than or equal to the common voltage; a plurality of source drivers, including a first source driver and a second source driver, wherein the first source driver is electrically connected to the plurality of the first sub-pixels, and the second source driver is electrically connected to the plurality of the second sub-pixels; a timing controller, electrically connected to the plurality of source drivers, for generating a first compensation signal and a second compensation signal in a time-sharing manner; The first compensation signal is used to control the first source driver and the second source driver to apply the positive polarity data voltage and the negative polarity data voltage to the first sub-pixels and the second sub-pixels in a first polarity order, respectively, wherein the positive polarity data voltage includes a positive polarity compensation value and the negative polarity data voltage includes a negative polarity compensation value; In which, the second compensation signal is used to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of the first sub-pixels in the first polarity sequence, and to control the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of the second sub-pixels in a second polarity sequence, and the second polarity sequence is opposite to the first polarity sequence.

2. The display panel according to claim 1, wherein The timing controller is used to obtain a refresh rate of the display panel and generate the first compensation signal or the second compensation signal according to the refresh rate.

3. The display panel according to claim 2, wherein: The timing controller is used to determine whether the display panel is in a variable frequency state according to the refresh rate; If the display panel is in a variable frequency state, the timing controller is configured to generate the first compensation signal; If the display panel is in a fixed frequency state, the timing controller is configured to generate the second compensation signal.

4. The display panel according to claim 3, wherein: The timing controller includes: A judgment module, configured to generate a judgment signal according to the refresh rate, wherein the judgment signal has a first amplitude in the variable frequency state and a second amplitude in the fixed frequency state; a first compensation module, configured to obtain the refresh rate and generate the first compensation signal when the display panel is in the variable frequency state, or to obtain the determination signal and generate the first compensation signal when the value of the determination signal is equal to the first amplitude; The second compensation module is configured to obtain the judgment signal and generate the second compensation signal when the value of the judgment signal is equal to the second amplitude.

5. The display panel according to claim 3 or 4, wherein: The start time of the second compensation signal is later than the end time of the corresponding first compensation signal, and the start time of the first compensation signal is later than the end time of the corresponding second compensation signal.

6. The display panel according to claim 1, wherein: Also includes: a gamma voltage generator, electrically connected to the plurality of source drivers, for transmitting a plurality of gamma voltages to the source drivers; In which, the timing controller is used to transmit the grayscale value corresponding to the sub-pixel to the source driver, and the source driver is used to generate the corresponding positive polarity data voltage or the negative polarity data voltage according to one of the first compensation signal and the second compensation signal, the grayscale value and the multiple gamma voltages.

7. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 6, comprising: Controlling the timing controller to generate the first compensation signal and the second compensation signal in a time-sharing manner; The first compensation signal is used to control the first source driver and the second source driver to apply the positive polarity data voltage and the negative polarity data voltage to the first sub-pixels and the second sub-pixels respectively in a first polarity sequence, and the difference between the positive polarity data voltage and the common voltage is not equal to the difference between the common voltage and the negative polarity data voltage; In which, the second compensation signal is used to control the first source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of first sub-pixels in the first polarity sequence, and the second source driver to load the positive polarity data voltage and the negative polarity data voltage to the plurality of second sub-pixels in the second polarity sequence, and the difference between the positive polarity data voltage and the common voltage is equal to the difference between the common voltage and the negative polarity data voltage.

8. The method for driving a display panel according to claim 7, wherein: The step of controlling the timing controller to generate the first compensation signal and the second compensation signal in a time-sharing manner includes: Controlling the timing controller to obtain a refresh rate of the display panel; The timing controller is controlled to generate the first compensation signal or the second compensation signal according to the refresh rate.

9. The method for driving a display panel according to claim 8, wherein: The step of generating the first compensation signal or the second compensation signal according to the refresh rate includes: Controlling the timing controller to determine whether the display panel is in a variable frequency state according to the refresh rate; If the display panel is in a variable frequency state, controlling the timing controller to generate the first compensation signal; If the display panel is in a fixed frequency state, the timing controller is controlled to generate the second compensation signal.

10. The method for driving a display panel according to claim 9, wherein: The timing controller includes a judgment module, a first compensation module and a second compensation module; The step of controlling the timing controller to determine whether the display panel is in a variable frequency state according to the refresh rate includes: Controlling the judgment module to generate a judgment signal according to the refresh rate, wherein the judgment signal has a first amplitude in the variable frequency state and a second amplitude in the fixed frequency state; The step of controlling the timing controller to generate the first compensation signal includes: controlling the first compensation module to obtain the judgment signal and generate the first compensation signal when the value of the judgment signal is equal to the first amplitude; Wherein, the step of controlling the timing controller to generate the second compensation signal includes: The second compensation module is controlled to obtain the judgment signal and generate the second compensation signal when the value of the judgment signal is equal to the second amplitude.

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