Encapsulation substrate and method for manufacturing the same

Abstract

The present invention provides an encapsulation substrate and a manufacturing method thereof. The encapsulation substrate includes disposing a circuit block on a substrate body through a bonding layer, then coating the circuit block with a coating layer, and then forming a circuit portion on the coating layer and forming conductive columns in the coating layer. Therefore, without making grooves, the circuit block can be buried in the coating layer, so the encapsulation substrate of the present invention can reduce the process time.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and particularly to a packaging substrate for carrying semiconductor chips and a manufacturing method thereof. Background Art

[0002] With the increasing demand for the functions and processing speeds of electronic products, the technologies currently applied in the field of chip packaging have also increased. For example, there are flip-chip type packaging modules such as Chip Scale Package (CSP for short), Direct Chip Attached (DCA for short), and Multi-Chip Module (MCM for short), or the technology of stacking chips three-dimensionally to integrate them into a three-dimensional integrated circuit (3D IC) chip stack technology, etc.

[0003] In order to meet the different electrical and functional requirements of semiconductor chips, the packaging substrate for carrying semiconductor chips can be configured with circuit layers of different specifications (such as line width / line pitch).

[0004] Figure 1A FIG. is a cross-sectional schematic view of a conventional packaging substrate 1a. As Figure 1A shown, the packaging substrate 1a includes: a core layer 10 having a plurality of conductive vias 100, an interposer circuit structure 11 disposed on the core layer 10 and electrically connected to the conductive vias 100, and at least one circuit block 12 disposed on the interposer circuit structure 11. The interposer circuit structure 11 is formed with a groove 110 for accommodating the circuit block 12 and enabling the circuit block 12 to be electrically connected to the interposer circuit structure 11 through a plurality of conductive bumps 120. Among them, the wiring specification of the circuit block 12 is different from that of the interposer circuit structure 11.

[0005] In the conventional packaging substrate 1a, the wiring specification adopted by the circuit block 12 is a smaller line width / line pitch (L / S), such as 2 micrometers (um), while the wiring specification adopted by the interposer circuit structure 11 is a larger line width / line pitch, such as more than 10 micrometers (um). In subsequent packaging processes, semiconductor chips 9a, 9b with different contact specifications can be placed on the circuit block 12 and the interposer circuit structure 11.

[0006] Furthermore, the circuit block 12 and the interposer circuit structure 11 are manufactured separately, so that the circuit block 12 and the interposer circuit structure 11 can be detected separately, and the circuit block 12 with normal detection can be disposed on the interposer circuit structure 11 with normal detection, which is beneficial to controlling the yield of the packaging substrate 1a.

[0007] However, when manufacturing the packaging substrate 1a, a groove 110 needs to be formed on the build-up circuit structure 11. As a result, not only is the process time long, but the manufacturing cost is significantly increased due to the need to add equipment for manufacturing the groove 110, leading to a substantial increase in the manufacturing cost of the packaging substrate 1a.

[0008] Furthermore, the circuit block 12 needs to be disposed on the build-up circuit structure 11 through a plurality of conductive bumps 120. As a result, not only are the related processes for the plurality of conductive bumps 120 increased, leading to an increase in the manufacturing cost of the packaging substrate 1a, but the circuit block 12 is prone to poor electrical connection due to inaccurate alignment, resulting in poor reliability of the packaging substrate 1a.

[0009] Therefore, in order to reduce the manufacturing cost, the industry has adopted a design without a groove, such as Figure 1B the packaging substrate 1b shown in the figure, so that when manufacturing the build-up circuit structure 11, the circuit block 12 is manufactured together, so that the circuit block 12 and the build-up circuit structure 11 are integrally arranged, and the circuit block 12 is buried in the build-up circuit structure 11.

[0010] However, in the existing packaging substrate 1b without a groove, the circuit block 12 and the build-up circuit structure 11 are integrally arranged. Therefore, after the circuit block 12 and the build-up circuit structure 11 are manufactured, the circuit block 12 and the build-up circuit structure 11 can be detected. Therefore, if the detection of the circuit block 12 or the build-up circuit structure 11 is defective before the semiconductor chips 9a, 9b are disposed, the packaging substrate 1b needs to be discarded, which not only significantly increases the manufacturing cost of the packaging substrate 1b, but also makes it difficult to improve the yield of the back-end packaging products using the packaging substrate 1b.

[0011] Therefore, how to overcome the various problems of the above-mentioned prior art has actually become a difficult problem that the industry urgently needs to overcome at present. Summary of the Invention

[0012] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate and a manufacturing method thereof, which can at least partially solve the problems in the prior art.

[0013] The packaging substrate of the present invention includes: a substrate body having at least one circuit layer; a circuit block bonded to the substrate body; a coating layer disposed on the substrate body to cover the circuit block; a conductive column buried in the coating layer and standing on the circuit layer to electrically connect the circuit layer; and a circuit portion formed on the coating layer, wherein the circuit portion has a conductive layer electrically connecting the conductive column and at least one conductive blind hole electrically connecting the circuit block and the conductive layer.

[0014] The present invention also provides a method for manufacturing an encapsulation substrate, comprising: providing a substrate body having at least one circuit layer and at least one circuit block; bonding the circuit block to the substrate body; forming a coating layer on the substrate body to coat the circuit block with the coating layer; and forming a circuit portion on the coating layer and forming conductive pillars in the coating layer to electrically connect the conductive pillars to the circuit layer, wherein the circuit portion has a conductive layer electrically connected to the conductive pillars and at least one conductive blind via electrically connecting the circuit block and the conductive layer.

[0015] In the foregoing encapsulation substrate and its manufacturing method, the substrate body includes a core layer having conductive vias and build-up circuit structures provided on opposite sides of the core layer, and the build-up circuit structure has at least one dielectric layer and the circuit layer bonded to the dielectric layer to electrically connect the circuit layer to the conductive vias.

[0016] In the foregoing encapsulation substrate and its manufacturing method, the conductive pillar and the conductive layer are integrally formed.

[0017] In the foregoing encapsulation substrate and its manufacturing method, the wiring specification of the circuit block is different from that of the circuit layer.

[0018] In the foregoing encapsulation substrate and its manufacturing method, the wiring specification of the circuit block is different from that of the circuit portion.

[0019] In the foregoing encapsulation substrate and its manufacturing method, the circuit block is a coreless circuit structure.

[0020] In the foregoing encapsulation substrate and its manufacturing method, the wiring specification of the circuit block is a redistribution layer specification.

[0021] In the foregoing encapsulation substrate and its manufacturing method, it further includes forming a bonding layer on the substrate body to bond the circuit block to the bonding layer. For example, the bonding layer is an Ajinomoto build-up film.

[0022] In the foregoing encapsulation substrate and its manufacturing method, the coating layer is an Ajinomoto build-up film.

[0023] As can be seen from the above, in the encapsulation substrate and its manufacturing method of the present invention, mainly by disposing the circuit block on the substrate body and then coating the circuit block with a coating layer, the circuit block can be buried in the coating layer without making a groove. Therefore, compared with the prior art, the encapsulation substrate of the present invention can not only reduce the process time, but also greatly reduce the manufacturing cost because there is no need to add equipment for making grooves, effectively reducing the manufacturing cost of the encapsulation substrate.

[0024] Furthermore, the circuit block and the substrate body are manufactured separately, so that the circuit block and the substrate body can be detected separately. The circuit block with normal detection can be disposed on the substrate body with normal detection, thereby improving the yield of the packaging substrate. Therefore, compared with the prior art, before the circuit block is disposed on the packaging substrate of the present invention, if the detection result of the circuit block or the substrate body is defective, only the circuit block or the substrate body needs to be replaced, thereby avoiding the problem of scrapping the whole packaging substrate, and further reducing the manufacturing cost of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A FIG. 1 is a schematic cross-sectional view of a conventional packaging substrate and its application.

[0026] Figure 1B FIG. 2 is a schematic cross-sectional view of another conventional packaging substrate and its application.

[0027] Figures 2A to 2E FIG. 3 is a schematic cross-sectional view of a manufacturing method of the packaging substrate of the present invention.

[0028] Figure 3 FIG. 4 is Figure 2E a schematic cross-sectional view of a subsequent packaging process.

[0029] MAIN COMPONENT SYMBOL DESCRIPTION

[0030] 1a, 1b, 2 Packaging substrates

[0031] 10, 20 Core layers

[0032] 100, 200 Conductive vias

[0033] 11 Build-up circuit structure

[0034] 110 Groove

[0035] 12, 24 Circuit blocks

[0036] 120, 30 Conductive bumps

[0037] 2a Substrate body

[0038] 2b Circuit board body

[0039] 20a First surface

[0040] 20b Second surface

[0041] 20c Plugging hole material

[0042] 201 First inner circuit layer

[0043] 202 Second inner circuit layer

[0044] 21 First build-up circuit structure

[0045] 210 First dielectric layer

[0046] 211 First circuit layer

[0047] 22 Second build-up circuit structure

[0048] 220 Second dielectric layer

[0049] 221 Second circuit layer

[0050] 23 Bonding layer

[0051] 240, 25a Insulating layer

[0052] 241 Wiring layer

[0053] 25 Coating layer

[0054] 250 Perforation

[0055] 251 First blind via

[0056] 252 Second blind via

[0057] 26 First circuit portion

[0058] 26a Second circuit portion

[0059] 260, 260a Conductive layer

[0060] 261 First conductive blind via

[0061] 262 Second conductive blind via

[0062] 27 Conductive column

[0063] 271 Electrical contact pad

[0064] 28 Solder mask layer

[0065] 280 Opening

[0066] 29 Surface treatment layer

[0067] 3 Electronic package

[0068] 31, 32 Electronic components

[0069] 31a, 32a Active surface

[0070] 31b, 32b Non-active surface

[0071] 310, 320 Electrode pads

[0072] 33 Solder ball

[0073] 9a, 9b semiconductor wafers

[0074] h1, h2 heights

[0075] L cutting path Detailed implementation manners

[0076] The following illustrates the implementation manners of the present invention through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0077] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration, and are not used to limit the scope for the implementation of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope for the implementation of the present invention.

[0078] Figures 2A to 2E It is a schematic cross-sectional view of the manufacturing method of the packaging substrate 2 of the present invention.

[0079] As Figure 2A shown, a substrate body 2a and a circuit board body 2b are provided. The substrate body 2a includes a core layer 20, a first build-up circuit structure 21 and a second build-up circuit structure 22 disposed on opposite sides of the core layer 20, and the circuit board body 2b includes a plurality of circuit blocks 24 arranged in an array.

[0080] The core layer 20 has opposite first surface 20a and second surface 20b, and a first inner circuit layer 201 and a second inner circuit layer 202 are respectively formed on the first surface 20a and the second surface 20b.

[0081] In this embodiment, the core layer 20 is of a single core layer specification, and its material can be selected according to requirements without special limitation. At least one conductive through hole 200 connecting the first and second inner circuit layers 201, 202 is formed in the core layer 20. For example, the conductive through hole 200 is a hollow columnar shape, and its hollow part can be filled with a plugging material 20c. There are various types of the plugging material 20c, such as conductive glue, ink, or others, without special limitation. It should be understood that in other embodiments, the conductive through hole 200 can also be a solid metal column without filling the plugging material 20c.

[0082] The described first build-up circuit structure 21 is formed on the first surface 20a of the core layer 20, and includes at least one first dielectric layer 210 formed on the core layer 20 and a first circuit layer 211 bonded to the first dielectric layer 210, so that the first circuit layer 211 is electrically connected to the first inner circuit layer 201.

[0083] In this embodiment, the material for forming the first dielectric layer 210 is such as polybenzoxazole (abbreviated as PBO), polyimide (abbreviated as PI), prepreg (abbreviated as PP), or other dielectric materials, and the material for forming the first circuit layer 211 is a conductive material such as copper.

[0084] (Polybenzoxazole, abbreviated as PBO), polyimide (abbreviated as PI), prepreg (abbreviated as PP), or other dielectric materials, and the material for forming the first circuit layer 211 is a conductive material such as copper.

[0085] The described second build-up circuit structure 22 is formed on the second surface 20b of the core layer 20, and includes at least one second dielectric layer 220 formed on the core layer 20 and a second circuit layer 221 bonded to the second dielectric layer 220, so that the second circuit layer 221 is electrically connected to the second inner circuit layer 202.

[0086] In this embodiment, the material for forming the second dielectric layer 220 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials, and the material for forming the second circuit layer 221 is a conductive material such as copper.

[0087] The described circuit block 24 is a coreless circuit structure, which has at least one insulating layer 240 and a wiring layer 241 bonded to the insulating layer 240, and the wiring specification of the wiring layer 241 is different from the wiring specifications of the first circuit layer 211 and the second circuit layer 221.

[0088] In this embodiment, the material for forming the insulating layer 240 is such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0089] Furthermore, the wiring layer 241 is of the redistribution layer (abbreviated as RDL) specification, and its line width / line pitch is smaller than the line width / line pitch of the first circuit layer 211 and the second circuit layer 221. For example, the wiring specification of the wiring layer 241 is a smaller line width / line pitch (L / S), such as 2 micrometers (um), while the wiring specifications adopted by the first circuit layer 211 and the second circuit layer 221 are larger line width / line pitches, such as more than 10 micrometers (um).

[0090] It should be understood that the circuit board body 2b can also be a board body with other configured wirings, such as an organic material board, a silicon board, a ceramic board, or other carrier boards with metal routing, and is not limited to the above.

[0091] As Figure 2B shown, a singulation process is performed along the cutting path L as Figure 2A shown to obtain a plurality of circuit blocks 24, and a bonding layer 23 is formed on the entire surface of the first build-up circuit structure 21 of the substrate body 2a to bond the circuit blocks 24 to the bonding layer 23.

[0092] In this embodiment, the bonding layer 23 is an insulating material, such as an Ajinomoto build-up film (ABF) or other dielectric materials, and is bonded to the first build-up circuit structure 21 by lamination. It should be understood that if the bonding layer 23 is other dielectric materials, it can also be formed on the first build-up circuit structure 21 by coating.

[0093] Furthermore, before setting the circuit block 24 onto the bonding layer 23, the circuit block 24 and the substrate body 2a are respectively detected to place the circuit block 24 with normal detection on the substrate body 2a with normal detection.

[0094] As Figure 2C shown, a coating layer 25 covering the circuit block 24 is formed on the bonding layer 23, so that the circuit block 24 is buried in the coating layer 25, and the height h1 of the circuit block 24 relative to the bonding layer 23 (or the substrate body 2a) is lower than the height h2 of the coating layer 25 relative to the bonding layer 23 (or the substrate body 2a). Then, a plurality of through holes 250 and a plurality of first blind holes 251 are formed on the coating layer 25, and the through holes 250 extend into the bonding layer 23 to expose the first circuit layer 211 in the through holes 250, and the first blind holes 251 correspond to the positions of the circuit blocks 24 to expose the wiring layer 241 in the first blind holes 251.

[0095] In this embodiment, the coating layer 25 is an insulating material, which can be the same as or different from the material of the bonding layer 23. For example, the coating layer 25 is an Ajinomoto build-up film (ABF) or other dielectric materials, and is bonded to the first build-up circuit structure 21 by lamination. It should be understood that if the coating layer 25 is other dielectric materials, it can also be formed on the bonding layer 23 by coating.

[0096] Furthermore, the multiple through-holes 250 and the multiple first blind vias 251 can be formed by mechanical drilling, laser drilling, etching, or other methods, without any particular limitation.

[0097] On the other hand, an insulating layer 25a can also be formed on the entire surface of the second build-up circuit structure 22 of the substrate body 2a, and multiple second blind vias 252 are formed on the insulating layer 25a to expose the second circuit layer 221 in the second blind vias 252. For example, the insulating layer 25a is made of the same material as the bonding layer 23 or the coating layer 25, such as an abf build-up film, to facilitate the simultaneous production of the first blind vias 251 and the second blind vias 252, and can save the manufacturing cost of the packaging substrate 2.

[0098] As Figure 2D shown, a patterning wiring operation is performed to form a conductive layer 260 on the coating layer 25, and conductive posts 27 electrically connecting the first circuit layer 211 and the conductive layer 260 are formed in each of the through-holes 250, and first conductive blind vias 261 electrically connecting the conductive layer 260 and the wiring layer 241 are formed in each of the first blind vias 251. Among them, the conductive layer 260 and the first conductive blind vias 261 serve as the first circuit portion 26, and the wiring specifications of the wiring layer 241 are different from those of the conductive layer 260.

[0099] In this embodiment, the line width / line pitch of the conductive layer 260 is the same as that of the first circuit layer 211, such as 10 micrometers (μm) or more.

[0100] Furthermore, the conductive posts 27 and the conductive layer 260 are integrally formed. Alternatively, in other embodiments, metal posts protruding from the bonding layer 23 can also be formed on the first circuit layer 211 first to serve as the conductive posts 27, and then the metal posts are coated with the coating layer 25, and the coating layer 25 is polished to expose the end faces of the metal posts, and then a conductive layer 260 electrically connecting the end faces of the conductive posts 27 is formed. Therefore, there are many manufacturing methods for through molding via (TMV), so the process of the conductive posts 27 has no particular limitation.

[0101] On the other hand, a second circuit portion 26a including another conductive layer 260a can be formed on the insulating layer 25a, and second conductive blind vias 262 electrically connecting the second circuit layer 221 and the conductive layer 260a are formed in the multiple second blind vias 252 of the second circuit portion 26a. It should be understood that the second circuit portion 26a and the first circuit portion 26 can be manufactured together so that the wiring specifications of the second circuit portion 26a are the same as those of the first circuit portion 26.

[0102] As Figure 2EAs shown, a solder mask layer 28 is formed on the cladding layer 25 and the insulating layer 25a, and a plurality of openings 280 are formed in each solder mask layer 28 to expose a plurality of conductive layers 260, 260a for use as electrical contact pads 271 for externally connecting other components.

[0103] In this embodiment, the exposed surface of the first circuit portion 26 can be electrically connected to at least one electronic component 31, 32 such as a semiconductor chip, such as Figure 3 the electronic package 3 shown, and the exposed surface of the second circuit portion 26a can be bonded with solder balls 33 for mounting on a circuit board (not shown). For example, the electronic components 31, 32 are active components, passive components, or a combination of both, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0104] Furthermore, in Figure 3 , a plurality of electronic components 31, 32 are semiconductor chips of the same or different specifications, which have opposite active surfaces 31a, 32a and non-active surfaces 31b, 32b. The active surfaces 31a, 32a have a plurality of electrode pads 310, 320 to electrically connect to the first circuit portion 26 through a plurality of conductive bumps 30, so that the plurality of electronic components 31, 32 are disposed on the packaging substrate 2 in a flip-chip manner. However, there are many packaging methods for semiconductor chips, such as wire bonding, which are not limited to the above.

[0105] Preferably, a surface treatment layer 29 can be formed on the exposed surfaces of the first circuit portion 26 and the second circuit portion 26a, such as Figure 3 shown, such as one of nickel, palladium, gold, tin, or a group composed thereof, to facilitate externally connecting other components.

[0106] Therefore, in the manufacturing method of the present invention, mainly by disposing the circuit block 24 on the substrate body 2a and then covering the circuit block 24 with the cladding layer 25, the circuit block 24 can be buried in the cladding layer 25 without making grooves. Therefore, compared with the prior art, the packaging substrate 2 of the present invention not only reduces the process time, but also greatly reduces the manufacturing cost because there is no need to add equipment for making grooves, effectively reducing the manufacturing cost of the packaging substrate 2.

[0107] Furthermore, the circuit block 24 and the substrate body 2a are separately manufactured, so that the circuit block 24 and the substrate body 2a can be separately detected. The circuit block 24 with normal detection can be disposed on the substrate body 2a with normal detection, thereby improving the yield of the packaging substrate 2. Therefore, compared with the prior art, before the circuit block 24 is disposed on the packaging substrate 2 of the present invention, if the detection result of the circuit block 24 or the substrate body 2a is defective, only the circuit block 24 or the substrate body 2a needs to be replaced, thereby avoiding the problem of scrapping the whole packaging substrate 2 and reducing the manufacturing cost of the packaging substrate 2.

[0108] In addition, the circuit block 24 is disposed on the first build-up circuit structure 21 through the bonding layer 23, so that other operations such as related processes of existing conductive bumps do not need to be added. Therefore, not only the manufacturing cost of the packaging substrate 2 can be reduced, but also the problem of poor electrical connection can be avoided because the circuit block 24 does not need to perform electrical alignment, effectively improving the reliability of the packaging substrate 2.

[0109] In addition, the wiring specification of the circuit block 24 can be designed to be an ultra-fine circuit level according to requirements to improve the wiring flexibility of the packaging substrate 2.

[0110] The present invention also provides a packaging substrate 2, including: a substrate body 2a, at least one circuit block 24, a coating layer 25, a plurality of conductive columns 27, and a first circuit portion 26.

[0111] The substrate body 2a has a first circuit layer 211 and a second circuit layer 221.

[0112] The circuit block 24 is combined with the substrate body 2a without being electrically connected to the first circuit layer 211 and the second circuit layer 221.

[0113] The coating layer 25 is disposed on the substrate body 2a to cover the circuit block 24, and the height h1 of the circuit block 24 relative to the bonding layer 23 (or the substrate body 2a) is lower than the height h2 of the coating layer 25 relative to the bonding layer 23 (or the substrate body 2a).

[0114] The conductive columns 27 are buried in the coating layer 25 and stand on the first circuit layer 211 to be electrically connected to the first circuit layer 211.

[0115] The first circuit portion 26 is formed on the coating layer 25. Wherein, the first circuit portion 26 has a conductive layer 260 electrically connected to the conductive columns 27 and at least one first conductive blind hole 261 electrically connecting the circuit block 24 and the conductive layer 260.

[0116] In one embodiment, the substrate body 2a includes a core layer 20 having conductive vias 200 and first and second build-up circuit structures 21, 22 disposed on opposite sides of the core layer 20. The first build-up circuit structure 21 has at least one first dielectric layer 210 and the first circuit layer 211 bonded to the first dielectric layer 210, and the second build-up circuit structure 22 has at least one second dielectric layer 220 and the second circuit layer 221 bonded to the second dielectric layer 220, so that the first circuit layer 211 and the second circuit layer 220 are electrically connected to the conductive vias 200.

[0117] In one embodiment, the conductive column 27 and the conductive layer 260 are integrally formed.

[0118] In one embodiment, the wiring specification of the circuit block 24 is different from that of the first circuit layer 211.

[0119] In one embodiment, the wiring specification of the circuit block 24 is different from that of the first circuit portion 26.

[0120] In one embodiment, the circuit block 24 is a coreless circuit structure

[0121] In one embodiment, the wiring specification of the circuit block 24 is a redistribution layer specification.

[0122] In one embodiment, the circuit block 24 is bonded to the substrate body 2a through a bonding layer 23. For example, the bonding layer 23 is an Ajinomoto build-up film.

[0123] In one embodiment, the coating layer 25 is an Ajinomoto build-up film.

[0124] In summary, for the packaging substrate and its manufacturing method of the present invention, by embedding the circuit block in the coating layer, there is no need to fabricate a groove. Therefore, the packaging substrate of the present invention can not only reduce the process time, but also significantly reduce the manufacturing cost because there is no need to add equipment for fabricating the groove, effectively reducing the manufacturing cost of the packaging substrate.

[0125] Furthermore, the circuit block and the substrate body are separately manufactured, so that the circuit block and the substrate body can be separately detected, and the circuit block with normal detection can be disposed on the substrate body with normal detection. Therefore, the manufacturing method of the present invention can avoid the problem of scrapping the entire packaging substrate.

[0126] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, and are not used to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the patent protection of the present invention shall be as set forth in the claims.

Claims

1. An encapsulation substrate, comprising: a substrate body having at least one circuit layer; a circuit block bonded to the substrate body; a coating layer disposed on the substrate body to coat the circuit block; a conductive column embedded in the coating layer and standing on the circuit layer to electrically connect to the circuit layer; and a circuit portion formed on the coating layer, wherein the circuit portion has a conductive layer electrically connected to the conductive column and at least one conductive blind hole electrically connecting the circuit block and the conductive layer wherein the substrate body bonds the circuit block through a bonding layer, and the bonding layer is formed on the entire surface of the substrate body.

2. The encapsulation substrate according to claim 1, wherein the substrate body includes a core layer having conductive vias and build-up circuit structures disposed on opposite sides of the core layer, and the build-up circuit structures have at least one dielectric layer and the circuit layer bonding to the dielectric layer to electrically connect the circuit layer to the conductive vias.

3. The encapsulation substrate according to claim 1, wherein the conductive column and the conductive layer are integrally formed.

4. The encapsulation substrate according to claim 1, wherein the wiring specification of the circuit block is different from that of the circuit layer.

5. The encapsulation substrate according to claim 1, wherein the wiring specification of the circuit block is different from that of the circuit portion.

6. The encapsulation substrate according to claim 1, wherein the circuit block is a coreless circuit structure.

7. The encapsulation substrate according to claim 1, wherein the wiring specification of the circuit block is a redistribution layer specification.

8. The encapsulation substrate according to claim 1, wherein the bonding layer is an Ajinomoto build-up film.

9. The encapsulation substrate according to claim 1, wherein the coating layer is an Ajinomoto build-up film.

10. A manufacturing method of an encapsulation substrate, comprising: providing a substrate body having at least one circuit layer and at least one circuit block; bonding the circuit block to the substrate body; forming a coating layer on the substrate body to coat the circuit block with the coating layer; and forming a circuit portion on the coating layer and forming a conductive column in the coating layer to electrically connect the conductive column to the circuit layer, wherein the circuit portion has a conductive layer electrically connected to the conductive column and at least one conductive blind hole electrically connecting the circuit block and the conductive layer, wherein bonding the circuit block to the substrate body further includes forming a bonding layer on the entire surface of the substrate body to bond the circuit block to the bonding layer.

11. The manufacturing method of the encapsulation substrate according to claim 10, wherein the substrate body includes a core layer having conductive vias and build-up circuit structures disposed on opposite sides of the core layer, and the build-up circuit structures have at least one dielectric layer and the circuit layer bonding to the dielectric layer to electrically connect the circuit layer to the conductive vias.

12. The manufacturing method of the encapsulation substrate according to claim 10, wherein the conductive column and the conductive layer are integrally formed.

13. The manufacturing method of the encapsulation substrate according to claim 10, wherein the wiring specification of the circuit block is different from that of the circuit layer.

14. The manufacturing method of the encapsulation substrate according to claim 10, wherein The wiring specification of the circuit block is different from that of the circuit portion.

15. The manufacturing method of the packaging substrate as claimed in claim 10, wherein, the circuit block is a coreless circuit structure.

16. The manufacturing method of the packaging substrate as claimed in claim 10, wherein, the wiring specification of the circuit block is the redistribution layer specification.

17. The manufacturing method of the packaging substrate as claimed in claim 10, wherein, the bonding layer is an Ajinomoto build-up film.

18. The manufacturing method of the packaging substrate as claimed in claim 10, wherein, the coating layer is an Ajinomoto build-up film.

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