A power semiconductor dynamic reverse bias test circuit, method and test equipment
By constructing a power semiconductor dynamic reverse bias test circuit that includes a switching circuit, a driving circuit, and a measurement circuit, the problems of circuit complexity and high cost in the prior art are solved, achieving the effect of simplifying the structure and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENXIN TECH (SHANGHAI) CO LTD
- Filing Date
- 2023-12-27
- Publication Date
- 2026-06-12
AI Technical Summary
Existing semiconductor dynamic reverse bias test circuits are complex and costly, making them unsuitable for mass production.
A power semiconductor dynamic reverse bias test circuit, consisting of a switching circuit, a driving circuit, and a measurement circuit, is used to switch the operating state through the switching circuit, use the driving circuit to output pulse complementary signals and DC complementary signals to simulate the operating conditions of the device, and perform testing through the measurement circuit, thereby reducing the number of components.
This simplifies the circuit structure, reduces testing costs, and improves testing efficiency and accuracy.
Smart Images
Figure CN117783805B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, and in particular to a dynamic reverse bias test circuit, method and test equipment for power semiconductors. Background Technology
[0002] Dynamic reverse bias testing of semiconductors is commonly used to evaluate the performance and reliability of semiconductor devices, especially wide-bandgap semiconductors, under dynamic reverse bias. During the dynamic reverse bias stress application phase, a square wave voltage is applied between the cathode and anode of the semiconductor device. During the leakage current detection phase, a reverse DC voltage is applied between the cathode and anode of the semiconductor device, and the change in leakage current is observed.
[0003] Currently, dynamic reverse bias testing of semiconductors typically requires at least a DC voltage source and stress generating switches to provide dynamic reverse bias stress voltage to the semiconductor under test, in order to simulate the reverse stress that the semiconductor experiences during actual operation. However, this method results in complex circuit structures, high costs, and is not suitable for large-scale manufacturing. Summary of the Invention
[0004] To reduce the cost of reverse bias test circuits, this application provides a power semiconductor dynamic reverse bias test circuit, method, and test equipment.
[0005] Firstly, this application provides a power semiconductor dynamic reverse bias test circuit, which adopts the following technical solution:
[0006] A power semiconductor dynamic reverse bias test circuit, comprising:
[0007] The switching circuit is connected to the power supply VCC and switches the working state according to the external trigger signal. The working state includes a stress application stage and a test stage.
[0008] The first driving circuit is used to connect to the first device under test (DUT1) to output a first driving signal to control the on / off state of the first device under test (DUT1).
[0009] The second driving circuit is used to connect to the second device under test (DUT2) to output a second driving signal to control the on / off state of the second DUT2; wherein, during the stress application phase, the second driving signal and the first driving signal are pulse complementary signals; during the testing phase, the second driving signal and the first driving signal are DC complementary signals; the first DUT1 and the second DUT2 are connected in series.
[0010] The measurement circuit is connected to the switching circuit and the second device under test (DUT2) and is used to output the test results of the first device under test and the test results of the second device under test during the testing phase.
[0011] By adopting the above technical solution, the working state is first switched using a switching circuit, and then the first driving circuit and the second driving circuit output the first driving signal and the second driving signal respectively. On the one hand, during the stress application stage, the actual operating conditions of the first device under test (DUT1) and the second device under test (DUT2) are simulated by outputting pulse complementary signals. On the other hand, during the testing stage, the first device under test (DUT1) and the second device under test (DUT2) are tested by the measurement circuit through the output of DC complementary signals to obtain the test results of the first device under test and the second device under test. By using the first driving circuit to directly drive the first device under test (DUT1) and the second driving circuit to directly drive the second device under test (DUT2), the first device under test (DUT1) and the second device under test (DUT2) form a half-bridge structure to provide dynamic reverse bias voltage. There is no need to set up other half-bridge structures to provide dynamic reverse bias voltage stress waveform, thereby reducing the required components and achieving the effect of cost saving.
[0012] Optionally, the switching circuit includes a switching switch SW, one end of which is connected to the power supply VCC and the measurement circuit, and the other end is connected to the second device under test (DUT2) and the measurement circuit.
[0013] By adopting the above technical solution, during the stress application stage, the switching switch SW is turned on, causing the measurement circuit to be short-circuited and not working, and the power supply VCC provides power to the second device under test (DUT2) and the first device under test (DUT1) to simulate the actual working conditions; during the testing stage, the switching switch SW is turned off, causing the measurement circuit to start working, so as to test the first device under test (DUT1) and the second device under test (DUT2).
[0014] Optionally, the measurement circuit samples resistor R1 and first amplifier U1;
[0015] The sampling resistor R1 is connected at one end to the switching circuit, the power supply VCC and the first input terminal of the first amplifier U1, and at the other end to the second device under test DUT2, the switching circuit and the second output terminal of the first amplifier U1.
[0016] The output of the first amplifier U1 is connected to an external circuit to output the test results of the first device under test and the test results of the second device under test.
[0017] By adopting the above technical solution, the sampling resistor R1 is connected in parallel with the switching circuit. When the switching circuit is on, the sampling resistor R1 is short-circuited. When the switching circuit is off, the sampling resistor R1 is connected in parallel with the first device under test (DUT1) and the second device under test (DUT2) in series, controlling the first device under test (DUT1) and the second device under test (DUT2) to conduct one by one. At this time, the current on the sampling resistor R1 is the leakage current of the first device under test (DUT1) or the second device under test (DUT2). Then, the first amplifier U1 amplifies the leakage current, thereby obtaining the measurement results of the first device under test (DUT1) and the second device under test (DUT2).
[0018] Optionally, a protection circuit is also included, which is disposed between the power supply VCC and the first device under test (DUT1) for overvoltage protection of the first device under test (DUT1) and the second device under test (DUT2).
[0019] By adopting the above technical solution, the protection circuit prevents the first device under test (DUT1) and the second device under test (DUT2) from being reverse-broken through the first device under test (DUT1) and the second device under test (DUT2), thus preventing the first device under test (DUT1) and the second device under test (DUT2) from being reverse-broken.
[0020] Optionally, the protection circuit includes a protection resistor R2, a second amplifier U2, a comparator U3, and a switching transistor Q1;
[0021] The protective resistor R2 is connected at one end to the first input terminal of the first device under test (DUT1) and the second amplifier (U2), and at the other end to the source of the switching transistor Q1 and the second input terminal of the second amplifier (U2).
[0022] The comparator U3 has its first input terminal connected to the output terminal of the second amplifier U2, its second input terminal used to receive a reference voltage signal, and its output terminal connected to the gate of the switching transistor Q1; the drain of the switching transistor Q1 is connected to the power supply VCC.
[0023] By adopting the above technical solution, the protection circuit is connected in series with the first device under test (DUT1) and the second device under test (DUT2). The second amplifier U2 collects and amplifies the voltage drop across the protection resistor R2. When the output of the second amplifier U2 exceeds the reference voltage signal, the comparator U3 outputs a signal to control the switch Q1 to turn off, thereby disconnecting the power supply VCC from the first device under test (DUT1), thus realizing the protection function for the first device under test (DUT1) and the second device under test (DUT2).
[0024] Optionally, the first device under test (DUT1) has a first terminal connected to the power supply VCC, a second terminal connected to the first terminal of the second device under test (DUT2) and the first drive circuit, and the control terminal of the first device under test (DUT1) is connected to the first drive circuit.
[0025] The second device under test (DUT2) has its second terminal connected to the second driving circuit, the switching circuit, and the measurement circuit, and its control terminal connected to the second driving circuit.
[0026] By adopting the above technical solution, it is convenient for the first driving circuit to control the on / off state of the first device under test (DUT1) and the second driving circuit to control the on / off state of the second device under test (DUT2).
[0027] Secondly, this application provides a dynamic reverse bias test method for power semiconductors, employing the following technical solution:
[0028] A method for dynamic reverse bias testing of power semiconductors, comprising:
[0029] The working state is switched according to an external trigger signal, and the working state includes a stress application stage and a test stage.
[0030] The first driving circuit outputs a first driving signal to control the on / off state of the first device under test (DUT1);
[0031] The second driving circuit outputs a second driving signal to control the on / off state of the second device under test (DUT2); wherein, during the stress application phase, the second driving signal and the first driving signal are pulse complementary signals; during the testing phase, the second driving signal and the first driving signal are DC complementary signals; the first device under test (DUT1) and the second device under test (DUT2) are connected in series.
[0032] During the testing phase, the measurement circuit outputs the test results of the first device under test and the test results of the second device under test.
[0033] Optionally, the testing phase includes a first testing phase and a second testing phase. During the testing phase, the measurement circuit outputs test results for a first device under test and test results for a second device under test, specifically including:
[0034] In the first test phase, the first driving circuit outputs a first driving signal to control the first device under test (DUT1) to turn off, and the second driving circuit outputs a second driving signal to control the second device under test (DUT2) to turn on.
[0035] The first test phase ends and the second test phase begins in response to the test result of the first device under test output by the measurement circuit.
[0036] In the second test phase, the first drive circuit outputs a first drive signal to control the first device under test (DUT1) to turn on, and the second drive circuit outputs a second drive signal to control the second device under test (DUT2) to turn off, until the measurement circuit outputs the test result of the second device under test.
[0037] Optionally, when both the first device under test (DUT1) and the second device under test (DUT2) are P-type transistors, in the first test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal; in the second test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal.
[0038] When both the first device under test (DUT1) and the second device under test (DUT2) are N-type transistors, in the first test phase, the first drive signal is a low-level signal and the second drive signal is a high-level signal; in the second test phase, the first drive signal is a low-level signal and the second drive signal is a high-level signal.
[0039] Thirdly, this application provides a testing device, which adopts the following technical solution:
[0040] A testing device, characterized in that it includes a power semiconductor dynamic reverse bias testing circuit as described above. Attached Figure Description
[0041] Figure 1 This is a block diagram of a power semiconductor dynamic reverse bias test circuit according to one embodiment of this application.
[0042] Figure 2 This is a connection structure diagram of a power semiconductor dynamic reverse bias test circuit according to one embodiment of this application.
[0043] Figure 3 This is a waveform diagram of the stress application stage in one embodiment of this application.
[0044] Figure 4 This is a waveform diagram of the test phase of one embodiment of this application.
[0045] Explanation of reference numerals in the attached diagram: 1. Switching circuit; 2. First drive circuit; 3. Second drive circuit; 4. Measurement circuit; 5. Protection circuit. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0047] This application discloses a dynamic reverse bias test circuit for power semiconductors. (Refer to...) Figure 1 ,2 A power semiconductor dynamic reverse bias test circuit includes:
[0048] Switching circuit 1 is connected to the power supply VCC and switches the working state according to the external trigger signal.
[0049] The working state includes the stress application stage and the testing stage; the power supply VCC is a DC power supply.
[0050] The first driving circuit 2 is used to connect to the first device under test (DUT1) to output a first driving signal to control the on / off state of the first device under test (DUT1).
[0051] The second driving circuit 3 is connected to the second device under test (DUT2) to output a second driving signal to control the on / off state of the DUT2. During the stress application phase, the second driving signal and the first driving signal are pulse complementary signals, meaning they are pulse width modulated signals with a preset duty cycle. During the testing phase, the second driving signal and the first driving signal are DC complementary signals. Complementarity means that the first driving signal and the second driving signal are always out of phase; if the first driving signal is high, the second driving signal is low, and vice versa.
[0052] Reference Figure 3 , Figure 3 These are waveforms during the stress application phase, where SW is the output of switching circuit 1, indicating that switching circuit 1 is on at this time. G_H is the waveform of the first drive signal during the stress application phase. G_L is the waveform of the second drive signal during the stress application phase. VGS_H is the waveform of the source-drain voltage of the first device under test (DUT1) under the control of the first drive signal. VGS_L is the waveform of the source-drain voltage of the second device under test (DUT2) under the control of the second drive signal. Figure 3 Vdc is the source-drain voltage.
[0053] Reference Figure 4 , Figure 3 These are waveforms during the test phase, where SW is the output of switching circuit 1, meaning switching circuit 1 is currently disconnected. G_H is the waveform of the first drive signal during the test phase. G_L is the waveform of the second drive signal during the test phase. VGS_H is the waveform of the source-drain voltage of the first device under test (DUT1) under the control of the first drive signal. VGS_L is the waveform of the source-drain voltage of the second device under test (DUT2) under the control of the second drive signal. Figure 4 Vdc is the source-drain voltage.
[0054] In this configuration, the first device under test (DUT1) and the second device under test (DUT2) are connected in series. Specifically, the first terminal of the first DUT1 is connected to the power supply VCC, and the second terminal is connected to the first terminal of the second DUT2 and the first drive circuit 2. The control terminal of the first DUT1 is connected to the first drive circuit 2. The second DUT2 has its second terminal connected to the second drive circuit 3, the switching circuit 1, and the measurement circuit 4, and its control terminal is connected to the second drive circuit 3. This facilitates the first drive circuit 2 to control the on / off state of the first DUT1, and the second drive circuit 3 to control the on / off state of the second DUT2.
[0055] It should be understood that the first device under test (DUT1) and the second device under test (DUT2) can both be N-type field-effect transistors (FETs) or both be P-type field-effect transistors (FETs).
[0056] Measurement circuit 4 is connected to switching circuit 1 and the second device under test (DUT2) and is used to output the test results of the first DUT and the second DUT during the testing phase.
[0057] The test results for both the first and second devices under test showed leakage current.
[0058] Combination Figure 4 The testing phase includes a first testing phase and a second testing phase. In the first testing phase, the second device under test (DUT2) is turned on and the first device under test (DUT1) is turned off. Leakage current detection is performed on the first device under test (DUT1) to obtain the test result of the first device under test. In the second testing phase, the first device under test (DUT1) is turned on and the second device under test (DUT2) is turned off. Leakage current detection is performed on the second device under test (DUT2) to obtain the test result of the second device under test.
[0059] It should be understood that the usage scenarios of the device under test (DUT) are usually controlled by PWM signals. For example, in a half-bridge structure, the half-bridge structure consists of two field-effect transistors (FETs). The two FETs alternately bear the reverse bias voltage. When one FET is turned on, the other FET is in the off state and bears the reverse bias voltage. In this embodiment, the first DUT1 and the second DUT2 are connected in series to form a half-bridge structure, thereby enabling the first DUT1 and the second DUT2 to alternately bear the reverse bias voltage, which is more in line with the operating conditions of the DUT itself.
[0060] It should also be understood that by forming a half-bridge structure with the first device under test (DUT1) and the second device under test (DUT2), the first device under test (DUT1) and the second device under test (DUT2) can be subjected to stress together during the same stress application stage, thereby enabling the leakage current of the first device under test (DUT1) and the second device under test (DUT2) under operating conditions to be tested, thus improving the testing efficiency.
[0061] In the above embodiment, the working state is first switched using the switching circuit 1, and then the first driving circuit 2 and the second driving circuit 3 output the first driving signal and the second driving signal respectively. On the one hand, during the stress application stage, the actual operating conditions of the first device under test (DUT1) and the second device under test (DUT2) are simulated by outputting pulse complementary signals. On the other hand, during the testing stage, the first device under test (DUT1) and the second device under test (DUT2) are tested by the measurement circuit 4 by outputting DC complementary signals to obtain the test results of the first device under test and the second device under test. By using the first driving circuit 2 to directly drive the first device under test (DUT1) and the second driving circuit 3 to directly drive the second device under test (DUT2), the first device under test (DUT1) and the second device under test (DUT2) form a half-bridge structure to provide dynamic reverse bias voltage. There is no need to set up other half-bridge structures to provide reverse bias voltage stress waveform, thereby reducing the required components and achieving the effect of cost saving.
[0062] It should be noted that dynamic reverse bias refers to applying a square wave voltage, rather than a DC voltage, to the device under test. In this embodiment, the first device under test (DUT1) and the second device under test (DUT2) form a half-bridge structure that can provide a square wave voltage. That is, the square wave voltage is provided by the device under test itself, so there is no need to set up other half-bridge structures or other components for providing square wave voltage.
[0063] Reference Figure 2 As one embodiment of the switching circuit 1, the switching circuit 1 includes a switching switch SW. One end of the switching switch SW is connected to the power supply VCC and the measurement circuit 4, and the other end is connected to the second device under test DUT2 and the measurement circuit 4.
[0064] Specifically, the changeover switch SW can be a single-pole single-throw switch or a single-pole double-throw switch. The common terminal of the single-pole double-throw switch is connected to the negative terminal of the DC power supply, and both the first and second contacts are empty.
[0065] In the above embodiment, during the stress application stage, the switching switch SW is turned on, causing the measurement circuit 4 to be short-circuited and not working, and the power supply VCC provides power to the second device under test (DUT2) and the first device under test (DUT1) to simulate the actual working conditions; during the testing stage, the switching switch SW is turned off, causing the measurement circuit 4 to start working in order to test the first device under test (DUT1) and the second device under test (DUT2).
[0066] Reference Figure 2 As one implementation of the measurement circuit 4, the measurement circuit 4 samples the resistor R1 and the first amplifier U1;
[0067] The sampling resistor R1 is connected at one end to the switching circuit 1, the power supply VCC and the first input terminal of the first amplifier U1, and at the other end to the second device under test DUT2, the switching circuit 1 and the second output terminal of the first amplifier U1.
[0068] The output of the first amplifier U1 is connected to an external circuit to output the test results of the first device under test and the test results of the second device under test.
[0069] The external circuit may be a processor, which transmits the test results of the first device under test and the test results of the second device under test to the processor for further processing and / or transmission.
[0070] In the above embodiment, the sampling resistor R1 is connected in parallel with the switching circuit 1. When the switching circuit 1 is turned on, the sampling resistor R1 is short-circuited. When the switching circuit 1 is turned off, the sampling resistor R1 is connected in parallel with the first device under test (DUT1) and the second device under test (DUT2) in series, controlling the first device under test (DUT1) and the second device under test (DUT2) to be turned on one by one. At this time, the current on the sampling resistor R1 is the leakage current of the first device under test (DUT1) or the second device under test (DUT2). The first amplifier U1 then amplifies the leakage current, thereby obtaining the measurement result of the first device under test (DUT1) and the measurement result of the second device under test (DUT2).
[0071] As a further embodiment of the power semiconductor dynamic reverse bias test circuit, the power semiconductor dynamic reverse bias test circuit also includes a protection circuit 5. The protection circuit 5 is disposed between the power supply VCC and the first device under test DUT1, and is used to provide overvoltage protection for the first device under test DUT1 and the second device under test DUT2.
[0072] In the above embodiment, the protection circuit 5 is used to prevent the rated reverse voltage of the first device under test (DUT1) and the second device under test (DUT2) from passing through the first device under test (DUT1) and the second device under test (DUT2), thereby preventing the first device under test (DUT1) and the second device under test (DUT2) from being reversely broken down.
[0073] As one implementation of the protection circuit 5, the protection circuit 5 includes a protection resistor R2, a second amplifier U2, a comparator U3, and a switching transistor Q1;
[0074] The protection resistor R2 is connected at one end to the first device under test DUT1 and the first input terminal of the second amplifier U2, and at the other end to the source of the switching transistor Q1 and the second input terminal of the second amplifier U2.
[0075] Comparator U3 has its first input terminal connected to the output terminal of the second amplifier U2, its second input terminal used to receive a reference voltage signal, and its output terminal connected to the gate of the switching transistor Q1; the drain of the switching transistor Q1 is connected to the power supply VCC.
[0076] In the above embodiment, the protection circuit 5 is connected in series with the first device under test (DUT1) and the second device under test (DUT2). The second amplifier U2 collects and amplifies the voltage drop across the protection resistor R2. When the output of the second amplifier U2 exceeds the reference voltage signal, the comparator U3 outputs a signal to control the switch Q1 to turn off, thereby disconnecting the power supply VCC from the first device under test (DUT1), thus realizing the protection function for the first device under test (DUT1) and the second device under test (DUT2).
[0077] This application discloses a dynamic reverse bias test method for power semiconductors. The dynamic reverse bias test method for power semiconductors includes:
[0078] The working state is switched according to an external trigger signal, and the working state includes a stress application stage and a test stage.
[0079] The first driving circuit 2 outputs a first driving signal to control the on / off state of the first device under test (DUT1);
[0080] The second driving circuit 3 outputs a second driving signal to control the on / off state of the second device under test (DUT2); wherein, during the stress application phase, the second driving signal and the first driving signal are pulse complementary signals; during the testing phase, the second driving signal and the first driving signal are DC complementary signals; the first device under test (DUT1) and the second device under test (DUT2) are connected in series.
[0081] During the testing phase, measurement circuit 4 outputs the test results of the first device under test and the test results of the second device under test.
[0082] The testing phase includes a first testing phase and a second testing phase.
[0083] As one implementation method where measurement circuit 4 outputs test results for the first device under test (DUT) and the second DUT during the testing phase, the specific output of test results for the first DUT and the second DUT by measurement circuit 4 during the testing phase includes:
[0084] In the first test phase, the first drive circuit 2 outputs a first drive signal to control the first device under test (DUT1) to turn off, and the second drive circuit 3 outputs a second drive signal to control the second device under test (DUT2) to turn on.
[0085] In response to the output of the test result of the first device under test by the measurement circuit 4, the first test phase ends and the second test phase begins.
[0086] In the second test phase, the first drive circuit 2 outputs a first drive signal to control the first device under test (DUT1) to turn on, and the second drive circuit 3 outputs a second drive signal to control the second device under test (DUT2) to turn off, until the measurement circuit 4 outputs the test result of the second device under test.
[0087] Specifically, when both the first device under test (DUT1) and the second device under test (DUT2) are P-type transistors, in the first test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal; in the second test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal.
[0088] When both the first device under test (DUT1) and the second device under test (DUT2) are N-type transistors, in the first test phase, the first drive signal is a low-level signal and the second drive signal is a high-level signal; in the second test phase...
[0089] This embodiment also discloses a test device, including a power semiconductor dynamic reverse bias test circuit as described above.
[0090] The power semiconductor dynamic reverse bias test method provided in this application can realize the power semiconductor dynamic reverse bias test circuit described above, and the specific working process of the power semiconductor dynamic reverse bias test method can be referred to the corresponding process in the above method embodiment.
[0091] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0092] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.
Claims
1. A power semiconductor dynamic reverse bias test circuit, characterized in that, include: The switching circuit (1) is connected to the power supply VCC and switches the working state according to the external trigger signal. The working state includes the stress application stage and the test stage. The first driving circuit (2) is used to connect to the first device under test (DUT1) to output a first driving signal to control the on / off state of the first device under test (DUT1); The second driving circuit (3) is used to connect to the second device under test (DUT2) to output a second driving signal to control the on / off state of the second device under test (DUT2); wherein, during the stress application stage, the second driving signal and the first driving signal are pulse complementary signals; during the test stage, the second driving signal and the first driving signal are DC complementary signals; the first device under test (DUT1) and the second device under test (DUT2) are connected in series. The measurement circuit (4) is connected to the switching circuit (1) and the second device under test (DUT2) and is used to output the test results of the first device under test and the test results of the second device under test during the test phase.
2. The power semiconductor dynamic reverse bias test circuit according to claim 1, characterized in that: The switching circuit (1) includes a switching switch SW. One end of the switching switch SW is connected to the power supply VCC and the measurement circuit (4), and the other end is connected to the second device under test DUT2 and the measurement circuit (4).
3. The power semiconductor dynamic reverse bias test circuit according to claim 1, characterized in that: The measurement circuit (4) includes a sampling resistor R1 and a first amplifier U1; The sampling resistor R1 is connected at one end to the switching circuit (1), the power supply VCC and the first input terminal of the first amplifier U1, and at the other end to the second device under test DUT2, the switching circuit (1) and the second output terminal of the first amplifier U1. The output of the first amplifier U1 is connected to an external circuit to output the test results of the first device under test and the test results of the second device under test.
4. The power semiconductor dynamic reverse bias test circuit according to claim 1, characterized in that: It also includes a protection circuit (5), which is located between the power supply VCC and the first device under test (DUT1) for overvoltage protection of the first device under test (DUT1) and the second device under test (DUT2).
5. The power semiconductor dynamic reverse bias test circuit according to claim 4, characterized in that: The protection circuit (5) includes a protection resistor R2, a second amplifier U2, a comparator U3, and a switching transistor Q1; The protective resistor R2 has one end connected to the first device under test DUT1 and the first input terminal of the second amplifier U2, and the other end connected to the source of the switching transistor Q1 and the second input terminal of the second amplifier U2. The comparator U3 has its first input terminal connected to the output terminal of the second amplifier U2, its second input terminal used to receive a reference voltage signal, and its output terminal connected to the gate of the switching transistor Q1; the drain of the switching transistor Q1 is connected to the power supply VCC.
6. The power semiconductor dynamic reverse bias test circuit according to claim 1, characterized in that: The first device under test (DUT1) has its first end connected to the power supply VCC, and its second end connected to the first end of the second device under test (DUT2) and the first driving circuit (2). The control terminal of the first device under test (DUT1) is connected to the first driving circuit (2). The second device under test (DUT2) has its second terminal connected to the second driving circuit (3), the switching circuit (1), and the measurement circuit (4), and its control terminal connected to the second driving circuit (3).
7. A method for dynamic reverse bias testing of power semiconductors, characterized in that: The working state is switched according to an external trigger signal, and the working state includes a stress application stage and a test stage. The first driving circuit (2) outputs a first driving signal to control the on / off state of the first device under test (DUT1); The second driving circuit (3) outputs a second driving signal to control the on / off state of the second device under test (DUT2); wherein, during the stress application stage, the second driving signal and the first driving signal are pulse complementary signals; during the test stage, the second driving signal and the first driving signal are DC complementary signals; the first device under test (DUT1) and the second device under test (DUT2) are connected in series. During the testing phase, the measurement circuit (4) outputs the test results of the first device under test and the test results of the second device under test.
8. The power semiconductor dynamic reverse bias test method according to claim 7, characterized in that: The testing phase includes a first testing phase and a second testing phase. During the testing phase, the measurement circuit (4) outputs the test results of the first device under test and the test results of the second device under test, specifically including: In the first test phase, the first drive circuit (2) outputs a first drive signal to control the first device under test (DUT1) to be turned off, and the second drive circuit (3) outputs a second drive signal to control the second device under test (DUT2) to be turned on. In response to the output of the test result of the first device under test by the measurement circuit (4), the first test phase ends and the second test phase begins; In the second test phase, the first drive circuit (2) outputs a first drive signal to control the first device under test (DUT1) to turn on, and the second drive circuit (3) outputs a second drive signal to control the second device under test (DUT2) to turn off, until the measurement circuit (4) outputs the test result of the second device under test.
9. The dynamic reverse bias test method for power semiconductors according to claim 8, characterized in that: When both the first device under test (DUT1) and the second device under test (DUT2) are P-type transistors, in the first test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal; in the second test phase, the first drive signal is a high-level signal and the second drive signal is a low-level signal. When both the first device under test (DUT1) and the second device under test (DUT2) are N-type transistors, in the first test phase, the first drive signal is a low-level signal and the second drive signal is a high-level signal; in the second test phase, the first drive signal is a low-level signal and the second drive signal is a high-level signal.
10. A testing device, characterized in that: Includes a power semiconductor dynamic reverse bias test circuit as described in any one of claims 1-6.