A hardware design verification method, device and storage medium

Abstract

The present disclosure relates to a hardware design verification method, device and storage medium. The method includes: determining a mixed language code for executing a target function for a register transfer level RTL module, the mixed language code is determined based on the parameters of the hardware design of the RTL module, the target function includes modifying the hardware design or verifying the hardware design, and the mixed language code includes an initial Python language code and at least one initial RTL-related language code; converting the initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code; generating a hardware design verification file based on the target RTL-related language code, and the hardware design verification file is used to determine a gate-level netlist to implement the target function for the hardware design. According to the embodiment of the present application, the efficiency of hardware design verification is improved and the error rate is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design and verification, and in particular to a hardware design verification method, device and storage medium. Background Art

[0002] Integrated circuits can include other programmable logic circuits such as field programmable gate arrays (FPGAs), and computer-aided integrated circuits such as application specific integrated circuits (ASICs). In the hardware design or verification of integrated circuits, the widely used programming languages ​​are register transfer level (RTL) related languages, which can be translated into gate-level netlists, and then traditional physical design tools can process the gate-level netlists into real hardware implementations.

[0003] In scenarios such as large-scale integration at the top level of a chip, there is a need to modify the hardware design on a large scale or verify the hardware design. However, existing technologies can usually only generate the top-level files of the module, and cannot automatically generate the underlying hardware design or verify the hardware design. The hardware design and verification process is complex, inflexible, and prone to errors. Therefore, a new hardware design verification method is urgently needed to reduce the workload of hardware design and verification, improve efficiency, and reduce the error rate. Summary of the invention

[0004] In view of this, the present disclosure proposes a hardware design verification method, device and storage medium.

[0005] According to one aspect of the present disclosure, a hardware design verification method is provided. The method comprises:

[0006] Determine a mixed language code for executing a target function for a register transfer level RTL module, the mixed language code is determined based on parameters of a hardware design of the RTL module, the target function includes modifying the hardware design or verifying the hardware design, and the mixed language code includes an initial Python language code and at least one initial RTL-related language code;

[0007] Converting an initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code;

[0008] A hardware design verification file is generated based on the target RTL related language code, and the hardware design verification file is used to determine the gate-level netlist to achieve the target function of the hardware design.

[0009] In a possible implementation, the parameters of the hardware design include one or more parameters including a unique identifier of an RTL module, and converting an initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code includes:

[0010] Based on the parameter containing the unique identifier of the RTL module, the unique identifier string in the mixed language code is replaced with the value of the parameter containing the unique identifier;

[0011] Convert the at least one initial RTL-related language code in the mixed language code into a Python language code, and use the converted Python language code and the initial Python language code as an intermediate Python language code;

[0012] Execute the intermediate Python language code and determine the target RTL related language code for the module.

[0013] In a possible implementation, the mixed language code is configured based on one or more of the following identifiers: a language distinguishing identifier, a retaining code identifier, a Python language code start identifier, a Python language code end identifier, and an indentation identifier.

[0014] In a possible implementation, determining a mixed language code for executing a target function for a register transfer level (RTL) module includes:

[0015] Insert the initial Python language code into a preset area in at least one initial RTL related language code to determine the mixed language code, the preset area includes: an area where the variable code in at least one initial RTL related language code is located, and an area where the code for controlling the variable is located.

[0016] In one possible implementation, the parameters of the hardware design also include the number of modules, the top-level names of the modules, variable strings in the signal names in the modules, the bit width parameters of the signals in the modules, and parameters indicating the hardware functions, and the initial Python language code includes code for parsing the parameters of the hardware design into Python variables.

[0017] In a possible implementation, the mixed language code further includes one or more language distinguishing identifiers, the language distinguishing identifiers are used to indicate whether the code line is a Python language code, at least one initial RTL-related language code in the mixed language code is converted into a Python language code, and the converted Python language code and the initial Python language code are used as intermediate Python language codes, including:

[0018] When the language distinguishing mark indicates that the code line is a Python language code, the initial Python language code in the code line is retained in the intermediate Python language code.

[0019] In a possible implementation, the mixed language code further includes maintaining a code identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0020] Keep the code in the mixed language code in the intermediate Python language code to keep the code mark line.

[0021] In a possible implementation, the mixed language code further includes a Python language code start identifier and a Python language code end identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0022] The initial Python language code within the Python language code start identifier and the Python language code end identifier in at least one initial RTL related language code is replaced with a parameter of a string type conversion function in the Python language.

[0023] In a possible implementation, the mixed language code further includes an indentation mark, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0024] According to the indentation mark, the space number of the predetermined step length is increased or decreased at the beginning of the predetermined line.

[0025] In a possible implementation, the initial Python language code further includes code for batch processing the initial RTL-related language code, where the batch processing includes loop copying or batch modifying the initial RTL-related language code.

[0026] In a possible implementation, the initial Python language code further includes code for selecting whether to display the initial RTL-related language code in the target RTL-related language code according to a parameter indicating a hardware function.

[0027] In a possible implementation, generating a hardware design verification file based on a target RTL-related language code includes:

[0028] Write the target RTL related language code of one or more RTL modules into the hardware design verification file, modify the file name of the hardware design verification file to generate the hardware design verification file, the file name of the hardware design verification file is related to any of the following:

[0029] The file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design.

[0030] According to another aspect of the present disclosure, a hardware design verification device is provided. The device includes:

[0031] A determination module is used to determine a mixed language code for executing a target function for a register transfer level RTL module, the mixed language code is determined based on parameters of a hardware design of the RTL module, the target function includes modifying the hardware design or verifying the hardware design, and the mixed language code includes an initial Python language code and at least one initial RTL-related language code;

[0032] A conversion module, used for converting an initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code;

[0033] The generation module is used to generate a hardware design verification file based on the target RTL related language code, and the hardware design verification file is used to determine the gate-level netlist to achieve the target function of the hardware design.

[0034] In a possible implementation, the hardware design parameters include one or more parameters including a unique identifier of an RTL module, and the conversion module is used to:

[0035] Based on the parameter containing the unique identifier of the RTL module, the unique identifier string in the mixed language code is replaced with the value of the parameter containing the unique identifier;

[0036] Convert at least one initial RTL-related language code in the mixed language code into a Python language code, and use the converted Python language code and the initial Python language code as an intermediate Python language code;

[0037] Execute the intermediate Python language code and determine the target RTL related language code for the module.

[0038] In a possible implementation, the mixed language code is configured based on one or more of the following identifiers: a language distinguishing identifier, a retaining code identifier, a Python language code start identifier, a Python language code end identifier, and an indentation identifier.

[0039] In a possible implementation, a module is determined to:

[0040] Insert the initial Python language code into a preset area in at least one initial RTL related language code to determine the mixed language code, the preset area includes: an area where the variable code in at least one initial RTL related language code is located, and an area where the code for controlling the variable is located.

[0041] In one possible implementation, the parameters of the hardware design also include the number of modules, the top-level names of the modules, variable strings in the signal names in the modules, the bit width parameters of the signals in the modules, and parameters indicating the hardware functions, and the initial Python language code includes code for parsing the parameters of the hardware design into Python variables.

[0042] In a possible implementation, the mixed language code further includes one or more language distinguishing identifiers, the language distinguishing identifiers are used to indicate whether the code line is a Python language code, at least one initial RTL-related language code in the mixed language code is converted into a Python language code, and the converted Python language code and the initial Python language code are used as intermediate Python language codes, including:

[0043] When the language distinguishing mark indicates that the code line is a Python language code, the initial Python language code in the code line is retained in the intermediate Python language code.

[0044] In a possible implementation, the mixed language code further includes maintaining a code identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0045] Keep the code in the mixed language code in the intermediate Python language code to keep the code mark line.

[0046] In a possible implementation, the mixed language code further includes a Python language code start identifier and a Python language code end identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0047] The initial Python language code within the Python language code start identifier and the Python language code end identifier in at least one initial RTL related language code is replaced with a parameter of a string type conversion function in the Python language.

[0048] In a possible implementation, the mixed language code further includes an indentation mark, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0049] According to the indentation mark, the space number of the predetermined step length is increased or decreased at the beginning of the predetermined line.

[0050] In a possible implementation, the initial Python language code further includes code for batch processing the initial RTL-related language code, where the batch processing includes loop copying or batch modifying the initial RTL-related language code.

[0051] In a possible implementation, the initial Python language code further includes code for selecting whether to display the initial RTL-related language code in the target RTL-related language code according to a parameter indicating a hardware function.

[0052] In a possible implementation, a module is generated to:

[0053] Write the target RTL related language code of one or more RTL modules into the hardware design verification file, modify the file name of the hardware design verification file to generate the hardware design verification file, the file name of the hardware design verification file is related to any of the following:

[0054] The file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design.

[0055] According to another aspect of the present disclosure, a hardware design verification device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0056] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0057] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0058] According to the embodiment of the present application, the mixed language code for executing the target function is determined by the parameters of the hardware design based on the RTL module, and the variable configuration file (i.e., the parameters of the RTL module hardware design) is separated from the relatively fixed mixed language code, so that one or more hardware design verification files of the same type can be generated by configuring a small amount of code, which can improve the reusability of the code, and one or more generated RTL-related language codes can be modified at the same time by modifying the configuration of the mixed language code once, thereby improving the efficiency of hardware design verification; by making the mixed language code include an initial Python language code and at least one initial RTL-related language code, it is more friendly to any integrated circuit-related technology, which is conducive to improving the efficiency of code writing; by utilizing the parameters containing the unique identifier of the RTL module, the mixed language code is processed to determine the target RTL-related language code of the module, which can realize automatic modification of the hardware design or verification of the hardware design, not only limited to the top-level file, but also can generate a hardware design verification file to achieve the target function, thereby reducing the workload, improving the efficiency, and reducing the error rate.

[0059] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0061] Figure 1 A schematic diagram showing an application scenario according to an embodiment of the present application.

[0062] Figure 2 A flowchart of a hardware design verification method according to an embodiment of the present application is shown.

[0063] Figure 3 A flowchart of a hardware design verification method according to an embodiment of the present application is shown.

[0064] Figure 4 A structural diagram of a hardware design verification device according to an embodiment of the present application is shown.

[0065] Figure 5 A structural diagram of a computer system 500 according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0066] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0067] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0068] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0069] Integrated circuits may include other programmable logic circuits such as field programmable gate arrays FPGAs, and computer-aided integrated circuits such as application-specific integrated circuits ASICs. In the hardware design or verification of integrated circuits, the widely used programming language is a register transfer level RTL-related language. The RTL-related language can be translated into a gate-level netlist, and then the traditional physical design tools can process the gate-level netlist into a real hardware implementation. In scenarios such as large-scale integration at the top level of a chip, there is a need to modify the hardware design on a large scale or to verify the hardware design. However, the existing technology can usually only generate the top-level file of the module, and cannot automatically generate the underlying hardware design or verify the hardware design. The complexity of hardware design and verification is high, not flexible enough and prone to errors. Therefore, there is an urgent need for a new hardware design verification method to reduce the workload during hardware design and verification, improve efficiency, and reduce the error rate.

[0070] In view of this, the present application proposes a hardware design verification method, device and storage medium. The hardware design verification method of the embodiment of the present application determines the mixed language code for executing the target function based on the parameters of the hardware design of the RTL module, separates the variable configuration file (i.e., the parameters of the RTL module hardware design) from the relatively fixed mixed language code, so that one or more hardware design verification files of the same type can be generated by configuring a small amount of code, which can improve the reusability of the code and if there is a need for modification later. By modifying the configuration of the mixed language code once, based on the method of the embodiment of the present application, one or more target RTL-related language codes can be converted according to the modified mixed language code, so as to achieve the effect of modifying one or more target RTL-related language codes at the same time, thereby improving the efficiency of hardware design verification; by making the mixed language code include the initial Python language code and at least one initial RTL-related language code, it is more friendly to integrated circuit-related technicians and is conducive to improving the efficiency of code writing; by utilizing the parameters containing the unique identifier of the RTL module, the mixed language code is processed to determine the target RTL-related language code of the module, so that the hardware design can be automatically modified or verified, which is not limited to the top-level file, and the hardware design verification file can be generated to achieve the target function, thereby reducing the workload, improving the efficiency, and reducing the error rate.

[0071] Figure 1 A schematic diagram showing an application scenario according to an embodiment of the present application is shown. Figure 1 As shown, the hardware design verification method of the embodiment of the present application can be used in the design or verification scenario of digital integrated circuits. Among them, the hardware design verification system of the present application can determine the parameters of the configured hardware design and the configured mixed language code including Python language code and at least one RTL related language code, and convert the mixed language code into RTL related language code (such as hardware description language (HDL)) based on the unique identification parameter of the RTL module. In this way, the hardware design verification file of one or more RTL related language codes can be automatically generated. Subsequently, the hardware design verification files of these RTL related language codes can be translated into the gate-level netlist of the chip through the existing logic synthesis tool, so that the gate-level netlist can be processed into a real hardware implementation using the existing physical design tools to modify the hardware design or verify whether the hardware design is reasonable.

[0072] For example, in scenarios such as large-scale integration at the top level of a chip, there is a need to modify the parameters of a module multiple times. When the amount of module code increases, the number of modifications will increase, and the resulting error rate will also be very high. Through the above-mentioned hardware design verification system, different mixed language codes can be determined according to the parameter configurations of different hardware designs. When there is a need to modify module parameters, only the configuration of the hardware design parameters needs to be modified once, and the corresponding hardware design verification file can be automatically generated based on the modified parameters through the configured mixed language code. There is no need for designers to manually modify the parameters in each code multiple times, which greatly improves efficiency and reduces error rates.

[0073] The above hardware design verification system can be deployed on a terminal device or a server. The server can be located locally or in the cloud. It can be a physical device or a virtual device, such as a virtual machine, a container, etc., and has a wireless communication function, wherein the wireless communication function can be set in the chip (system) or other parts or components of the server. The wireless communication function can be realized, for example, through mobile communication technologies such as 2G / 3G / 4G / 5G, as well as Wi-Fi, Bluetooth, frequency modulation (FM), digital radio, satellite communication, etc. Communication can also be carried out through wired connection to achieve interaction with other devices.

[0074] The following Figure 2 and Figure 3 , the hardware design verification method of the embodiment of the present application is introduced.

[0075] See also Figure 2 , showing a flowchart of a hardware design verification method according to an embodiment of the present application. The method can be used in the above-mentioned hardware design verification system, such as Figure 2 As shown, the method may include:

[0076] Step S201 : determining a mixed language code for executing a target function for a register transfer level (RTL) module.

[0077] The mixed language code may be determined based on parameters of the hardware design of the RTL module.

[0078] The parameters of the hardware design can be obtained through configuration. For example, the parameters can be configured through a file in a JSON file, a YAML file, an EXCEL file, or a combination of files in multiple formats, and the file can include the parameter name and parameter value.

[0079] The parameters of the hardware design may include one or more parameters containing a unique identifier of an RTL module, and there is a one-to-one mapping relationship between the unique identifier and the RTL module, and a certain RTL module can be uniquely identified by the unique identifier. Generally, the parameters containing the unique identifier of the RTL module may be private parameters of the RTL module (i.e., only acting on the specific RTL module).

[0080] Optionally, the parameters of the hardware design may also include the number of modules, the top-level name of the module, the variable character string in the signal name in the module, the bit width parameter of the signal in the module, and the parameter indicating the hardware function. These parameters may be used as the common parameters of the RTL module.

[0081] One or more submodules can be instantiated in each module, signals can be defined inside the submodules, and the top-level name of the module can identify the name of the top-level module of the one or more submodules. The parameter indicating the hardware function can be used to indicate whether the corresponding module has the corresponding hardware function.

[0082] Among them, for example, the number of modules can be a public parameter in the hardware design (i.e., it can be applied to all modules), and for example, the variable string in the signal name in the module, the bit width parameter of the signal in the module, the parameter indicating the hardware function, etc. can be a private parameter in the hardware (i.e., it can be applied to a certain module). The parameter name of the private parameter can include the unique identifier of the RTL module. Taking the file format of the configuration parameter as JSON as an example, in a certain section of parameter information in the JSON file, the parameter name of the bit width parameter of the signal in the module as a private parameter can be "Inst_0_Width", including the unique identifier of the RTL module "Inst_0".

[0083] According to the embodiments of the present application, the parameters are not limited to the top-level modules, and the parameters involved in various hardware design verification processes are comprehensively covered, so that more designs can be automatically modified or more hardware designs can be verified during the hardware design verification process, making the modification of hardware design or verification of hardware design more efficient and reducing the error rate.

[0084] The above-mentioned target function may include modifying the hardware design or verifying the hardware design, and the mixed language code may include an initial Python language code and at least one initial RTL-related language code.

[0085] Optionally, the RTL-related language may include one or more of the following:

[0086] HDL, JSON, YAML, Markdown, Makefile, scripting language (tool command language, TCL), verdi rc, Coverage exclusion, design constraint file (synopsys design constrains, SDC), lintwaiver, unified power format (unified power format, UPF), C / C++ language for generating hardware design verification files. Among them, HDL language includes but is not limited to Verilog, VHDL, ABEL, CUPL, AHDL, MACHX, PALASM, Systemverilog and any combination of the above.

[0087] According to the embodiments of the present application, by including one or more RTL-related languages ​​in the mixed language code, it is more friendly to digital integrated circuit technicians and is beneficial to improving the efficiency of writing hardware design or verification codes.

[0088] Mixed language codes can be pre-configured based on different target functions. The following is a detailed introduction to mixed language codes.

[0089] In S201, an initial Python language code may be inserted into a preset area in at least one initial RTL-related language code to determine a mixed language code.

[0090] The preset area includes: an area where a variable code in at least one initial RTL-related language code is located, and an area where a code for controlling a variable is located.

[0091] For example, the variable coding region in at least one initial RTL-related language code can be replaced with the variable coding of the initial Python language code, and the variable can be controlled by inserting the initial Python language code into the region where the coding for controlling the variable in the replaced at least one initial RTL-related language code is located. This is conducive to improving the writing efficiency of hardware design or verification code.

[0092] The present application does not limit the preset area, and it can also be other variable parts in at least one initial RTL related language code, wherein by inserting the initial Python language code, the change of at least one initial RTL related language code can be controlled.

[0093] The mixed language code may be configured based on one or more of the following identifiers: a language distinguishing identifier, a retaining code identifier, a Python language code start identifier, a Python language code end identifier, and an indentation identifier.

[0094] The language distinguishing mark can be used to indicate whether the code line is Python language code; the keep code mark can be used to retain the code of the line where the keep code mark is located in the mixed language code; the Python language code start mark and the Python language code end mark can be used to replace the initial Python language code with the parameters of the string type conversion function in the Python language; the indentation mark can be used to increase or decrease the number of spaces of a predetermined step at the beginning of a predetermined line.

[0095] The method of configuring mixed languages ​​using the above flags will be further introduced later.

[0096] In order to make the parameters of the hardware design more comprehensively applicable to various hardware design verification files, the mixed language code may optionally include code for parsing the parameters into Python variables.

[0097] The code used to parse the parameters into Python variables can be Python code. For example, the code can be a loading function of a JSON file, a loading code of a YAML file, a parsing code of an EXCEL file, or other parsing code containing a custom configuration method of parameter names and parameter values. The code used to parse the parameters into Python variables can also be a combination of one or more of the above codes.

[0098] An example of a Python variable is a variable of dictionary type, the key of the dictionary variable can be the parameter name, and the value can be the parameter value. For example, the Python language code "Para = my_function.ParseConfig()" can parse the parameter into the Python dictionary variable Para, and "my_function.ParseConfig()" can represent the parsing code of the custom configuration method.

[0099] According to the embodiments of the present application, parameters can be parsed into Python variables, so that the parameters of the hardware design can be more comprehensively applied to various hardware design verification files in the future without being limited to the top-level modules, making it more flexible to modify or verify the hardware design.

[0100] In order to convert the mixed language code into a single language code later, the mixed language code may include a language distinguishing mark to distinguish different languages ​​in the mixed language code. Optionally, the mixed language code may also include one or more language distinguishing marks.

[0101] The language distinguishing mark can be used to indicate the language type of the code line, indicating that the code line complies with the grammatical specification of the language of that type. For example, the language distinguishing mark can be used to indicate whether the code line is Python language code.

[0102] The form of the language distinguishing mark can be pre-set. For example, in the case of multiple different languages, the mixed language code can include multiple language distinguishing marks. For example, by adding a " <py> ”、" <verilog> ”、" <vhdl>" is used to distinguish Python, Verilog, and VHDL. In the case of two different languages ​​(such as Python and Verilog), only one language identifier can be used. <py>" can indicate that the code line is a Python type code. If there is no language distinguishing identifier, it can indicate that the code line is a Verilog type code.

[0103] In order to facilitate the conversion of the mixed language code, the mixed language code may also include a code retention mark, so that the corresponding code is retained when the mixed language code is subsequently converted. Optionally, the mixed language code may also include a code retention mark.

[0104] For example, a code retention mark may be added at the beginning of a code line to indicate that the code line is retained and not processed when the mixed language code is subsequently converted. The form of the code retention mark may be pre-set, for example, it may be " <kp>" as the retention code identification.

[0105] Since in the mixed language code, there may be a situation where the HDL-related language code is mixed with the Python language code, that is, the main body of the line of code belongs to the HDL-related language code and follows the grammatical specifications of the HDL-related language, but there is also a part of the Python language code in it. In order to distinguish different languages ​​in the same line of code, the Python language code start mark and the Python language code end mark can be added to the HDL-related language code line. Optionally, the mixed language code can also include the Python language code start mark and the Python language code end mark.

[0106] The Python language code in the Python language code start mark and the Python language code end mark may be data that can be converted into a string, for example, the Python language code may be a numerical variable, a string variable, a formula, a function, etc. that conforms to the Python language grammar specification. The form of the Python language code start mark and the Python language code end mark may be pre-set. For example, "<" may be used as the Python language code start mark, and ">" may be used as the Python language code end mark, and the code between "<" and ">" is the Python language code to be converted into a string.

[0107] Since the mixed language code can be configured in advance, in order to apply the mixed language code to the corresponding RTL module in the subsequent conversion process of the mixed language code, the code for filtering parameters can be added to the mixed language code so that the private parameters of the corresponding RTL module can be obtained during the conversion process.

[0108] Optionally, the mixed-language code may also include a code for filtering private parameters of a module by a unique identifier.

[0109] Through this code, the unique identification string therein can be replaced with the value of the parameter containing the unique identification. For example, the unique identification string in the code can be replaced with the value of the parameter containing the unique identification through parameter input methods such as argparse in the Python language, or an identifier representing the unique identification string of the RTL module, such as "<#ID>", can be added to the code. In the subsequent process of converting the code, the identifier of the string can be converted into a parameter containing the unique identification of the RTL module. Thus, the parameter name, parameter value, or a combination of the two of the private parameters including the unique identification of the RTL module can be filtered out by using the corresponding filtering code through the unique identification. For example, since the parameters can be parsed into Python dictionary variables in the above process, the parameter name, parameter value, or a combination of the two of the private parameters can be filtered out by extracting dictionary keys, values, key-value pairs, etc.

[0110] The mixed language code may also include code for extracting common parameters of the module, wherein the code may filter the common parameters of the module by using the above-mentioned method of extracting dictionary keys, values, key-value pairs, etc., through the identification of custom common parameters.

[0111] According to the embodiments of the present application, in the process of modifying or verifying the hardware design, the corresponding RTL modules and the mixed language codes can be associated with each other, and the corresponding private parameters of the modules can be screened according to the modification or verification requirements, so that the hardware design verification files can be automatically generated in batches and more flexibly to meet the needs of modification or verification of different hardware designs.

[0112] Since the syntax specifications of Python and HDL related languages ​​have different specifications for whether the beginning of the code lines of different functions need to be indented, it is impossible to use column operations to batch convert the code lines in this case. In order to enable the subsequent conversion of the mixed language code to quickly and accurately determine whether the relevant code lines are indented, relevant indentation marks can be added to the mixed language code. Optionally, the mixed language code can also include an indentation mark.

[0113] Among them, the indentation mark can include an indentation start mark and an indentation end mark, which can be used to indicate that the corresponding Python language code enters / exits a loop, selection, function, and other functional codes. The form of the indentation mark can be pre-set, and this application does not limit the form of the mark. For example, "#{" can be used as the indentation start mark and "#}" can be used as the indentation end mark.

[0114] Since the mixed language code can be configured in advance, in order to adapt to different RTL modules, the mixed language code can also choose to generate different codes according to different hardware design parameter configurations, hiding the codes under other configurations. For example, since the parameters of the hardware design can include parameters indicating the hardware functions, the initial Python language code can optionally include a code for selecting whether to display the initial RTL-related language code in the target RTL-related language code according to the parameters indicating the hardware functions.

[0115] Among them, the conditional selection code in the Python language code can be used to realize the selection of whether to display the initial RTL-related language code in the target RTL-related language code according to the parameters indicating the hardware function. For example, the "if" syntax in the Python language can be used. When the corresponding parameter indicates that the RTL module has the corresponding hardware function, the initial RTL-related language code related to the hardware function after the "if" syntax is displayed in the target RTL-related language code. Otherwise, the initial RTL-related language code related to the hardware function after the "if" syntax can be hidden in the target RTL-related language code.

[0116] According to the embodiments of the present application, the display of the initial RTL-related language code can be controlled based on the parameter configuration of different hardware designs, thereby improving the efficiency of hardware design modification or verification.

[0117] In order to further improve efficiency and implement batch processing of the initial RTL-related language code, optionally, the initial Python language code may also include code for the initial RTL-related language code.

[0118] The batch processing may include loop copying or batch modification of the initial RTL-related language code. The loop copying or batch modification of the initial RTL-related language code may be implemented through conditional loop codes in the Python language code. For example, the contents of the initial RTL-related language code corresponding to multiple RTL modules may be modified or copied regularly through the "for" syntax in the Python language.

[0119] According to an embodiment of the present application, by utilizing the initial Python language code in the mixed language code to batch process the initial RTL related language code, regular copying and modification can be achieved, which can improve the accuracy compared to manual copying or modification, and can further improve the writing efficiency of related hardware design or verification code, ultimately improving the overall efficiency of hardware design or verification.

[0120] In order to ensure the correctness of the compilation process and visualize the compilation process, optionally, the initial Python language code can also include a code for checking whether the parameter configuration is correct. In the case where the parameter configuration is incorrect, the code for checking whether the parameter configuration is correct can be used to print an error message.

[0121] For example, since the parameters of the hardware design have been parsed into the relevant Python variables in the above process, the code for checking whether the parameter configuration is correct can be used to check whether the relevant Python variable configuration is correct, for example, when the relevant Python variable is invalid, print an error message. The error message can be pre-set, for example, a string: "Error Config!", indicating a parameter configuration error.

[0122] Return to see Figure 2 Based on the above-mentioned mixed language code configuration specification, in the process of modifying or verifying the hardware design, the parameters containing the unique identifier of the RTL module can be obtained to map the configured mixed language code to the RTL module corresponding to the unique identifier, and determine the hardware design verification file for the RTL module, see below.

[0123] Step S202: converting the initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code.

[0124] For example, the configured parameters can be obtained through the unique identifier, and the mixed language code can be translated into the target RTL related language code through the designed compiler.

[0125] However, since the mixed language code may include Python language code such as conditional loops, it is relatively complicated to design a compiler to identify relevant keywords (such as "for") and then to copy the RTL related language code in a loop. Therefore, in the embodiment of the present application, the mixed language code can also be translated into an intermediate Python language code, that is, an intermediate Python script is generated, and then the target RTL related language code can be determined by executing the intermediate Python script. Thus, functions such as conditional selection and conditional loops can be directly implemented by executing Python scripts, which simplifies the compilation process. In addition, during the compilation process, the Python compiler can be used to detect problems in the mixed language code that do not conform to the grammatical specifications of the Python language, thereby ensuring the correctness of the hardware design modification or verification process. This process can be seen below Figure 3 Introduction in.

[0126] Figure 3 FIG. 1 is a flowchart of a hardware design verification method according to an embodiment of the present application. Figure 3 As shown, optionally, step S202 may include:

[0127] Step S301 : Based on the parameter containing the unique identifier of the RTL module, the unique identifier string in the mixed language code is replaced with the value of the parameter containing the unique identifier.

[0128] Among them, the parameter containing the unique identifier of the RTL module can be obtained through command line input. Based on the unique identifier contained in the parameter, the configured mixed language code can be mapped to the corresponding RTL module, so that the mixed language code is associated with the RTL module indicated by the unique identifier.

[0129] For example, the unique identification string in the mixed language code can be replaced with the value of the parameter containing the unique identification of the RTL module through parameter input methods such as argparse in the Python language. Alternatively, when there is an identifier representing the unique identification string of the RTL module in the mixed language code (such as "<#ID>"), the identifier of the string can be replaced with the value of the parameter containing the unique identification of the RTL module.

[0130] Step S302: convert at least one initial RTL-related language code in the mixed language code into a Python language code, and use the converted Python language code and the initial Python language code as an intermediate Python language code.

[0131] This process can be implemented based on a designed compiler, which can process the mixed language code based on the method described below to generate intermediate Python language code.

[0132] Optionally, step S302 may include:

[0133] Convert at least one initial RTL-related language code in the mixed-language code to a string in the Python language.

[0134] The content of the string may be an RTL-related language code, so as to facilitate the subsequent generation of a target RTL-related language code based on the intermediate Python language code.

[0135] According to the embodiment of the present application, the mixed language code can be unified into Python language code, and the characteristic of easy accumulation and concatenation of string variables in Python language is utilized in the conversion process, so that hardware design verification files based on RTL related languages ​​can be generated more conveniently later.

[0136] Optionally, in S302, it is possible to:

[0137] When the language distinguishing mark indicates that the code line is a Python language code, the initial Python language code in the code line is retained in the intermediate Python language code.

[0138] For example, when the language distinguishing mark indicates that the line of code is Python language code, the line of initial Python language code may be kept unchanged on the basis of removing the language distinguishing mark.

[0139] Optionally, when the language distinguishing identifier indicates that the line of code is non-Python language code (such as HDL language code), the HDL language code can be used as the content of the string variable in the Python language code on the basis of removing the language distinguishing identifier. To facilitate the subsequent generation of the target RTL language code, a newline character can also be added at the end of the string.

[0140] Optionally, in step S302, the following steps may be performed:

[0141] Keep the code in the mixed language code in the intermediate Python language code to keep the code mark line.

[0142] For example, for a code identifier such as " <kp>”) can keep the remaining code in the code line unchanged on the basis of removing the code mark.

[0143] According to the embodiments of the present application, it is possible to be more flexible when writing hardware design modification or verification codes, so that mixed language codes can meet the diverse needs in the hardware design verification process.

[0144] Optionally, in step S302, the following steps may be performed:

[0145] The Python language code within the Python language code start identifier and the Python language code end identifier in at least one initial RTL related language code is replaced with a parameter of a string type conversion function in the Python language.

[0146] The Python language code start mark and Python language code end mark usually appear in the code line of RTL related language. The Python language code in the two marks can be used as the parameter of the Python string type conversion function and spliced ​​into the corresponding position of the Python string corresponding to the RTL related language code in the line. For example, for " <width-1>", "<" can represent the start mark of Python language code, ">" can represent the end mark of Python language code, and "WIDTH-1" between the two belongs to Python language code. When the line of mixed language code is replaced, "WIDTH-1" can be used as a parameter of the conversion function to calculate the final data and converted into a string to be spliced ​​into the string corresponding to the line of code. Optionally, when the corresponding line of mixed language code is replaced, the Python variables between "<" and ">" can also be used to generate parameters recognizable by RTL related languages ​​(such as HDL) (such as the `define parameter in HDL), so that they can be converted into strings as RTL related language codes in the future to be spliced ​​into the string corresponding to the line of code.

[0147] According to the embodiments of the present application, it is possible to distinguish different languages ​​within the same line of code, and it is convenient to process the parameters of the hardware design during the process of hardware design modification or verification, thereby improving the efficiency of hardware design verification.

[0148] Optionally, step S302 may further include:

[0149] According to the indentation mark, the space number of the predetermined step length is increased or decreased at the beginning of the predetermined line.

[0150] For example, in the process of converting mixed language codes, based on the indentation marker, after removing the indentation marker, a predetermined number of spaces can be added to the beginning of a code line where an indentation start marker exists or the next code line of the code line. A predetermined number of spaces can also be reduced at the beginning of a code line where an indentation end marker exists or the next code line of the code line.

[0151] According to the embodiments of the present application, the problem of different indentation specifications for different types of languages ​​can be solved, so that in the process of converting mixed language codes, it is possible to quickly and accurately determine whether the relevant code lines are indented, achieve fast and correct batch conversion of code lines, and improve the efficiency of hardware design verification.

[0152] Step S303, executing the intermediate Python language code to determine the target RTL related language code for the module.

[0153] The target RTL-related language code for the module can be generated by executing the intermediate Python language code and accumulating string variables. In this case, the compiler can add the code for initializing the string variable and writing the hardware design verification file of the RTL-related language at the beginning and end of the intermediate Python language code, and the content in the final string variable is the RTL-related language code for the module.

[0154] You can also write a function and execute the intermediate Python code to write the generated string directly into the hardware design verification file of the RTL related language.

[0155] In the process of executing the intermediate Python language, by executing the conditional selection, conditional loop and other functions of the Python language, the initial RTL related language code can also be hidden, displayed and copied and modified in batches.

[0156] During the execution of the intermediate Python language, you can also execute the code used to check whether the parameter configuration is correct. If the parameter configuration is incorrect, print an error message.

[0157] For example, the code can check whether the relevant Python variables are configured correctly, for example, if the relevant Python variables are invalid, print an error message. The error message can be pre-set, for example, a string: "ErrorConfig!", indicating a parameter configuration error.

[0158] According to an embodiment of the present application, by replacing the unique identification string in the mixed language code with the value of the parameter containing the unique identification based on the unique identification of the RTL module, it is possible to associate the configured mixed language code with the corresponding RTL module, so that the parameters of the RTL module can be applicable to all hardware design verification files without being limited to the top-level module. By first generating an intermediate Python language code and then determining the target RTL-related language code for the module by executing the intermediate Python language code, it is possible to directly implement functions such as conditional selection and conditional looping by executing the Python script, thereby simplifying the compilation process. In addition, during the compilation process, the Python compiler can be used to detect problems in the mixed language code that do not conform to the grammatical specifications of the Python language, thereby ensuring the correctness of the hardware design modification or verification process and improving the efficiency of hardware design verification.

[0159] Step S203, generating a hardware design verification file based on the target RTL related language code.

[0160] Among them, the hardware design verification file can be used to determine the gate-level netlist. Through the existing physical design tools, the gate-level netlist can be processed into a real hardware implementation to achieve the target function of hardware design modification or hardware design verification.

[0161] The hardware design verification file may be based on an RTL-related language. The RTL-related language code obtained based on the above process may correspond to one or more RTL modules. The RTL-related language code of one or more modules may be written into a hardware design verification file.

[0162] When the target RTL-related language code for the module is generated by accumulating string variables, the content in the string variable can be written into the hardware design verification file through the code for writing the hardware design verification file of the RTL-related language in the string variable; the generated string can also be directly written into the hardware design verification file of the RTL-related language by writing a function and executing the intermediate Python code to generate a hardware design verification file.

[0163] According to the embodiment of the present application, the mixed language code for executing the target function is determined by the parameters of the hardware design based on the RTL module, and the variable configuration file (i.e., the parameters of the RTL module hardware design) is separated from the relatively fixed mixed language code, so that one or more hardware design verification files of the same type can be generated by configuring a small amount of code, which can improve the reusability of the code, and one or more generated RTL-related language codes can be modified at the same time by modifying the configuration of the mixed language code once, thereby improving the efficiency of hardware design verification; by making the mixed language code include an initial Python language code and at least one initial RTL-related language code, it is more friendly to any integrated circuit-related technology, which is conducive to improving the efficiency of code writing; by utilizing the parameters containing the unique identifier of the RTL module, the mixed language code is processed to determine the target RTL-related language code of the module, which can realize automatic modification of the hardware design or verification of the hardware design, not only limited to the top-level file, but also can generate a hardware design verification file to achieve the target function, thereby reducing the workload, improving the efficiency, and reducing the error rate.

[0164] In the process of generating the hardware design verification file, the file names of the hardware design verification file may also be modified in batches. Optionally, step S203 may include:

[0165] Write the target RTL related language code of one or more modules into the hardware design verification file, and modify the file name of the hardware design verification file to generate the hardware design verification file.

[0166] The method of writing the target RTL related language code into the hardware design verification file can be referred to above, wherein the file name of the hardware design verification file can be related to any of the following:

[0167] The file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design.

[0168] For example, the file name of the modified hardware design verification file can include the file name of the mixed language code or the unique identifier of the module or the name of the RTL module. The file name of the hardware design verification file can also be customized, such as the parameter name of the configured hardware design, which is not limited by this application.

[0169] According to an embodiment of the present application, by making the file name of the hardware design verification file related to any one of the file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design, the efficiency of the hardware design verification process can be further improved and the generated hardware design verification file can be made more standardized.

[0170] Figure 4 FIG. 2 shows a structural diagram of a hardware design verification device according to an embodiment of the present application. Figure 4 As shown, the device comprises:

[0171] A determination module 401 is used to determine a mixed language code for executing a target function for a register transfer level RTL module, the mixed language code is determined based on parameters of a hardware design of the RTL module, the target function includes modifying the hardware design or verifying the hardware design, and the mixed language code includes an initial Python language code and at least one initial RTL-related language code;

[0172] A conversion module 402, configured to convert an initial Python language code and at least one initial RTL-related language code in the mixed language code into a target RTL-related language code;

[0173] The generation module 403 is used to generate a hardware design verification file based on the target RTL related language code, and the hardware design verification file is used to determine the gate-level netlist to achieve the target function of the hardware design.

[0174] In a possible implementation, the hardware design parameters include one or more parameters including a unique identifier of an RTL module, and the conversion module 402 is used to:

[0175] Based on the parameter containing the unique identifier of the RTL module, the unique identifier string in the mixed language code is replaced with the value of the parameter containing the unique identifier;

[0176] Convert at least one initial RTL-related language code in the mixed language code into a Python language code, and use the converted Python language code and the initial Python language code as an intermediate Python language code;

[0177] Execute the intermediate Python language code and determine the target RTL related language code for the module.

[0178] In a possible implementation, the mixed language code is configured based on one or more of the following identifiers: a language distinguishing identifier, a retaining code identifier, a Python language code start identifier, a Python language code end identifier, and an indentation identifier.

[0179] In a possible implementation, the determination module 401 is configured to:

[0180] Insert the initial Python language code into a preset area in at least one initial RTL related language code to determine the mixed language code, the preset area includes: an area where the variable code in at least one initial RTL related language code is located, and an area where the code for controlling the variable is located.

[0181] In one possible implementation, the parameters of the hardware design also include the number of modules, the top-level names of the modules, variable strings in the signal names in the modules, the bit width parameters of the signals in the modules, and parameters indicating the hardware functions, and the initial Python language code includes code for parsing the parameters of the hardware design into Python variables.

[0182] In a possible implementation, the mixed language code further includes one or more language distinguishing identifiers, the language distinguishing identifiers are used to indicate whether the code line is a Python language code, at least one initial RTL-related language code in the mixed language code is converted into a Python language code, and the converted Python language code and the initial Python language code are used as intermediate Python language codes, including:

[0183] When the language distinguishing mark indicates that the code line is a Python language code, the initial Python language code in the code line is retained in the intermediate Python language code.

[0184] In a possible implementation, the mixed language code further includes maintaining a code identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0185] Keep the code in the mixed language code in the intermediate Python language code to keep the code mark line.

[0186] In a possible implementation, the mixed language code further includes a Python language code start identifier and a Python language code end identifier, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0187] The initial Python language code within the Python language code start identifier and the Python language code end identifier in at least one initial RTL related language code is replaced with the parameter of the string type conversion function in the Python language.

[0188] In a possible implementation, the mixed language code further includes an indentation mark, converting at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, including:

[0189] According to the indentation mark, the space number of the predetermined step length is increased or decreased at the beginning of the predetermined line.

[0190] In a possible implementation, the initial Python language code further includes code for batch processing the initial RTL-related language code, where the batch processing includes loop copying or batch modifying the initial RTL-related language code.

[0191] In a possible implementation, the initial Python language code further includes code for selecting whether to display the initial RTL-related language code in the target RTL-related language code according to a parameter indicating a hardware function.

[0192] In a possible implementation, the generating module 403 is used to:

[0193] Write the target RTL related language code of one or more RTL modules into the hardware design verification file, modify the file name of the hardware design verification file to generate the hardware design verification file, the file name of the hardware design verification file is related to any of the following:

[0194] The file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design.

[0195] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0196] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0197] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0198] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0199] Figure 5 FIG. 5 shows a structural diagram of a computer system 500 according to an embodiment of the present application. Figure 5 As shown, the computer system 500 may include a server 510, and the server 510 may include an input and output unit 512, a memory 514, and a processor 520. The term "computer-readable medium" in the present invention refers to any medium that participates in providing instructions to the processor 520, such as, but not limited to, optical disks, magnetic disks, read-only memories, random access memories, solid-state devices and drives, or any other tangible medium suitable for storing electrical signals, or computer-readable signal media, which may include transient media such as carrier waves.

[0200] The input / output unit 512 may be used to process inputs from the user interface 502 and the operation interface 504 , which may utilize input devices such as, but not limited to, a keyboard, a mouse, a touch device, or a voice command.

[0201] Server 510 may be connected to external storage 506, which may include removable storage, such as, but not limited to, a portable hard drive, optical media (CD or DVD), disk media, or any other medium from which a computer can read executable instructions. Server 510 may also be connected to output device 508, such as a display that outputs data and other information to a user, and requests additional information from a user. The connection between server 510 and user interface interface 502, operator interface interface 504, external storage 506, and output device 508 may be through a wireless protocol, such as, but not limited to, the 802.11 standard, Bluetooth, or mobile phone protocol, or through a physical transmission protocol, such as cable or optical fiber. Output device 508 may also further serve as an input device for interacting with a user.

[0202] The processor 520 may be configured to execute instructions to perform the above method. For example, the processor 520 may obtain the pre-configured hardware design parameters stored in the memory 514 and the mixed language code for executing the target function. The processor 520 may also obtain the parameters containing the unique identifier through the input and output unit 512, so that the processor 520 may process the mixed language code based on the parameters containing the unique identifier, determine the RTL-related language code for the module, and generate a hardware design verification file based on the RTL-related language code.

[0203] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0204] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0205] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0206] The computer program instructions for performing the disclosed operation may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of a computer-readable program instruction, and the electronic circuit may execute a computer-readable program instruction, thereby realizing various aspects of the present disclosure.

[0207] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0208] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0209] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0210] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0211] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. < / kp> < / kp> < / py> < / vhdl> < / verilog> < / py>

Claims

1. A hardware design verification method, characterized in that: The method comprises: Determine a mixed language code for executing a target function for a register transfer level (RTL) module, wherein the mixed language code is determined based on parameters of a hardware design of the RTL module, wherein the target function includes modifying the hardware design or verifying the hardware design, and wherein the mixed language code includes an initial Python language code and at least one initial RTL-related language code; Converting the initial Python language code and the at least one initial RTL-related language code in the mixed language code into a target RTL-related language code, wherein the target RTL-related language code is obtained by executing an intermediate Python language code, wherein the intermediate Python language code includes a converted Python language code and an initial Python language code, and wherein the converted Python language code is obtained by converting at least one initial RTL-related language code in the mixed language code into a Python language code; Generate a hardware design verification file based on the target RTL related language code, wherein the hardware design verification file is used to determine a gate-level netlist to implement the target function for the hardware design; The determining of a mixed language code for executing a target function for a register transfer level (RTL) module includes: Inserting an initial Python language code into a preset area in at least one initial RTL-related language code to determine the mixed language code, the preset area includes: an area where variable encoding is located in at least one initial RTL-related language code, and an area where encoding for controlling the variables is located, and the initial Python language code includes code for parsing parameters of the hardware design into Python variables.

2. The method according to claim 1, characterized in that The parameters of the hardware design include one or more parameters including a unique identifier of an RTL module, and the converting the initial Python language code and the at least one initial RTL-related language code in the mixed language code into a target RTL-related language code includes: Based on the parameter containing the unique identification of the RTL module, replacing the unique identification string in the mixed language code with the value of the parameter containing the unique identification of the RTL module; Converting the at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code; The intermediate Python language code is executed to determine the target RTL related language code for the module.

3. The method according to claim 1, characterized in that The mixed language code is configured based on one or more of the following identifiers: a language distinguishing identifier, a retaining code identifier, a Python language code start identifier, a Python language code end identifier, and an indentation identifier.

4. The method according to claim 1, characterized in that The parameters of the hardware design also include the number of modules, the top-level names of the modules, variable character strings in the signal names in the modules, bit width parameters of the signals in the modules, and parameters indicating hardware functions.

5. The method according to claim 2, characterized in that: The mixed language code further includes one or more language distinguishing marks, wherein the language distinguishing marks are used to indicate whether the code line is a Python language code. The converting the at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, includes: When the language distinguishing mark indicates that the code line is a Python language code, the initial Python language code in the code line is retained in the intermediate Python language code.

6. The method according to claim 2, wherein the mixed language code further comprises a code identification, wherein the converting the at least one initial RTL-related language code in the mixed language code into a Python language code and using the converted Python language code and the initial Python language code as an intermediate Python language code comprises: The code of the line where the retaining code identifier is located in the mixed language code is retained in the intermediate Python language code.

7. The method according to claim 2, characterized in that: The mixed language code further includes a Python language code start mark and a Python language code end mark, and the converting of the at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, includes: The initial Python language code from the Python language code start identifier to the Python language code end identifier in the at least one initial RTL related language code is replaced with a parameter of a string type conversion function in the Python language.

8. The method according to claim 2, characterized in that: The mixed language code further includes an indentation mark, and the converting the at least one initial RTL-related language code in the mixed language code into a Python language code, and using the converted Python language code and the initial Python language code as an intermediate Python language code, includes: According to the indentation mark, spaces of a predetermined step length are increased or decreased at the beginning of a predetermined line.

9. The method according to claim 2, characterized in that: The initial Python language code also includes code for batch processing of the initial RTL-related language code, wherein the batch processing includes cyclically copying or batch modifying the initial RTL-related language code.

10. The method according to claim 2, characterized in that The initial Python language code also includes code for selecting whether to display the initial RTL-related language code in the target RTL-related language code according to a parameter indicating a hardware function.

11. The method according to claim 1, characterized in that: The generating of the hardware design verification file based on the target RTL related language code includes: The target RTL-related language code of one or more RTL modules is written into the hardware design verification file, and the file name of the hardware design verification file is modified to generate the hardware design verification file, wherein the file name of the hardware design verification file is related to any one of the following: The file name of the mixed language code, the unique identifier of the RTL module, the name of the RTL module, and the parameter name of the customized hardware design.

12. A hardware design verification device, characterized in that: The device comprises: A determination module, configured to determine a mixed language code for executing a target function for a register transfer level (RTL) module, wherein the mixed language code is determined based on parameters of a hardware design of the RTL module, wherein the target function includes modifying the hardware design or verifying the hardware design, and wherein the mixed language code includes an initial Python language code and at least one initial RTL-related language code; a conversion module, configured to convert the initial Python language code and the at least one initial RTL-related language code in the mixed language code into a target RTL-related language code, wherein the target RTL-related language code is obtained by executing an intermediate Python language code, wherein the intermediate Python language code includes a converted Python language code and an initial Python language code, and wherein the converted Python language code is obtained by converting at least one initial RTL-related language code in the mixed language code into a Python language code; A generation module, used to generate a hardware design verification file based on the target RTL related language code, wherein the hardware design verification file is used to determine a gate-level netlist to implement the target function for the hardware design; The determining module is used to: Inserting an initial Python language code into a preset area in at least one initial RTL-related language code to determine the mixed language code, the preset area includes: an area where variable encoding is located in at least one initial RTL-related language code, and an area where encoding for controlling the variables is located, and the initial Python language code includes code for parsing parameters of the hardware design into Python variables.

13. A hardware design verification device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 11 when executing the instructions stored in the memory.

14. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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