A semiconductor power device and a method of manufacturing the same

Abstract

A semiconductor power device and a method for manufacturing the same. The semiconductor power device includes a semiconductor substrate layer, a drift layer on the semiconductor substrate layer, a gate structure in part of the drift layer or covering part of the upper surface of the drift layer, a well region in the drift layer on both sides of the gate structure in a width direction, a source region in part of the well region, a Schottky anode layer on part of the surface of the drift layer laterally away from the side of the gate structure and part of the surface of the well region, the Schottky anode layer being spaced from the source region, and a current blocking layer in the drift layer at the bottom of the well region. The semiconductor power device effectively suppresses bipolar degradation effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor power device and its fabrication method. Background Technology

[0002] Benefiting from its unipolar conduction transport mechanism and superior material properties, SiC-based MOSFETs often operate at higher frequencies than Si-based IGBTs at the same power density. Their larger bandgap and higher thermal conductivity also ensure safe and stable operation. Over the past decade, with improvements in substrate quality and advancements in fabrication technology, SiC-based MOSFETs have been increasingly used in photovoltaics, railways, and new energy vehicles. In practical applications, the body diode (PN junction) of a SiC-based MOSFET is often used as a freewheeling diode. However, due to the high bandgap of SiC (3.26 eV), the turn-on voltage of a SiC-based diode is much higher than that of a Si-based diode, leading to significant losses during the freewheeling phase. Furthermore, due to the numerous defects in SiC epitaxial materials, when the body diode is turned on, the recombination of electrons and holes causes stacking faults to propagate in the drift region, triggering a bipolar degradation effect and resulting in device performance degradation. While this problem can be solved by externally connecting a SiC Schottky diode in reverse parallel as a freewheeling diode, it leads to an increase in area and cost, severely limiting the miniaturization and high power density development of power electronic devices.

[0003] The SiC-based MOSFET structure with integrated Schottky diode can improve the third quadrant characteristics of SiC-based MOSFETs, suppress bipolar degradation effects, and optimize switching characteristics, giving SiC-based MOSFETs greater advantages in high-frequency applications.

[0004] However, the effectiveness of existing JBS-MOSFET integrated structures in suppressing bipolar degradation effects needs to be improved. Summary of the Invention

[0005] The technical problem to be solved by this invention is to overcome the fact that the effect of suppressing bipolar degradation effect in the prior art still needs to be improved.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; a gate structure located in a portion of the drift layer or covering a portion of the upper surface of the drift layer; a well region located in the drift layer on both sides of the gate structure in the width direction; a source region located in a portion of the well region; a Schottky anode layer located on a portion of the surface of the drift layer and a portion of the surface of the well region on the side of the well region laterally away from the gate structure, wherein the Schottky anode layer and the source region are spaced apart; and a current blocking layer located in the drift layer at the bottom of the well region.

[0007] Optionally, the conductivity type of the current blocking layer is the same as that of the well region, and the doping concentration of the current blocking layer is less than that of the well region; the current blocking layer is located in the drift layer at the bottom of the well region and is in contact with the bottom surface of the well region, and the current blocking layer is not located on the side of the well region; or, the current blocking layer is located in the drift layer at the bottom of the well region and also extends into the drift layer on the side of the well region laterally away from the gate structure, the current blocking layer at the bottom of the well region is spaced from the well region, and the current blocking layer located on the side of the well region is in contact with the sidewall of the well region and / or the Schottky anode layer.

[0008] Optionally, the doping concentration of the current blocking layer is 0.01 to 0.5 times that of the doping concentration of the well region.

[0009] Optionally, the doping concentration of the current blocking layer is 1×10⁻⁶. 16 atom / cm 3 ~5×10 17 atom / cm 3 .

[0010] Optionally, the longitudinal distance between the current blocking layer at the bottom of the well region and the well region is less than or equal to 1 micrometer.

[0011] Optionally, the current blocking layer is a semi-insulating layer or an insulating layer; the current blocking layer is in contact with or spaced from the bottom surface of the well region.

[0012] Optionally, the longitudinal distance between the top surface of the current blocking layer and the bottom surface of the well region is less than or equal to 1 micrometer.

[0013] Optionally, the semi-insulating layer is an Ar-doped region.

[0014] Optionally, the insulating layer is made of SiO2.

[0015] Optionally, the thickness of the current blocking layer located at the bottom of the well region is 0.1µm to 1µm.

[0016] Optionally, the gate structure is located in a portion of the drift layer, the source region is in contact with the sidewall of the gate structure, and the current blocking layer is spaced apart from the sidewall of the gate structure.

[0017] Optionally, the lateral spacing between the current blocking layer at the bottom of the well region and the sidewall of the gate structure is 0.1µm to 1µm.

[0018] Optionally, it further includes: a doped protective layer located in the drift layer, the doped protective layer including a main doped protection zone and a connecting doped zone, the main doped protection zone being located in the drift layer at the bottom of the gate structure and in contact with the bottom surface of the gate structure, the connecting doped zone being located on a portion of the sidewall surface on both sides of the gate structure in the width direction, the connecting doped zone connecting the well region and the main doped protection zone, the dimension of the connecting doped zone in the length direction of the gate structure being much smaller than the dimension of the main doped protection zone in the length direction of the gate structure and much smaller than the dimension of the current blocking layer in the length direction of the gate structure; the conductivity type of the doped protective layer is the same as the conductivity type of the well region, and the doping concentration of the doped protective layer is greater than or equal to the doping concentration of the well region; the semiconductor power device further includes: a secondary current blocking layer located in the drift layer at the bottom of the main doped protection zone, the secondary current blocking layer being in contact with or spaced from the bottom surface of the main doped protection zone.

[0019] Optionally, the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is less than that of the primary doped protective layer.

[0020] Optionally, the semiconductor power device further includes: a front electrode, which is in contact with the source region and the Schottky anode layer; when the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the secondary current blocking layer is spaced apart from the bottom surface of the main doped protective layer, the secondary current blocking layer also extends into the drift layers on both sides of the gate structure in the length direction and is in contact with the front electrode.

[0021] Optionally, the secondary current blocking layer is a semi-insulating layer or an insulating layer.

[0022] Optionally, it further includes: a JFET region; the well region is located on both sides of the JFET region in the width direction of the gate structure; the well region has a channel region located between the source region and the JFET region; the gate structure is located above the JFET region and spans a portion of the source region and the channel region on both sides of the JFET region; the current blocking layer does not extend below the JFET region.

[0023] The present invention also provides a method for fabricating a semiconductor power device, comprising: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming a well region in the drift layer; forming a current blocking layer in the drift layer, the current blocking layer being located in the drift layer at the bottom of the well region; forming a source region in a portion of the well region; forming a gate structure in a portion of the drift layer or on a portion of the upper surface of the drift layer, the well region being located on both sides of the gate structure in the width direction; forming a Schottky anode layer, the Schottky anode layer being located on a portion of the drift layer and a portion of the well region on the side of the well region laterally away from the gate structure, the Schottky anode layer being spaced apart from the source region.

[0024] Optionally, the conductivity type of the current blocking layer is the same as that of the well region, and the doping concentration of the current blocking layer is less than that of the well region; the current blocking layer is located in the drift layer at the bottom of the well region and is in contact with the bottom surface of the well region, and the current blocking layer is not located on the side of the well region; or, the current blocking layer is located in the drift layer at the bottom of the well region and also extends into the drift layer on the side of the well region laterally away from the gate structure, the current blocking layer at the bottom of the well region is spaced from the well region, and the current blocking layer located on the side of the well region is in contact with the sidewall of the well region and / or the Schottky anode layer.

[0025] Optionally, the current blocking layer is a semi-insulating layer or an insulating layer; the current blocking layer is in contact with or spaced from the bottom surface of the well region.

[0026] Optionally, the drift layer has a JFET region; the well region is located on both sides of the JFET region in the width direction of the gate structure; the well region has a channel region located between the source region and the JFET region; the step of forming a gate structure on a portion of the upper surface of the drift layer is: forming a gate structure above the JFET region and above a portion of the source region on both sides of the JFET region and above the channel region; the current blocking layer does not extend below the JFET region.

[0027] Optionally, a gate structure is formed in a portion of the drift layer; the source region is in contact with the sidewall of the gate structure; and the current blocking layer is spaced apart from the sidewall of the gate structure.

[0028] Optionally, the method further includes: forming a doped protective layer in the drift layer, the doped protective layer including a main doped protection zone and a connecting doped zone, the main doped protection zone being located in the drift layer at the bottom of the gate structure and in contact with the bottom surface of the gate structure, the connecting doped zone being located on a portion of the sidewall surface of the gate structure in the width direction, the connecting doped zone connecting the well region and the main doped protection zone, the dimension of the connecting doped zone in the length direction of the gate structure being much smaller than the dimension of the main doped protection zone in the length direction of the gate structure and much smaller than the dimension of the current blocking layer in the length direction of the gate structure, the conductivity type of the doped protective layer being the same as the conductivity type of the well region, and the doping concentration of the doped protective layer being greater than or equal to the doping concentration of the well region; and forming a secondary current blocking layer in the drift layer at the bottom of the main doped protection zone, the secondary current blocking layer being in contact with or spaced from the bottom surface of the main doped protection zone.

[0029] Optionally, the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is less than that of the primary doped protective layer.

[0030] Optionally, when the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the secondary current blocking layer is spaced apart from the bottom surface of the main doped protective layer, the secondary current blocking layer also extends into the drift layers on both sides of the gate structure in the length direction; the method for fabricating the semiconductor power device further includes: forming a front electrode, the front electrode being in contact with the source region, the Schottky anode layer and the secondary current blocking layer.

[0031] Optionally, the secondary current blocking layer is a semi-insulating layer or an insulating layer.

[0032] The technical solution of this invention has the following technical effects:

[0033] The semiconductor power device provided by this invention comprises a Schottky diode consisting of a Schottky anode layer and a drift layer at the bottom of the Schottky anode layer. When the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, electron current flows through the Schottky diode but not through the channel region and the source region. A current blocking layer is provided in the drift layer at the bottom of the well region. When the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the injection efficiency of the current blocking layer into the drift layer at the bottom of the current blocking layer is relatively small. Alternatively, the current blocking layer increases the barrier height for the well region to inject holes into the drift layer, making it more difficult for the well region to inject holes into the drift layer. This reduces the probability of electron-hole recombination and effectively suppresses the propagation of stacking faults in the drift layer caused by electron-hole recombination, thus effectively reducing the bipolar degradation effect. Attached Figure Description

[0034] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a semiconductor power device;

[0036] Figure 2 A schematic diagram of a semiconductor power device provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0038] Figure 4 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0039] Figure 5 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0040] Figure 6 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0041] Figure 7 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0042] Figure 8 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0043] Figure 9 A schematic diagram of a semiconductor power device provided in another embodiment of the present invention;

[0044] Figures 10 to 14 A structural diagram illustrating the fabrication process of a semiconductor power device according to an embodiment of the present invention;

[0045] Figure 15 A structural diagram illustrating the fabrication process of a semiconductor power device according to another embodiment of the present invention;

[0046] Figures 16 to 19 This is a structural diagram illustrating the fabrication process of a semiconductor power device according to another embodiment of the present invention. Detailed Implementation

[0047] A semiconductor power device, reference Figure 1It includes: a semiconductor substrate layer 100; a drift layer 110; a gate structure 180; a well region 120; a source region 130; a Schottky anode layer 150; a JFET region 101; and a drain metal region 102. The Schottky anode layer 150 and the drift layer 110 at the bottom of the Schottky anode layer 150 constitute a Schottky diode. When the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region 102, the electron current (e.g., ...) Figure 1 The direction indicated by the solid arrow in the middle) flows through the Schottky diode, and there is also a portion of hole current (such as...). Figure 1 (The direction indicated by the dashed line arrow) The propagation of stacking faults caused by electron-hole recombination in the drift layer also exhibits a bipolar degradation effect.

[0048] Based on this, the present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer; a gate structure located in a portion of the drift layer or covering a portion of the upper surface of the drift layer; a well region located in the drift layer on the side of the gate structure; a source region located in a portion of the well region; a Schottky anode layer located on a portion of the surface of the drift layer and a portion of the surface of the well region on the side of the source region laterally away from the gate structure, wherein the Schottky anode layer and the source region are spaced apart; and a current blocking layer located in the drift layer at the bottom of the well region. The semiconductor power device can effectively reduce bipolar degradation effects.

[0049] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0052] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0053] Example 1

[0054] One embodiment of the present invention provides a semiconductor power device, with reference to... Figure 2 ,include:

[0055] Semiconductor substrate layer 100;

[0056] Drift layer 110 located on the semiconductor substrate layer 100;

[0057] Gate structure 180 covers part of the upper surface of drift layer 110;

[0058] Well regions 120 located in the drift layers 110 on both sides of the gate structure 180 in the width direction;

[0059] Source region 130 is located in a portion of the well region 120;

[0060] Schottky anode layer 150 is located on a portion of the surface of drift layer 110 and a portion of the surface of well region 120 on the side of well region 120 that is laterally away from gate structure 180. Schottky anode layer 180 and source region 130 are spaced apart.

[0061] A current blocking layer 160 is located in the drift layer 110 at the bottom of the well region 120.

[0062] In this embodiment, a SiC-based semiconductor power device is used as an example for illustration. Accordingly, the semiconductor substrate 100 is silicon carbide (SiC) doped with conductive ions. New-generation semiconductor power devices, represented by SiC, possess higher reverse breakdown voltage, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance, and are therefore considered a new hope in the field of power conversion. It should be noted that the material of the semiconductor substrate 100 is not limited in this embodiment. In one embodiment, the conductive ions in the semiconductor substrate 100 are N-type ions.

[0063] In one embodiment, the drift layer 110 is doped with N-type conductive ions. Further, the material of the drift layer is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the drift layer 110 can also be other materials. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0064] The conductivity type of the well region 120 is opposite to that of the drift layer 110. In this embodiment, when the conductivity type of the drift layer 110 is N-type, the conductivity type of the well region 120 is P-type.

[0065] The conductivity type of the source region 130 is opposite to that of the well region 120. In this embodiment, when the conductivity type of the well region 120 is P-type, the conductivity type of the source region 130 is N-type.

[0066] In this embodiment, the semiconductor power device further includes: a JFET region 101; a well region 120 located on both sides of the JFET region 101 in the width direction of the gate structure 180; the well region 120 having a channel region 140 located between the source region 130 and the JFET region 101. The current blocking layer 160 does not extend below the JFET region 101.

[0067] In this embodiment, the gate structure 180 is located above the JFET region 101 and spans a portion of the source region 130 and the channel region 140 on both sides of the JFET region 101. The gate structure 180 includes a gate dielectric layer 181 and a gate electrode layer 182, with the gate electrode layer 182 located on the gate dielectric layer 181. The gate dielectric layer 181 is made of silicon oxide, and the gate electrode layer 182 is made of polysilicon. In one embodiment, the well region 120 is located in the drift layers 110 on both sides of the width direction of the gate structure 180.

[0068] In this embodiment, the Schottky anode layer 150 is located on a portion of the surface of the drift layer 110 and the surface of the well region 120, on the side of the well region 120 laterally away from the gate structure 180. The Schottky anode layer 150 and the source region 130 are spaced apart. In this embodiment, the semiconductor power device further includes a drain metal region 102, located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 110. The gate structure 180, well region 120, source region 130, drift layer 110, semiconductor substrate layer 100, and drain metal region 102 are used to form a metal-oxide-semiconductor field-effect transistor (MOSFET). The Schottky anode layer 150 and the drift layer 110 at the bottom of the Schottky anode layer 150 form a Schottky diode. When the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the electron current flows through the Schottky diode but not through the channel region and the source region 130. Figure 2 The solid arrows in the diagram indicate the direction of the electron current. In this embodiment, the Schottky diode and the metal-oxide-semiconductor field-effect transistor are integrated together. When the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region, the turn-on of the body diode formed by the body well region 120 and the drift layer 110 at the bottom of the well region 120 is suppressed to a certain extent. This improves the third quadrant characteristics of the MOSFET to a certain extent, suppresses the bipolar degradation effect, and optimizes the switching characteristics. Optimized switching characteristics mean that the on-state voltage drop of the semiconductor power device is lower when the Schottky diode is turned on. The on-state voltage drop of the semiconductor power device is equal to the voltage difference between the source region 130 and the drain metal region, resulting in lower conduction losses.

[0069] The current blocking layer 160 does not extend below the JFET region 101. The purpose is to prevent the current blocking layer 160 from blocking the path of the MOSFET forward current (the path from the region near the well region 120 in the JFET region 101 down to the drain metal region 160) when the MOSFET is forward-biased (the gate structure is turned on and the potential applied to the source region 130 is lower than the potential applied to the drain metal region).

[0070] In this embodiment, the current blocking layer 160 is located in the drift layer 110 at the bottom of the well region 120 and extends into the drift layer 110 on the side of the well region 120 laterally away from the gate structure 180. The current blocking layer 160 at the bottom of the well region 120 is spaced apart from the well region 120. The current blocking layer 160 located on the side of the well region 120 is in contact with the sidewall of the well region 120 and with the Schottky anode layer 150. The contact between the current blocking layer 160 and the Schottky anode layer 150 makes the current blocking layer 160 and the Schottky anode layer 150 at the same potential.

[0071] In this embodiment, the conductivity type of the current blocking layer 160 is the same as that of the well region 120, and the doping concentration of the current blocking layer 160 is less than that of the well region 120.

[0072] In this embodiment, based on the Schottky anode layer 150, a current blocking layer 160 is provided in the drift layer 110 at the bottom of the well region 120. Since the doping concentration of the current blocking layer 160 is lower than that of the well region 120, when the gate structure 180 is turned off and the potential applied to the source region 130 is higher than that applied to the drain metal region, the injection efficiency of holes injected from the current blocking layer 160 at the bottom of the well region 120 to the drift layer 110 at the bottom of the current blocking layer 160 is reduced. This reduces the probability of electron-hole recombination and effectively suppresses the propagation of stacking faults in the drift layer caused by electron-hole recombination, thus effectively reducing the bipolar degradation effect. Since the current blocking layer 160 is at the same potential as the Schottky anode layer 150, when the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region, the voltage across the body diode formed by the well region 120 and the drift layer 110 at the bottom of the well region 120 is less than the turn-on voltage of the body diode. Thus, the body diode formed by the well region 120 and the drift layer 110 at the bottom of the well region 120 is clamped and difficult to conduct.

[0073] In this embodiment, when the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region, the body diode formed by the well region 120 and the drift layer 110 at the bottom of the well region 120 is not conducting. The current blocking layer 160 effectively controls the carrier type of the MOSFET during freewheeling, ensuring that only electrons participate in conduction during freewheeling. This not only effectively improves the reverse recovery characteristics but also avoids bipolar degradation caused by electron-hole recombination in bipolar transport, increasing device reliability. Since there is no excess carrier storage, the reverse recovery characteristics are improved, and the reverse recovery power consumption is reduced.

[0074] Because the bipolar degradation effect is effectively reduced, the performance degradation of semiconductor power devices is effectively avoided, thus improving the long-term reliability of semiconductor power devices.

[0075] In this embodiment, the semiconductor power device further includes: a front electrode 170, which contacts the source region 130 and the Schottky anode layer 150; and an isolation dielectric layer 190, which surrounds the side surface and top surface of the gate electrode layer 182. The front electrode 170 covers the gate structure 180, and the isolation dielectric layer 190 isolates the front electrode 170 and the gate electrode layer 182. The material of the isolation dielectric layer 190 includes silicon oxide. In this embodiment, it also includes: a drain metal region 102 located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 110.

[0076] In one embodiment, the doping concentration of the current blocking layer 160 is 0.01 to 0.5 times that of the doping concentration of the well region 120, for example, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.2, 0.3, 0.4, or 0.5 times. The doping concentration of the current blocking layer 160 is less than or equal to 0.5 times the doping concentration of the well region 120. This means that when the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region, the injection efficiency of the current blocking layer 160 at the bottom of the well region 120 into the drift layer 110 at the bottom of the current blocking layer 160 is reduced to a greater extent, which more effectively improves the bipolar degradation effect. However, if the doping concentration of the current blocking layer 160 is less than 0.01 times the doping concentration of the well region 120, the doping concentration of the current blocking layer 160 is too small, which makes it easy for the current blocking layer 160 at the bottom of the well region 120 to be completely depleted. On the one hand, the current blocking layer 160 and the Schottky anode layer 150 are likely to lose their equipotential function, and the body diode is difficult to clamp. On the other hand, the potential barrier between the current blocking layer 160 and the drift layer 110 is low. Therefore, the blocking effect of the current blocking layer 160 on the holes that may be injected into the body diode is weakened.

[0077] In one embodiment, the doping concentration of the current blocking layer 160 is 1×10⁻⁶. 16 atom / cm 3 ~5×10 17 atom / cm 3 .

[0078] It should be noted that the doping concentration of well region 120 cannot be too low. This is because if the doping concentration of well region 120 is too low, during the reverse breakdown voltage process of the semiconductor power device (when the gate structure is turned off and the potential applied to source region 130 is lower than the potential applied to drain metal region), the body diode formed by well region 120 and the drift layer 110 at the bottom of well region 120 will bear a reverse bias voltage. The depletion layer in well region 120 will have a large unfolding thickness, and the depletion layer will contact the front electrode 170, which will cause the body diode to punch through. Therefore, reducing the doping concentration of well region 120 cannot be used to reduce the bipolar degradation effect.

[0079] In one embodiment, the longitudinal distance between the current blocking layer 160 at the bottom of the well region 120 and the well region 120 is less than or equal to 1 micrometer and greater than 0 micrometer, for example, 1 micrometer, 8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer, or 0.01 micrometer. The advantage of this arrangement is that it prevents the current blocking layer 160 at the bottom of the well region 120 from being too far from the well region 120. If the distance is too great, the drift layer 110 sandwiched between the well region 120 and the current blocking layer 160 at the bottom of the well region 120 may not be completely depleted. In this case, it only changes the path of the hole current in the body diode. When the body diode is turned on, the hole current of the body diode will flow through the drift layer 110 below the JFET region 101, and the blocking effect of the current blocking layer 160 on the hole current of the body diode is weakened. The longitudinal distance between the current blocking layer 160 at the bottom of the well region 120 and the well region 120 refers to the distance between the top surface of the current blocking layer 160 at the bottom of the well region 120 and the bottom surface of the well region 120. The longitudinal distance between the current blocking layer 160 at the bottom of the well region 120 and the well region 120 is greater than 0 micrometers, that is, the current blocking layer 160 at the bottom of the well region 120 and the well region 120 are spaced apart. The advantage is that the current blocking layer 160 at the bottom of the well region 120 and the drift layer 110 between the current blocking layer 160 and the well region 120 form a PN junction, and the drift layer between the current blocking layer 160 and the well region 120 forms a PN junction with the well region 120. In this way, when the gate structure is turned off and the potential applied on the source region is higher than the potential applied on the drain metal region, these two PN junctions form a potential barrier for holes in the well region 120, thus better preventing holes in the well region 120 from being injected into the drift layer 110 at the bottom of the current blocking layer 160.

[0080] In this embodiment, when the gate structure 180 is turned off and the potential applied to the source region 130 is higher than the potential applied to the drain metal region, the drift layer 110 located between the well region 120 and the current blocking layer 160 at the bottom of the well region 120 is completely depleted. The potential barriers that the holes in the well region 120 need to overcome include the potential barrier between the well region 120 and the drift layer 110 at the bottom of the well region 120, as well as the potential barrier between the drift layer 110 and the current blocking layer 160. In this way, the blocking effect of the current blocking layer 160 on the holes of the body diode is enhanced.

[0081] In one embodiment, the thickness of the current blocking layer 160 located at the bottom of the well region 120 is 0.1µm to 1µm. This design has the advantage that if the thickness of the current blocking layer 160 at the bottom of the well region 120 is too small, it is easily depleted. On the one hand, the current blocking layer 160 and the Schottky anode layer 150 easily lose their equipotential function, making it difficult to clamp the body diode. On the other hand, the potential barrier between the current blocking layer 160 and the drift layer 110 is low, thus weakening the blocking effect of the current blocking layer 160 on holes that may be injected into the body diode, and reducing its current blocking effect. Conversely, if the thickness of the current blocking layer 160 at the bottom of the well region 120 is too large, it will be detrimental to reducing the on-resistance of the MOSFET when the gate structure 180 is turned on and the potential applied to the source region 130 is lower than the potential applied to the drain metal region.

[0082] Example 2

[0083] The difference between this embodiment and Embodiment 1 is that: (Refer to...) Figure 3 The current blocking layer 160a located on the side of the well region 120 is in contact with the Schottky anode layer 150 but not with the sidewall of the well region 120.

[0084] The description of the current blocking layer 160a at the bottom of the well region 120 is the same as that of the current blocking layer 160 at the bottom of the well region 120 in Example 1.

[0085] Figure 3 The solid arrow in the image indicates the direction of the electron current.

[0086] All other aspects of this embodiment are the same as those in Embodiment 1, and will not be described in detail here.

[0087] Example 3

[0088] The difference between this embodiment and Embodiment 1 is that: (Refer to...) Figure 4 The current blocking layer 160b located on the side of the well region 120 is in contact with the sidewall of the well region 120 but not with the Schottky anode layer 150.

[0089] Since the current blocking layer 160b on the side of the well region 120 is in contact with the sidewall of the well region 120, when the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the voltage difference between the well region 120 and the body diode formed by the drift layer 110 at the bottom of the well region 120 is very small. Thus, the body diode formed by the well region 120 and the drift layer 110 at the bottom of the well region 120 is clamped and difficult to conduct.

[0090] The description of the current blocking layer 160b at the bottom of the well region 120 is the same as that of the current blocking layer 160 at the bottom of the well region 120 in Example 1.

[0091] Figure 4 The solid arrow in the image indicates the direction of the electron current.

[0092] All other aspects of this embodiment are the same as those in Embodiment 1, and will not be described in detail here.

[0093] Example 4

[0094] The difference between this embodiment and Embodiment 1 is that: (Refer to...) Figure 5 The gate structure 180c is located in a portion of the drift layer 110, the well region 120 is located on both sides of the gate structure 180c in the width direction, the source region 130c is in contact with the sidewall of the gate structure 180c, and the current blocking layer 160c is spaced apart from the sidewall of the gate structure 180c. In one embodiment, the well region 120 surrounds the gate structure 180c.

[0095] The current blocking layer 160c is located in the drift layer 110 at the bottom of the well region 120 and also extends into the drift layer 110 on the side of the well region 120 laterally away from the gate structure 180c. The current blocking layer 160c at the bottom of the well region 120 is spaced apart from the well region 120. The current blocking layer 160c located on the side of the well region 120 is in contact with the sidewall of the well region 120 and in contact with the Schottky anode layer 150.

[0096] For a description of the concentration, thickness, and distance from the trap region of the current blocking layer 160c, please refer to Example 1.

[0097] The gate structure 180c includes a gate dielectric layer 181c and a gate electrode layer 182c. The gate dielectric layer 181c is located at the bottom and sidewall of the gate electrode layer 182c. The material of the gate dielectric layer 181c includes silicon oxide, and the material of the gate electrode layer 182c includes polysilicon.

[0098] The semiconductor power device further includes an isolation dielectric layer 190c covering the top surface of the gate electrode layer 182c. Further, to better isolate the gate electrode layer 182c and the front electrode 170c, the isolation dielectric layer 190c covers the top surface of the gate electrode layer 182c and a portion of the surface of the source region 130c. The material of the isolation dielectric layer 190c includes silicon oxide. The front electrode 170c covers the isolation dielectric layer 190c, a portion of the surface of the source region 130c, and the Schottky anode layer 150. The semiconductor power device also includes an ohmic contact region 131c, the conductivity type of which is opposite to that of the source region 130c, and the Schottky anode layer 150 covers a portion of the surface of the ohmic contact region 131c.

[0099] In this embodiment, the current blocking layer 160c is spaced apart from the sidewall of the gate structure 180c. The purpose of this arrangement is to prevent the current blocking layer 160c from blocking the flow path of the forward current (the area of ​​the source region 130c near the gate structure 180c passes downward through the well region 120 and the drift layer 110, the semiconductor substrate layer 100 and the drain metal region 102) when the MOSFET is forward-biased (when the gate structure 180c is turned on and the potential applied to the source region 130 is lower than the potential applied to the drain metal region).

[0100] In one embodiment, the lateral spacing between the current blocking layer 160c at the bottom of the well region 120 and the sidewall of the gate structure 180c is 0.1µm to 1µm, for example, 0.1µm, 0.3µm, 0.5µm, 0.8µm or 1µm.

[0101] In this embodiment, it further includes: a doping protection layer located in the drift layer 110, the doping protection layer including a main doping protection zone 200 and a connection doping region (not shown), the main doping protection zone 200 being located in the drift layer 110 at the bottom of the gate structure 180c and in contact with the bottom surface of the gate structure 180c, the connection doping region being located on a portion of the sidewall surface of the gate structure 180c on both sides in the width direction, the connection doping region connecting the well region 120 and the main doping protection zone 200, the connection doping region having a dimension far greater than that of the gate structure 180c in the length direction. The size of the main doped protection layer 200 in the length direction of the gate structure 180c is smaller than that of the current blocking layer 160c in the length direction of the gate structure 180c; the conductivity type of the doped protection layer is the same as that of the well region 120, the doping concentration of the doped protection layer is greater than or equal to the doping concentration of the well region 120, and the doping concentration of the main doped protection layer 200 is greater than or equal to the doping concentration of the well region 120; the secondary current blocking layer 210 is located in the drift layer 110 at the bottom of the main doped protection layer 200. Figure 5 The example shown uses a spaced subcurrent blocking layer 210 from the bottom surface of the main doped protection zone 200. In other embodiments, the subcurrent blocking layer is in contact with the bottom surface of the main doped protection zone.

[0102] The current blocking layer 160c and the connection doped region do not overlap. Furthermore, the current blocking layer 160c and the connection doped region are spaced apart. Alternatively, the connection doped region overlaps with a portion of the length of the current blocking layer 160c (along the length direction of the gate structure).

[0103] In this embodiment, the doping concentration of the secondary current blocking layer 210 is less than that of the doping protection layer, and the doping concentration of the secondary current blocking layer 210 is less than that of the primary doping protection layer 200. In a specific embodiment, the doping concentration of the secondary current blocking layer 210 is 0.01 to 0.5 times the doping concentration of the primary doping protection layer 200, for example, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.2, 0.3, 0.4, or 0.5 times.

[0104] In one embodiment, the doping concentration of the secondary current blocking layer 210 is less than the doping concentration of the well region 120.

[0105] The main doped protection zone 200 serves several purposes: reducing the electric field strength at the bottom edge of the gate structure 180c, protecting the gate dielectric layer 181c, and preventing the gate dielectric layer 181c from being broken down. The connecting doped region serves to connect the well region 120 and the main doped protection zone 200. Since the potential applied to the source region 130 is ground, the main doped protection zone 200 is interconnected with the well region 120 through the connecting doped region, ensuring that the semiconductor power device can perform high-speed switching operations, and that changes in the hole charge region within the main doped protection zone 200 can keep pace with changes in the drain potential.

[0106] In this embodiment, when the gate structure 180c is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the injection efficiency of the secondary current blocking layer 210 to inject holes into the drift layer 110 at the bottom of the secondary current blocking layer 210 is reduced. This reduces the probability of electron-hole recombination, further suppressing the propagation of stacking faults caused by electron-hole recombination in the drift layer 110, and effectively reducing the bipolar degradation effect.

[0107] When the doping concentration of the secondary current blocking layer 210 is less than the doping concentration of the primary doped protection zone 200, and the secondary current blocking layer 210 is spaced apart from the bottom surface of the primary doped protection zone 200, a PN junction is formed between the secondary current blocking layer 210 and the drift layer 110 between the secondary current blocking layer 210 and the primary doped protection zone 200. Similarly, a PN junction is formed between the primary doped protection zone 200 and the drift layer 110 between the secondary current blocking layer 210 and the primary doped protection zone 200. Thus, when the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, these two PN junctions form a potential barrier for holes in the primary doped protection zone 200, thereby better preventing holes in the primary doped protection zone 200 from being injected into the drift layer 110 at the bottom of the secondary current blocking layer 210.

[0108] In one embodiment, the longitudinal distance between the main doped protection zone 200 and the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 is less than or equal to 1 micrometer and greater than 0 micrometer, for example, 1 micrometer, 8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer or 0.01 micrometer. The advantage of this design is that it prevents the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 from being too far from the main doped protection zone 200. If the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 is too far from the main doped protection zone 200, the drift layer 110 sandwiched between the main doped protection zone 200 and the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 is prone to being in a state of incomplete depletion. Thus, when the PN junction formed by the main doped protection zone 200 and the drift layer at the bottom of the main doped protection zone 200 is turned on, the hole current in the main doped protection zone 200 will easily flow through the side of the secondary current blocking layer 210 and down to the drift layer 110, weakening the blocking effect of the secondary current blocking layer 210 on the hole current. The longitudinal distance between the main doped protection zone 200 and the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 refers to the distance between the top surface of the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 and the bottom surface of the main doped protection zone 200.

[0109] Furthermore, when the conductivity type of the secondary current blocking layer 210 is the same as that of the doped protective layer, and the secondary current blocking layer 210 is spaced apart from the bottom surface of the main doped protection zone 200, the secondary current blocking layer 210 also extends into the drift layers 110 on both sides of the gate structure 180c in the longitudinal direction and contacts the front electrode 170c. This facilitates the clamping of the diode formed by the main doped protection zone 200 and the drift layer 110 at the bottom of the main doped protection zone 200.

[0110] In one embodiment, the thickness of the secondary current blocking layer 210 located at the bottom of the main doped protection zone 200 is 0.1µm to 1µm. The advantage of this configuration is that if the thickness of the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 is too small, it is easily depleted. On the one hand, the secondary current blocking layer 210 and the front electrode 170c easily lose their equipotential function, making it difficult to clamp the diode formed by the main doped protection zone 200 and the drift layer at its bottom. On the other hand, the potential barrier between the secondary current blocking layer 210 and the drift layer 110 is low, thus weakening the blocking effect of the secondary current blocking layer 210 on holes. If the thickness of the secondary current blocking layer 210 at the bottom of the main doped protection zone 200 is too large, it is detrimental to reducing the on-resistance of the MOSFET.

[0111] It should be noted that in other embodiments, the secondary current blocking layer can be a semi-insulating layer or an insulating layer. When the secondary current blocking layer is a semi-insulating layer or an insulating layer, when the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the secondary current blocking layer can increase the barrier for the main doped protection zone to inject holes into the drift layer, making it more difficult for the main doped protection zone to inject holes into the drift layer, thus reducing the probability of electron-hole recombination.

[0112] When the secondary current blocking layer is a semi-insulating layer or an insulating layer, it is located in the drift layer at the bottom of the main doped protection zone, and is in contact with or spaced from the bottom surface of the main doped protection zone. Preferably, the longitudinal distance between the top surface of the secondary current blocking layer and the bottom surface of the main doped protection zone is less than or equal to 1 micrometer, such as 1 micrometer, 0.8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer, or 0.01 micrometer. In one embodiment, the thickness of the secondary current blocking layer at the bottom of the main doped protection zone is 0.1µm to 1µm.

[0113] In one embodiment, the secondary current blocking layer is an Ar-doped region as a semi-insulating layer. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0114] In one embodiment, the insulating layer of the secondary current blocking layer is made of SiO2.

[0115] It should be noted that the secondary current blocking layer and the doping protection layer may not be set, or the secondary current blocking layer may not be set when the doping protection layer is set.

[0116] Figure 5 The solid arrow in the image indicates the direction of the electron current.

[0117] The contents that are the same as those in Example 1 will not be described in detail here.

[0118] Example 5

[0119] The difference between this embodiment and embodiment 4 is that: (Refer to...) Figure 6The current blocking layer 160d located on the side of the well region 120 is in contact with the Schottky anode layer 150 but not with the sidewall of the well region 120.

[0120] The description of the current blocking layer 160d at the bottom of the well region 120 is the same as that of the current blocking layer 160c at the bottom of the well region 120 in Example 4.

[0121] The descriptions of the doped protective layer and the secondary current blocking layer in this embodiment are the same as those in Embodiment 4.

[0122] It should be noted that the secondary current blocking layer and the doping protection layer may not be set, or the secondary current blocking layer may not be set when the doping protection layer is set.

[0123] Figure 6 The solid arrow in the image indicates the direction of the electron current.

[0124] All other aspects of this embodiment are the same as those in Embodiment 4, and will not be described in detail here.

[0125] Example 6

[0126] The difference between this embodiment and embodiment 4 is that: (Refer to...) Figure 7 The current blocking layer 160e located on the side of the well region 120 is in contact with the sidewall of the well region 120 but not with the Schottky anode layer 150.

[0127] The description of the current blocking layer 160e at the bottom of the well region 120 is the same as that of the current blocking layer 160c at the bottom of the well region 120 in Example 4.

[0128] The descriptions of the doped protective layer and the secondary current blocking layer in this embodiment are the same as those in Embodiment 4.

[0129] It should be noted that the secondary current blocking layer and the doping protection layer may not be set, or the secondary current blocking layer may not be set when the doping protection layer is set.

[0130] Figure 7 The solid arrow in the image indicates the direction of the electron current.

[0131] All other aspects of this embodiment are the same as those in Embodiment 4, and will not be described in detail here.

[0132] Example 7

[0133] The difference between this embodiment and Embodiment 1 is that: (Refer to...) Figure 8 The current blocking layer 160f is located in the drift layer 110 at the bottom of the well region 120 and is in contact with the bottom surface of the well region 120. The current blocking layer 160f is not located on the side of the well region 120.

[0134] The conductivity type of the current blocking layer 160f is the same as that of the well region 120, and the doping concentration of the current blocking layer 160f is lower than that of the well region 120. The description of the doping concentration of the current blocking layer 160f is the same as that of the current blocking layer 160 in Example 1, and will not be detailed further. The current blocking layer 160f does not extend below the JFET region 101.

[0135] The thickness of the current blocking layer 160f at the bottom of the well region 120 is described with reference to the thickness of the current blocking layer 160 in Embodiment 1, and will not be described in detail again.

[0136] Figure 8 The solid arrow in the image indicates the direction of the electron current.

[0137] All other aspects of this embodiment are the same as those in Embodiment 1, and will not be described in detail here.

[0138] Example 8

[0139] The difference between this embodiment and embodiment 4 is that: (Refer to...) Figure 9 The current blocking layer 160g is located in the drift layer 110 at the bottom of the well region 120 and is in contact with the bottom surface of the well region 120. The current blocking layer 160g is not located on the side of the well region 120.

[0140] The conductivity type of the current blocking layer 160g is the same as that of the well region 120, and the doping concentration of the current blocking layer 160g is lower than that of the well region 120. The description of the doping concentration of the current blocking layer 160g is the same as that of the current blocking layer 160c in Example 4, and will not be detailed further.

[0141] The thickness of the current blocking layer 160g at the bottom of the well region 120 is described in the same manner as the thickness of the current blocking layer 160c in Example 4, and will not be described in detail again.

[0142] The location and structure of the gate structure 180c are described in Example 4.

[0143] The current blocking layer 160g is spaced from the sidewall of the gate structure 180c, and the distance between the sidewall of the current blocking layer 160g and the gate structure 180c is as described in Example 4.

[0144] This embodiment also includes a doping protective layer and a secondary current blocking layer 210. The description of the doping protective layer and the secondary current blocking layer 210, as well as their positional relationship with the doping protective layer and the current blocking layer 160g, are the same as in Embodiment 4. It should be noted that in other embodiments, the secondary current blocking layer can be a semi-insulating layer or an insulating layer. It should also be noted that in other embodiments, the secondary current blocking layer and the doping protective layer may not be provided, or the secondary current blocking layer may be omitted when the doping protective layer is provided.

[0145] When the secondary current blocking layer is a semi-insulating layer or an insulating layer, the description of the secondary current blocking layer is as described in Example 4.

[0146] Figure 9 The solid arrow in the image indicates the direction of the electron current.

[0147] All other aspects of this embodiment are the same as those in Embodiment 4, and will not be described in detail here.

[0148] Example 9

[0149] The difference between this embodiment and embodiment 7 is that the current blocking layer is a semi-insulating layer or an insulating layer.

[0150] The current blocking layer is located in the drift layer at the bottom of the well region and contacts the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer does not extend below the JFET region.

[0151] When the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the current blocking layer increases the barrier height for the well region to inject holes into the drift layer, making it more difficult for the well region to inject holes into the drift layer.

[0152] In one embodiment, the current blocking layer is an Ar-doped region as a semi-insulating layer. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0153] In one embodiment, the insulating layer of the current blocking layer is made of SiO2.

[0154] In this embodiment, the thickness of the current blocking layer is the same as that in Example 7.

[0155] All other aspects of this embodiment are the same as those in Embodiment 7, and will not be described in detail here.

[0156] Example 10

[0157] The difference between this embodiment and embodiment 8 is that the current blocking layer is a semi-insulating layer or an insulating layer.

[0158] The current blocking layer is located in the drift layer at the bottom of the well region and contacts the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer is spaced apart from the sidewalls of the gate structure.

[0159] When the gate structure is turned off and the potential applied to the source region is higher than the potential applied to the drain metal region, the current blocking layer increases the barrier height for the well region to inject holes into the drift layer, making it more difficult for the well region to inject holes into the drift layer.

[0160] In one embodiment, the current blocking layer is an Ar-doped region as a semi-insulating layer. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0161] In one embodiment, the insulating layer of the current blocking layer is made of silicon oxide.

[0162] The thickness of the current blocking layer at the bottom of the well region is described in Example 8 and will not be repeated in detail. The description of the spacing between the current blocking layer and the gate structure is also in accordance with the description in Example 8 and will not be repeated in detail.

[0163] All other aspects of this embodiment are the same as those in Embodiment 8, and will not be described in detail here.

[0164] Example 11

[0165] The difference between this embodiment and embodiment 9 is that the current blocking layer is spaced apart from the bottom surface of the well region.

[0166] The current blocking layer is located in the drift layer at the bottom of the well region and is spaced apart from the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer does not extend below the JFET region.

[0167] Preferably, the longitudinal distance between the top surface of the current blocking layer and the bottom surface of the well region is less than or equal to 1 micrometer, for example, 1 micrometer, 0.8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer or 0.01 micrometer.

[0168] All other aspects of this embodiment are the same as those in Embodiment 9, and will not be described in detail here.

[0169] Example 12

[0170] The difference between this embodiment and embodiment 10 is that the current blocking layer is spaced apart from the bottom surface of the well region.

[0171] The current blocking layer is located in the drift layer at the bottom of the well region and is spaced from the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer is spaced from the sidewalls of the gate structure.

[0172] All other aspects of this embodiment are the same as those in Embodiment 10, and will not be described in detail here.

[0173] Example 13

[0174] This embodiment provides a method for fabricating a semiconductor power device, comprising: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming a well region in the drift layer; forming a current blocking layer in the drift layer, the current blocking layer being located in the drift layer at the bottom of the well region; forming a source region in a portion of the well region; forming a gate structure on a portion of the upper surface of the drift layer, the well region being located on both sides of the gate structure in the width direction; forming a Schottky anode layer, the Schottky anode layer being located on a portion of the surface of the drift layer and a portion of the surface of the well region on the side of the well region laterally away from the gate structure, the Schottky anode layer being spaced apart from the source region.

[0175] In this embodiment, the conductivity type of the current blocking layer is the same as that of the well region, and the doping concentration of the current blocking layer is less than that of the well region.

[0176] The current blocking layer is located in the drift layer at the bottom of the well region and extends into the drift layer on the side of the well region laterally away from the gate structure. The current blocking layer at the bottom of the well region is spaced apart from the well region, and the current blocking layer on the side of the well region is in contact with the sidewall of the well region and the Schottky anode layer.

[0177] The drift layer has a JFET region; the well region is located on both sides of the JFET region; the well region has a channel region located between the source region and the JFET region; the current blocking layer does not extend below the JFET region.

[0178] The step of forming a gate structure on a portion of the upper surface of the drift layer is as follows: forming a gate structure above the JFET region and above a portion of the source region and the channel region on both sides of the JFET region.

[0179] The following references Figures 10 to 14 The preparation process of this embodiment is described in detail.

[0180] refer to Figure 10 A semiconductor substrate 100 is provided; a drift layer 110 is formed on the semiconductor substrate.

[0181] refer to Figure 11 A first sub-current blocking layer 161 is formed in the drift layer 110. The lateral width of the first sub-current blocking layer 161 is smaller than its height.

[0182] In this embodiment, the method further includes: forming a patterned first mask layer (not shown) on the drift layer 110, the first mask layer being used to define the position of the first sub-current blocking layer 161; performing a first ion implantation on the drift layer 110 using the first mask layer as a mask to form the first sub-current blocking layer 161; and removing the first mask layer after forming the first sub-current blocking layer 161.

[0183] refer to Figure 12 A well region 120 is formed in the drift layer 110; a second sub-current blocking layer 162 is formed, located in the drift layer 110 at the bottom of the well region 120. The second sub-current blocking layer 162 and the first sub-current blocking layer 161 are connected to form a current blocking layer 160. The current blocking layer 160 partially surrounds the well region 120.

[0184] After removing the first mask layer, a patterned second mask layer (not shown) is formed on the drift layer 110. The second mask layer is used to define the positions of the well region 120 and the second subcurrent blocking layer 162. The drift layer 110 is then implanted with a second ion using the second mask layer as a mask to form the well region 120. The drift layer 110 is then implanted with a third ion using the second mask layer as a mask to form the second subcurrent blocking layer 162. The implantation depth of the third ion implantation is greater than the implantation depth of the second ion implantation.

[0185] In one embodiment, a second sub-current blocking layer 162 is formed after the well region 120 is formed. In another embodiment, the well region 120 is formed after the second sub-current blocking layer 162 is formed. In still other embodiments, a first sub-current blocking layer is formed after the second sub-current blocking layer and the well region are formed.

[0186] For further description of the current blocking layer 160, please refer to Example 1.

[0187] refer to Figure 13 A source region 130 is formed in a portion of the well region 120.

[0188] A sidewall is formed on the sidewall of the second mask layer; a source region 130 is formed in a portion of the well region 120 using the sidewall and the second mask layer as masks. The sidewall and the second mask layer are then removed.

[0189] The sidewall is made of silicon nitride.

[0190] refer to Figure 14 A gate structure 180 is formed on a portion of the upper surface of the drift layer 110, and the well region 120 is located on both sides of the gate structure 180 in the width direction; a Schottky anode layer 150 is formed, which is located on a portion of the surface of the drift layer 110 and a portion of the surface of the well region 120 on the side of the well region 120 that is laterally away from the gate structure 180, and the Schottky anode layer 150 and the source region 130 are spaced apart.

[0191] After removing the sidewalls and the second mask layer, a gate structure 180 and a Schottky anode layer 150 are formed.

[0192] The drift layer 110 has a JFET region 101; the well region 120 is located on both sides of the JFET region 101; the well region 120 has a channel region 140, which is located between the source region 130 and the JFET region 101; the current blocking layer 160 does not extend below the JFET region 101.

[0193] The step of forming a gate structure 180 on a portion of the upper surface of the drift layer 110 is as follows: the gate structure 180 is formed above the JFET region 101 and above a portion of the source region 130 and the channel region 140 on both sides of the JFET region 101.

[0194] This embodiment further includes: forming an isolation dielectric layer 190 on the sidewall surface and top surface of the gate electrode layer 182; forming a front electrode 170, which contacts the source region 130 and the Schottky anode layer 150. The front electrode 170 covers the gate structure 180, and the isolation dielectric layer 190 isolates the front electrode 170 and the gate electrode layer 182. This embodiment also includes: forming a drain metal region 102 on the side surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0195] The preparation method of this embodiment can form the semiconductor power device of Example 1.

[0196] Example 14

[0197] The difference between this embodiment and embodiment 13 is that the current blocking layer located on the side of the well region is in contact with the Schottky anode layer but not with the sidewall of the well region.

[0198] Adjust the relative positions of the first mask layer and the second mask layer so that the second subcurrent blocking layer is in contact with the Schottky anode layer but not with the sidewall of the well region.

[0199] The contents that are the same as those in Example 13 will not be described in detail here.

[0200] The preparation method of this embodiment can form the semiconductor power device of Example 2.

[0201] Example 15

[0202] The difference between this embodiment and embodiment 13 is that the current blocking layer located on the side of the well region is in contact with the sidewall of the well region but not with the Schottky anode layer.

[0203] The contents that are the same as those in Example 13 will not be described in detail here.

[0204] The preparation method of this embodiment can form the semiconductor power device of Example 3.

[0205] Example 16

[0206] The difference between this embodiment and embodiment 13 is that: (Refer to...) Figure 15 A gate structure 180c is formed in partial drift 110, a well region 120 is located on both sides of the gate structure 180c in the width direction, a source region 130c is in contact with the sidewall of the gate structure 180c, and a current blocking layer 160c is spaced from the sidewall of the gate structure 180c.

[0207] In this embodiment, the method further includes: forming a doped protective layer in the drift layer, the doped protective layer including a main doped protection zone 200 and a connecting doped region (not shown), the main doped protection zone 200 being located in the drift layer 110 at the bottom of the gate structure 180c and in contact with the bottom surface of the gate structure 180c, the connecting doped region being located on a portion of the sidewall surface on both sides of the gate structure 180c in the width direction, the connecting doped region connecting the well region 120 and the main doped protection zone 200, the dimension of the connecting doped region in the length direction of the gate structure 180c being much smaller than the dimension of the main doped protection zone 200 in the length direction of the gate structure 180c and much smaller than the dimension of the current blocking layer 160c in the length direction of the gate structure 180c, the conductivity type of the doped protective layer being the same as the conductivity type of the well region 120, and the doping concentration of the doped protective layer being greater than or equal to the doping concentration of the well region 120; and forming a secondary current blocking layer 210 in the drift layer 110 at the bottom of the main doped protection zone 200, the secondary current blocking layer 210 being spaced apart from the bottom surface of the main doped protection zone 200. In other embodiments, the secondary current blocking layer is in contact with the bottom surface of the primary doped protection zone 200.

[0208] In one embodiment, the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is less than that of the primary doped protective layer. The process for forming the doped protective layer includes an ion implantation process, and the process for forming the secondary current blocking layer 210 also includes an ion implantation process. The descriptions of the secondary current blocking layer 210 and the doped protective layer refer to the descriptions of the secondary current blocking layer and the doped protective layer in Embodiment 4.

[0209] When the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the secondary current blocking layer is spaced apart from the bottom surface of the main doped protective layer, the secondary current blocking layer also extends into the drift layers on both sides of the gate structure in the length direction; the method for fabricating the semiconductor power device further includes: forming a front electrode, the front electrode being in contact with the source region, the Schottky anode layer and the secondary current blocking layer.

[0210] In one embodiment, the secondary current blocking layer is a semi-insulating layer or an insulating layer, and the secondary current blocking layer is in contact with or spaced from the bottom surface of the primary doped protection zone. Preferably, the longitudinal distance between the top surface of the secondary current blocking layer and the bottom surface of the primary doped protection zone is less than or equal to 1 micrometer, for example, 1 micrometer, 0.8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer, or 0.01 micrometer.

[0211] In one embodiment, the secondary current blocking layer is an Ar-doped region as the semi-insulating layer. The process for forming the secondary current blocking layer includes an ion implantation process. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0212] In one embodiment, the insulating material used in the secondary current blocking layer is SiO2. The process for forming the secondary current blocking layer includes: performing oxygen ion implantation in the drift layer at the bottom of the main doped protected zone, followed by annealing the oxygen ion implanted region.

[0213] It should be noted that the secondary current blocking layer and the doping protection layer may not be set, or the secondary current blocking layer may not be set when the doping protection layer is set.

[0214] Example 17

[0215] The difference between this embodiment and embodiment 16 is that the current blocking layer located on the side of the well region is in contact with the Schottky anode layer but not with the sidewall of the well region.

[0216] All other aspects of this embodiment are the same as those in Embodiment 16, and will not be described in detail here.

[0217] Example 18

[0218] The difference between this embodiment and embodiment 16 is that the current blocking layer located on the side of the well region is in contact with the sidewall of the well region but not with the Schottky anode layer.

[0219] All other aspects of this embodiment are the same as those in Embodiment 16, and will not be described in detail here.

[0220] Example 19

[0221] refer to Figure 16 A semiconductor substrate 100 is provided; a drift layer 110 is formed on the semiconductor substrate.

[0222] refer to Figure 17 A well region 120 is formed in the drift layer 110; a current blocking layer 160f is formed in the drift layer 110, the current blocking layer 160f is located in the drift layer 110 at the bottom of the well region 120 and is in contact with the bottom surface of the well region 120, and the current blocking layer 160f is not located on the side of the well region 120.

[0223] After forming the well region 120, a current blocking layer 160f is formed, or the well region 120 is formed after forming the current blocking layer 160f.

[0224] The conductivity type of the current blocking layer 160f is the same as that of the well region 120, and the doping concentration of the current blocking layer 160f is less than that of the well region 120. The description of the doping concentration of the current blocking layer 160f is the same as that of the current blocking layer 160 in Example 13, and will not be detailed further.

[0225] In one embodiment, the process for forming the current blocking layer 160f is an ion implantation process.

[0226] refer to Figure 18 A source region 130 is formed in a portion of the well region 120.

[0227] refer to Figure 19A gate structure 180 is formed on a portion of the upper surface of the drift layer 110, and the well region 120 is located on both sides of the gate structure 180 in the width direction; a Schottky anode layer 150 is formed, which is located on a portion of the surface of the drift layer 110 and a portion of the surface of the well region 120 on the side of the well region 120 that is laterally away from the gate structure 180, and the Schottky anode layer 150 and the source region 130 are spaced apart.

[0228] The semiconductor power device further includes: a JFET region 101; a well region 120 located on both sides of the JFET region 101 in the width direction of the gate structure 180; a channel region 140 in the well region 120, the channel region 140 being located between the source region 130 and the JFET region 101; and a current blocking layer 160 not extending below the JFET region 101.

[0229] The step of forming a gate structure 180 on a portion of the upper surface of the drift layer 110 is as follows: the gate structure 180 is formed above the JFET region 101 and above a portion of the source region 130 and the channel region 140 on both sides of the JFET region 101.

[0230] This embodiment further includes: forming an isolation dielectric layer 190 on the sidewall surface and top surface of the gate electrode layer 182; forming a front electrode 170, which contacts the source region 130 and the Schottky anode layer 150. The front electrode 170 covers the gate structure 180, and the isolation dielectric layer 190 isolates the front electrode 170 and the gate electrode layer 182. This embodiment also includes: forming a drain metal region 102 on the side surface of the semiconductor substrate layer 100 facing away from the drift layer 110.

[0231] Example 20

[0232] The difference between this embodiment and Embodiment 19 is that: a gate structure is formed during partial drift, with the well regions located on both sides of the gate structure in the width direction. The source region is in contact with the sidewalls of the gate structure; the current blocking layer is spaced apart from the sidewalls of the gate structure.

[0233] In this embodiment, the method further includes: forming a doped protective layer in the drift layer, the doped protective layer including a main doped protective layer and a connecting doped region, the main doped protective layer being located in the drift layer at the bottom of the gate structure and in contact with the bottom surface of the gate structure, the connecting doped region being located on a portion of the sidewall surface of the gate structure in the width direction, the connecting doped region connecting the well region and the main doped protective layer, the dimension of the connecting doped region in the length direction of the gate structure being much smaller than the dimension of the main doped protective layer in the length direction of the gate structure and much smaller than the dimension of the current blocking layer in the length direction of the gate structure, the conductivity type of the doped protective layer being the same as the conductivity type of the well region, and the doping concentration of the doped protective layer being greater than or equal to the doping concentration of the well region; and forming a secondary current blocking layer in the drift layer at the bottom of the main doped protective layer, the secondary current blocking layer being in contact with or spaced from the bottom surface of the main doped protective layer.

[0234] In one embodiment, the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is lower than that of the primary doped protective layer. The process for forming the secondary current blocking layer includes an ion implantation process, and the process for forming the doped protective layer also includes an ion implantation process.

[0235] In one embodiment, the secondary current blocking layer is a semi-insulating layer or an insulating layer. Preferably, the longitudinal distance between the top surface of the secondary current blocking layer and the bottom surface of the well region is less than or equal to 1 micrometer, for example, 1 micrometer, 0.8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer, or 0.01 micrometer.

[0236] In one embodiment, the secondary current blocking layer is an Ar-doped region as the semi-insulating layer. The process for forming the secondary current blocking layer includes an ion implantation process. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0237] In one embodiment, the insulating material used in the secondary current blocking layer is SiO2. The process for forming the secondary current blocking layer includes: performing oxygen ion implantation in the drift layer at the bottom of the doped protective layer, followed by annealing the oxygen ion implanted region.

[0238] The description of the secondary current blocking layer and the doped protective layer is given in Example 16.

[0239] Example 21

[0240] The difference between this embodiment and embodiment 19 is that the current blocking layer is a semi-insulating layer or an insulating layer.

[0241] The current blocking layer is located in the drift layer at the bottom of the well region and contacts the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer does not extend below the JFET region.

[0242] When the current blocking layer is a semi-insulating layer, the process for forming the current blocking layer includes ion implantation.

[0243] In one embodiment, the current blocking layer is an Ar-doped region as a semi-insulating layer. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0244] In one embodiment, the insulating material used in the current blocking layer is SiO2. The steps of forming the current blocking layer include: performing oxygen ion implantation in the drift layer at the bottom of the well region, followed by annealing the oxygen ion implanted region.

[0245] In this embodiment, the thickness of the current blocking layer is the same as that of the current blocking layer in Embodiment 19.

[0246] All other aspects of this embodiment are the same as those in Embodiment 19, and will not be described in detail here.

[0247] Example 22

[0248] The difference between this embodiment and embodiment 20 is that the current blocking layer is a semi-insulating layer or an insulating layer.

[0249] The current blocking layer is located in the drift layer at the bottom of the well region and contacts the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer is spaced apart from the sidewalls of the gate structure.

[0250] In one embodiment, the current blocking layer is an Ar-doped region as a semi-insulating layer. In a specific embodiment, the Ar doping concentration in the Ar-doped region is 1 × 10⁻⁶. 16 atom / cm 3 ~5×10 18 atom / cm 3 For example, 1×10 16 atom / cm 3 1×10 17 atom / cm 3 1×10 18 atom / cm 3 Or 5×10 18 atom / cm 3 .

[0251] When the current blocking layer is a semi-insulating layer, the process for forming the current blocking layer includes ion implantation.

[0252] In one embodiment, the insulating material used in the current blocking layer is SiO2. The steps of forming the current blocking layer include: performing oxygen ion implantation in the drift layer at the bottom of the well region, followed by annealing the oxygen ion implanted region.

[0253] The thickness of the current blocking layer at the bottom of the well region is described in accordance with Example 20 and will not be repeated in detail. The description of the spacing between the current blocking layer and the gate structure is also in accordance with the description of Example 20 and will not be repeated in detail.

[0254] All other aspects of this embodiment are the same as those in Embodiment 20, and will not be described in detail here.

[0255] Example 23

[0256] The difference between this embodiment and embodiment 21 is that the current blocking layer is spaced apart from the bottom surface of the well region.

[0257] The current blocking layer is located in the drift layer at the bottom of the well region and is spaced apart from the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer does not extend below the JFET region.

[0258] Preferably, the longitudinal distance between the top surface of the current blocking layer and the bottom surface of the well region is less than or equal to 1 micrometer, for example, 1 micrometer, 0.8 micrometer, 0.6 micrometer, 0.4 micrometer, 0.2 micrometer, 0.1 micrometer, 0.05 micrometer or 0.01 micrometer.

[0259] All other aspects of this embodiment are the same as those in Embodiment 21, and will not be described in detail here.

[0260] Example 24

[0261] The difference between this embodiment and embodiment 22 is that the current blocking layer is spaced apart from the bottom surface of the well region.

[0262] The current blocking layer is located in the drift layer at the bottom of the well region and is spaced from the bottom surface of the well region. The current blocking layer is not located on the side of the well region. The current blocking layer is spaced from the sidewalls of the gate structure.

[0263] All other aspects of this embodiment are the same as those in Embodiment 22, and will not be described in detail here.

[0264] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor power device, characterized in that, include: Semiconductor substrate layer; A drift layer located on the semiconductor substrate layer; The gate structure is located in part of the drift layer or covers part of the upper surface of the drift layer; The well regions are located in the drift layers on both sides of the gate structure in the width direction; The source region is located in a portion of the well region; Schottky anode layer, located on a portion of the surface of the drift layer and a portion of the surface of the well region on the side of the well region laterally away from the gate structure, Schottky anode layer and source region are separated; A current blocking layer is located in a drift layer at the bottom of the well region. The conductivity type of the current blocking layer is the same as that of the well region, and the doping concentration of the current blocking layer is less than that of the well region. The current blocking layer is located in a drift layer at the bottom of the well region and extends into a drift layer on the side of the well region that is laterally away from the gate structure. The current blocking layer at the bottom of the well region is spaced from the well region, and the current blocking layer on the side of the well region is in contact with the Schottky anode layer.

2. The semiconductor power device according to claim 1, characterized in that, The doping concentration of the current blocking layer is 0.01 to 0.5 times that of the well region.

3. The semiconductor power device according to claim 1, characterized in that, The doping concentration of the current blocking layer is 1×10⁻⁶. 16 atom / cm 3 ~5×10 17 atom / cm 3 .

4. The semiconductor power device according to claim 1, characterized in that, The longitudinal distance between the current blocking layer at the bottom of the well region and the well region is less than or equal to 1 micrometer.

5. The semiconductor power device according to any one of claims 1 to 4, characterized in that, The thickness of the current blocking layer located at the bottom of the well region is 0.1µm to 1µm.

6. The semiconductor power device according to claim 1, characterized in that, The gate structure is located in a portion of the drift layer, and the source region is in contact with the sidewall of the gate structure; the current blocking layer is spaced apart from the sidewall of the gate structure.

7. The semiconductor power device according to claim 6, characterized in that, The lateral spacing between the current blocking layer at the bottom of the well region and the sidewall of the gate structure is 0.1µm to 1µm.

8. The semiconductor power device according to claim 6, characterized in that, Also includes: A doped protective layer is located in the drift layer, the doped protective layer including a main doped protection zone, the main doped protection zone being located in the drift layer at the bottom of the gate structure and in contact with the bottom surface of the gate structure; the conductivity type of the doped protective layer is the same as the conductivity type of the well region, and the doping concentration of the doped protective layer is greater than or equal to the doping concentration of the well region; The semiconductor power device further includes: a secondary current blocking layer located in the drift layer at the bottom of the main doping protection zone, wherein the secondary current blocking layer is in contact with or spaced from the bottom surface of the main doping protection zone.

9. The semiconductor power device according to claim 8, characterized in that, The doping protection layer further includes a connection doping region located on a portion of the sidewall surface of the gate structure in the width direction. The connection doping region connects the well region and the main doping protection region. The dimension of the connection doping region in the length direction of the gate structure is much smaller than the dimension of the main doping protection region in the length direction of the gate structure and much smaller than the dimension of the current blocking layer in the length direction of the gate structure.

10. The semiconductor power device according to claim 8, characterized in that, The conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is less than that of the primary doped protective layer.

11. The semiconductor power device according to claim 10, characterized in that, The semiconductor power device further includes: a front electrode, which is in contact with the source region and the Schottky anode layer; when the conductivity type of the secondary current blocking layer is the same as that of the doping protection layer, and the secondary current blocking layer is spaced apart from the bottom surface of the main doping protection layer, the secondary current blocking layer also extends into the drift layer on both sides of the gate structure in the length direction and is in contact with the front electrode.

12. The semiconductor power device according to claim 8, characterized in that, The secondary current blocking layer is a semi-insulating layer or an insulating layer.

13. The semiconductor power device according to claim 1, characterized in that, Also includes: JFET region; The well region is located on both sides of the JFET region in the width direction of the gate structure; the well region has a channel region located between the source region and the JFET region; the gate structure is located above the JFET region and spans a portion of the source region and the channel region on both sides of the JFET region; The current blocking layer does not extend below the JFET region.

14. A method for fabricating a semiconductor power device, characterized in that, include: Provide semiconductor substrate layer; A drift layer is formed on the semiconductor substrate layer; A trap region is formed in the drift layer; A current blocking layer is formed in the drift layer, the current blocking layer is located in the drift layer at the bottom of the well region, the conductivity type of the current blocking layer is the same as that of the well region, and the doping concentration of the current blocking layer is less than that of the well region; A source region is formed in a portion of the well region; A gate structure is formed in part of the drift layer or on part of the upper surface of the drift layer, wherein the well region is located on both sides of the gate structure in the width direction; A Schottky anode layer is formed, which is located on a portion of the surface of the drift layer and a portion of the surface of the well region on the side of the well region that is laterally away from the gate structure. The Schottky anode layer is spaced from the source region. The current blocking layer is located in the drift layer at the bottom of the well region and extends into the drift layer on the side of the well region that is laterally away from the gate structure. The current blocking layer at the bottom of the well region is spaced apart from the well region, and the current blocking layer on the side of the well region is in contact with the Schottky anode layer.

15. The method for fabricating a semiconductor power device according to claim 14, characterized in that, The drift layer has a JFET region; the well region is located on both sides of the JFET region in the width direction of the gate structure; the well region has a channel region, which is located between the source region and the JFET region; The step of forming a gate structure on a portion of the upper surface of the drift layer is as follows: forming a gate structure above the JFET region and above a portion of the source region and the channel region on both sides of the JFET region; The current blocking layer does not extend below the JFET region.

16. The method for fabricating a semiconductor power device according to claim 14, characterized in that, A gate structure is formed in a portion of the drift layer; the source region is in contact with the sidewall of the gate structure; and the current blocking layer is spaced apart from the sidewall of the gate structure.

17. The method for fabricating a semiconductor power device according to claim 16, characterized in that, Also includes: A doped protective layer is formed in the drift layer, the doped protective layer including a main doped protection zone, the main doped protection zone being located in the drift layer at the bottom of the gate structure and in contact with the bottom surface of the gate structure, the conductivity type of the doped protective layer being the same as that of the well region, and the doping concentration of the doped protective layer being greater than or equal to the doping concentration of the well region; a secondary current blocking layer is formed in the drift layer at the bottom of the main doped protection zone, the secondary current blocking layer being in contact with or spaced from the bottom surface of the main doped protection zone.

18. The method for fabricating a semiconductor power device according to claim 17, characterized in that, The doping protection layer further includes a connection doping region located on a portion of the sidewall surface of the gate structure in the width direction. The connection doping region connects the well region and the main doping protection region. The dimension of the connection doping region in the length direction of the gate structure is much smaller than the dimension of the main doping protection region in the length direction of the gate structure and much smaller than the dimension of the current blocking layer in the length direction of the gate structure.

19. The method for fabricating a semiconductor power device according to claim 17, characterized in that, The conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the doping concentration of the secondary current blocking layer is less than that of the primary doped protective layer.

20. The method for fabricating a semiconductor power device according to claim 19, characterized in that, When the conductivity type of the secondary current blocking layer is the same as that of the doped protective layer, and the secondary current blocking layer is spaced apart from the bottom surface of the main doped protective layer, the secondary current blocking layer also extends into the drift layers on both sides of the gate structure in the length direction. The method for fabricating the semiconductor power device further includes: forming a front electrode, wherein the front electrode is in contact with the source region, the Schottky anode layer and the secondary current blocking layer.

21. The method for fabricating a semiconductor power device according to claim 17, characterized in that, The secondary current blocking layer is a semi-insulating layer or an insulating layer.

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