Integrated circuit with backside power rail

Abstract

Integrated chips and methods of forming integrated chips include forming a layer stack over a substrate, the layer stack including a device stack over a first sacrificial layer. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate side of the layer stack. The substrate side of the layer stack is etched to form a trench, the trench stopping on the first etch stop layer. A conductive line is formed in the trench.

Description

Background Technology

[0001] This invention relates generally to the manufacture of integrated chips, and more specifically to the manufacture of integrated chips having a rear power rail and a rear power distribution network.

[0002] Burying power rails within the substrate beneath the chip device helps organize power and routing in small devices and allows for the use of back-side power distribution networks. However, as devices shrink in size and are placed close together, forming buried power rails between cell spaces becomes challenging. Summary of the Invention

[0003] A method of forming an integrated chip includes: forming a layer stack on a substrate, the layer stack including a device stack on a first sacrificial layer; replacing the first sacrificial layer with a first etch stop layer; removing the substrate to expose a substrate side of the layer stack; etching the substrate side of the layer stack to form a trench, the trench stopping on the first etch stop layer; and forming conductive lines in the trench.

[0004] An integrated chip includes a front-side device having a channel structure and a source / drain structure above a substrate. A buried power rail is located in the substrate, below the front-side device. A first etch-stop layer is located between the buried power rail and the front-side device. Electrical contacts extend through the substrate to form an electrical connection between the buried power rail and the front-side device.

[0005] An integrated chip includes front-side devices above a substrate, each front-side device having a channel structure and a source / drain structure, and having an inter-device distance between adjacent pairs of front-side devices. A buried power rail is located in the substrate, below the pairs of front-side devices, and has a width greater than the inter-device distance. Electrical contacts extend through the substrate to form an electrical connection between the buried power rail and the front-side devices.

[0006] These and other features and advantages will become clear from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0007] The following description will provide details of preferred embodiments with reference to the following figures, in which:

[0008] Figure 1 This is a top view of an integrated chip having multiple transistor devices including n-type devices and p-type devices according to an embodiment of the present invention.

[0009] Figure 2 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of a semiconductor layer stack on a substrate including two different types of sacrificial layers;

[0010] Figure 3 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the patterning of layer stacks into different regions that can be used to form n-type devices and p-type devices;

[0011] Figure 4 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of filler around the patterned stack;

[0012] Figure 5 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the patterning of device regions into different device stacks.

[0013] Figure 6 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the removal of a type of sacrificial semiconductor layer using selective etching, which retains other semiconductor layers in the device stack;

[0014] Figure 7 This is a cross-sectional view of the steps of manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of a set of etch stop layers in the gaps left by selectively removing the sacrificial layer;

[0015] Figure 8 This is a cross-sectional view of the steps in the fabrication of an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of a dielectric structure to separate the device stack;

[0016] Figure 9 This is a cross-sectional view of the manufacturing steps of an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of the source / drain structure;

[0017] Figure 10 This is a cross-sectional view of the manufacturing process of an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of electrical contacts that extend downwards into the underlying substrate layer to the source / drain structure.

[0018] Figure 11 This is a cross-sectional view of the manufacturing steps of an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of the back-end line layer and the carrier layer;

[0019] Figure 12 This is a cross-sectional view of a step in the manufacturing of an integrated chip with buried power rails according to an embodiment of the present invention, showing that the chip has been flipped over, where excess substrate material has been removed to expose the bottom etch stop layer;

[0020] Figure 13 This is a cross-sectional view of the manufacturing process of an integrated chip with buried power rails according to an embodiment of the present invention, showing the etching from the trench into the substrate, stopping at an etch stop layer to prevent over-etching into the front-side device;

[0021] Figure 14 This is a cross-sectional view of the steps in manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of buried power rails in a trench;

[0022] Figure 15 This is a cross-sectional view of the steps in manufacturing an integrated chip with buried power rails according to an embodiment of the present invention, showing the formation of a back-side power distribution network connected to the buried power rails; and

[0023] Figure 16 This is a block diagram / flowchart of a method for manufacturing an integrated chip with buried power rails according to an embodiment of the present invention. Detailed Implementation

[0024] Buried power rails can be used to connect to a back-side power distribution network, where power is supplied to the device assembly via interconnects formed beneath the device assembly. Instead of using a process that carefully controls the substrate thickness, an etch-stop feature that prevents over-etching of the back-side power rails completely removes the substrate, shorting the back-side power rails to the device region on the front side of the wafer. The back-side power rails can then be formed on the back side of the wafer, where an etch-stop feature buried in the fins makes electrical contact with the device region of the front-side device to control the formation of such power rails.

[0025] Now refer to the accompanying drawings, in which the same reference numerals denote the same or similar elements, and first refer to... Figure 1 The diagram shows a top view of an integrated chip. This view shows a set of nanosheets, each corresponding to an exemplary semiconductor device. For example, the nanosheets may include a p-type nanosheet field-effect transistor 102 and an n-type nanosheet field-effect transistor 104. A gate structure 106 is formed across nanosheets 102 and 104, and is cut into appropriate portions by a gate notch 108.

[0026] Two cross-sections are indicated and will be mentioned herein, where the first cross-section A shows the region of the fin that cuts through the gate and channel regions, and the second cross-section B shows the region of the fin that cuts through the source / drain regions. Although this embodiment is described with a specific focus on nanosheet devices, it should be understood that the principle can also be applied to other types of devices, such as nanowire transistors, fin field-effect transistors, planar devices, and so on.

[0027] See now Figure 2This shows a cross-sectional view of the steps involved in fabricating an integrated chip with buried power rails along section A. A layer stack on substrate 202 is shown. The stack includes a set of first sacrificial layers 204 located between different regions of the stack. Fin region 206 and substrate region 208 are formed of semiconductor material. Device stack 220 is formed of a set of alternating layers including a second sacrificial layer 212 and a channel layer 214.

[0028] Substrate 102 may be a bulk semiconductor substrate. In one example, the bulk semiconductor substrate may be a silicon-containing material. Exemplary examples of silicon-containing materials suitable for bulk semiconductor substrates include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polycrystalline silicon, epitaxial silicon, amorphous silicon, and their multilayers. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be used, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide.

[0029] Similarly, the first sacrificial layer 204, fin region 206, substrate region 208, second sacrificial layer 212, and channel layer 214 can be formed of suitable semiconductor materials. For example, the substrate 202, fin region 206, and substrate region 208 can all be formed of silicon. In contrast, the first sacrificial layer 204 and the second sacrificial layer 212 can be formed of silicon-germanium with specific germanium concentrations. For example, the first sacrificial layer 204 can have a germanium concentration of about 60% (e.g., a value in the range of about 50% to about 65%), while the second sacrificial layer 212 can have a germanium concentration of about 30% (e.g., a value in the range of about 25% to about 35%). These different germanium concentrations correspond to different etch rates, allowing for selective etching of the sacrificial layers.

[0030] As used herein, the term "selectivity" in relation to material removal processes means that the removal rate of a first material is greater than the removal rate of at least one other material in the structure to which the material removal process is applied. Thus, for a given etching process, a higher germanium concentration in the first sacrificial layer 204 may cause those layers to be etched away first, leaving silicon and a relatively intact silicon-germanium layer. Similarly, a lower concentration of silicon-germanium layer may be selectively etched away, leaving a relatively intact remaining silicon layer.

[0031] To form this stack, any suitable group of sequential deposition processes can be used. In particular, it is explicitly anticipated that each successive layer can be epitaxially grown from the previous layer, but it should be understood that other deposition processes can be used alternatively. As used herein, “epitaxical growth and / or deposition” refers to growing a semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material on the deposition surface. In embodiments using silicon and silicon-germanium for different layers, these materials have similar crystal structures and can be epitaxially grown from each other to form a stack.

[0032] See now Figure 3 The diagram shows a cross-sectional view of the steps involved in fabricating an integrated chip with buried power rails along section A. The layer stack is patterned to form distinct regions, including a first region 302 and a second region 304. This patterning can be performed by forming a mask 306 using, for example, a photolithography process, wherein the mask 306 is formed from any suitable hard mask material such as silicon nitride. Anisotropic etching can then be used to etch down into the layer stack. As used herein, anisotropic etching refers to an etching process that removes material in a directional manner, wherein the removal rate in the etch direction is substantially greater than the removal rate in other directions.

[0033] For example, reactive ion etching (RIE) is a form of plasma etching in which the surface to be etched is placed on an RF power supply electrode during etching. Furthermore, during RIE, the surface to be etched has a potential that accelerates the etchant material extracted from the plasma toward the surface, wherein the chemical etching reaction occurs in a direction perpendicular to the surface. Other examples of anisotropic etching that can be used for this purpose of the invention include ion beam etching, plasma etching, or laser ablation. Patterning can be performed using timed non-selective etching, which can etch all the different materials in the stack. In some cases, patterning may over-etch the stack, thereby removing some material from the substrate 202.

[0034] Now for reference Figure 4 The diagram shows a cross-sectional view of the steps in the fabrication of an integrated chip with buried power rails along section A. A pad 402 is conformally formed over a first region 302 and a second region 304, with a protective layer formed on the sidewalls of these regions. The pad 402 can be formed of any suitable dielectric material (e.g., silicon nitride) and can be formed by any suitable conformal deposition process.

[0035] For example, the pad 402 can be formed by any suitable process, including, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). CVD is a deposition process in which a deposit is formed due to a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). The solid products of the reaction are deposited on the surface of the film, coating, or layer to which the solid product is to be formed. Variations of CVD processes can also be employed, including but not limited to atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof. In alternative embodiments using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface.

[0036] A filler 404 is deposited around the first device region 302 and the second device region 304. The filler 404 may be formed of any suitable dielectric material (e.g., silicon dioxide). While CVD is explicitly anticipated as a method for depositing the filler 404, it should be understood that any suitable directional or non-directional deposition process may be used alternatively. The dielectric material may be deposited to a height above the mask 304 and may be ground to the height of the mask 304, for example, using a chemical mechanical planarization (CMP) process. CMP is performed using, for example, chemical or granular slurries and mechanical forces to gradually remove the upper layer of the device. The slurry may be formulated to be insoluble in, for example, work function metal layer materials, causing the CMP process to be unable to advance beyond that layer.

[0037] Now for reference Figure 5 The diagram shows a cross-sectional view of the steps involved in fabricating an integrated chip with buried power rails along section A. First region 302 and second region 304 can be patterned to divide the corresponding stack into first fins 502 and second fins 504, respectively. Any suitable patterning process, such as forming a photomask followed by timed anisotropic etching or a series of such etchings, can be used.

[0038] See now Figure 6 The diagram shows a cross-sectional view of the steps involved in fabricating an integrated chip with buried power rails along section A. For example, the first sacrificial layer 204 is selectively etched away using an isotropic etching process that preferentially removes the material used to remove the first sacrificial layer 204. Any suitable isotropic etching process can be used, such as wet or dry chemical etching. This leaves a gap 602 in the fins 502 and 504.

[0039] Now for reference Figure 7 The diagram shows a cross-sectional view of the steps in the fabrication of an integrated chip with buried power rails along section A. Gap 602 is filled by an etch stop layer 702. The etch stop layer 702 can be formed of any suitable dielectric material that is selectively etchable relative to the materials of the pad 402 and the filler 404. For example, carbon-doped silicon dioxide (SiOC) or silicon carbide can be used for this purpose. The etch stop layer 702 can be formed by a conformal deposition process (such as CVD or ALD) to fill gap 602. Excess material on the sidewalls of fins 502 / 504 can then be removed using selective anisotropic etching.

[0040] See now Figure 8 The diagram shows a cross-sectional view of the steps involved in fabricating an integrated chip with buried power rails along section A. Pad 802 is conformally formed, for example, of silicon nitride on the exposed sidewalls of fins 502 / 504. The gaps are then filled with filler 804 using any suitable deposition process. Filler 804 can be any suitable dielectric material, such as silicon dioxide.

[0041] At this stage, Figure 1 The structures of sections A and B shown are separate. The region indicated by section A is processed to form a gate structure around channel layer 214, wherein the second sacrificial layer 212 is etched away. A gate stack, including a gate dielectric and a gate conductor, is then formed around and between channel layers 214, with internal spacers formed between the channel layers to insulate the gate stack from the surrounding material.

[0042] In the region indicated by section B, the second sacrificial layer 212 and channel layer 214 may be replaced by source / drain regions. In some exemplary embodiments, anisotropic etching may be used to etch away the second sacrificial layer 212 and channel layer 214 in these regions. The source / drain regions can then be epitaxially grown from the remaining channel layer sidewall surfaces in the gate region. The source / drain regions may be doped, either by in-situ doping during growth or by implantation. Thus, the source / drain regions for the first fin 502 may be n-type doped, while the source / drain regions for the second fin 504 may be p-type doped.

[0043] See now Figure 9 A cross-sectional view along section B shows steps in the fabrication of an integrated chip with buried power rails. An n-type source / drain structure 902 and a p-type source / drain structure 904 are shown. An interlayer dielectric 906 is formed around these structures to protect them and electrically insulate them. A dashed outline of the location of the channel layer 214 is also shown, which remains on a plane different from the plane shown (e.g., section B).

[0044] See now Figure 10 The diagram shows a cross-sectional view along section B of the fabrication process of an integrated chip with buried power rails. Conductive contacts 1002 are formed through interlayer dielectric 906 to contact source / drain regions 902 and 904. These contacts can be formed by etching holes in the interlayer dielectric and depositing any conductive material in the holes. Conductive contacts 1002 can be formed of any suitable conductive material. Some contacts may include extensions 1004 extending downward between the fins to the height of fin region 206.

[0045] The conductive contact 1002 may comprise a silicide pad material, an adhesive metal pad, and a conductive metal filler. Examples of silicide pad materials include nickel, titanium, and nickel-platinum. Examples of adhesive pads include titanium nitride and tantalum nitride, and examples of conductive metals include tungsten, molybdenum, copper, ruthenium, cobalt, and their alloys. After metal deposition, a CMP process can be used to remove excess metal above the interlayer dielectric (ILD) 906.

[0046] See now Figure 11The diagram shows a cross-sectional view along section B of the fabrication process of an integrated chip with buried power rails. Back-end interconnects 1102 are formed on the top surface, specifically providing interconnects to contacts 1002. The back-end layer provides connectivity to other devices on the chip, to off-chip devices, to power or ground rails, and to any other suitable devices. The back-end layer may have multiple metal / via levels, such as with copper damascene filler. A chip carrier wafer 1104 is attached to the back-end layer 1102 via wafer bonding processes such as copper-copper bonding or dielectric-to-dielectric bonding. The chip carrier 1104 can be formed of any suitable material, such as a silicon substrate, or another wafer with a built-in chip on top, and can be used to move and manipulate the chip.

[0047] See now Figure 12 The diagram shows a cross-sectional view along section B of the steps in the fabrication of an integrated chip with buried power rails. Using chip carrier 1104, the chip can be inverted and flipped. The substrate 202 can be etched away to expose pads 402 and etch stop layer 702, for example, using any suitable combination of wafer grinding, polishing, and etching processes. The substrate removal process can begin with a rapid etching process, such as wafer grinding, to remove most of the wafer. When the substrate is thinned to, for example, tens or hundreds of nanometers, a highly selective silicon etching process can be used to stop the substrate removal process on pads 402 and 702.

[0048] See now Figure 13 The diagram shows a cross-sectional view along section B of the steps in the fabrication of an integrated chip with buried power rails. A back-side interlayer dielectric 1302 is deposited over pad 402 using any suitable deposition process. For example, CVD can be used to deposit a silicon dioxide layer. A pattern mask 1304 is then formed over the interlayer dielectric 1302, and the pattern mask 1304 can be patterned using any suitable process. For example, the pattern mask 1304 can be formed from an organic planarization layer and can be formed using a photolithography process. The pattern mask 1304 can then be used to perform timed anisotropic etching to define trenches in the chip. The anisotropic etching can be non-selective, such that material is removed from the interlayer dielectric 1302, the etch stop layer 702, and the fin 206. The timed anisotropic etching can be timed to reach down to the middle of the fin 206 without reaching the contact extension 1004.

[0049] Another anisotropic etching can then be performed to remove material from the fins 206 and filler 404. This etching can be performed until the etch stop layer 702 is exposed beneath the fins 206, thereby preventing accidental short circuits to front-end process devices. For example, the etch stop layer 702 can be detected by: a chemical sensor that detects when material from the etch stop layer 702 is removed by etching; by using a laser that reflects off the etch stop layer 702 when it is exposed; or by an etching process that can be adjusted to make the etch rate of the etch stop layer very low. The etching can together form a buried power rail (or back power rail) trench 1306 and expose a portion of the contact extension 1004.

[0050] See now Figure 14 The diagram shows a cross-sectional view along section B of a step in the fabrication of an integrated chip with buried power rails. Buried power rails 1402 are formed in trench 1306. Buried power rails 1402 can be formed of any suitable conductive material and can be formed using any suitable deposition process. Buried power rails 1402 may include a dielectric diffusion barrier 1404, which is formed as a pad on the surface of trench 1306 prior to a bulk of conductive material to prevent the conductive material from diffusing into the surrounding material. This dielectric barrier 1404 can be formed of any suitable dielectric material.

[0051] By patterning the trench 1306 from the back of the chip, a buried power rail 1402 can be formed. The width of the buried power rail 1402 is greater than the width that would be possible if the space for such a rail were created by etching downward between the fins, where the width of the rail would be limited by the space between the fins. Furthermore, a lower-resistance metal, such as copper, can be used, and this process is less likely to cause wafer stress or bending.

[0052] See now Figure 15 The diagram shows a cross-sectional view of a step in the fabrication of an integrated chip with buried power rails along section B. A backside power distribution network 1502 may be formed on the chip to provide connectivity to the buried power rails 1402. Like the back-end process layer 1102, the backside power distribution network 1502 can be used to provide connections between different devices, power supplies, grounds, and any other suitable electrical interconnects or vias.

[0053] See now Figure 16 This illustrates a method for forming an integrated chip with buried power rails. Frame 1602 forms a layer stack on substrate 202, as shown... Figure 2As shown. The layer stack may include a device stack 220 and a sacrificial layer 204, which may be removed in a subsequent processing step to form an etch stop layer. The layer stack can be formed by a sequential epitaxial growth process, wherein each layer is grown from the material of the previous layer.

[0054] Box 1604 is patterned with stacked layers to form, for example, regions 302 and 304. These regions may correspond to, for example, n-type and p-type devices. Box 1604 can be formed using, for example, a photolithography process defining mask 306, followed by anisotropic etching, such as RIE. Box 1606 uses a conformal deposition process to form a pad 402 over regions 302 and 304, and then forms a filler 404 around the pad 402.

[0055] Box 1610 uses, for example, a mask and anisotropic etching to etch down into regions 302 and 304 to form fins 502 and 504. This exposes the sidewall surfaces of fins 502 and 504. Box 1612 then replaces the first sacrificial layer 204 with an etch stop layer 702. The first sacrificial layer 204 can be removed using selective isotropic etching, which preferentially removes material from the first sacrificial layer 204 through its exposed sidewall surfaces. The etch stop layer 702 can be formed, for example, by a conformal deposition process followed by selective anisotropic etching, which removes deposited material from areas not protected by fins 502 and 504. Box 1614 uses a conformal deposition process to form a pad 802, which is then used to fill the gaps with filler 804.

[0056] Box 1616 can be used to form any suitable device using device stack 220. This step may include multiple sub-steps, such as etching away the second sacrificial layer 212 and forming the gate stack. Box 1618 can be used, for example, to form the source / drain structures 902 / 904 on the respective fins 502 and 504 by epitaxial growth from the remaining channel layer in the gate region. Although it is specifically envisioned that transistors can be formed in this manner, it should be understood that any suitable device (or no device at all) may be formed at this stage.

[0057] Frame 1619 forms contact electrodes 1002, including contact extensions 1004 extending downward along the fins. These electrodes 1002 can be formed by etching holes into the interlayer dielectric 906 and filler 404 using anisotropic etching, followed by any suitable deposition process of conductive material. Frame 1620 forms a back-end process layer 1102, which provides electrical connections to the electrodes 1002.

[0058] Box 1622, for example, uses chip carrier 1104 to flip the chip. This exposes the underside of substrate 202. Box 1624 then uses, for example, any suitable combination of etching and polishing to remove substrate 202 to expose pad 402. Box 1626 performs a first anisotropic etching into fin 206, for example, using timed anisotropic etching. Box 1628 then performs a second selective anisotropic etching that stops on etch stop layer 702 to form trench 1306.

[0059] Frame 1630 forms a buried power rail 1402 in aperture 1306. The formation of the buried power rail 1402 may include a first conformal deposition of a diffusion barrier material, followed by a second deposition of a conductive material filling the aperture. Frame 1632 forms a back-side power distribution network 1502 in contact with the buried power rail 1402, thereby providing electrical connection to the buried power rail 1402.

[0060] It should be understood that the present invention will be described based on the given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may vary within the scope of the present invention.

[0061] It should also be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, the element may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intermediate elements present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements present.

[0062] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk, or virtual hard disk such as in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the associated chip design to be formed on the wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0063] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer either as bare dies (i.e., as a single wafer with multiple unpackaged chips) or in a package. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with any one or two surface interconnects or buried interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0064] It should also be understood that material compounds will be described based on the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound; for example, SiGe includes SixGe1-x (where x is less than or equal to 1), etc. Furthermore, other elements may be included in the compound and still function according to the principles of the invention. Compounds with additional elements will be referred to herein as alloys.

[0065] References to this principle in the specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this principle. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0066] It should be understood that, for example, in the cases of “A / B,” “A and / or B,” and “at least one of A and B,” the use of any of the following “ / ,” “and / or,” and “at least one of” is intended to include selecting only the first listed item (A), or only the second listed item (B), or selecting both options (A and B). As another example, in the cases of “A, B, and / or C” and “at least one of A, B, and C,” this wording is intended to cover only the selection of the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed items (A and C), or only the second and third listed items (B and C), or all three options (A, B, and C). It will be apparent to those skilled in the art that this can be extended for many of the listed items.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should be further understood that, when used herein, the terms “comprising,” “including,” “containing,” and / or “comprising” specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0068] For ease of description, this document uses spatial relative terms such as "below," "under," "lower," "above," and "upper" to describe the relationship of one element or feature relative to another, as shown in the figure. It will be understood that spatial relative terms are intended to cover more than just the relationship between elements or features. Figure 1 Different orientations of a device in use or operation beyond those depicted in the figure. For example, if a device in the figure is flipped, a device described as "below" or "under" other elements or features will be oriented "above" other elements or features. Thus, the term "below" can include both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as "between" two layers, the layer may be the only layer between the two layers, or one or more intermediate layers may exist.

[0069] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0070] Preferred embodiments of the rear power rail (which are intended to be illustrative and not restrictive) have been described. It should be noted that modifications and variations can be made by those skilled in the art based on the above teachings. Therefore, it should be understood that changes may be made to the specific embodiments disclosed within the scope of the invention as outlined in the appended claims. Various aspects of the invention, having the details and features required by patent law, have thus been described, and the claimed and desired protection by a patent certificate is set forth in the claims.

Claims

1. A method for forming an integrated chip, comprising: A layer stack is formed on a substrate, the layer stack including a device stack on a first sacrificial layer; Replace the first sacrificial layer with the first etch stop layer; Remove the substrate to expose the substrate side of the layer stack; The substrate side of the stacked layers is etched to form a trench, stopping at the first etch stop layer; as well as Conductive lines are formed in the trench.

2. The method according to claim 1, further comprising: A device is formed by stacking the devices on the device side of the stacked layers.

3. The method of claim 2, wherein a device contact is formed, the device contact being in electrical contact with the device, and the device contact includes an extension partially extending through the layer stack, wherein, The conductive wire is in electrical contact with the extension.

4. The method according to claim 3, wherein, Etching the substrate side of the layer stack includes a first non-selective anisotropic etching that partially penetrates the layer stack, followed by a second selective anisotropic etching that exposes the extension and stops at the first etch stop layer.

5. The method according to claim 1, further comprising: Anisotropic etching is performed into the layer stack to expose the side surfaces of the layer stack.

6. The method of claim 5, wherein replacing the first sacrificial layer comprises: The first sacrificial layer is etched away isotropically using isotropic etching.

7. The method according to claim 6, wherein, Replacing the first sacrificial layer includes: depositing an etch-stop material using a conformal deposition process, followed by selective anisotropic etching to remove the etch-stop material from the exposed surface.

8. The method according to claim 7, wherein, The layer stack includes a second sacrificial layer below the first sacrificial layer.

9. The method of claim 8, wherein isotropically etching away the first sacrificial layer comprises: The second sacrificial layer is etched away isotropically, and the deposition of the etch-stop material therein also produces a second etch-stop layer.

10. The method according to claim 9, wherein, Removing the substrate includes performing selective etching that stops on the second etch stop layer.

11. An integrated chip, comprising: The front-side device, located above the substrate, has a channel structure and a source / drain structure; Buried power rails in the substrate, below the front-side device; A first etch stop layer is located between the buried power rail and the front-side device; Electrical contacts that pass through the substrate to form an electrical connection between the buried power rail and the front-side device; as well as A second etch stop layer is located between the first etch stop layer and the front device.

12. The integrated chip of claim 11, further comprising a third etch stop layer through which the buried power rail passes.

13. The integrated chip of claim 11, further comprising a rear power distribution network, the rear power distribution network including interconnections electrically contacting the buried power rails.

14. The integrated chip according to claim 11, wherein, The buried power rail is wider on the back side of the substrate than at the location where the electrical contact makes the electrical connection with the buried power rail.

15. An integrated chip, comprising: Multiple front-side devices, each having a channel structure and a source / drain structure above a substrate, and having inter-device distances between adjacent pairs of front-side devices among the multiple front-side devices; A buried power rail is embedded in the substrate, below the front-side device pair, and has a width greater than the distance between the devices. Electrical contacts that pass through the substrate to form an electrical connection between the buried power rail and the front-side device; A first etch stop layer is located between the buried power rail and the front-side device. as well as A second etch stop layer is located between the first etch stop layer and the front device.

16. The integrated chip of claim 15, further comprising a rear power distribution network, the rear power distribution network including interconnections electrically contacting the buried power rails.

17. The integrated chip according to claim 15, wherein, The buried power rail is wider on the back side of the substrate than at the location where the electrical contact makes the electrical connection with the buried power rail.

Images