Compact quasi-Z-source dual-output inverter and its carrier PWM modulation method

Abstract

A compact quasi-Z-source dual-output inverter and its carrier PWM modulation method of the present invention belong to the technical field of power electronic conversion devices; it includes 2 DC input power supplies connected in sequence, 2 symmetrical quasi-Z-source networks, 18 switching modules, and each of the two output terminals of each phase leg is connected with a set of three-phase resistive-inductive loads. And a carrier PWM modulation method of injecting the third harmonic and adding a DC offset and a DC pulsating quantity is given for the proposed inverter. Two modulation waves of injecting the third harmonic and adding a DC offset and a DC pulsating quantity are respectively compared with the in-phase stacked carriers. According to the switching states and comparison results, the logical operations for generating the driving signals of each switching module are deduced, so that the DC input voltage can realize single-stage boost and output two sets of three-phase AC voltages with adjustable phases and amplitudes through the inverter circuit, and the DC voltage utilization rate of the inverter is improved and the harmonic distortion rate of the output is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronic conversion devices, and particularly relates to a compact quasi-Z-source dual-output inverter and a carrier PWM modulation method thereof. Background Art

[0002] In recent years, dual AC output systems have been importantly applied in fields such as electric vehicles and new energy power generation grid connection. The core of a dual AC system is a dual-output inverter. Existing dual-output inverters all fall within the category of buck inverters. For a photovoltaic grid-connected system, an additional boost circuit needs to be added at the front stage, increasing the complexity and control difficulty of the system. The compact quasi-Z-source dual-output inverter proposed by the invention has the functions of boosting and inverting in a single-stage mode, simplifying the topological structure. The carrier PWM modulation method proposed by the invention injects third harmonics into the modulation wave and adds a DC offset and a DC pulsation amount, which can improve the utilization rate of the DC bus voltage to a certain extent. This modulation method is simple and easy to implement, with lower harmonic distortion rate and higher efficiency.

[0003] So far, there has been no literature report or practical application on a compact quasi-Z-source dual-output inverter and a carrier PWM modulation method thereof. Summary of the Invention

[0004] The object of the invention is to propose a compact quasi-Z-source dual-output inverter with small volume, low cost, reasonable structure and boosting ability for a three-phase three-level dual-output inverter with boosting ability from the perspectives of cost saving and reduction of the inverter volume; and to provide a scientific, reasonable, highly applicable and prominent-effective modulation method.

[0005] To achieve the above object, the specific technical solutions of the compact quasi-Z-source dual-output inverter and the carrier PWM modulation method of the invention are as follows:

[0006] A compact quasi-Z-source dual-output inverter, characterized in that it includes two DC power supplies V dc1 , V dc2 , an upper-side quasi-Z-source network, a lower-side quasi-Z-source network and a three-level inverter with two AC output ports; wherein, the positive pole of the DC power supply V dc1 is connected to the input end of the upper-side quasi-Z-source network, the negative pole of the DC power supply V dc2 is connected to the input end of the lower-side quasi-Z-source network, and the two DC power supplies V dc1 , V dc2The midpoint is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network; the output terminal of the upper quasi-Z-source network is connected to the positive terminal P of the three-level inverter, the output terminal of the lower quasi-Z-source network is connected to the negative terminal N of the three-level inverter, and the midpoint O of the two groups of quasi-Z-source networks is connected to the midpoint of the three-level inverter; the three-level inverter has three-phase bridge arms: phase-A bridge arm, phase-B bridge arm and phase-C bridge arm, and each phase bridge arm is composed of 6 switching modules S 1x ~S 6x where x ∈ {a, b, c};

[0007] The two groups of quasi-Z-source network circuits include inductor L1, inductor L2, inductor L3, inductor L4, capacitor C U1 、capacitor C U2 、capacitor C L1 、capacitor C L2 、diode D1, diode D2. One end of inductor L1 is connected to the positive pole of DC power supply V dc1 , the other end of inductor L1 is connected to the anode of diode D1 and the negative pole of capacitor C U1 , the cathode of diode D1 is connected to one end of inductor L2 and the positive pole of capacitor C U2 , the positive pole of capacitor C U1 is connected to the other end of inductor L2 and the positive terminal P of the three-level inverter; the positive pole of DC power supply V dc2 is connected to the negative pole of DC power supply V dc1 , the negative pole of DC power supply V dc2 is connected to one end of inductor L3, the other end of inductor L3 is connected to the cathode of diode D2 and the positive pole of capacitor C L2 , the anode of diode D2 is connected to one end of inductor L4 and the negative pole of capacitor C L1 , the negative pole of capacitor C L2 is connected to the other end of inductor L4 and the negative terminal N of the three-level inverter, the negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 , and the point where the negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 is defined as midpoint O;

[0008] Each of the switching modules consists of an insulated gate bipolar transistor T kx and an anti-parallel diode D kx . The subscript symbol kx of symbol T kx and symbol D kx represents the switching module where it is located, where x ∈ {a, b, c} and k ∈ {1, 2, 3, 4, 5, 6}; in the switching module S kx , the anode of diode D kx is connected to the insulated gate bipolar transistor Tkx is connected to the emitter, and diode D kx has its anode connected to the emitter of insulated gate bipolar transistor T kx at the point where they are connected, which is defined as the emitter of switching module S k x; the cathode of diode D kx is connected to the collector of insulated gate bipolar transistor T kx and diode D kx has its cathode connected to the collector of insulated gate bipolar transistor T kx at the point where they are connected, which is defined as the collector of switching module S kx ; the collector; the A-phase bridge arm has two output terminals, namely AC output terminal A1 and AC output terminal A2, the B-phase bridge arm has two output terminals, namely AC output terminal B1 and AC output terminal B2, and the C-phase bridge arm has two output terminals, namely AC output terminal C1 and AC output terminal C2; the three AC output terminals A1, B1, and C1 together form the inverter stage 1; the three AC output terminals A2, B2, and C2 together form the inverter stage 2; the three-phase resistive-inductive load carried by the inverter stage 1 is Z LA1 、Z LB1 、Z LC1 ,and the three-phase resistive-inductive load carried by the inverter stage 2 is Z LA2 、Z LB2 、Z LC2 ;

[0009] The collector of switching module S 1a is connected to the positive terminal P of the three-level inverter, the emitter of switching module S 1a is connected to the collector of switching module S 2a ,the emitter of switching module S 2a is connected to the collector of switching module S 3a ,the emitter of switching module S 3a is connected to the collector of switching module S 4a ,the emitter of switching module S 4a is connected to the negative terminal N of the three-level inverter; the point where the emitter of switching module S 1a is connected to the collector of switching module S 2a is defined as AC output terminal A1; the point where the emitter of switching module S 3a is connected to the collector of switching module S 4a is defined as AC output terminal A2;

[0010] The collector of switching module S 1b is connected to the positive terminal P of the three-level inverter, the emitter of switching module S1b is connected to the collector of switching module S 2b ,the emitter of switching module S 2b is connected to the collector of switching module S 3bis connected to the collector of, and the switch module S 3b 's emitter is connected to the switch module S 4b 's collector, and the switch module S 4b 's emitter is connected to the negative terminal N of the three-level inverter; Connect the emitter of the switch module S 1b to the emitter of the switch module S 2b and the connected point of the collector is defined as the AC output terminal B1; Connect the emitter of the switch module S 3b to the emitter of the switch module S 4b and the connected point of the collector is defined as the AC output terminal B2;

[0011] The switch module S 1c 's collector is connected to the positive terminal P of the three-level inverter, and the switch module S 1c 's emitter is connected to the switch module S 2c 's collector, and the switch module S 2c 's emitter is connected to the switch module S 3c 's collector, and the switch module S 3c 's emitter is connected to the switch module S 4c 's collector, and the switch module S 4c 's emitter is connected to the negative terminal N of the three-level inverter; Connect the emitter of the switch module S 1c to the emitter of the switch module S 2c and the connected point of the collector is defined as the AC output terminal C1; Connect the emitter of the switch module S 3c to the emitter of the switch module S 4c and the connected point of the collector is defined as the AC output terminal C2;

[0012] The switch module S 5a 's collector is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network, and the switch module S 5a 's emitter is connected to the emitter of the switch module S 6a and the switch module S 6a 's collector is connected to the emitter of the switch module S 2a ;

[0013] The switch module S 5b 's collector is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network, and the switch module S 5b 's emitter is connected to the emitter of the switch module S 6b and the switch module S 6b 's collector is connected to the emitter of the switch module S 2b ;

[0014] The switch module S 5c 's collector is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network, and the switch module S5c The emitter of 6c is connected to the emitter of the switch module S 6c The collector of 2c is connected to the emitter of the switch module S

[0015] The three-phase resistive-inductive load Z LA1 , Z LB1 , Z LC1 One end of each is respectively connected to the AC output terminals A1, B1, C1. The other ends of the three-phase resistive-inductive loads Z LA1 , Z LB1 , Z LC1 are connected to each other; One end of the three-phase resistive-inductive loads Z LA2 , Z LB2 , Z LC2 are respectively connected to the AC output terminals A2, B2, C2. The other ends of the three-phase resistive-inductive loads Z LA2 , Z LB2 , Z LC2 are connected to each other.

[0016] The present invention also provides a carrier PWM modulation method for a compact quasi-Z-source dual-output inverter, which includes the following steps:

[0017] Step 1: Set the same number of switch modules and reasonable switching states for the A-phase, B-phase, and C-phase bridge arms of the compact quasi-Z-source dual-output inverter. There is a constraint relationship and they are the same between the potential of the upper output terminal and the potential of the lower output terminal on the same phase of each phase bridge arm of the compact quasi-Z-source dual-output inverter. For the A-phase bridge arm, the potential V a1 ≥ the potential V a2 of the lower output terminal. Each of the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm has 6 switch modules and 8 reasonable switching states. For the A-phase bridge arm:

[0018] Switching state 1: Switch modules S 1a , switch modules S 2a , switch modules S 3a , switch modules S 5a are turned on. At this time, the potential V a1 of the upper output terminal is U dc / 2, and the potential V a2 of the lower output terminal is U dc / 2;

[0019] Switching state 2: Switch modules S 1a , switch modules S 3a , switch modules S 5a , switch modules S 6a are turned on. At this time, the potential V a1 of the upper output terminal is U dc / 2, the potential of the lower output terminal V a2 is 0;

[0020] Switch state 3: Switch modules S 1a , switch module S 4a , switch module S 5a , switch module S 6a conduct, at this time, the potential of the upper output terminal V a1 is U dc / 2, the potential of the lower output terminal V a2 is -U dc / 2;

[0021] Switch state 4: Switch modules S 2a , switch module S 3a , switch module S 5a , switch module S 6a conduct, at this time, the potential of the upper output terminal V a1 is 0, and the potential of the lower output terminal V a2 is 0;

[0022] Switch state 5: Switch modules S 2a , switch module S 4a , switch module S 5a , switch module S 6a conduct, at this time, the potential of the upper output terminal V a1 is 0, and the potential of the lower output terminal V a2 is -U dc / 2;

[0023] Switch state 6: Switch modules S 2a , switch module S 3a , switch module S 4a , switch module S 6a conduct, at this time, the potential of the upper output terminal V a1 is -U dc / 2, and the potential of the lower output terminal V a2 is -U dc / 2;

[0024] Switch state 7: Switch modules S 1a , switch module S 3a , switch module S 4a , switch module S 5a , switch module S 6a conduct, at this time, the potential of the upper output terminal V a1 is U dc / 2, and the potential of the lower output terminal V a2 is 0;

[0025] Switch state 8: Switch modules S 1a , switch module S 2a, Switch module S 4a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential of the upper output terminal V a1 is 0, and the potential of the lower output terminal V a2 is -U dc / 2;

[0026] The switching states of the B-phase bridge arm and the C-phase bridge arm are the same as those of the A-phase bridge arm;

[0027] Step 2: For the upper quasi-Z-source network, when in the direct-through state, switch modules S 1a , switch module S 2a , switch module S 3a , switch module S 4a conduct, diode D1 is reverse-biased and turns off, power supply V dc1 and capacitor C U1 charge inductor L1, and capacitor C U2 charges inductor L2; when in the non-direct-through state, diode D1 conducts, and power supply V dc1 and inductors L1 and L2 charge capacitors C U1 , C U2 and supply energy to the load; for the lower quasi-Z-source network, when in the direct-through state, switch modules S 3a , switch module S 4a , switch module S 5a , switch module S 6a conduct, diode D2 is reverse-biased and turns off, power supply V dc2 and capacitor C L2 charge inductor L3, and capacitor C L1 charges inductor L4; when in the non-direct-through state, diode D2 conducts, and power supply V dc2 and inductors L3 and L4 charge capacitors C L1 , C L2 and supply energy to the load; when the upper quasi-Z-source network is in the direct-through state, the lower quasi-Z-source network is in the non-direct-through state; when the lower quasi-Z-source network is in the direct-through state, the upper quasi-Z-source network is in the non-direct-through state;

[0028] Step 3: Adopt carrier PWM modulation with injected third harmonic and added DC offset and DC pulsation, use two triangular carriers u c1 and u c2 , and adopt the in-phase stacking method, that is, the phases of the two triangular carriers u c1 , u c2 are the same, the amplitudes are the same, and the variation range of u c1 is 0 to 1, and the variation range of u c2 is -1 to 0;

[0029] Define the direct duty cycles d1 and d2 of the upper quasi-Z-source network and the lower quasi-Z-source network. The expressions for the direct duty cycles of the upper quasi-Z-source network and the lower quasi-Z-source network are as follows:

[0030] d1 = T1 / T s

[0031] d2 = T2 / T s

[0032] Among them, T s represents the time of a switching period, and T1 and T2 are the times of direct conduction within a switching period T of the upper quasi-Z-source network and the lower quasi-Z-source network respectively; s within;

[0033] Define two sets of injected third harmonics as u x13 and u x23 , where the expression for the first set of third harmonics u x13 is as follows:

[0034]

[0035] The expression for the second set of third harmonics u x23 is as follows:

[0036]

[0037] Among them, a is the multiple of the injected third harmonic;

[0038] Define two sets of sinusoidal modulation waves u x1 and u x2 , where the expression for the first set of sinusoidal modulation waves u x1 is as follows:

[0039]

[0040] The expression for the second set of sinusoidal modulation waves u x2 is as follows:

[0041]

[0042] Among them, m1 and m2 are the modulation depths of the first set of modulation waves and the second set of modulation waves respectively. The value range of m1 is from 0 to 1 - d1, and the value range of m2 is from 0 to 1 - d2; ω1 and ω2 are the angular frequencies of the first set and the second set of modulation waves respectively, are the initial phase angles of the first set and the second set of modulation waves respectively, and the value range is from -π / 2 to π / 2; U offect1 is the DC offset of the first set of modulation waves, U offect2is the DC offset of the second set of modulation waves; the periods of the two sets of modulation waves are set as T3 and T4 respectively, that is, T3 = 2π / ω1 and T4 = 2π / ω2;

[0043] The modulation wave u x1 , u x2 are respectively compared with two triangular carrier waves u c1 , u c2 to determine the potentials V x1 , V x2 of the two output terminals. The specific comparison method is as follows:

[0044] ① If u x1 > u c1 , V x1 is U dc / 2; if u x1 ≤ u c2 , V x1 is -U dc / 2; if u c2 ≤ u x1 ≤ u c1 , V x1 is 0;

[0045] ② If u x2 > u c2 , V x2 is 0; if u x2 ≤ u c2 , V x2 is -U dc / 2;

[0046] Define two DC pulsating quantities V U and V L with periodic changes. The DC pulsating quantities V U , V L are respectively compared with the triangular carrier waves u c1 , u c2 to control the direct-through duty ratio of the quasi-Z-source network. The value range of V U is 0.5 to 1, and the value range of V L is -1 to -0.5;

[0047] Step 4: Define the line voltage amplitudes between phase A and phase B of the two sets of AC outputs as U A1B1 , U A2B2 . The relationship between the AC output line voltage amplitudes U A1B1 , U A2B2 and the modulation degrees m1, m2 of the two sets of sine modulation waves is:

[0048]

[0049] Step Five: Analyze and generate the logic operations for driving signals of each switch module; a driving signal value of 1 indicates that the switch module is turned on, and a driving signal value of 0 indicates that the switch module is turned off.

[0050] Compare the first set of modulation waves u x1 with the carrier wave u c1 and generate a signal e1 according to the comparison result:

[0051]

[0052] Compare the first set of modulation waves u x1 with the carrier wave u c2 and generate a signal e2 according to the comparison result:

[0053]

[0054] Compare the second set of modulation waves u x2 with the carrier wave u c1 and generate a signal e3 according to the comparison result:

[0055]

[0056] Compare the second set of modulation waves u x2 with the carrier wave u c2 and generate a signal e4 according to the comparison result:

[0057]

[0058] Generate a signal e5 from signal e1 and signal e2:

[0059]

[0060] where represents the logical NOT operation on u, and the symbol “&” represents the logical AND operation;

[0061] Generate a signal e6 from signal e3 and signal e4:

[0062]

[0063] Compare the DC pulsation quantity V U with the carrier wave u c1 and generate a signal e7 according to the comparison result:

[0064]

[0065] Compare the DC pulsation quantity V L with the carrier wave u c2 and generate a signal e8 according to the comparison result:

[0066]

[0067] According to the signals e1 to e8 and the 8 reasonable switching states of the compact quasi-Z-source dual-output inverter, analyze the driving signals s 1x ~s 6x of each of the 6 switching modules S 1x ~s 6x , where x ∈ {a, b, c}.

[0068] ① When the potential V x1 of the upper output terminal is U dc / 2 and the potential V x2 of the lower output terminal is U dc / 2; when the potential V x1 of the upper output terminal is U dc / 2 and the potential V x2 of the lower output terminal is 0; when the potential V x1 of the upper output terminal is U dc / 2 and the potential V x2 of the lower output terminal is -U dc / 2, the switching module S 1x conducts, and the expression of the driving signal s 1x of the switching module S 1x is:

[0069] s 1x = e1 ∨ (e2 & e9)

[0070] The symbol "∨" represents the logical OR operation, and the symbol "&" represents the logical AND operation;

[0071] ② When the potential V x1 of the upper output terminal is U dc / 2 and the potential V x2 of the lower output terminal is U dc / 2; when the potential V x1 of the upper output terminal is 0 and the potential V x2 of the lower output terminal is 0; when the potential V x1 of the upper output terminal is 0 and the potential V x2 of the lower output terminal is -U dc / 2; when the potential V x1 of the upper output terminal is -U dc / 2 and the potential V x2 of the lower output terminal is -U dc / 2, the switching module S 2x conducts, and the expression of the driving signal s 2x of the switching module S 2x is:

[0072]

[0073] represents the logical NOT operation on u;

[0074] ③ At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, when the switch module S 3x conducts, and the drive signal s 3x of the switch module S 3x has the expression:

[0075]

[0076] ④ At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, when the switch module S 4x conducts, and the drive signal s 4x of the switch module S 4x has the expression:

[0077]

[0078] ⑤ At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential Vx1 is 0, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is -U dc / 2, the switch module S 5x conducts, and the drive signal s of the switch module S 5x has the following expression: 5x Expression is:

[0079]

[0080] ⑥ When the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is -U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2, the switch module S 6x conducts, and the drive signal s of the switch module S 6x has the following expression: 6x Expression is:

[0081]

[0082] Step Five: Through Steps One - Four, the drive signals of the 18 switch modules of the compact quasi-Z-source dual-output inverter can be obtained, completing the carrier PWM modulation, so that the compact quasi-Z-source dual-output inverter outputs two sets of three-phase three-level AC outputs with adjustable phases and amplitudes.

[0083] The compact quasi-Z-source dual-output inverter and its carrier PWM modulation method of the present invention have the following advantages:

[0084] 1. A compact quasi-Z-source dual-output inverter of the present invention can boost the DC input voltage and output two sets of three-phase AC voltages with adjustable phases and amplitudes through an inverter circuit. It has a simple structure, low cost, and wide applications.

[0085] 2. Compared with a two-level inverter, a single switch of a compact quasi-Z-source dual-output inverter of the present invention bears lower voltage stress, and the output waveform is closer to a sine wave; compared with a three-level inverter, it is more suitable for photovoltaic grid-connected application scenarios.

[0086] 3. A compact quasi-Z-source dual-output inverter of the present invention has a large utilization rate of the DC-link voltage, and the switching devices bear small voltage stress, with a simple structure and low cost;

[0087] 4. The carrier PWM modulation method used injects the third harmonic into the modulation wave and adds a DC offset and a DC pulsation, which is simple and easy to implement, has a lower harmonic distortion rate and higher efficiency, and is scientific, reasonable, highly applicable, and outstanding in performance. Description of the Drawings

[0088] Figure 1 It is a topological structure diagram of a compact quasi-Z-source dual-output inverter of the present invention.

[0089] Figure 2 It is a schematic diagram of switching state 1.

[0090] Figure 3 It is a schematic diagram of switching state 2.

[0091] Figure 4 It is a schematic diagram of switching state 3.

[0092] Figure 5 It is a schematic diagram of switching state 4.

[0093] Figure 6 It is a schematic diagram of switching state 5.

[0094] Figure 7 It is a schematic diagram of switching state 6.

[0095] Figure 8 It is a schematic diagram of switching state 7.

[0096] Figure 9 It is a schematic diagram of switching state 8.

[0097] Figure 10 It is a comparison schematic diagram of the modulation wave, the DC pulsation wave and the carrier.

[0098] Figure 11 It is a logic operation diagram for generating drive signals.

[0099] Figure 12 Upper DC-link voltage U Upn Waveform diagram.

[0100] Figure 13 Lower DC-link voltage U Lpn Waveform diagram.

[0101] Figure 14 For the line voltage U output by the upper group output inverter stage 1 A1B1 Waveform diagram.

[0102] Figure 15 For the line voltage U output by the lower set of output inverter stages 2 A2B2 Waveform diagram.

[0103] Figure 16 For the waveform diagram of the upper output three-phase load current.

[0104] Figure 17 For the waveform diagram of the lower output three-phase load current. Specific implementation manner

[0105] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a compact quasi-Z-source dual-output inverter and its carrier PWM modulation method of the present invention in conjunction with the accompanying drawings.

[0106] A compact quasi-Z-source dual-output inverter and its carrier PWM modulation method of the present invention include two sequentially connected DC input power supplies, two symmetrical quasi-Z-source networks, 18 switching modules, and each of the two output ends of each phase bridge arm is provided with a set of three-phase resistive-inductive loads. And a carrier PWM modulation method of injecting third harmonics and adding DC offset and DC pulsation amount is given for the proposed inverter. The two modulation waves injecting third harmonics and adding DC offset and DC pulsation amount are respectively compared with the in-phase stacked carriers. According to the switching state and comparison results, the logical operation for generating the driving signals of each switching module is deduced, so that the DC input voltage can realize single-stage boost and output two sets of three-phase AC voltages with adjustable phases and amplitudes through the inverter circuit, and improve the DC voltage utilization rate of the inverter and reduce the output harmonic distortion rate. It can be widely applied to new energy grid-connected application scenarios, solves the problem of low efficiency of the two-stage structure, and has the advantages of reasonable structure, scientific modulation method, and outstanding performance.

[0107] Referring to Figure 1 , a compact quasi-Z-source dual-output inverter of the present invention includes: It includes two sets of DC power supplies V dc1 , V dc2 connected in sequence, two symmetrical quasi-Z-source networks, and the midpoints of the two sets of DC power supplies are connected to the midpoints of the two sets of quasi-Z-source networks, phase A bridge arm, phase B bridge arm and phase C bridge arm. Each phase bridge arm is composed of 6 switching modules S 1x ~S 6x , where x ∈ {a, b, c}; The phase A bridge arm has two output ends, namely the upper output end A1 and the lower output end A2. The phase B bridge arm has two output ends, namely the upper output end B1 and the lower output end B2. The phase C bridge arm has two output ends, namely the upper output end C1 and the lower output end C2; The three upper output ends A1, B1 and C1 together form inverter stage 1; The three lower output ends A2, B2 and C2 together form inverter stage 2; The three-phase resistive-inductive loads carried by inverter stage 1 are Z LA1 , Z LB1, Z LC1 , the three-phase resistive-inductive load carried by the inverter stage 2 is Z LA2 , Z LB2 , Z LC2 ;

[0108] The quasi-Z-source network circuit includes inductor L1, inductor L2, inductor L3, inductor L4, capacitor C U2 , capacitor C U2 , capacitor C L1 , capacitor C L2 , diode D1, diode D2. One end of inductor L1 is connected to the positive pole of power supply V dc1 , the other end of inductor L1 is connected to the anode of diode D1 and the negative pole of capacitor C U1 , the cathode of diode D1 is connected to one end of inductor L2 and the positive pole of capacitor C U2 , the positive pole of capacitor C U1 is connected to the other end of inductor L2 and the positive terminal P of the three-level inverter; the positive pole of power supply V dc2 is connected to the negative pole of power supply V dc1 , the negative pole of power supply V dc2 is connected to one end of inductor L3, the other end of inductor L3 is connected to the cathode of diode D2 and the positive pole of capacitor C L2 , the anode of diode D2 is connected to one end of inductor L4 and the negative pole of capacitor C L1 , the negative pole of capacitor C L2 is connected to the other end of inductor L4 and the negative terminal N of the three-level inverter, the negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 , and the point where the negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 is defined as the midpoint O;

[0109] Each of the switch modules consists of an insulated gate bipolar transistor T kx and an anti-parallel diode D kx . The subscript symbol kx of symbol T kx and symbol D kx indicates the switch module it belongs to, where x ∈ {a, b, c} and k ∈ {1, 2, 3, 4, 5, 6}; the anode of diode D kx in the switch module S kx is connected to the emitter of insulated gate bipolar transistor T kx , and the point where the anode of diode D kx is connected to the emitter of insulated gate bipolar transistor T kx is defined as the emitter of switch module S kx , the anode of diode D kxThe cathode of is connected to the collector of the insulated gate bipolar transistor T kx and the cathode of the diode D kx is connected to the collector of the insulated gate bipolar transistor T kx The connection point of the collector is defined as the switch module S kx of the collector;

[0110] The collector of the switch module S 1a is connected to the positive terminal P of the three-level inverter, and the emitter of the switch module S 1a is connected to the collector of the switch module S 2a The emitter of the switch module S 2a is connected to the collector of the switch module S 3a The emitter of the switch module S 3a is connected to the collector of the switch module S 4a The emitter of the switch module S 4a is connected to the negative terminal N of the three-level inverter; the connection point of the emitter of the switch module S 1a and the collector of the switch module S 2a is defined as the AC output terminal A1; the connection point of the emitter of the switch module S 3a and the collector of the switch module S 4a is defined as the AC output terminal A2;

[0111] The collector of the switch module S 1b is connected to the positive terminal P of the three-level inverter, and the emitter of the switch module S 1b is connected to the collector of the switch module S 2b The emitter of the switch module S 2b is connected to the collector of the switch module S 3b The emitter of the switch module S 3b is connected to the collector of the switch module S 4b The emitter of the switch module S 4b is connected to the negative terminal N of the three-level inverter; the connection point of the emitter of the switch module S 1b and the collector of the switch module S 2b is defined as the AC output terminal B1; the connection point of the emitter of the switch module S 3b and the collector of the switch module S 4b is defined as the AC output terminal B2;

[0112] The collector of the switch module S 1c is connected to the positive terminal P of the three-level inverter, and the emitter of the switch module S 1c is connected to the collector of the switch module S 2c The emitter of the switch module S 2c is connected to the collector of the switch module S 3cis connected to the collector of, and the switch module S 3c 's emitter is connected to the switch module S 4c 's collector, and the switch module S 4c 's emitter is connected to the negative terminal N of the three-level inverter; the emitter of the switch module S 1c is connected to the emitter of the switch module S 2c 's collector, and the connection point is defined as the AC output terminal C1; the emitter of the switch module S 3c is connected to the emitter of the switch module S 4c 's collector, and the connection point is defined as the AC output terminal C2;

[0113] The collector of the switch module S 5a is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of the switch module S 5a is connected to the emitter of the switch module S 6a , and the collector of the switch module S 6a is connected to the emitter of the switch module S 2a ;

[0114] The collector of the switch module S 5b is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of the switch module S 5b is connected to the emitter of the switch module S 6b , and the collector of the switch module S 6b is connected to the emitter of the switch module S 2b ;

[0115] The collector of the switch module S 5c is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of the switch module S 5c is connected to the emitter of the switch module S 6c , and the collector of the switch module S 6c is connected to the emitter of the switch module S 2c ;

[0116] The three-phase resistive-inductive load Z LA1 , Z LB1 , Z LC1 's one ends are respectively connected to the upper output terminals A1, B1, C1. The three-phase resistive-inductive load Z LA1 , Z LB1 , Z LC1 's other ends are connected together; the three-phase resistive-inductive load Z LA2 , Z LB2 , Z LC2 's one ends are respectively connected to the lower output terminals A2, B2, C2. The three-phase resistive-inductive load Z LA2 , Z LB2 , Z LC2 's other ends are connected together.

[0117] As Figure 1 shown, by applying a reasonable driving signal to the switching module, a compact quasi-Z-source dual-output inverter of the present invention can realize boosting the DC input voltage and inverting it into two sets of three-phase AC voltages with adjustable phases and amplitudes.

[0118] Referring to Figures 2 - 11 , a carrier PWM modulation method for a compact quasi-Z-source dual-output inverter of the present invention includes the following steps:

[0119] Step 1: Set the same number of switching modules and reasonable switching states for the A-phase, B-phase, and C-phase bridge arms of the compact quasi-Z-source dual-output inverter. There is a constraint relationship between the potential of the upper output terminal and the potential of the lower output terminal on each phase bridge arm of the compact quasi-Z-source dual-output inverter, and they are the same. For the A-phase bridge arm, the potential of the upper output terminal V a1 ≥ the potential of the lower output terminal V a2 . The A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm all have 6 switching modules and 8 reasonable switching states. For the A-phase bridge arm:

[0120] Switching state 1: Switching modules S 1a , switching module S 2a , switching module S 3a , switching module S 5a conduct. At this time, the potential of the upper output terminal V a1 is U dc / 2, and the potential of the lower output terminal V a2 is U dc / 2;

[0121] Switching state 2: Switching modules S 1a , switching module S 3a , switching module S 5a , switching module S 6a conduct. At this time, the potential of the upper output terminal V a1 is U dc / 2, and the potential of the lower output terminal V a2 is 0;

[0122] Switching state 3: Switching modules S 1a , switching module S 4a , switching module S 5a , switching module S 6a conduct. At this time, the potential of the upper output terminal V a1 is U dc / 2, and the potential of the lower output terminal V a2 is -U dc / 2;

[0123] Switching state 4: Switching modules S2a , switch module S 3a , switch module S 5a , switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is 0, and the potential V of the lower output terminal a2 is 0;

[0124] Switch state 5: Switch module S 2a , switch module S 4a , switch module S 5a , switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is 0, and the potential V of the lower output terminal a2 is -U dc / 2;

[0125] Switch state 6: Switch module S 2a , switch module S 3a , switch module S 4a , switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is -U dc / 2, and the potential V of the lower output terminal a2 is -U dc / 2;

[0126] Switch state 7: Switch module S 1a , switch module S 3a , switch module S 4a , switch module S 5a , switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is U dc / 2, and the potential V of the lower output terminal a2 is 0;

[0127] Switch state 8: Switch module S 1a , switch module S 2a , switch module S 4a , switch module S 5a , switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is 0, and the potential V of the lower output terminal a2 is -U dc / 2;

[0128] The switching states of the B-phase bridge arm and the C-phase bridge arm are the same as those of the A-phase bridge arm;

[0129] Step 2: For the upper-side quasi-Z-source network, when it is in the direct-through state, switch module S 1a, Switch module S 2a , Switch module S 3a , Switch module S 4a conducts, diode D1 is reverse-biased and turned off, and power supply V dc1 and capacitor C U1 charge inductor L1, and capacitor C U2 charges inductor L2; when in the non-through state, diode D1 conducts, and power supply V dc1 and inductors L1, L2 charge capacitor C U1 , C U2 and supply energy to the load; for the lower quasi-Z-source network, when in the through state, switch modules S 3a , Switch module S 4a , Switch module S 5a , Switch module S 6a conduct, diode D2 is reverse-biased and turned off, and power supply V dc2 and capacitor C L2 charge inductor L3, and capacitor C L1 charges inductor L4; when in the non-through state, diode D2 conducts, and power supply V dc2 and inductors L3, L4 charge capacitor C L1 , C L2 and supply energy to the load; when the upper quasi-Z-source network is in the through state, the lower quasi-Z-source network is in the non-through state; when the lower quasi-Z-source network is in the through state, the upper quasi-Z-source network is in the non-through state;

[0130] Step 3: Adopt carrier PWM modulation with injected third harmonics and added DC offset and DC pulsation, and use two triangular carriers u c1 and u c2 , and adopt the in-phase stacking method, that is, the frequencies of the two triangular carriers u c1 , u c2 are the same, the amplitudes are the same, and the variation range of u c1 is 0 to 1, and the variation range of u c2 is -1 to 0; the two carriers are as shown in Figure 10 ;

[0131] Define the through duty cycles d1 and d2 of the upper quasi-Z-source network and the lower quasi-Z-source network. The expressions for the through duty cycles of the upper quasi-Z-source network and the lower quasi-Z-source network are:

[0132] d1 = T1 / T s

[0133] d2 = T2 / T s

[0134] where, T sRepresents the time of a switching period, where T1 and T2 are the switching periods T of the upper quasi-Z-source network and the lower quasi-Z-source network respectively s The time of in-phase conduction within;

[0135] Define two groups of injected third harmonics as u x13 and u x23 , where x ∈ {A, B, C}. The expression of the first group of third harmonics u x13 is:

[0136]

[0137] The expression of the second group of third harmonics u x23 is:

[0138]

[0139] where a is the multiple of the injected third harmonic; are the initial phase angles of the first group and the second group of third harmonics respectively, and the value range of

[0140] Define two groups of sinusoidal modulation waves u x1 and u x2 , where x ∈ {A, B, C}. The expression of the first group of sinusoidal modulation waves u x1 is:

[0141]

[0142] The expression of the second group of sinusoidal modulation waves u x2 is:

[0143]

[0144] where m1 and m2 are the modulation depths of the first group of modulation waves and the second group of modulation waves respectively. The value range of m1 is 0 to 1 - d1, and the value range of m2 is 0 to 1 - d2; ω1 and ω2 are the angular frequencies of the first group and the second group of modulation waves respectively, are the initial phase angles of the first group and the second group of modulation waves respectively, and the value range of offect1 is -π / 2 to π / 2; U offect2 is the DC offset of the first group of modulation waves, and U Figure 11 is the DC offset of the second group of modulation waves; the periods of the two groups of modulation waves are set as T3 and T4 respectively, that is, T3 = 2π / ω1, T4 = 2π / ω2; the two groups of modulation waves are as

[0145] Define two DC pulsating quantities V U and V LTo control the direct-through duty ratio of the quasi-Z-source network, V U ranges from 0.5 to 1, and V L ranges from -1 to -0.5;

[0146] The modulation waves u x1 and u x2 are respectively compared with two triangular carrier waves u c1 and u c2 to determine the potentials of the two sets of output terminals V x1 and V x2 , where x ∈ {A, B, C}. The specific comparison method is as follows:

[0147] ① If u x1 > u c1 , V x1 is U dc / 2; if u x1 ≤ u c2 , V x1 is -U dc / 2; if u c2 ≤ u x1 ≤ u c1 , V x1 is 0; the potential of the AC output terminal of inverter 1, V x1 is as shown in Figure 11 ;

[0148] ② If u x2 > u c2 , V x2 is 0; if u x2 ≤ u c2 , V x2 is -U dc / 2; the potential of the AC output terminal of inverter 2, V x2 is as shown in Figure 11 ;

[0149] Step 4: Define the line voltage amplitudes between phase A and phase B of the two sets of AC outputs as U A1B1 and U A2B2 . The relationship between the AC output line voltage amplitudes U A1B1 and U A2B2 and the modulation degrees m1 and m2 of the two sets of sine modulation waves is as follows:

[0150]

[0151] Step 5: Analyze the logic operations for generating the drive signals of each switch module; a drive signal value of 1 indicates that the switch module is turned on, and a drive signal value of 0 indicates that the switch module is turned off;

[0152] Compare the first set of modulation wave u x1 with the carrier wave uc1 Compare, and generate a signal e1 according to the comparison result:

[0153]

[0154] Compare the first set of modulated waves u x1 with the carrier wave u c2 Compare, and generate a signal e2 according to the comparison result:

[0155]

[0156] Compare the second set of modulated waves u x2 with the carrier wave u c1 Compare, and generate a signal e3 according to the comparison result:

[0157]

[0158] Compare the second set of modulated waves u x2 with the carrier wave u c2 Compare, and generate a signal e4 according to the comparison result:

[0159]

[0160] Generate a signal e5 from the signal e1 and the signal e2:

[0161]

[0162] wherein, represents performing a logical NOT operation on u, and the symbol "&" represents a logical AND operation;

[0163] Generate a signal e6 from the signal e3 and the signal e4:

[0164]

[0165] Compare the DC pulsating quantity V U with the carrier wave u c1 , and generate a signal e7 according to the comparison result:

[0166]

[0167] Compare the DC pulsating quantity V L with the carrier wave u c2 , and generate a signal e8 according to the comparison result:

[0168]

[0169] Analyze the drive signals s of the 6 switching modules S 1x ~S 6x of each phase leg according to the signals e1~e8 and 8 reasonable switching states of the compact quasi-Z-source dual-output inverter1x ~s 6x , where x ∈ {a, b, c}:

[0170] ① At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, the switch module S 1x conducts, and the drive signal s 1x of the switch module S 1x has the expression:

[0171] s 1x = e1 ∨ (e2 & e9)

[0172] The symbol "∨" represents the logical OR operation, and the symbol "&" represents the logical AND operation;

[0173] ② At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, the switch module S 2x conducts, and the drive signal s 2x of the switch module S 2x has the expression:

[0174]

[0175] represents the logical NOT operation on u;

[0176] ③ At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is -U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2, the switch module S 3x conducts, and the driving signal s 3x of the switch module S 3x has the expression:

[0177]

[0178] ④ When the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is -U dc / 2; the potential of the upper output terminal V x1 is -U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2, the switch module S 4x conducts, and the driving signal s 4x of the switch module S 4x has the expression:

[0179]

[0180] ⑤ When the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is U dc / 2; the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is U dc / 2, and the potential of the lower output terminal V x2 is -U dc / 2; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is 0; the potential of the upper output terminal V x1 is 0, and the potential of the lower output terminal V x2 is -U dc / 2, the switch module S5x Conduct, switch module S 5x The drive signal s of 5x The expression is:

[0181]

[0182] ⑥ At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, when the switch module S 6x conducts, the switch module S 6x The drive signal s of 6x The expression is:

[0183]

[0184] According to the above analysis, a logic circuit capable of generating a power switch drive signal is obtained, as shown in Figure 11 shown. In the figure, the symbol represents a comparison operation. When the positive terminal "+" input signal is greater than the negative terminal "-" input signal, the output is a high level "1", otherwise, the output is a low level "0".

[0185] Step six: Through steps one to five, the drive signals of the 18 switch modules of the compact quasi-Z-source dual-output inverter can be obtained, and the carrier PWM modulation is completed, so that the compact quasi-Z-source dual-output inverter outputs two sets of three-phase three-level AC outputs with adjustable phases and amplitudes.

[0186] To verify the effectiveness of a carrier PWM modulation method for a compact quasi-Z-source dual-output inverter of the present invention, a simulation circuit is built through MATLAB / Simulink. The simulation parameters are as follows: both groups of DC power supplies are 240V, the rated boost ratios of the upper and lower quasi-Z-source networks are both 1.25, the DC link voltage is 600V, and the quasi-Z-source network capacitors C U1 = C U2 = C L1 = C L2= 2500 uF, the inductors of the quasi-Z-source network L1 = L2 = L3 = L4 = 1.5 mF, the carrier frequency is 10 kHz, the resistance of the three-phase resistive-inductive load connected to the first set of AC outputs is 10 Ω, and the inductance is 10 mH; the resistance of the three-phase resistive-inductive load connected to the second set of AC outputs is 10 Ω, and the inductance is 10 mH; the modulation index m1 of the first set of modulation waves is 0.8, and the frequency is 50 Hz; the modulation index m2 of the second set of modulation waves is 0.7, and the frequency is 50 Hz.

[0187] The simulation results are as Figures 12 - 17 shown, Figure 12 The waveform of the upper DC-link voltage U Upn shows that the upper DC-link voltage is stable at 300 V, meeting the 1.25-fold rated boost ratio; Figure 13 The waveform of the lower DC-link voltage U Lpn shows that the lower DC-link voltage is stable at 300 V, meeting the 1.25-fold rated boost ratio; Figure 14 is the waveform of the line voltage U A1B1 output by the upper output inverter stage 1, and the waveform shows that the load line voltage has five levels: 600 V, 300 V, 0 V, -300 V, and -600 V; Figure 15 is the waveform of the line voltage U A2B2 output by the lower output inverter stage 2, and the waveform shows that the load line voltage has five levels: 600 V, 300 V, 0 V, -300 V, and -600 V; Figure 16 The waveform of the upper output three-phase load current is shown, and the fundamental amplitude is 22.38 A, and the frequency is 50 Hz; Figure 17 The waveform of the lower output three-phase load current is shown, and the fundamental amplitude is 19.59 A, and the frequency is 50 Hz.

[0188] The above simulation results show that the carrier PWM modulation method of the compact quasi-Z-source dual-output inverter of the present invention can independently adjust the amplitudes and phases of the two sets of output voltages of the compact quasi-Z-source dual-output inverter.

[0189] It can be understood that the present invention is described through some embodiments. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A carrier PWM modulation method for a compact quasi-Z-source dual-output inverter, characterized in that, Inject the third harmonic into the modulation wave and add a DC offset and a DC pulsation. For the 6 conventional switching states and 2 switching states with the quasi-Z-source direct connection added of the A-phase bridge arm, B-phase bridge arm, and C-phase bridge arm of the compact quasi-Z-source dual-output inverter, use two groups of modulation waves that inject the third harmonic and add a DC offset and a DC pulsation to compare with the in-phase stacked carrier waves respectively, and derive the logical operations for generating the drive signals of each switching module according to the switching states and comparison results; It includes the following steps: Step 1: There is a constraint relationship between the potential of the upper output terminal and the potential of the lower output terminal on each phase leg of the compact quasi-Z-source dual-output inverter, and they are the same. For the A-phase leg, the potential of the upper output terminal V a1 ≥ the potential of the lower output terminal V a2 ; Set the same number of switching modules and reasonable switching states for the A-phase bridge arm, B-phase bridge arm, and C-phase bridge arm of the compact quasi-Z-source dual-output inverter. Each phase bridge arm has 6 switching modules and 8 reasonable switching states. For the A-phase bridge arm: Switch state 1: Switch module S 1a , Switch module S 2a , Switch module S 3a , Switch module S 5a conducts. At this time, the potential V a1 of the upper output terminal is U dc / 2, and the potential V a2 of the lower output terminal is U dc / 2; Switch state 2: Switch module S 1a and switch module S 3a and switch module S 5a and switch module S 6a conduct. At this time, the potential V of the upper output terminal a1 is U dc / 2, and the potential V of the lower output terminal a2 is 0; Switch state 3: Switch module S 1a , Switch module S 4a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is U dc / 2, and the potential V of the lower output terminal a2 is -U dc / 2; Switch state 4: Switch module S 2a , Switch module S 3a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is 0, and the potential V of the lower output terminal a2 is 0; Switch state 5: Switch module S 2a , Switch module S 4a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is 0, and the potential V of the lower output terminal a2 is -U dc / 2; Switch state 6: Switch module S 2a , Switch module S 3a , Switch module S 4a , Switch module S 6a conducts. At this time, the potential V of the upper output terminal a1 is -U dc / 2, and the potential V of the lower output terminal a2 is -Udc / 2; Switch state 7: Switch module S 1a , Switch module S 3a , Switch module S 4a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential V a1 of the upper output terminal is U dc / 2, and the potential V a2 of the lower output terminal is 0; Switch state 8: Switch module S 1a , Switch module S 2a , Switch module S 4a , Switch module S 5a , Switch module S 6a conducts. At this time, the potential of the upper output terminal V a1 is 0, and the potential of the lower output terminal V a2 is -U dc / 2; The switching states of the B-phase bridge arm and the C-phase bridge arm are the same as those of the A-phase bridge arm by the same token; Step 2: For the upper quasi-Z-source network, when in the direct-through state, switch module S 1a , switch module S 2a , switch module S 3a , switch module S 4a conduct, diode D1 bears reverse voltage and turns off, power supply V dc1 and capacitor C U1 charge inductor L1, capacitor C U2 charges inductor L2; when in the non-direct-through state, diode D1 conducts, power supply V dc1 and inductors L1, L2 charge capacitors C U1 , C U2 and supply energy to the load; for the lower quasi-Z-source network, when in the direct-through state, switch module S 3a , switch module S 4a , switch module S 5a , switch module S 6a conduct, diode D2 bears reverse voltage and turns off, power supply V dc2 and capacitor C L2 charge inductor L3, capacitor C L1 charges inductor L4; when in the non-direct-through state, diode D2 conducts, power supply V dc2 and inductors L3, L4 charge capacitors C L1 , C L2 and supply energy to the load; when the upper quasi-Z-source network is in the direct-through state, the lower quasi-Z-source network is in the non-direct-through state; when the lower quasi-Z-source network is in the direct-through state, the upper quasi-Z-source network is in the non-direct-through state; Step 3: Adopt carrier PWM modulation that injects the third harmonic and adds DC offset and DC pulsation, and use two triangular carriers u c1 and u c2 , and adopt the in-phase stacking method, that is, the phases of the two triangular carriers u c1 and u c2 are the same, the frequencies are the same, and the variation range of u c1 is 0 to 1, and the variation range of u c2 is -1 to 0; Step 4: Define that the line voltage amplitudes between two groups of AC outputs, phase A and phase B, are U A1B1 , U A2B2 , respectively. The relationship between the line voltage amplitudes U A1B1 , U A2B2 between phase A and phase B of the AC output and the modulation depths m1, m2 of two groups of sine modulation waves is as follows: Step 5: The logical operations for generating the drive signals of each switching module; A drive signal value of 1 indicates that the switching module is turned on; a drive signal value of 0 indicates that the switching module is turned off; Compare the first set of modulated waves u x1 with the carrier wave u c1 and generate a signal e1 based on the comparison result: Compare the first set of modulated waves u x1 with the carrier wave u c2 and generate a signal e2 according to the comparison result: Compare the second set of modulation waves u x2 with the carrier wave u c1 and generate a signal e3 according to the comparison result: Compare the second set of modulated waves u x2 with the carrier wave u c2 and generate a signal e4 according to the comparison result: Generate signal e5 from signal e1 and signal e2: Among them, represents the logical NOT operation on u, and the symbol "&" represents the logical AND operation; Generate signal e6 from signal e3 and signal e4: The DC pulsation V U and the carrier wave u c1 , according to the comparison result, generate the signal e7: The DC pulsation V L and the carrier wave u c2 , according to the comparison result, generate the signal e8: According to the signals e1 to e8 and the eight reasonable switching states of the compact quasi-Z-source dual-output inverter, analyze the driving signals s 1x ~S 6x of the six switching modules S 1x ~s 6x , where x ∈ {a, b, c}: At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2. When the switch module S 1x conducts, the driving signal s 1x of the switch module S 1x has the following expression: s 1x = e1 ∨ (e2 & e9) The symbol "∨" represents the logical OR operation, and the symbol "&" represents the logical AND operation; At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; when the potential V x1 at the upper output terminal is 0 and the potential V x2 at the lower output terminal is 0; when the potential V x1 at the upper output terminal is 0 and the potential V x2 at the lower output terminal is -U dc / 2; when the potential V x1 at the upper output terminal is -U dc / 2 and the potential V x2 at the lower output terminal is -U dc / 2, the switch module S 2x conducts, and the drive signal s 2x of the switch module S 2x has the following expression: means performing a logical NOT operation on u; At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2, the switch module S 3x conducts, and the drive signal s 3x of the switch module S 3x has the following expression: At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; when the potential V x1 at the upper output terminal is 0 and the potential V x2 at the lower output terminal is -U dc / 2; when the potential V x1 at the upper output terminal is -U dc / 2 and the potential V x2 at the lower output terminal is -U dc / 2, the switch module S 4x conducts, and the drive signal s 4x of the switch module S 4x has the following expression: At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is U dc / 2; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is -U dc / 2, the switch module S 5x conducts, and the drive signal s 5x of the switch module S 5x has the expression: At the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2; at the upper output terminal, the potential V x1 is 0, and at the lower output terminal, the potential V x2 is 0; at the upper output terminal, the potential V x1 is -U dc / 2, and at the lower output terminal, the potential V x2 is -U dc / 2. When this occurs, the switch module S 6x conducts, and the drive signal s 6x of the switch module S 6x has the following expression:

2. The carrier PWM modulation method of the compact quasi-Z-source dual-output inverter according to claim 1, characterized in that Define the direct connection duty ratios d1 and d2 of the upper quasi-Z-source network and the lower quasi-Z-source network in step 3. The expressions for the direct connection duty ratios of the upper quasi-Z-source network and the lower quasi-Z-source network are: d1 = T1 / T s d2 = T2 / T s Among them, T s represents the time of a switching period, and T1 and T2 are the conduction times within a switching period T of the upper quasi-Z-source network and the lower quasi-Z-source network respectively s respectively; Define two sets of injected third harmonics as u x13 and u x23 , where the expression of the first set of third harmonics u x13 is: The second group of third harmonics u x23 has the following expression: where a is the multiple of the injected third harmonic; Define two sets of sinusoidal modulation waves u x1 and u x2 , where the expression of the first set of sinusoidal modulation wave u x1 is: The second group of sine modulation waves u x2 has the following expression: wherein, m1 and m2 are the modulation depths of the first group of modulation waves and the second group of modulation waves respectively, the value range of m1 is from 0 to 1 - d1, and the value range of m2 is from 0 to 1 - d2; ω1 and ω2 are the angular frequencies of the first group and the second group of modulation waves respectively, which are the initial phase angles of the first group and the second group of modulation waves respectively, whose value range is from -π / 2 to π / 2; U offect1 is the DC offset of the first group of modulation waves, and U offect2 is the DC offset of the second group of modulation waves; the periods of the two groups of modulation waves are set as T3 and T4 respectively, that is, T3 = 2π / ω1, T4 = 2π / ω2; Modulating wave u x1 and u x2 respectively compare magnitudes with triangular carrier waves u c1 and u c2 to determine the potential V x1 at the upper output terminal and the potential V x2 at the lower output terminal; Define two periodically varying DC pulsating quantities V U and V L . The DC pulsating quantities V U and V L are respectively compared with the triangular carrier waves u c1 and u c2 to control the direct-through duty ratios of the upper quasi-Z-source network and the lower quasi-Z-source network. The value range of V U is 0.5 to 1, and the value range of V L is -1 to -0.

5.

3. A compact quasi-Z-source dual-output inverter using the carrier PWM modulation method of the compact quasi-Z-source dual-output inverter described in claim 1 or 2, characterized in that, Comprising two sets of DC power supplies V connected in sequence dc1 、V dc2 、an upper quasi-Z-source network, a lower quasi-Z-source network, and a three-level inverter with two AC output ports; wherein, the positive pole of the DC power supply V dc1 is connected to the input end of the upper quasi-Z-source network, the negative pole of the DC power supply V dc2 is connected to the input end of the lower quasi-Z-source network, and the midpoints of the two sets of DC power supplies V dc1 、V dc2 are connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network; the output end of the upper quasi-Z-source network is connected to the positive extreme P of the three-level inverter, the output end of the lower quasi-Z-source network is connected to the negative extreme N of the three-level inverter, and the midpoint O of the two sets of quasi-Z-source networks is connected to the midpoint of the three-level inverter; the three-level inverter has three-phase bridge arms: an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm, and each phase bridge arm is composed of 6 switching modules S 1x ~S 6x wherein, x ∈ {a, b, c}, and each switching module is composed of an insulated gate bipolar transistor T kx and an anti-parallel diode D kx ; the subscript symbol kx of the symbol T kx and the symbol D kx represents the switching module where it is located, wherein, x ∈ {a, b, c}, k ∈ {1, 2, 3, 4, 5, 6}.

4. The compact quasi-Z-source dual-output inverter according to claim 3, characterized in that, The structures of the upper quasi-Z-source network and the lower quasi-Z-source network include inductor L1, inductor L2, inductor L3, inductor L4, capacitor C U1 , capacitor C U2 , capacitor C L1 , capacitor C L2 , diode D1, diode D2. One end of inductor L1 is connected to the positive pole of DC power supply V dc1 . The other end of inductor L1 is connected to the anode of diode D1 and the negative pole of capacitor C U1 . The cathode of diode D1 is connected to one end of inductor L2 and the positive pole of capacitor C U2 . The positive pole of capacitor C U1 is connected to the other end of inductor L2 and the positive terminal P of the three-level inverter; The positive pole of DC power supply V dc2 is connected to the negative pole of DC power supply V dc1 . The negative pole of DC power supply V dc2 is connected to one end of inductor L3. The other end of inductor L3 is connected to the cathode of diode D2 and the positive pole of capacitor C L2 . The anode of diode D2 is connected to one end of inductor L4 and the negative pole of capacitor C L1 . The negative pole of capacitor C L2 is connected to the other end of inductor L4 and the negative terminal N of the three-level inverter. The negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 . And the point where the negative pole of capacitor C U2 is connected to the positive pole of capacitor C L1 is defined as the midpoint O.

5. The compact quasi-Z-source dual-output inverter according to claim 3, characterized in that, The switch module S kx The anode of the diode D kx is connected to the emitter of the insulated gate bipolar transistor T kx and the point where the anode of the diode D kx is connected to the emitter of the insulated gate bipolar transistor T kx is defined as the emitter of the switch module S kx The cathode of the diode D kx is connected to the collector of the insulated gate bipolar transistor T kx and the point where the cathode of the diode D kx is connected to the collector of the insulated gate bipolar transistor T kx is defined as the collector of the switch module S kx The A-phase bridge arm has two output terminals, namely the AC output terminal A1 and the AC output terminal A2. The B-phase bridge arm has two output terminals, namely the AC output terminal B1 and the AC output terminal B2. The C-phase bridge arm has two output terminals, namely the AC output terminal C1 and the AC output terminal C2. The three AC output terminals A1, B1 and C1 together form the inverter stage 1. The three AC output terminals A2, B2 and C2 together form the inverter stage 2. The three-phase resistive-inductive load carried by the inverter stage 1 is Z LA1 , Z LB1 , Z LC1 , and the three-phase resistive-inductive load carried by the inverter stage 2 is Z LA2 , Z LB2 , Z LC2 ; Three-phase resistive-inductive load Z LA1 , Z LB1 , Z LC1 One ends of are respectively connected to the AC output terminals A1, B1, and C1. The other ends of the three-phase resistive-inductive loads Z LA1 , Z LB1 , Z LC1 are connected to each other; One ends of the three-phase resistive-inductive loads Z LA2 , Z LB2 , Z LC2 are respectively connected to the AC output terminals A2, B2, and C2. The other ends of the three-phase resistive-inductive loads Z LA2 , Z LB2 , Z LC2 are connected to each other.

6. The compact quasi-Z-source dual-output inverter according to claim 3, wherein, Switch module S 1a The collector of which is connected to the positive terminal P of the three-level inverter. The emitter of switch module S 1a is connected to the collector of switch module S 2a The emitter of which is connected to the collector of switch module S 2a is connected to the collector of switch module S 3a The emitter of which is connected to the collector of switch module S 3a is connected to the collector of switch module S 4a The emitter of which is connected to the collector of switch module S 4a is connected to the negative terminal N of the three-level inverter; The emitter of switch module S 1a is connected to the collector of switch module S 2a The point of connection is defined as the AC output terminal A1; The emitter of switch module S 3a is connected to the collector of switch module S 4a The point of connection is defined as the AC output terminal A2; The collector of switch module S 5a is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of switch module S 5a is connected to the emitter of switch module S 6a The collector of which is connected to the emitter of switch module S 6a is connected to the emitter of switch module S 2a ​ 7. The compact quasi-Z-source dual-output inverter according to claim 3, wherein Switch module S 1b The collector of is connected to the positive terminal P of the three-level inverter. The emitter of switch module S 1b is connected to the collector of switch module S 2b The emitter of is connected to the collector of switch module S 2b is connected to the collector of switch module S 3b The emitter of is connected to the collector of switch module S 3b is connected to the collector of switch module S 4b The emitter of is connected to the collector of switch module S 4b is connected to the negative terminal N of the three-level inverter. The emitter of switch module S 1b is connected to the collector of switch module S 2b The connection point of is defined as the AC output terminal B1. The emitter of switch module S 3b is connected to the collector of switch module S 4b The connection point of is defined as the AC output terminal B2. The collector of switch module S 5b is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of switch module S 5b is connected to the emitter of switch module S 6b The collector of is connected to the emitter of switch module S 6b is connected to the emitter of switch module S 2b ​ 8. The compact quasi-Z-source dual-output inverter according to claim 3, wherein Switch module S 1c The collector of which is connected to the positive terminal P of the three-level inverter. The emitter of switch module S 1c is connected to the collector of switch module S 2c The emitter of which is connected to the collector of switch module S 2c is connected to the collector of switch module S 3c The emitter of which is connected to the collector of switch module S 3c is connected to the collector of switch module S 4c The emitter of which is connected to the collector of switch module S 4c is connected to the negative terminal N of the three-level inverter. The emitter of switch module S 1c is connected to the collector of switch module S 2c The connection point of which is defined as the AC output terminal C1. The emitter of switch module S 3c is connected to the collector of switch module S 4c The connection point of which is defined as the AC output terminal C2. The collector of switch module S 5c is connected to the midpoint O of the upper quasi-Z-source network and the lower quasi-Z-source network. The emitter of switch module S 5c is connected to the emitter of switch module S 6c The collector of which is connected to the emitter of switch module S 6c is connected to the emitter of switch module S 2c ​

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