Test stimulus compression method, device and circuit based on variable-length LFSR

Abstract

The present application discloses a test stimulus compression method, device and circuit based on variable-length LFSR. The circuit includes: a variable-length LFSR module, the variable-length LFSR module has an excitation input end for receiving the original test stimulus in the original test vector of the chip to be tested, and a signal input end for receiving a control signal. The variable-length LFSR module is used to select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, call the target LFSR, and compress the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, where different LFSRs match different numbers of determined bits; a multiplexed phase shift module adapted to the variable-length LFSR module is connected to the variable-length LFSR module, each phase shift module in the multiplexed phase shift module corresponds to an LFSR, and the phase shift module is used to process the output dependency of the corresponding LFSR. The present application solves the technical problem of a large amount of test data in the related art.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a test stimulus compression method, device and circuit based on variable-length LFSR. Background Art

[0002] This section is intended to provide a background or context to what is stated in the claims or specification, and no admission is made that what is described herein is prior art by inclusion in this section.

[0003] In the field of integrated circuit design, Electronic Design Automation (EDA) tools are large-scale industrial software that assists designers in completing circuit design work. Digital integrated circuits will inevitably introduce some defects during manufacturing. In order to effectively test the chip, EDA tools are needed to perform design for testability (DFT) and automatic test pattern generation (ATPG) on the circuit. After tape-out, the test instrument uses the test vectors generated by ATPG to test the chip. As the scale of digital integrated circuits gradually increases, the amount of test data and the number of channels required for testing also increase. However, the data bandwidth and number of test channels of the test instrument are limited, which leads to an increase in test costs. This requires reducing the amount of test data and test time, that is, test compression.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a test stimulus compression method, device and circuit based on a variable-length LFSR, so as to at least solve the technical problem of a large amount of test data in the related art.

[0006] According to one aspect of an embodiment of the present application, a test stimulus compression circuit based on a variable-length LFSR is provided, comprising: a variable-length LFSR module, the variable-length LFSR module having a stimulus input end for receiving an original test stimulus in an original test vector of a chip to be tested, and a signal input end for receiving a control signal, the variable-length LFSR module being used to select a target LFSR that matches the number of determined bits in the original test stimulus from a plurality of LFSRs according to the control signal, calling the target LFSR, and compressing the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits; a multiplexed phase shift module adapted to the variable-length LFSR module, connected to the variable-length LFSR module, each phase shift module in the multiplexed phase shift module corresponding to an LFSR, and the phase shift module being used to process the output dependency of the corresponding LFSR.

[0007] Optionally, the variable-length LFSR module includes: a first decoder, used to decode the scan input of the stimulus input end to obtain the original test stimulus; multiple triggers, the multiple LFSRs multiplex the multiple triggers; a second decoder, used to select triggers from the multiple triggers according to the control signal of the signal input end to form the target LFSR.

[0008] According to another aspect of an embodiment of the present application, a test instrument is further provided, comprising the above-mentioned test stimulus compression circuit based on variable-length LFSR.

[0009] According to another aspect of an embodiment of the present application, a test stimulus compression method based on a variable-length LFSR is also provided, including: obtaining an original test stimulus and a control signal in an original test vector of a chip to be tested; selecting a target LFSR that matches the number of determined bits in the original test stimulus from a plurality of LFSRs according to the control signal, and calling the target LFSR, and compressing the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

[0010] Optionally, a target LFSR that matches the number of determined bits in the original test stimulus is selected from multiple LFSRs according to the control signal, and the target LFSR is called, and the original test stimulus is compressed using a time-series linear transformation method to obtain a compressed test stimulus, including: inputting the control signal into the test stimulus compression circuit of the variable-length LFSR to instruct the test stimulus compression circuit of the variable-length LFSR to select the target LFSR that matches the number of determined bits in the original test stimulus, and inputting the original test stimulus into the test stimulus compression circuit of the variable-length LFSR; obtaining the compressed test stimulus obtained by the test stimulus compression circuit of the variable-length LFSR compressing the test stimulus using the target LFSR.

[0011] Optionally, before obtaining the original test stimulus in the original test vector of the chip to be tested, the method also includes: in the process of generating the test stimulus of the chip to be tested through ATPG, using a test vector generation decision method for the determined number of bits to reduce the number of determined bits in the generated test stimulus.

[0012] Optionally, a test vector generation decision method for a certain number of bits is used to reduce the number of certain bits in the generated test stimulus, including: using a preset calculation method to calculate the controllability of each logic gate based on the type of logic gates in the chip to be tested and the topological relationship of the circuit; when running an adjustment decision, making adjustments based on the calculated controllability to generate a test stimulus for the chip to be tested.

[0013] According to another aspect of an embodiment of the present application, a test stimulus compression device based on a variable-length LFSR is also provided, including: an acquisition unit, used to acquire the original test stimulus and control signal in the original test vector of the chip to be tested; a compression unit, used to select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, and call the target LFSR, and use a time-series linear transformation method to compress the original test stimulus to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

[0014] According to another aspect of an embodiment of the present application, a storage medium is further provided, which includes a stored program, and the above method is executed when the program is run.

[0015] According to another aspect of an embodiment of the present application, an electronic device is further provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above method through the computer program.

[0016] According to one aspect of the present application, a computer program product or a computer program is provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the embodiments of the above method.

[0017] In an embodiment of the present application, the compression circuit includes a variable-length LFSR module and an adapted multiplexed phase shift module. The variable-length LFSR module has an excitation input end for receiving an original test stimulus in an original test vector of the chip to be tested and a signal input end for receiving a control signal. The variable-length LFSR module is used to select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, call the target LFSR, and use a sequential linear transformation method to compress the original test stimulus to obtain a compressed test stimulus, where different LFSRs match different numbers of determined bits; each phase shift module in the multiplexed phase shift module corresponds to an LFSR, and the phase shift module is used to process the output dependency of the corresponding LFSR. In the technical solution of the present application, a test stimulus compression scheme for a variable-length LFSR is proposed. For test stimuli with different numbers of determined bits, LFSRs of different lengths are used for compression, thereby solving the technical problem of a large amount of test data in the related technology and reducing the overall LFSR initialization time; a decision method for generating a test vector for a determined number of bits is proposed, so that the number of determined bits in the generated test stimulus is smaller, thereby improving the test stimulus compression capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 is a schematic diagram of a test stimulus compression circuit based on a variable-length LFSR according to an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a test stimulus compression circuit based on a variable-length LFSR according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of the relationship between the characteristic polynomial and the LFSR in a finite field according to an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a test stimulus compression circuit based on a variable-length LFSR according to an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of the structure of an optional LFSR according to an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of an optional controllability according to an embodiment of the present application;

[0025] Figure 7 is a flow chart of a test stimulus compression method based on a variable-length LFSR according to an embodiment of the present application;

[0026] Figure 8 is a flow chart of a test stimulus compression method based on a variable-length LFSR according to an embodiment of the present application;

[0027] Fig. 9 is a schematic diagram of a test stimulus compression device based on a variable-length LFSR according to an embodiment of the present application;

[0028] Fig.10 It is a structural block diagram of a terminal according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In testability design, scan chain technology can be used to improve the testability of the chip. Scan chain technology replaces the triggers in the chip with scan units, and strings these scan units into multiple scan chains. Suppose the number of scan chains is M, and the length of the longest scan chain is L. Then, all scan units can be assigned values ​​through M scan ports and L scan clock cycles. The data volume of the test vectors on the scan chain accounts for a large proportion of the total test vectors. Therefore, test compression technology is to compress the test data on the scan chain.

[0032] The test vector can be divided into two parts: test stimulus and test response. The test stimulus refers to the input of the scan chain of the circuit under test, and the test response refers to the expected output of the scan chain of the circuit under test. The corresponding test compression technology is also divided into two categories: test stimulus compression and test response compression. This scheme is a test stimulus compression scheme. Through test stimulus compression, the number of M scan ports is compressed into N, thereby reducing the amount of test data. Test stimulus compression methods are divided into encoding method, broadcast scanning method, and linear transformation method. In the linear transformation method, the test stimulus compression can be converted into a linear equation group to solve the problem by constructing a circuit corresponding to a linear equation group. The linear transformation method can be divided into a combination linear transformation method and a sequential linear transformation method according to the type of circuit. Among them, the compression rate of the sequential transformation method is higher than that of the combination linear transformation method.

[0033] After analysis, the inventors realized that there are two types of data in the test stimulus: determined bits and don't care bits. Logical value 0 or logical value 1 belongs to determined bits. Changing the numerical value of the determined bit will make the test stimulus unable to detect the corresponding fault; the logical value of the don't care bit (or uncertain bit, which can be represented by X) can be modified arbitrarily without affecting the detection of the fault.

[0034] The goal of test stimulus compression is to compress the test stimulus data y into x, and then decompress x into y1 through the circuit, while the logical values ​​of the determined bits in y1 and y remain unchanged. The corresponding time-series linear transformation method needs to ensure the corresponding test stimulus data y, select the linear equations corresponding to the determined bits, and construct a linear equation group. The linear equation group can be solved successfully, and the solution x of the equation is the corresponding compressed data.

[0035] If the linear equations can be solved successfully, the rank of the linear matrix corresponding to the linear equations must be large enough. The rank of the linear matrix is ​​determined by the corresponding circuit structure. The length of the LFSR (LFSR stands for Linear Feedback Shift Register, which is a sequence generator commonly used in digital circuits and cryptography. LFSR consists of a group of flip-flops (usually D flip-flops) and some logic gates to generate a cyclic binary sequence) in the sequential linear transformation method determines the rank of the linear matrix.

[0036] In order to compress all test stimuli successfully, the rank of the linear matrix must be greater than the maximum number of determined bits in the test stimulus, and the corresponding LFSR must be large enough for the linear transformation method of timing. It takes two steps to decompress the compressed data x into y. The first step is to initialize the LFSR to specific data, and the second step is to decompress the test data and load it onto the scan chain. Therefore, the overall test stimulus application time is the LFSR initialization time plus the scan chain data loading time. The LFSR initialization time depends on the size D of the LFSR and the number of ports N scanned after compression. The scan chain data loading time depends on the length of the scan chain. Since the test application time is related to the test cost, reducing the test time can effectively reduce the test cost.

[0037] In the previous sequential linear transformation method, the size of the LFSR is fixed and depends on the maximum number of determined bits in all test stimuli. However, the number of determined bits in the test stimuli is different. The number of determined bits in most test stimuli is much smaller than the number of determined bits in the maximum test stimulus. It can be seen that for most test stimuli, such a large LFSR is not required. For these test stimuli, using an LFSR of size D will waste LFSR initialization time and increase the test cost.

[0038] During the research on test stimulus compression technology, the following two problems were found:

[0039] 1) The length of the LFSR in the sequential linear transformation method is fixed and depends on the maximum number of confirmed bits in the test stimulus. However, the number of confirmed bits in different test stimuli is different, and the number of confirmed bits of most test stimuli is much smaller than the number of confirmed bits of the maximum test stimulus. Therefore, using a fixed-size LFSR to compress all test stimuli will waste LFSR initialization time.

[0040] 2) The test excitation compression ability depends on the number of determined bits in the test excitation. If the number of determined bits in the test excitation is small, compression can be performed with fewer scan input ports. Assume that the number of scan input ports before compression is M, the length of the scan chain is L, and the data volume of a single test excitation is M*L. When the number of determined bits in the test excitation is S1, the compressed scan port number can be set to N1, and the size of the LFSR can be set to D1. Then the compressed data volume is N1*L + D1. If the number of determined bits can be reduced, the compressed port number can be set to N2, and the size of the LFSR can be set to D2, where N2 < N1 and D2 < D1. It can be seen that the fewer the number of determined bits, the better the compression effect. The number of determined bits in the test excitation depends on the decision method adopted in test vector generation. The purpose of the current decision method in test vector generation is to generate test excitation faster, rather than generating test excitation with fewer determined bits.

[0041] To address the above two problems, the present invention proposes a variable-length test excitation compression scheme. For test excitations with different numbers of determined bits, LFSRs with different lengths are used for compression, and a test vector generation decision is proposed to enable the generation of test excitation with fewer determined bits.

[0042] According to one aspect of the embodiments of the present application, an embodiment of a test excitation compression circuit based on a variable-length LFSR is provided, as Figure 1 shown, including a variable-length LFSR module 11 and a multiplexing phase shift module 12.

[0043] The variable-length LFSR module 11 (i.e., multi-poly-LFSR) has an excitation input terminal for receiving the original test excitation (i.e., scan chain input) in the original test vector of the chip under test, and a signal input terminal (i.e., control line) for receiving a control signal. The variable-length LFSR module is used to select a target LFSR that matches the number of determined bits in the original test excitation from multiple LFSRs according to the control signal, call the target LFSR, and use the timing linear transformation method to compress the original test excitation to obtain the compressed test excitation. Different LFSRs match different numbers of determined bits.

[0044] The above-mentioned variable-length LFSR module includes a first decoder (i.e., input decoder) for decoding the scan input at the excitation input terminal to obtain the original test excitation; multiple flip-flops, and multiple LFSRs (refer to Figure 2 ) multiplex multiple flip-flops (refer to Figure 4); a second decoder (ie, decoder), configured to select a trigger from a plurality of triggers to form a target LFSR according to a control signal at the signal input terminal.

[0045] The multiplex phase shifter module 12 (ie, Mux Phase Shifter) adapted to the variable-length LFSR module is connected to the variable-length LFSR module. Each phase shifter in the multiplex phase shifter module corresponds to one LFSR. The phase shifter module is used to process the output dependency of the corresponding LFSR.

[0046] In the technical solution of the present application, a test stimulus compression scheme for a variable-length LFSR is proposed to solve the two problems of using the same LFSR for compression of different test stimuli, which causes a waste of initialization time and the decision method for test vector generation is not optimized for the number of determined bits. The variable-length LFSR device reduces the initialization time of the overall LFSR; the decision method for test vector generation based on the number of determined bits reduces the number of determined bits in the test stimulus and improves the test compression rate.

[0047] According to another aspect of an embodiment of the present application, a test instrument is further provided, including the above-mentioned test stimulus compression circuit based on variable-length LFSR, and the specific implementation method refers to the previous embodiment.

[0048] According to another aspect of the embodiment of the present application, a test stimulus compression method based on a variable-length LFSR is also provided. Figure 7 As shown, the method may include the following steps:

[0049] Step S202, obtaining original test stimulus and control signal in the original test vector of the chip to be tested.

[0050] It should be noted that in the process of generating test stimulus for the chip to be tested through ATPG, a test vector generation decision method for a certain number of bits is used to reduce the number of certain bits in the generated test stimulus. Specifically: based on the type of logic gates in the chip to be tested and the topological relationship of the circuit, a preset calculation method can be used to calculate the controllability of each logic gate. When the operation adjustment decision is made, it is adjusted according to the calculated controllability to generate the test stimulus for the chip to be tested.

[0051] Step S204, select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, call the target LFSR, and use the time-series linear transformation method to compress the original test stimulus to obtain a compressed test stimulus, and different LFSRs match different numbers of determined bits.

[0052] In the above scheme, a control signal can be input into the test stimulus compression circuit of the variable-length LFSR to instruct the test stimulus compression circuit of the variable-length LFSR to select a target LFSR that matches the number of determined bits in the original test stimulus, and input the original test stimulus into the test stimulus compression circuit of the variable-length LFSR; the test stimulus compression circuit of the variable-length LFSR obtains the compressed test stimulus by compressing the test stimulus using the target LFSR.

[0053] Through the above steps, the original test stimulus and control signal in the original test vector of the chip to be tested are obtained; according to the control signal, a target LFSR that matches the number of determined bits in the original test stimulus is selected from multiple LFSRs, and the target LFSR is called, and the original test stimulus is compressed using a sequential linear transformation method to obtain a compressed test stimulus. Different LFSRs match different numbers of determined bits. By compressing the test stimulus, the technical problem of a large amount of test data in related technologies can be solved. In addition, a test stimulus compression scheme of a variable-length LFSR is adopted. For test stimuli with different numbers of determined bits, LFSRs of different lengths are used for compression, thereby reducing the overall LFSR initialization time.

[0054] In the technical solution of the present application, a test stimulus compression scheme for a variable-length LFSR is proposed. For test stimuli with different determined numbers of bits, LFSRs of different lengths are used for compression, thereby reducing the overall LFSR initialization time; a decision method for generating a test vector for a determined number of bits is proposed, so that the number of determined bits in the generated test stimulus is smaller, and the controllability of each logic gate is calculated. When making an adjustment decision, a minimum controllability is selected for adjustment based on the calculated controllability, thereby ensuring a smaller number of determined bits, thereby improving the test stimulus compression capability. As an optional embodiment, the following describes the test stimulus compression scheme for a variable-length LFSR and the decision method for generating a test vector for a determined number of bits:

[0055] The test stimulus compression scheme of the variable length LFSR of the present invention is as follows Figure 1As shown, it includes two main modules, a variable-length LFSR module multi-poly-LFSR, and a multiplexed phase shift module Mux Phase Shifter adapted to the variable-length LFSR (the LFSR acts as a decoder, while the phase shifter reduces the correlation of the LFSR output and can expand the dimension of the LFSR output). The input port of the device is divided into two parts. The first part is the compressed scan input port, denoted as Scan Channel Input, and the other part is the input port controlline of the control signal, which is used to select which length of LFSR and the corresponding Phase Shifter, and the output port is connected to the scan chain.

[0056] Multi-poly-LFSR implements switching between multiple LFSRs, such as Figure 2 As shown, multi-poly-LFSR contains a group of LFSRs (i.e., multiple LFSRs), represented by P = {LFSR1, LFSR2,…, LFSRn}. The LFSRs in P have different sizes and connection relationships, and share the same scan input. P can correspond to a set of linear matrices {M_LFSR1, M_LFSR2…, M_LFSRn}, that is, LFSR1 corresponds to the matrix M_LFSR1, LFSR2 corresponds to the matrix M_LFSR2,…, LFSRn corresponds to the matrix M_LFSRn. This set of linear matrices is used for compression, and each linear matrix must be a column full rank matrix to ensure a high success rate in solving the corresponding set of equations. Each LFSR can correspond to a characteristic polynomial on a finite field, and its LFSR size and the feedback relationship of the LFSR can be determined by the characteristic polynomial on the finite field corresponding to the LFSR (the correspondence between the characteristic polynomial in the finite field and the LFSR, such as Figure 3 As shown, for the characteristic polynomial x 4 +x 3 +1, the highest power is 4, then the LFSR has four registers Q3, Q2, Q1, Q0, where x 3 If the coefficient is not 0, Q3 has a lead as the input of the XOR gate. Figure 4 The plus sign indicates that this lead becomes the feedback lead. If the expression is x 4 +x 2 +1, then Q2 has a feedback signal as the input of the XOR gate). The characteristic polynomial of LFSR corresponds to an adjoint matrix, and its adjoint matrix is ​​also the linear matrix corresponding to LFSR. If the linear matrix is ​​to be a column full rank matrix, the characteristic polynomial must be a primitive polynomial over the finite field GF(2^n), where n is the size of the LFSR.

[0057] Figure 2 The structure in is mapped into a circuit such as Figure 4 As shown, Figure 4 The circuit structure in the embodiment reuses the registers in the LFSR, reducing the area overhead of the circuit. The number of registers is equal to the number of registers of the largest LFSR. When the number of registers is fixed, the structure realizes switching between LFSRs of different sizes and different feedback relationships according to the input control signal. The structure realizes switching between LFSRs by adding an AND gate on each feedback lead (the XOR gate is represented by a symbol with a plus sign in a circle, and the feedback lead is the lead of the register Qn…Q1 connected to the XOR gate). The input of the AND gate is the feedback signal and the selection signal output by the trigger. The output of the AND gate is connected to the XOR gate. When the selection signal is 0, the output of the AND gate is 0, and one input of the XOR gate is 0. At this time, the logic of the XOR gate is equivalent to a buffer, and this feedback logic is equivalent to being shielded. In this way, different feedback relationships are realized. When a smaller LFSR is to be realized, it is only necessary to shield all the low-order feedback signals, thereby changing the number of registers contained in the LFSR. The connection relationship between the compressed scan input and different LFSRs is also different, so a decoder is used to realize the conversion between different connection relationships.

[0058] Each LFSR corresponds to a Phase Shifter module to solve the problem of dependency between LFSR outputs. The LFSR acts as a decoder, while the Phase Shifter reduces the correlation of the LFSR output and expands the dimension of the LFSR output. Figure 5 is a LFSR with two inputs, see Figure 5 Lead 1 and lead 2 in the circuit, the function of LFSR is to decode two inputs into four outputs, namely Q3, Q2, Q1, Q0, which are used as the input of the circuit to be tested. The randomness here refers to the dependence between the outputs of Q1 and Q0. If in the first clock cycle, the value of Q1 is 1 and the value of Q0 is 0, when in the second clock cycle, the value of Q0 is the value of the previous clock cycle of Q1, that is, the value of Q0 in the nth clock cycle depends on the value of Q1 in the n-1th clock cycle. When the output of the circuit is more than four, for example, there are 8, a circuit is needed to map the four outputs of LFSR to the eight inputs of the circuit and alleviate the dependence between the values ​​of these 8 inputs. Phase Shifter is an XOR circuit that can play this role.

[0059] Different LFSRs have different corresponding Phase Shifter connection relationships. The present invention proposes a MUX Phase Shifter structure that uses a smaller circuit area to achieve switching between multiple Phase Shifters. Mux Phase Shifter includes two parts, a decoder and a multi-input XOR logic gate. The output of each Mux Phase Shifter corresponds to a multi-input XOR logic gate. The number of inputs of the XOR logic gate only needs to count the maximum number of inputs required by the XOR logic gate corresponding to a single Phase Shifter. The input of the XOR gate is selected by a decoder.

[0060] The process of test stimulus compression is as follows Figure 8 As shown, first, a fault is selected from the fault set for test vector generation. If a test vector is successfully generated, the largest LFSR is used to compress the vector. The largest LFSR is used for decompression to ensure test coverage. If compression is successful, the generated vector is compacted, and the compacted vector is taken out for fault simulation. The vector is re-compressed before fault simulation. This compression step is to select an LFSR of appropriate size from multiple LFSRs to decompress the vector, which can reduce the size of the compressed vector. When 32 vectors are collected, the vector is loaded into the fault simulator for fault simulation. After the fault simulation, the fault is re-selected for test vector generation.

[0061] The above is an introduction to the first main invention point of the present application. Next, the second main invention point of the present invention will be introduced: a decision method for generating a test vector for a certain number of bits.

[0062] In the test vector generation method, decisions are usually made based on the testability of the leads. Testability analysis is divided into two categories: controllability and observability. Controllability is used to measure the difficulty of controlling the leads to 0 or 1, while observability is used to measure the difficulty of fault effects propagating to the circuit output. Making decisions based on testability will increase the probability of successful decisions.

[0063] The present invention proposes a new method for calculating controllability, so that the goal of ATPG decision-making is to reduce the number of determined bits in the generated vector as much as possible. The calculation method measures the minimum number of input pins required to control a lead to 0 or 1. The calculation method is to initialize the input pin to 0, and then traverse the logic gates in the circuit according to the hierarchy, and calculate the controllability of the output according to the input according to the type of logic gate. The calculation rules for each type of logic gate are shown in Table 1 below.

[0064] Table 1

[0065]

[0066] by Figure 5 Take for example (to simplify the problem, phase shifter is not considered at this time), if the vector generated by ATPG is 1, 0, 1, x (x represents an uncertain value), then after the input of LFSR passes through the LFSR circuit, the values ​​of Q3, Q2, Q1, and Q0 must be 1, 0, 1, x (x represents an uncertain value). Assuming that the initialization values ​​are all 0, if a legal input can make Q2 and Q1 0 or 1 at the same time, the compression fails. When there are few certain bits in the vector, such as 1, 0, x, x, it can be found that the input can be 1 or 0. It can be proved that the fewer the certain values, the higher the probability of being compressed (LFSR can correspond to a matrix, and the problem of whether it can be compressed can be converted into the problem of solving a system of linear equations. The fewer equations that need to be solved, the higher the probability of successful solution. The specific proof is omitted here).

[0067] like Figure 6 For the darker values, the 0 controllability and 1 controllability of a, b, and c are 1, expressed as 1 / 1. Taking the OR gate with b and c as inputs as an example, the calculation rules in the table show that the 0 controllability of the output of the OR gate is equal to the sum of the 0 controllability of the inputs, which is 2, and the 1 controllability of the output is the minimum value of the 1 controllability of the inputs, which is 1. The 0 / 1 controllability of the output of the OR gate can be expressed as 2 / 1.

[0068] There are many methods for generating test vectors. The following uses the classic D algorithm as an example to explain how to make decisions. The D algorithm uses D-frontier and J-frontier to describe the current state of the algorithm. The D-frontier contains all the outputs in the circuit that are X, and the input has a fault response of D or The J-frontier is a set of logic gates in the circuit whose output is a certain value but whose input value has not been adjusted. The two main parts of the D algorithm process are fault propagation and logic value adjustment. The purpose of the fault propagation routine is to propagate the fault effect to the output. The running process selects a logic gate from the D-frontier, assigns the unassigned input pin of the logic gate to a non-controlled value, and adds it to the J-frontier. When the fault effect propagates to the output pin of the circuit, the fault propagation routine stops. The logic value adjustment routine determines the logic value of the input pin of the circuit so that the logic assignment required for fault propagation can be achieved. It does this by taking a logic gate from the J-frontier, assigning the input of its logic gate according to the output value, and then updating the set of J-frontier. Each assignment in the adjustment phase should be implied as much as possible and checked for consistency. If a conflict occurs, backtracking is required. In the adjustment phase, it is necessary to ensure that the fault effect on the output still exists, otherwise it will fall back to the propagation phase and re-propagate the fault effect. When there is a fault effect on the output of the circuit and J-frontier is an empty set, the algorithm ends. The above D algorithm process includes two types of decisions: propagation decision and adjustment decision. The decision method proposed in this paper is a method for adjustment decision. This method first calculates the controllability of each logic gate based on the topological relationship between the logic gate type and the circuit using the calculation method in Table 1. When making an adjustment decision, the smallest controllability is selected for adjustment based on the calculated controllability.

[0069] The present invention optimizes the effect of test stimulus compression from two aspects. The test stimulus compression effect is evaluated by two indicators, namely, test application time and test data volume. A test stimulus compression device for a variable-length LFSR reduces the initialization time of the LFSR, thereby reducing the test application time. A test vector generation decision method for a certain number of bits is used, so that the certain bits in the generated test stimulus are reduced, so the number of scan ports after compression can be smaller, thereby reducing the test data volume.

[0070] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0071] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0072] According to another aspect of the embodiment of the present application, a variable-length LFSR-based test stimulus compression device for implementing the above-mentioned variable-length LFSR-based test stimulus compression method is also provided. Fig. 9 As shown, the device may include:

[0073] An acquisition unit 91 is used to acquire original test stimulus and control signal in the original test vector of the chip to be tested;

[0074] The compression unit 93 is used to select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, and call the target LFSR to compress the original test stimulus using a time-series linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

[0075] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the above modules, as part of the device, can be run in a corresponding hardware environment, can be implemented by software, and can also be implemented by hardware, wherein the hardware environment includes a network environment.

[0076] According to another aspect of an embodiment of the present application, a server or terminal for implementing the above-mentioned test stimulus compression method based on variable-length LFSR is also provided.

[0077] Fig.10 is a structural block diagram of a terminal according to an embodiment of the present application, such as Fig.10 As shown, the terminal may include: one or more (only one is shown) processors 1001, a memory 1003, and a transmission device 1005, such as Fig.10 As shown, the terminal may also include an input and output device 1007 .

[0078] Among them, the memory 1003 can be used to store software programs and modules, such as the program instructions / modules corresponding to the test stimulus compression method and device based on variable-length LFSR in the embodiment of the present application. The processor 1001 executes various functional applications and data processing by running the software programs and modules stored in the memory 1003, that is, the above-mentioned test stimulus compression method based on variable-length LFSR is realized. The memory 1003 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1003 may further include a memory remotely arranged relative to the processor 1001, and these remote memories can be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0079] The above-mentioned transmission device 1005 is used to receive or send data via a network, and can also be used for data transmission between a processor and a memory. Specific examples of the above-mentioned network may include a wired network and a wireless network. In one example, the transmission device 1005 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 1005 is a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.

[0080] Specifically, the memory 1003 is used to store application programs.

[0081] The processor 1001 may call the application program stored in the memory 1003 through the transmission device 1005 to perform the following steps:

[0082] The original test stimulus and control signal in the original test vector of the chip to be tested are obtained; a target LFSR matching the number of determined bits in the original test stimulus is selected from a plurality of LFSRs according to the control signal, and the target LFSR is called, and the original test stimulus is compressed using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

[0083] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0084] It can be understood by those skilled in the art that Fig.10The structure shown is for illustration only, and the terminal may be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (Mobile Internet Devices, MID), a PAD, or other terminal devices. Fig.10 It does not limit the structure of the above electronic device. For example, the terminal may also include Fig.10 More or fewer components (such as network interfaces, display devices, etc.) shown in, or having Fig.10 Different configurations are shown.

[0085] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0086] The embodiment of the present application further provides a storage medium. Optionally, in this embodiment, the storage medium can be used to execute the program code of the test stimulus compression method based on variable-length LFSR.

[0087] Optionally, in this embodiment, the storage medium may be located on at least one network device among a plurality of network devices in the network shown in the above embodiment.

[0088] Optionally, in this embodiment, the storage medium is configured to store program codes for executing the following steps:

[0089] The original test stimulus and control signal in the original test vector of the chip to be tested are obtained; a target LFSR matching the number of determined bits in the original test stimulus is selected from a plurality of LFSRs according to the control signal, and the target LFSR is called, and the original test stimulus is compressed using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

[0090] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0091] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0092] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0093] If the integrated units in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in the above computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

[0094] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0095] In the several embodiments provided in the present application, it should be understood that the disclosed client can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0096] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0098] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A test stimulus compression circuit based on a variable-length LFSR, characterized in that: include: A variable-length LFSR module, wherein the variable-length LFSR module has an excitation input end for receiving an original test stimulus in an original test vector of the chip to be tested and a signal input end for receiving a control signal, wherein the variable-length LFSR module is used to select a target LFSR that matches the number of determined bits in the original test stimulus from a plurality of LFSRs according to the control signal; calling the target LFSR, and compressing the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits; A multiplexed phase shift module adapted to the variable-length LFSR module, connected to the variable-length LFSR module, each phase shift module in the multiplexed phase shift module corresponds to one LFSR, and the phase shift module is used to process the output dependency of the corresponding LFSR; Among them, the variable-length LFSR module includes: a first decoder, used to decode the scan input of the stimulus input end to obtain the original test stimulus; multiple triggers, the multiple LFSRs multiplex the multiple triggers; a second decoder, used to select triggers from the multiple triggers according to the control signal of the signal input end to form the target LFSR.

2. A testing instrument, characterized in that: It includes the test stimulus compression circuit based on variable-length LFSR as described in claim 1.

3. A test stimulus compression method based on variable-length LFSR, characterized in that: Applied to the test stimulus compression circuit based on the variable-length LFSR according to claim 1, the test stimulus compression method comprises: Obtaining original test stimulus and control signal in original test vector of the chip under test; According to the control signal, a target LFSR matching the number of determined bits in the original test stimulus is selected from multiple LFSRs, and the target LFSR is called to compress the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

4. The method according to claim 3, characterized in that The method comprises: selecting a target LFSR matching the number of bits determined in the original test stimulus from a plurality of LFSRs according to the control signal, calling the target LFSR, and compressing the original test stimulus using a sequential linear transformation method to obtain a compressed test stimulus, including: Inputting the control signal into the test stimulus compression circuit of the variable-length LFSR to instruct the test stimulus compression circuit of the variable-length LFSR to select the target LFSR that matches the number of determined bits in the original test stimulus, and inputting the original test stimulus into the test stimulus compression circuit of the variable-length LFSR; The test stimulus compression circuit of the variable-length LFSR is used to obtain the compressed test stimulus obtained by compressing the original test stimulus using the target LFSR.

5. The method according to claim 3 or 4, characterized in that: Before obtaining the original test stimulus in the original test vector of the chip to be tested, the method further includes: In the process of generating the test stimulus of the chip to be tested by ATPG, a test vector generation decision method for the number of determined bits is used to reduce the number of determined bits in the generated test stimulus.

6. The method according to claim 5, characterized in that Use a test vector generation decision method for determining the number of bits to reduce the number of bits in the generated test stimulus, including: According to the types of logic gates in the chip to be tested and the topological relationship of the circuit, the controllability of each logic gate is calculated using a preset calculation method; When the adjustment decision is executed, the adjustment is performed according to the calculated controllability, thereby generating the test stimulus of the chip under test.

7. A test stimulus compression device based on variable length LFSR, characterized in that: Applicable to the test stimulus compression circuit based on the variable-length LFSR according to claim 1, the test stimulus compression device comprises: An acquisition unit, used for acquiring original test stimulus and control signal in the original test vector of the chip to be tested; A compression unit is used to select a target LFSR that matches the number of determined bits in the original test stimulus from multiple LFSRs according to the control signal, and call the target LFSR to compress the original test stimulus using a time-series linear transformation method to obtain a compressed test stimulus, wherein different LFSRs match different numbers of determined bits.

8. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program executes the method described in any one of claims 3 to 6 when executed.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor executes the method described in any one of claims 3 to 6 through the computer program.

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