High-precision time-to-digital converter based on multi-level quantization

Abstract

This invention discloses a high-precision time-to-digital converter based on multi-level quantization, comprising: a counter for coarse quantization of a time signal to obtain a reference number of cycles included in the time signal; a start signal channel for intermediate quantization of a first remaining time using a first delay chain to obtain a first internal number of cycles, and fine quantization of the first remaining time by multiplexing the first delay chain into a ring oscillator to obtain a first residual quantization result; and a stop signal channel for obtaining a second residual quantization result and a second internal number of cycles through a similar process. According to the high-precision time converter provided by this invention, by multiplexing the delay chain into a ring oscillator to fine quantize the residual time instead of using two delay chains to quantize the time signal, the delay difference generated by two delay chains can be avoided, thereby improving the efficiency of time signal quantization; at the same time, by multiplexing the delay chains, the area overhead can be reduced, simplifying the structure of the high-precision time converter.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to a high-precision time-to-digital converter based on multi-level quantization. Background Technology

[0002] In recent years, high-precision time interval measurement technology has been widely used in medical image scanning, phase-locked loop (PLL) technology, and lidar imaging technology. Among these technologies, high-precision, high-dynamic-range, and high-switching-rate time-to-digital converters (TD-to-time converters) are the core components for achieving high-precision time interval measurement. T-to-digital converters can be broadly classified into two categories based on their implementation principles: analog implementations based on time-to-voltage converters and analog-to-digital converters, and digital implementations based on delay chains and ring oscillators. Analog-based T-to-digital converters are often difficult to migrate to advanced CMOS processes due to their characteristics, are susceptible to temperature and noise, and consume significant area and power. Furthermore, increasing the dynamic range significantly degrades their accuracy and linearity. In contrast, digital implementations offer advantages such as high integration, small area, low power consumption, and strong circuit robustness, making them the mainstream trend in T-to-digital converter implementation.

[0003] One traditional implementation of a digital-logic time-to-digital converter (DTC) uses a delay chain composed of buffers or inverters. A start signal representing the duration of a pulse travels along the delay chain until a stop signal triggers a D flip-flop to register the state of the delay chain at that moment. However, this traditional structure has drawbacks: its resolution is limited by the propagation delay of the inverters in the delay chain, and the delay unit delay is susceptible to PVT unless DLL locking is used. To further improve the converter's resolution, another traditional method is to use a vernier technique, employing two delay chains composed of different delay units, with the resolution being the delay difference between the delay units in the two chains. However, to cover a large dynamic range, the total number of delay units will increase exponentially, posing significant challenges to circuit matching and area considerations.

[0004] Therefore, traditional time-to-digital converters have low quantization efficiency and large area overhead. Summary of the Invention

[0005] This invention provides a high-precision time-to-digital converter based on multi-level quantization, which can solve the problems of large latency and low efficiency of blockchain networks when reaching consensus based on the sharding results obtained from the current blockchain network sharding method.

[0006] In a first aspect, embodiments of the present invention provide a high-precision time-to-digital converter based on multi-level quantization, comprising: A counter is used to coarsely quantize a time signal to obtain the number of reference periods included in the time signal. A start signal channel includes a first delay chain, which is used to perform intermediate quantization on the first remaining time to obtain the first internal cycle number; and to perform fine quantization on the first remaining time by multiplexing the first delay chain into a ring oscillator to obtain the first residual quantization result; wherein, the first remaining time is the time difference between the start time of the time signal and the start time of the first reference cycle, and the first reference cycle is the first cycle of the reference clock signal after the start time of the time signal; The stop signal channel includes a second delay chain. The stop signal channel is used to perform intermediate quantization on the second remaining time through the second delay chain to obtain the second internal cycle number; and to perform fine quantization on the second remaining time by multiplexing the second delay chain into a ring oscillator to obtain the second residual quantization result; wherein, the second remaining time is the time difference between the end time of the time signal and the start time of the last reference cycle, and the last reference cycle is the first cycle of the reference clock signal after the end time of the time signal; The start signal channel is also used to send the reference cycle number, the first internal cycle number, and the first residual quantization result to the receiver. The stop signal channel is also used to send the second internal cycle number and the second residual quantization result to the receiver, so that the receiver can determine the length of the time signal based on the reference cycle number, the first internal cycle number, the first residual quantization result, the second internal cycle number, and the second residual quantization result.

[0007] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: According to the high-precision time converter provided by the present invention, the delay chain is multiplexed into a ring oscillator to refine the residual time, instead of using two delay chains to quantize the time signal; the delay difference generated by two delay chains can be avoided, thereby improving the resolution of the time signal and reducing the error; at the same time, by multiplexing the delay chain, the area overhead can be reduced and the structure of the high-precision time converter can be simplified. Attached Figure Description

[0008] Figure 1 A schematic diagram of a high-precision time-to-digital converter based on multi-level quantization is provided in an embodiment of the present invention. Figure 2 A signal schematic diagram provided for an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating a scenario for quantizing a time signal, provided as an embodiment of the present invention. Figure 4 A schematic diagram of the specific structure of a stop signal channel provided by the present invention; Figure 5 A detailed structural diagram of a high-precision time-to-digital converter based on multi-level quantization provided by the present invention; Figure 6 This is a schematic diagram of a specific structure of a delay chain provided in an embodiment of the present invention; Figure 7 A schematic diagram of an internal clock signal provided in an embodiment of the present invention; Figure 8 A specific structural diagram of an amplifier provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the specific structure of an interpolator and a residual difference extraction unit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a specific structure of an encoding unit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the specific structure of a counter provided in an embodiment of the present invention.

[0009] Figure label: 1: Counter; 2: Start signal channel; 21: First delay chain; 22: First residual extraction unit; 221: First interpolator and residual extraction unit; 222: First encoding unit; 223: First amplifier; 224: First logic signal generation unit; 23: First storage unit; 3: Stop signal channel; 31: Second delay chain; 32: Second residual extraction unit; 321: Second interpolator and residual extraction unit; 322: Second encoding unit; 323: Second amplifier; 324: Second logic signal generation unit; 33: Second storage unit; 4: Parallel-to-serial conversion unit; 5: Delay phase-locked loop. Detailed Implementation

[0010] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0011] Example 1 Figure 1 The diagram shown illustrates the structure of a high-precision time-to-digital converter based on multi-level quantization, as provided in an embodiment of the present invention. By way of example and not limitation, the high-precision time-to-digital converter 100 may include a counter 1, a start signal channel 2, and a stop signal channel 3.

[0012] Counter 1 is used to coarsely quantize the time signal to obtain the number of reference periods included in the time signal; The start signal channel 2 includes a first delay chain 21. The start signal channel 2 is used to perform intermediate quantization on the first remaining time through the first delay chain 21 to obtain the first internal cycle number; and to perform fine quantization on the first remaining time by multiplexing the first delay chain 21 as a ring oscillator to obtain the first residual quantization result. The stop signal channel 3 includes a second delay chain 31. The stop signal channel 3 is used to perform intermediate quantization on the second remaining time through the second delay chain 31 to obtain the second internal cycle number; and to perform fine quantization on the second remaining time by multiplexing the second delay chain 31 as a ring oscillator to obtain the second residual quantization result.

[0013] The start signal channel 2 is also used to send the reference cycle number, the first internal cycle number, and the first residual quantization result to the receiver; the stop signal channel 3 is also used to send the second internal cycle number and the second residual quantization result to the receiver, so that the receiver can determine the length of the time signal based on the reference cycle number, the first internal cycle number, the first residual quantization result, the second internal cycle number, and the second residual quantization result.

[0014] For example, the first remaining time is the time difference between the start time of the time signal and the start time of the first reference period.

[0015] For example, the first reference period is the first period of the reference clock signal after the start of the time signal.

[0016] For example, see Figure 2 , Figure 2 In the time signal, Start and Stop are obtained by sampling the rising edge of the start time and the rising edge of the end time, respectively. in This represents the length of the time signal. The starting point of the first reference period is at the dashed line 201, which is the first period of the reference clock signal after the start of the time signal. The first remaining time is the time between the dashed lines 201 and 202 in the diagram above.

[0017] For example, the second remaining time is the time difference between the end of the time signal and the start of the last reference period.

[0018] For example, the last reference period is the first period of the reference clock signal after the end of the time signal.

[0019] For example, see Figure 2 The starting point of the last reference period is Figure 2 The second remaining time is the time between the dashed lines 203 and 204.

[0020] For example, see Figure 2 The reference period number is the number of reference periods included in the time interval between the start time of the time signal and the start time of the last reference period mentioned above.

[0021] For example, see Figure 2The time between the start time of the time signal and the start time of the last reference period mentioned above is... If there are 2 reference periods, then the number of reference periods is 2.

[0022] In some embodiments, the input terminal of counter 1 can be connected to the output terminal of start signal channel 2 and the output terminal of stop signal channel 3.

[0023] In one possible implementation, the start signal channel 2 can be used to perform intermediate quantization on the first remaining time through the first delay chain 21 to obtain the first internal cycle number. By multiplexing the first delay chain 21 into a ring oscillator to finely quantize the first residual time, the first residual quantization result is obtained.

[0024] For example, the first residual time is the difference obtained by subtracting the product of the first remaining time and the number of the first internal cycles.

[0025] For example, the internal period is one period of the internal clock signal, and the internal period can be 1 / N of the reference period, where N is an integer greater than or equal to 2.

[0026] For example, see Figure 2 Internal clock signals CLK0-CLK 16 The internal period is 1 / 16 of the reference period. The first remaining time includes 14 internal periods, so the number of the first internal periods is 14. The first remaining time minus these 14 periods is the time between dashed lines 205 and 202. This is the first residual time.

[0027] In one example, see Figure 1 The start signal channel 2 may include a first delay chain 21, a first residual difference extraction unit 22, and a first storage unit 23. The first delay chain 21 is used to perform intermediate quantization on the time signal to obtain N first internal clock phase signals. The first residual difference extraction unit 22 is used to extract the residual of the first remaining time based on the first internal clock phase signals to obtain a first internal cycle number and a first residual difference time. Then, the first residual difference extraction unit 22 can send a first enable signal to the first delay chain 21, and simultaneously multiplex the first delay chain 21 into a ring oscillator, causing the first delay chain 21 to finely quantize the first residual difference time to obtain a first N clock signal. The first delay chain 21 sends the first N clock signal to the first residual difference extraction unit 22. The first residual difference extraction unit 22 determines the first residual difference quantization result based on the first N clock signal. The first residual difference extraction unit 22 sends the first internal cycle number and the first residual difference quantization result to the first storage unit 23, which stores them and sends them to the receiving end.

[0028] For example, see Figure 3Both the first and second residual quantization results can be the number of oscillation cycles of the delay chain that is reused as a ring oscillator.

[0029] In one example, the output of the first delay chain 21 can be connected to the input of the first residual difference extraction unit 22, and the input of the first delay chain 21 can be connected to the first output of the first residual difference extraction unit 22. The second output of the first residual difference extraction unit 22 can be connected to the first input of the first storage unit 23. The second input of the first storage unit 23 can be connected to the output of the counter 1 as the input of the start signal channel 2.

[0030] For example, the first storage unit 23 may also receive a reference number of cycles from the counter 1, store it, and send it to the receiving end.

[0031] In one possible implementation, the stop signal channel 3 can be used to perform intermediate quantization on the second remaining time through the second delay chain 31 to obtain the second internal cycle number. The second residual time is further refined by multiplexing the second delay chain 31 into a ring oscillator to obtain the second residual quantization result.

[0032] For example, the second residual time is the difference obtained by subtracting the product of the second residual time and the number of the inner cycles and the number of the second inner cycles from the second residual time.

[0033] For example, see Figure 2 The second remaining time includes 8 internal cycles. Subtracting these 8 cycles from the second remaining time yields the second residual time. .

[0034] In one example, see Figure 1 The stop signal channel may include a second delay chain 31, a second residual difference extraction unit 32, and a second storage unit 33. The second delay chain 31 is used to perform intermediate quantization on the time signal to obtain N second internal clock phase signals. The second residual difference extraction unit 32 is used to extract the residual difference of the second remaining time based on the second internal clock phase signals to obtain the second internal cycle number and the second residual difference time. Then, the second residual difference extraction unit 32 can send a second enable signal to the second delay chain 31, and simultaneously multiplex the second delay chain 31 into a ring oscillator, causing the second delay chain 31 to finely quantize the second residual difference time to obtain a second N clock signal. The second delay chain 31 sends the N clock signal to the second residual difference extraction unit 32. The second residual difference extraction unit 32 determines the second residual difference quantization result based on the second N clock signal. The second residual difference extraction unit 32 sends the second internal cycle number and the second residual difference quantization result to the second storage unit 33, which stores them and sends them to the receiving end.

[0035] In one example, the output of the second delay chain 31 can be connected to the input of the second residual extraction unit 32, and the input of the second delay chain 32 can be connected to the first output of the second residual extraction unit 32. The second output of the second residual extraction unit 32 can be connected to the first input of the second storage unit 33.

[0036] Optionally, the second input terminal of the second storage unit 33 can be connected to the output terminal of the counter 1 as the input terminal of the stop signal channel 3.

[0037] In one possible implementation, the first residual quantization result may include the first oscillation period number and the first phase encoding result, and the second residual quantization result may include the second oscillation period number and the second phase encoding result.

[0038] In one example, the length of the time signal can satisfy the following formula:

[0039] in, The length of the time signal; It is the product of the reference period number and the reference period; It is the product of the first internal cycle number and the internal cycle number; , This is the number of the first oscillation period. The oscillation period of the first delay chain 21, which is reused as a ring oscillator, This is the result of the first phase encoding; It is the product of the second inner period number and the inner period number. , This is the number of the second oscillation period. The oscillation period of the second delay chain 31, which is reused as a ring oscillator, This is the result of the second phase encoding.

[0040] Generally, .

[0041] Optionally, a high-precision time-to-digital converter can repeatedly convert the same time signal multiple times to obtain multiple lengths of the time signal. Averaging these multiple lengths reduces the nonlinear error that may be introduced in a single residual difference extraction. That is, a cyclic sliding scaling scheme is used to improve the nonlinearity of the high-precision time-to-digital converter.

[0042] The high-precision time converter provided by the present invention uses a delay chain multiplexed into a ring oscillator to finely quantize the residual time, instead of using two delay chains to quantize the time signal; this avoids the delay difference caused by two delay chains, thereby improving the quantization efficiency of the time signal; at the same time, by multiplexing the delay chain, the area overhead can be reduced and the structure of the high-precision time converter can be simplified.

[0043] Example 2 Figure 4 The diagram shown is a schematic representation of the specific structure of a stop signal channel provided by the present invention.

[0044] Based on the high-precision time-to-digital converter proposed in Example 1, Figure 4 The specific structure of stop signal channel 3 is shown.

[0045] See Figure 4 The stop signal channel 3 may include a second delay chain 31, a second residual extraction unit 32, and a second storage unit 33.

[0046] The second residual extraction unit 32 may include: The second interpolator and residual extraction unit 321 can be used to extract the residual of the second remaining time based on the second internal clock phase signal to obtain the second residual time and N second internal clock phase sampling signals. The second encoding unit 322 is used to encode the second internal clock phase sampling signal to obtain the second internal cycle number. The second amplifier 323 is used to amplify the second residual time by N times to obtain the second amplified residual signal. The second logic signal generation unit 324 is used to convert the second amplified residual signal into a second enable signal, and send the second enable signal to the second delay chain 31 so that the second delay chain 31 can refine the second residual time to obtain the second N clock signal.

[0047] Specifically, see Figure 3 The time signal is input from the second logic signal generation unit 324 and transmitted to the second delay chain 31. The second delay chain 31 can obtain the second remaining time by recording the time between the end time of the time signal and the start time of the first reference cycle after the time signal using the internal clock of the second delay chain 31. Intermediate quantization is then performed directly on the second remaining time to obtain 16 second internal clock phase signals. (See [link]). Figure 4 CLK0-CLK 16 Then CLK0-CLK 16The data is transmitted to the second interpolator and the residual extraction unit 321.

[0048] The second interpolator and residual extraction unit 321 are based on CLK0-CLK 16 The second residual time is determined, and a residual start signal and a residual end signal are generated and transmitted to the second amplifier 323. Upon receiving the residual start time, the second amplifier 323 sends a second amplified residual signal to the second logic signal generation unit 324. Upon receiving the residual end signal, it waits for N-1 residual time intervals before sending an amplified end signal to the second logic signal generation unit 324, thus amplifying the residual time by a factor of N. The second logic signal generation unit 324 converts the second amplified residual signal into a second enable signal EN and the amplified end signal into a reset signal, sending them to the second delay chain 31, which is multiplexed as a ring oscillator. The second delay chain 31 refines the time between the two signals to generate a second N-clock signal, for example... Figure 3 The CLK16 in the second encoding unit 322 is then sent to the second encoding unit 322 to obtain the second residual quantization result. The second encoding unit 322 can send both the obtained second internal cycle number and the second residual quantization result to the second storage unit 33.

[0049] Example 3 Figure 5 The diagram shown is a specific structural diagram of a high-precision time-to-digital converter based on multi-level quantization provided by the present invention.

[0050] For example, Figure 5 The high-precision digital converter in this example is based on the specific structure of the high-precision digital converter and the stop signal channel 3 provided in Example 2. Figure 5 The structure of the stop signal channel 3, which is not shown in the figure, and Embodiment 2 are similar. Figure 4 The stop signal channel 3 described in the text is the same.

[0051] See Figure 5 The high-precision digital converter 100 may also include a parallel-to-serial unit 4 and a delay phase-locked loop 5.

[0052] The output of the delay phase-locked loop can be connected to the outputs of the first delay chain 21 and the second delay chain 31 to control the voltage of the reference clock signal. The parallel-to-serial conversion unit 4 can be connected to the second input of the start signal channel 2 (i.e., the input of the first storage unit 23) and the second input of the stop signal channel 3 (i.e., the input of the second storage unit 33) to convert the reference cycle number obtained by the counter 1 from parallel to serial and send it to the first storage unit 23 and / or the second storage unit 33.

[0053] The first reference period sampling signal generated by the first logic signal generation unit 224 and the second reference signal sampling period generated by the second logic signal generation unit 324 can be sent to the counter 1 through the first storage unit 23 and the second storage unit 33, respectively. The counter 1 starts coarse quantization upon receiving the first reference period sampling signal and ends coarse quantization upon receiving the second reference period sampling signal, resulting in the following... Figure 2 The results of coarse quantization are shown.

[0054] In some embodiments, see Figure 5 The residual extraction unit 22 in the start signal channel 2 includes: The first interpolator and the residual extraction unit 221 are used to extract the residual from the first remaining time based on the first internal clock phase signal to obtain the first residual time and N first internal clock phase sampling signals. The first encoding unit 222 is used to encode the first internal clock phase sampling signal to obtain the first internal cycle number; The first amplifier 223 is used to amplify the first residual time by N times to obtain the first amplified residual signal. The first logic signal generation unit 224 is used to convert the first amplified residual signal into a first enable signal and send the first enable signal to the first delay chain 21 so that the first delay chain 21 can refine the first residual time to obtain the first N clock signal. The first encoding unit 222 is also used to encode the first N clock signal to obtain the first internal cycle number.

[0055] Specifically, see Figure 2 and Figure 5 The time signal is input from the first logic signal generation unit 224 and transmitted to the first delay chain 21. The first delay chain 21 can obtain the first remaining time by recording the end time of the time signal and the start time of the first reference cycle of the internal clock of the first delay chain 21 after the start time of the time signal. Intermediate quantization is then performed directly on the first remaining time to obtain 16 first internal clock phase signals. (See [link]). Figure 4 CLK0-CLK 16 Then CLK0-CLK 16 The data is transmitted to the first interpolator and the residual extraction unit 221.

[0056] The first interpolator and the residual extraction unit 221 are based on CLK0-CLK 16The first residual time is determined, and a residual start signal and a residual end signal are generated. These signals are then transmitted to the first amplifier 223. Upon receiving the residual start time, the first amplifier 223 sends a first amplified residual signal to the first logic signal generation unit 224. Upon receiving the residual end signal, it waits for N-1 residual time periods before sending an amplified end signal to the first logic signal generation unit 224, thereby amplifying the residual time by a factor of N.

[0057] The first logic signal generation unit 224 converts the first amplified residual signal into a first enable signal and the amplification end signal into a reset signal; and sends the two signals to the first delay chain 21, which is multiplexed as a ring oscillator. At the same time, a reset is performed when the amplification end signal is received.

[0058] The time between the two is refined by the first delay chain 21 to generate the first N clock signal, for example. Figure 4 The first internal cycle number and the first residual quantization result are then sent to the first encoding unit 222 to obtain the first residual quantization result. The first encoding unit 222 can send both the obtained first internal cycle number and the first residual quantization result to the first storage unit 23.

[0059] Optionally, the first logic signal generation unit 224 is further configured to generate a first reference period sampling signal based on the time signal at the start time, and send the first reference period sampling signal to the first interpolator and the residual difference extraction unit 221, so that the first interpolator and the residual difference extraction unit 221 determine whether the start time of the clock signal arrives in the first half-cycle of the reference clock signal. Simultaneously, the first reference period sampling signal is sent to the storage unit, which forwards it to the counter 1, causing the counter 1 to begin coarse quantization of the time signal.

[0060] Similarly, stop signal channel 3 can generate a second reference period sampling signal based on the time signal at the end time to determine whether the time signal has ended in the working period of the reference clock signal.

[0061] When the start of the time signal is synchronized with the first half of the reference clock signal's cycle, counter 1 uses the first half of the reference clock signal minus the second half as the reference period. When the start of the time signal is synchronized with the second half of the reference clock signal's cycle, counter 1 uses the second half of the reference clock signal minus the first half as the reference period. This ensures a more accurate number of reference periods, avoiding errors such as overcounting or undercounting by half a cycle.

[0062] Example 4 Figure 6 The diagram shown is a specific structural illustration of a delay chain provided in an embodiment of the present invention. It is intended as an example and not a limitation. Figure 3The delay chains shown can be the first delay chain 21 and / or the second delay chain 31 in the high-precision time-to-digital converter 200. The following explanation uses the first delay chain 21 as an example.

[0063] See Figure 3 The first delay chain 21 can be composed of N sub-delay units, with the output buffered by an inverter. The delay sub-units control the delay time using the control voltage VC provided by the delay phase-locked loop, and their operation can be controlled by the first enable signal EN. The sub-delay units are constructed by cascading inverters.

[0064] For example, the reference clock signal is obtained from an inverter. D pre Input the first delay chain 21. See also Figure 7 The first delay chain 21 can divide the reference period of the reference clock signal into N parts using N, for example, 16, internal clock signals with the same phase difference.

[0065] When refining the first residual time, the first delay chain 21 can be used with an additional inverter. D inv By connecting the beginning and end of the delay chain to form a ring oscillator, the overflow problem that may occur when using the first delay chain 21 for transmission is solved due to the excessive delay between the first amplified residual signal and the amplification end signal after time amplification.

[0066] For example, since the high-precision time-to-digital converter 100 of the present invention includes two identical delay chains, namely the first delay chain 21 and the second delay chain 31, which perform intermediate quantization and fine quantization on the start and end times of the time signal respectively, it can avoid the shrinkage or widening of the pulse width caused by the mismatch between the rise and fall times of the unidirectional amplifier, which would degrade the gain and linearity of the time amplifier.

[0067] Example 5 Figure 8 The diagram shown illustrates a specific structure of an amplifier provided by the present invention. By way of example and not limitation, the amplifier may be a first amplifier 223 in the start signal channel 2 and / or a second amplifier 323 in the stop signal channel 3. The following description uses the first amplifier 223 as an example.

[0068] See Figure 8 The first amplifier 223 in the middle first passes the rising edge signal of each output node through an XOR gate to generate short pulses T1-T. 16Then, the first amplified residual signal and the amplification end signal are generated through an OR gate 16_OR. Since the offset times of the amplifiers in the start signal channel 2 and the stop signal channel 3 are the same, they can cancel each other out when the receiver calculates the length of the time signal, eliminating the need for an additional offset time quantization structure and further reducing area overhead.

[0069] Example 6 Figure 9 The diagram shown illustrates a specific structure of an interpolator and residual extraction unit provided by the present invention. This is intended as an example and not a limitation. Figure 9 The interpolator and residual extraction unit in the diagram can be a first interpolator and residual extraction unit 221 and / or a second interpolator and residual extraction unit 321. The following explanation uses the first interpolator and residual extraction unit 221 as an example.

[0070] See Figure 9 The dynamic differential comparator is multiplexed to sample the first internal clock phase signal, obtaining the first residual time and the first internal clock phase sample signal; it can also be used as a register to store the first residual time and the first internal clock phase sample signal. The dynamic differential comparator is located at the internal clock signal CLK terminal (see...). Figure 9 The 901 in the code is used for comparison when it is high and for automatic reset when it is low. When the sampling signal of the first reference cycle arrives, the high and low potentials of each phase are sampled, and the start time of the clock signal is determined to be synchronized with the first half cycle of the reference clock signal based on the sampling results.

[0071] The first interpolator and the residual difference extraction unit 221 extract the time interval between the rising edge of the first reference period sampling signal (i.e., the start time of the time signal) and the first internal cycle of the internal clock signal after the start time of the time signal, thus obtaining the first residual difference time. Before the arrival of the first reference period sampling signal, the dynamic differential comparator outputs... All are at low potentials. After passing through a NAND gate, all PMOS switches are turned off, pulling the gate voltages of M1-M16 to ground. The normally open M0 transistor pulls node N0 to a high potential. When the first reference cycle sampling signal arrives, the dynamic differential comparator samples the multi-phase CLK0-CLK at that moment. 16 The potential state of the signal is determined based on the sampling results. Select the corresponding PMOS switch. When N first internal clock phase signals arrive, the DFF (see...) Figure 9 The 902 in the middle generates a stop signal.

[0072] Introducing NAND gates, which are not present in traditional structures, into the interpolator and residual difference extraction unit can avoid errors in time residual difference extraction under certain specific conditions.

[0073] See Figure 7When the sampling signal of the first reference cycle approaches the falling edge of CLK2, which is the end of one internal cycle of the second internal clock signal, the corresponding switches of CLK1 and CLK2 are turned on. The start time of the next nearest internal clock signal cycle is CLK1, and the correct trigger time should be the time after the rising edge of CLK1 and the delay unit τ2 (the time indicated by the yellow dashed line). However, since the time delay τ2 in the first delay chain 21 is greater than the comparator discrimination time τ1, when the comparator determines the result, the drain of the switch in the CLK2 branch is at a high potential, which will cause an incorrect trigger at this time (the time indicated by the blue dashed line). To avoid this phenomenon, this invention introduces a NAND gate connection. and ,Right now Figure 9 The red part in the middle, if and only if and When both are at high potentials, the corresponding PMOS switch is turned on, so the switch of the CLK2 branch will be turned off, effectively avoiding errors in residual time extraction.

[0074] Example 7 Figure 10 The diagram shown is a specific structural schematic of an encoding unit provided in an embodiment of the present invention. It is intended as an example and not a limitation. Figure 10 The coding unit can be a first coding unit 222 and / or a second coding unit 322. The following explanation uses the first coding unit 222 as an example.

[0075] The first encoding unit 222 reuses the same encoding scheme when encoding the first internal clock phase sampling signal and the first N clock signal. During intermediate quantization, the effective position is located at the output result of the dynamic differential comparator in the interpolator. Q n The transition from high to low potential occurs at the point where, during fine quantization, due to the presence of inverter delay units in the circular delay chain, the effective position at the end of quantization is located at... Q n At the high-low potential transition point, there are two high-low potential transition scenarios.

[0076] Therefore, see Figure 10 In (a) of this invention, a selector circuit is used to select the corresponding output result based on the selection signal potential. Q n or The input back-end encoding circuit ensures correct determination of the valid position. During fine quantization, the phase state of the first N clock signal is sampled by amplifying the end signal and used as the selection signal S_ENC. If the phase of the first N clock signal CLK16 is low, it indicates that a high-level signal was being transmitted when the first delay chain 21 stopped, and the valid position is located at... Q n The output result will be generated at the point where the potential changes from high to low. Qn The signal is fed into the back-end encoding circuit. Conversely, if the sampling CLK16 phase is high, the output result will be sent. Input to the back-end circuit to achieve the reuse of the encoding circuit.

[0077] See Figure 10 In (b), a 2-bit counter is implemented using D flip-flops to detect CLK during fine quantization, with both rising and falling edges of the D flip-flops acting as the counter. 16 Phase changes, combined with encoding, yield a 2-bit binary code. Because a circular delay chain structure is used in the fine quantization process, the added inverter delay unit introduces an extra phase during fine quantization, causing the 4-bit digital code to be unable to cover all phase information.

[0078] Therefore, see Figure 10 In step (c), an XOR gate is introduced into the counter inside the encoding unit to separately determine the number of times the signal passes through the inverter delay unit during fine quantization. The input and output nodes of the inverter are connected to the two ends of the XOR gate. If the XOR gate outputs a low level, it indicates that the signal stops exactly at CLK when fine quantization ends. 16 At this point, and without changing the CLK0 phase, since the counter for the detection cycle is controlled by CLK... 16 Driven by the inverter, the number of times the signal passes through the inverter is 1 less than the counter result. If the XOR gate output is high, the potential transition is in other phases, and the number of times the signal passes through the inverter is equal to the counter result.

[0079] Example 8 Figure 11 The diagram shown is a schematic representation of the specific structure of a counter provided by the present invention.

[0080] Counter 1 counts the number of rising edges of the reference clock between the start and end times of the time signal, i.e., the number of reference cycles. Since the start and end times of the time signal are asynchronous with the reference clock signal, if the start and end times of the time signal occur very close to the rising edge of the reference clock, it may cause an error in counting the number of rising edges. Therefore, this invention adopts a double-edge synchronization method to provide stable and compatible counter results.

[0081] See Figure 11 In (a), counter 1 can determine the position of the start and end times of the time signal relative to the period of the reference clock signal based on the sampled signal of the first reference period. The interpolation encoding result OUT from the encoding unit... 3M (see Figure 10 The condition is checked using 1001 in the code. If OUT 3MA low voltage after encoding indicates that the timing signal is in the first half of the reference clock cycle. In this case, the rising edge of the reference clock is used to count the reference cycle count. Conversely, if OUT... 3M A low level indicates that the timing signal is in the second half of the reference clock cycle, and the falling edge of the reference clock is used to count the reference cycle number.

[0082] This invention employs a dual-selector synchronization structure, OUT 3M Control the front-end selector to select the correct rising or falling edge of the reference clock signal. Sample to obtain OUT. 3M When using DFF (see Figure 11 The 1101) generates synchronous rising edge Open_Start and Open_Stop signals as selection signals for the back-end selector. Only when the OUT is correctly sampled... 3M After the signal is received, the correct reference clock can be transmitted to the back-end circuit via the dual-selector circuit to control the counter. Simultaneously, the initial phase of the CLK input of the D flip-flop (DDF) must be high to prevent the D flip-flop from triggering momentarily if the initial phase is low and the reference clock is high when the dual-selector is on, thus causing a counting error. (See also...) Figure 11 In (b), selector Mux5 (see...) Figure 11 The function of 1102) is consistent with that of selector MUX3 / 4, ensuring that the trigger does not trigger incorrectly when the gating signal arrives.

[0083] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A high-precision time-to-digital converter based on multi-level quantization, characterized in that, include: Counter (1), the counter (1) is used to coarsely quantize the time signal to obtain the number of reference periods included in the time signal; A start signal channel (2) is provided, which includes a first delay chain (21). The start signal channel (2) is used to perform intermediate quantization on the first remaining time through the first delay chain (21) to obtain a first internal cycle number; and to perform fine quantization on the first remaining time by multiplexing the first delay chain (21) into a ring oscillator to obtain a first residual quantization result; wherein, the first remaining time is the time difference between the start time of the time signal and the start time of the first reference cycle, and the first reference cycle is the first cycle of the reference clock signal after the start time of the time signal; A stop signal channel (3) is provided, comprising a second delay chain (31). The stop signal channel (3) is used to perform intermediate quantization on the second remaining time through the second delay chain (31) to obtain a second internal cycle number; and to perform fine quantization on the second remaining time by multiplexing the second delay chain (31) into a ring oscillator to obtain a second residual quantization result; wherein, the second remaining time is the time difference between the end time of the time signal and the start time of the last reference cycle, and the last reference cycle is the first cycle of the reference clock signal after the end time of the time signal; The start signal channel (2) is also used to send the reference period number, the first internal period number and the first residual quantization result to the receiving end, and the stop signal channel (3) is also used to send the second internal period number and the second residual quantization result to the receiving end, so that the receiving end can determine the length of the time signal based on the reference period number, the first internal period number, the first residual quantization result, the second internal period number and the second residual quantization result.

2. The high-precision time-to-digital converter according to claim 1, characterized in that, The start signal channel (2) is specifically used for: The first internal cycle number is obtained by intermediate quantization of the first remaining time through the first delay chain (21); The first residual time is refined by multiplexing the first delay chain (21) into a ring oscillator to obtain the first residual quantization result, wherein the first residual time is the difference obtained by subtracting the product of the internal period and the number of the first internal period from the first remaining time.

3. The high-precision time-to-digital converter according to claim 2, characterized in that, The start signal channel (2) further includes a first residual extraction unit (22) and a first storage unit (23); The first delay chain (21) is used to perform intermediate quantization on the time signal to obtain N first internal clock phase signals, where N is an integer greater than or equal to 2; The first residual extraction unit (22) is used to extract the residual from the first remaining time according to the first internal clock phase signal to obtain the first internal cycle number and the first residual time; The first delay chain (21) is also used to refine the first residual time to obtain the first N clock signal; The first residual extraction unit (22) is further configured to determine the first residual quantization result based on the first N clock signal; The first storage unit (23) is used to store and send the reference period number, the first internal period number and the first residual quantization result to the receiving end.

4. The high-precision time-to-digital converter according to claim 3, characterized in that, The first residual extraction unit (22) includes: The first interpolator and the residual extraction unit (221) are used to extract the residual from the first remaining time based on the first internal clock phase signal to obtain the first residual time and N first internal clock phase sampling signals. The first encoding unit (222) is used to encode the first internal clock phase sampling signal to obtain the first internal cycle number; The first amplifier (223) is used to amplify the first residual time by N times to obtain the first amplified residual signal; The first logic signal generation unit (224) is used to convert the first amplified residual signal into a first enable signal and send the first enable signal to the first delay chain (21) so that the first delay chain (21), which is multiplexed as a ring oscillator, refines the first residual time to obtain the first N clock signal. The first encoding unit (222) is also used to encode the first N clock signal to obtain the first residual quantization result.

5. The high-precision time-to-digital converter according to claim 4, characterized in that, The first logic signal generation unit (224) is further configured to generate a first reference period sampling signal at the beginning of the time signal and send the first reference period sampling signal to the first interpolator and the residual difference extraction unit (221) so that the first interpolator and the residual difference extraction unit (221) can determine whether the time signal arrives in the first half of the reference clock signal.

6. The high-precision time-to-digital converter according to claim 5, characterized in that, The stop signal channel (3) is specifically used for: The second internal cycle number is obtained by intermediate quantization of the second remaining time using the second delay chain; The second residual time is refined by multiplexing the second delay chain (31) into a ring oscillator to obtain the second residual quantization result, wherein the second residual time is the difference obtained by subtracting the product of the internal period and the number of the second internal periods from the second residual time.

7. The high-precision time-to-digital converter according to claim 6, characterized in that, The stop signal channel (3) further includes a second residual extraction unit (32) and a second storage unit (33); The second delay chain (31) is used to perform intermediate quantization on the time signal to obtain N second internal clock phase signals; The second residual extraction unit (32) is used to extract the residual from the second remaining time according to the second internal clock phase signal to obtain the second internal cycle number and the second residual time; The second delay chain (31) is also used to refine the second residual time to obtain the second N clock signal; The second residual extraction unit (32) is also used to determine the second residual quantization result based on the second N clock signal; The second storage unit (33) is used to store and send the second internal cycle number and the second residual quantization result to the receiving end.

8. The high-precision time-to-digital converter according to claim 7, characterized in that, The second residual extraction unit (32) includes: The second interpolator and residual extraction unit (321) are used to extract the residual from the second remaining time based on the second internal clock phase signal to obtain the second residual time and N second internal clock phase sampling signals. The second encoding unit (322) is used to encode the second internal clock phase sampling signal to obtain the second internal cycle number; The second amplifier (323) is used to amplify the second residual time by N times to obtain the second amplified residual signal; The second logic signal generation unit (324) is used to convert the second amplified residual signal into a second enable signal and send the second enable signal to the second delay chain (31) so that the second delay chain (31), which is multiplexed as a ring oscillator, refines the second residual time to obtain the second N clock signal. The second encoding unit (322) is also used to encode the second N clock signal to obtain the second residual quantization result.

9. The high-precision time-to-digital converter according to claim 8, characterized in that, The second logic signal generation unit (324) is further configured to generate a second reference period sampling signal based on the time signal, and send the second reference period sampling signal to the second interpolator and residual difference extraction unit (321) so that the second interpolator and residual difference extraction unit (321) can determine whether the time signal has ended in the first half of the reference clock signal.

10. The high-precision time-to-digital converter according to claim 9, characterized in that, The first residual quantization result includes the first oscillation period number and the first phase encoding result; the second residual quantization result includes the second oscillation period number and the second phase encoding result. The length of the time signal satisfies the following formula: in, The length of the time signal; It is the product of the number of reference periods and the reference period; It is the product of the first internal cycle number and the internal cycle; , This is the number of the first oscillation period. The oscillation period of the first delay chain (21) that is reused as a ring oscillator. This is the result of the first phase encoding; It is the product of the second internal cycle number and the internal cycle. , This is the number of the second oscillation period. The oscillation period of the second delay chain (31) that is multiplexed as a ring oscillator. This is the result of the second phase encoding.

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