Control system core single machine virtual prototype interface, design method and storage medium
By building the 1553B bus model and its related models in Simulink and defining the data transmission module, the problem of insufficient data communication between stand-alone models in the system-level aircraft model is solved, and effective data transmission and bus failure injection are realized.
Patent Information
- Application Number
- CN202311806841.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2043-12-26
AI Technical Summary
When building a system-level aircraft model in Simulink, the 1553B bus model between stand-alone models is missing, resulting in insufficient data communication.
By building a 1553B bus model, bus controller model, remote terminal model and bus monitor model in Simulink, and defining the sending module and receiving module, data splitting, packaging, transmission and unpacking are realized.
It realizes data transmission between each stand-alone model in the system-level model, solves the problem of insufficient data communication, and has the function of injecting the bus fault.
Smart Images
Figure CN117851297B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of virtual prototype interface and design method, and in particular to a control system core single machine virtual prototype interface, design method and storage medium. Background Art
[0002] MIL-STD-1553B bus is a digital time-division command / response multiplexed data bus inside an aircraft. It has the advantages of stable transmission, anti-interference, light load, and high speed. MIL-STD-1553B bus has become a key technology for the interconnection of modern aviation airborne system equipment and is widely used in military, industrial, and scientific and technological fields.
[0003] In the process of aircraft model building, the models of each aircraft stand-alone terminal device are mainly built for the verification of the stand-alone model. Many of these models are built in Simulink. However, when building a system model, the connections between the models are often direct, lacking actual data communication between the stand-alone models. Therefore, in the current Simulink system-level aircraft model building process, there is a lack of 1553B bus models that cooperate with the stand-alone models. Summary of the invention
[0004] The purpose of the present invention is to provide a control system core stand-alone virtual prototype interface, design method and storage medium, and to build a 1553B virtual interface model through Simulink to solve the problem of lack of data communication between stand-alone models in the system-level model.
[0005] To achieve the above object, the present invention provides a control system core stand-alone virtual prototype interface design method, comprising the following steps:
[0006] Step 1: Build the 1553B bus model, bus controller model, remote terminal model, and bus monitor model in Simulink;
[0007] Step 2, according to the function of the 1553B bus model, define each terminal function to be split into a sending module and a receiving module, and define different numbers for indicating the command word, data word, and status word according to the frame format of 1553B;
[0008] Step 3, the receiving module determines the type of the received word and processes the record, and the sending module receives the instruction from the receiving module and sends the transmission data;
[0009] Step 4, synthesizing the data received by the bus controller model and the remote terminal model and inputting the signals into the terminal;
[0010] Step 5: Establish a data interaction model between the bus controller model, the remote terminal model and the terminal device, split and package the data through the data interaction model and input the data into the bus controller model and the remote terminal model;
[0011] Step six: unpack the data received by the terminal device according to the packaging logic through the data interaction model and input it into the terminal device.
[0012] Preferably, in step one, the bus controller model, the remote terminal model, and the bus monitor model are connected via a 1553B bus model.
[0013] Preferably, in step 2, the receiving module and the sending module are configured separately, and the two models interact through specific instructions.
[0014] Preferably, in step three, the receiving module requires the bus controller model, the remote terminal model and the bus monitor model to perform data processing, and the receiving module determines the type of the received word: if it is a command word, it is processed by the remote terminal model; if it is a data word, it is processed by the bus controller model and the remote terminal model; if it is a status word, it is processed by the bus controller model.
[0015] Preferably, the bus controller model and the remote terminal model require a sending module to transmit data. In the remote terminal model, if the sending module receives a sending instruction from the receiving module, it first sends a status word, and then sends the data received from the terminal to the 1553B bus model one by one; if the sending module receives a receiving completion instruction from the receiving module, it sends a status word; the sending module is controlled by the bus enable port to transmit the bus command word data. After the bus enable port is enabled, the sending module starts to transmit the bus command word, so that the bus can perform data transmission.
[0016] Preferably, in step four, the data output from each bus controller model and remote terminal model to the 1553B bus model is bitwise ORed to synthesize a signal which is then connected and input to each terminal; there is an algebraic loop in this step, and a delay model is added between the receiving module and the sending module to delay by one step.
[0017] Preferably, in step five, the data interaction model splits and packages the data to be sent by the terminal device into frames of 16 bits in length according to the data requirements of the terminal device, and inputs the data into the bus controller model and the remote terminal model.
[0018] Preferably, the control system core stand-alone virtual prototype interface design method also includes injecting faults into the 1553B bus model, setting a transmission line of a certain bus to zero or inverting a certain bit to inject faults into the 1553B bus model.
[0019] A control system core stand-alone virtual prototype interface is constructed by a control system core stand-alone virtual prototype interface design method.
[0020] A storage medium stores information designed by a control system core single-machine virtual prototype interface design method.
[0021] Therefore, the present invention adopts the above-mentioned control system core stand-alone virtual prototype interface, design method and storage medium, establishes a 1553B bus model, a bus controller model, a remote terminal model, and a bus monitor model in Simulink, and realizes data transmission between each stand-alone model in the aircraft system-level model according to the bus logic through the receiving module and the sending module, and can inject faults into the bus, thereby solving the problem of lack of data communication between stand-alone models in the system-level model.
[0022] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a flow chart of an embodiment of a method for designing a virtual prototype interface of a core stand-alone control system of the present invention;
[0024] Figure 2 It is a relationship connection diagram between various models in an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The technical solution of the present invention is further described below through the accompanying drawings and embodiments.
[0026] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. The terms "set", "install" and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two elements. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0027] Example
[0028] like Figure 1 As shown, a control system core stand-alone virtual prototype interface design method according to the present invention comprises the following steps:
[0029] Step 1: Build a 1553B bus model, a bus controller model, a remote terminal model, and a bus monitor model in Simulink, and connect the bus controller model, the remote terminal model, and the bus monitor model through the 1553B bus model.
[0030] The simulation feature of Simulink is to simulate by step length. Due to the high bus frequency speed, the rate of 1553B is 1Mbps or 4Mbps. If the simulation is performed at 1bit, the simulation step length of 1Mbps rate needs to be 1e-6s. The simulation step length is too short, which seriously affects the simulation rate. The length of a 1553B word is 20 bits, the first three bits are the header, the middle 16 bits are the valid bits, and the last bit is the parity bit. Therefore, the 1553B bus model uses a word length of 1553B as a simulation step length, and models the bus transmission of the most important 16 valid bits in the middle, which can greatly improve the simulation rate; the simulation step length of the 1Mbps 1553B bus can be increased to 2e-5s, and the simulation frequency can be reduced to 50000Hz.
[0031] like Figure 2 As shown, the 1553B bus model is used to simulate the connection between the bus controller (BC), remote terminal (RT) and bus monitor (BM) on the 1553B data bus. For the BC model, the input and output interface connected to the bus, the input and output interface with the terminal device, the bus startup interface, and the command word register interface are established. The command word register interface is used for BC to read the command word, which can be read from the workspace or file. For the RT model, the input and output interface connected to the bus and the input and output interface with the terminal device are established. For the BM model, the input interface from the bus to the model and the output interface from the model to the terminal device are established.
[0032] Step 2: According to the functions of the 1553B bus model, define each terminal function to be split into a sending module and a receiving module, configure the receiving module and the sending module respectively, and the two modules interact through specific instructions. And according to the frame format of 1553B, define different numbers (0, 1, 2) for the command word, data word, and status word to indicate.
[0033] Step three, for the receiving module, BC, RT and BM all need this module, and use the Sfunction module to write Matlab language code to implement it. First, determine the type of word received. If it is a command word, RT needs to process it and split and determine the received word according to the 1553B command frame format. If it is determined to be a sending instruction of this terminal, count it and pass it to the sending module to send the instruction within the counting cycle; if it is determined to be a receiving instruction of this terminal, count and receive the data word within the counting cycle, and send the receiving completion instruction to the sending module after the reception is completed; if it is determined to be a non-terminal instruction, count it and do not operate within the counting cycle; if it is a mode instruction, send the mode code to the terminal device.
[0034] If it is a data word, BC and RT need to be processed, and BM only needs to be recorded. If the BC receiving module receives a receiving instruction from the sending module or the RT receiving module is within the receiving count cycle, the data in the data word is extracted and sent to the terminal device.
[0035] If it is a status word, only BC is processed, split according to the status frame format of the bus 1553B model and judged and processed.
[0036] For the sending module, only BC and RT need this module, and the Sfunction module is also used to write Matlab language code. In RT, if the sending module receives a sending instruction from the receiving module, it will first send the status word, and then send the data received from the terminal to the bus one by one. If the sending module receives a receiving completion instruction from the receiving module, it will send the status word.
[0037] In BC, the sending module is controlled by the bus enable port to start bus data transmission, read and parse the set command word, send the command word and send the data word according to the requirements of the command word, and send a receiving instruction to the receiving module in BC.
[0038] Step 4: Perform bitwise OR operation on the data output to the bus by each BC and RT model, synthesize a signal and then connect the input to each terminal to simulate the bus connection.
[0039] There is an algebraic loop in this step. Add a delay model between the receiving and sending modules of the model to delay by one step to ensure that the simulation can proceed normally.
[0040] Step 5: Establish a data interaction module between the BC and RT models and the terminal device. According to the data requirements of the terminal device, split and package the data that the terminal device needs to send according to the length of a 16-bit frame, and then input it into the BC and RT models.
[0041] Step six: During the process of step five, the data that the terminal device needs to receive is unpacked according to the logic when it is packaged through the data interaction module, restored to the original data and then input into the terminal device.
[0042] In addition, when building the bus 1553B model, the transmission line of a certain bus can be always set to zero or a certain bit can be inverted to perform fault injection into the 1553B bus model.
[0043] A control system core stand-alone virtual prototype interface described in the present invention is constructed according to the control system core stand-alone virtual prototype interface design method.
[0044] The storage medium storage described in the present invention is designed by the control system core single-machine virtual prototype interface design method.
[0045] Therefore, the present invention adopts the above-mentioned control system core stand-alone virtual prototype interface, design method and storage medium, and builds a 1553B virtual interface model through Simulink to solve the problem of lack of data communication between stand-alone models in the system-level model.
[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.
Claims
1. A control system core stand-alone virtual prototype interface design method, characterized by: The following steps are involved: Step 1: Build the 1553B bus model, bus controller model, remote terminal model, and bus monitor model in Simulink; Step 2: According to the function of the 1553B bus model, each bus terminal is split into a sending module and a receiving module, and different numbers are defined for command words, data words, and status words according to the 1553B frame format; Step 3, the receiving module determines the type of the received word and processes the record, and the sending module receives the instruction from the receiving module and sends the transmission data; Step 4, synthesizing the data received by the bus controller model and the remote terminal model and inputting the signals into the terminal; Step 5: Establish a data interaction model between the bus controller model, the remote terminal model and the terminal device, split and package the data through the data interaction model and input the data into the bus controller model and the remote terminal model; Step 6: unpack the data received by the terminal device according to the packaging logic through the data interaction model, and input the data into the terminal device; In step 3, the receiving module needs the bus controller model, remote terminal model and bus monitor model to process data. The receiving module determines the type of word received: if it is a command word, it is processed by the remote terminal model; if it is a data word, it is processed by the bus controller model and remote terminal model; If it is a status word, it is processed through the bus controller model; First, determine the type of word received. If it is a command word, RT needs to process it and split the received word according to the 1553B command frame format and determine it; if it is determined to be a sending instruction of this terminal, count it and pass it to the sending module to send the instruction within the counting cycle; if it is determined to be a receiving instruction of this terminal, count and receive the data word within the counting cycle, and send the receiving completion instruction to the sending module after the reception is completed; if it is determined to be a non-terminal instruction, count it and do not operate within the counting cycle; if it is a mode instruction, send the mode code to the terminal device; If it is a data word, BC and RT need to be processed, and BM only needs to be recorded; if the BC receiving module receives a receiving instruction from the sending module or the RT receiving module is within the receiving count cycle, the data in the data word is extracted and sent to the terminal device; If it is a status word, only BC is processed, split according to the status frame format of the bus 1553B model, and judged and processed; The bus controller model and the remote terminal model require a sending module to transmit data. In the remote terminal model, if the sending module receives a sending instruction from the receiving module, it first sends a status word and then sends the data received from the terminal to the 1553B bus model one by one. If the sending module receives the receiving completion instruction from the receiving module, it sends the status word; in the bus controller model, the sending module is controlled by the bus enable port to perform data transmission of the bus command word. After the bus enable port is enabled, the sending module starts to transmit the bus command word, so that the bus can perform data transmission; In step 4, the data output from each bus controller model and remote terminal model to the 1553B bus model are bitwise ORed to synthesize a signal and then connected to each terminal; there is an algebraic loop in this step, and a delay model is added between the receiving module and the sending module to delay by one step; In step 5, the data interaction model splits and packages the data that the terminal device needs to send according to the length of a 16-bit frame according to the data requirements of the terminal device, and inputs it into the bus controller model and the remote terminal model; The control system core single-machine virtual prototype interface design method also includes injecting faults into the 1553B bus model, setting a transmission line of a certain bus to zero or inverting a certain bit to inject faults into the 1553B bus model.
2. The control system core stand-alone virtual prototype interface design method according to claim 1 is characterized by: In step 1, the bus controller model, the remote terminal model, and the bus monitor model are connected via the 1553B bus model.
3. The control system core stand-alone virtual prototype interface design method according to claim 2 is characterized by: In step 2, the receiving module and the sending module are configured separately, and the two models interact through specific instructions.
4. A control system core stand-alone virtual prototype interface, characterized in that: The control system core stand-alone virtual prototype interface is constructed by the control system core stand-alone virtual prototype interface design method described in any one of claims 1-3.
5. A storage medium, characterized in that: The storage medium stores the design through the control system core stand-alone virtual prototype interface design method described in any one of claims 1-3.