A high-speed data transmission method and system for multi-threaded DMA

Abstract

The present invention discloses a high-speed data transmission method of multi-threaded DMA, which includes: configuring the interface connection mode between the first processor and the second processor to generate a DMA transmission channel; starting the interrupt thread of the first processor, polling and monitoring the register content information in the second processor to generate multiple interrupt instructions including semaphores; responding to the interrupt instruction, executing multiple working threads of the first processor, and obtaining the data transmission information of the second processor through the DMA transmission channel; wherein, in the first processor, multiple working threads are respectively bound to independent processor cores for operation. According to the method and system disclosed in the present invention, by binding the interrupt thread to each working thread on different processing cores, it is possible to avoid the competition overhead caused by multiple threads occupying the physical resources of the processor, and reduce the time overhead of memory access. Thereby, the data transmission rate between different types of processors is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer network and communication technology, and in particular to a multi-thread DMA high-speed data transmission method and system. Background Art

[0002] With the continuous updating and iteration of technologies such as artificial intelligence and big data, the speed of existing data transmission systems can no longer meet the speed and real-time requirements of communication systems and data acquisition systems. With the rapid development of integrated circuit technology, high-speed data transmission between multiple processors has also become a technical problem that needs to be solved urgently.

[0003] Current processors such as CPU processors usually adopt a multi-core architecture. In a multi-core processor system, each core has its own local cache to accelerate memory access. When a CPU core accesses a memory page, if the memory page does not exist in the local cache of the CPU core or the memory page exists but has been modified by other CPU cores and becomes a dirty page, the page needs to be reloaded, which takes a lot of time and reduces the data transmission and processing speed. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a multi-thread DMA high-speed data transmission method and system, which can avoid the competition overhead caused by multiple threads occupying the physical resources of the processor by binding each working thread to a processing core, reduce the time overhead of memory access, and thus improve the transmission rate between different types of processors.

[0005] In order to solve the above technical problems, the first aspect of the present invention discloses a high-speed data transmission method of multi-threaded DMA, the method comprising: configuring the interface connection mode between the first processor and the second processor to generate a DMA transmission channel; starting the interrupt thread of the first processor, polling and monitoring the register content information in the second processor to generate multiple interrupt instructions including semaphores; in response to the interrupt instructions, executing multiple working threads of the first processor, and obtaining the data transmission information of the second processor through the DMA transmission channel; wherein, in the first processor, the interrupt thread and the multiple working threads are respectively bound to independent processor cores and run.

[0006] In some implementations, configuring the interface connection mode between the first processor and the second processor to generate a DMA transmission channel includes: merging multiple PCIe channels through the second processor to generate a DMA transmission channel for parallel data transmission.

[0007] In some embodiments, polling and monitoring the register content information in the second processor to generate multiple interrupt instructions including a semaphore includes: polling and monitoring the interrupt count of the interrupt register in the second processor; if it is monitored that the interrupt count increases by one unit, generating an interrupt request instruction for the second processor; in response to the interrupt request instruction, the first processor releases the semaphore of the corresponding working thread, and generates multiple interrupt instructions including the semaphore.

[0008] In some embodiments, in response to the interrupt instruction, multiple working threads of the first processor are executed, and data transmission information of the second processor is obtained through the DMA transmission channel, including: obtaining the workload of the multiple working threads contained in the interrupt instruction, and executing the corresponding working threads; when the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate a consistent data transmission information output of the second processor.

[0009] In some implementations, the first processor and the second processor include at least one of a CPU processor, a GPU processor, a FPGA processor, and an ARM processor.

[0010] The second aspect of the present invention discloses a multi-threaded DMA high-speed data transmission system, the system comprising: a first processor; a second processor; a DMA transmission channel, which is generated by configuring the interface connection method between the first processor and the second processor; wherein the first processor comprises: an interrupt thread, when the interrupt thread of the first processor is started, polling and monitoring the register content information in the second processor to generate multiple interrupt instructions including semaphores; multiple working threads, which are used to respond to the interrupt instructions, execute the multiple working threads of the first processor, and obtain the data transmission information of the second processor through the DMA transmission channel; wherein, in the first processor, the interrupt thread and the multiple working threads are respectively bound to independent processor cores for operation.

[0011] In some implementations, the DMA transmission channel is implemented by merging multiple PCIe channels through a second processor to generate a DMA transmission channel for parallel data transmission.

[0012] In some embodiments, the interrupt thread includes: polling and monitoring the interrupt number of the interrupt register in the second processor; if it is monitored that the interrupt number increases by one unit, generating an interrupt request instruction for the second processor; in response to the interrupt request instruction, the first processor releases the semaphore of the corresponding working thread and generates multiple interrupt instructions including the semaphore.

[0013] In some embodiments, the working thread includes: obtaining the workload of multiple working threads contained in the interrupt instruction and executing the corresponding working threads; when the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate a consistent data transmission information output of the second processor.

[0014] In some implementations, the first processor and the second processor include at least one of a CPU processor, a GPU processor, a FPGA processor, and an ARM processor.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The implementation of the present invention can firstly realize independent memory access of multi-core threads, by binding each working thread to a processor core, avoiding the competition overhead caused by multiple threads occupying the physical resources of the processor. At the same time, by independently allocating independent memory space for each working thread of the application layer, and not sharing memory space with other processor cores, dirty pages and reloading pages are avoided, and the time overhead of memory access is reduced.

[0017] Secondly, the interrupt processing of the polling register of the present application no longer adopts the traditional interrupt mode, and does not implement the interrupt by notifying the application layer through the kernel interrupt, but implements the interrupt response by polling the registers of other processor cards. The polling of registers can effectively reduce the overhead caused by the kernel notifying the application layer through interrupts; at the same time, the number of semaphores released and the number of interrupt response threads triggered are determined according to the number of interrupts, so as to avoid the loss of interrupts due to untimely responses.

[0018] Therefore, the resource utilization rate of the present application is high. Most of the current CPUs are multi-core processors. Different threads of the program are bound to run on independent CPU cores to achieve concurrent processing of data, effectively improving the resource utilization efficiency of the platform. In addition, the data transmission speed is fast, and the advantages of the PCIe bus can be fully utilized to transmit multiple channels of PCIe serial transmission in parallel, taking into account the advantages of high-speed serial transmission and parallel transmission, and merging multiple channels into a read-write channel to ensure high transmission rate and high real-time performance. In addition, the number of interrupts is obtained by polling the register instead of responding to interrupts at the kernel layer, which avoids the loss of interrupts caused by untimely interrupt responses in high-speed transmission, improves the robustness of data transmission, greatly reduces the packet loss rate of transmission, and can achieve systematic stable transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic flow chart of a high-speed data transmission method of a multi-threaded DMA disclosed in an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a high-speed data transmission system framework of a multi-threaded DMA disclosed in an embodiment of the present invention;

[0021] Figure 3 The present invention is a schematic diagram of the structure of a high-speed data transmission device of a multi-threaded DMA disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] For better understanding and implementation, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The terms "including" and "having" and any variations thereof in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products or apparatus.

[0024] The embodiment of the present invention discloses a method and system for high-speed data transmission of multi-threaded DMA, which can improve resource utilization. Currently, most CPUs are multi-core processors. Programs are bound to a separate CPU core for operation to achieve concurrent data processing, effectively improving the resource utilization efficiency of the platform. In addition, the data transmission speed is fast, and the advantages of the PCIe bus can be fully utilized to transmit multiple channels of PCIe serial transmission in parallel, taking into account the advantages of high-speed serial transmission and parallel transmission, and merging multiple channels into a read-write channel to ensure high transmission rate and high real-time performance. In addition, the number of interrupts is obtained by polling and reading registers instead of responding to interrupts at the kernel layer, which avoids interrupt loss caused by untimely interrupt response during high-speed transmission, improves the robustness of data transmission, greatly reduces the packet loss rate of transmission, and can achieve systematic stable transmission.

[0025] Embodiment 1

[0026] See also Figure 1 , Figure 1 The present invention is a flowchart of a high-speed data transmission method of a multi-threaded DMA disclosed in an embodiment of the present invention. The high-speed data transmission method of the multi-threaded DMA can be applied to a data transmission system of multiple processors, and the present invention does not limit the application scenario of the high-speed data transmission method of the multi-threaded DMA. Figure 1As shown, the high-speed data transmission method of the multi-threaded DMA may include the following operations:

[0027] Step 101: configuring an interface connection mode between a first processor and a second processor to generate a DMA transmission channel.

[0028] The first processor and the second processor may include a CPU processor, a GPU processor, an FPGA processor, an ARM processor, or other types of processors, and the present application does not limit the type of processor. In this embodiment, in order to explain the implementation of the method in detail and clearly, the first processor is a CPU processor, which can be applied to a Linux operating system, and the second processor is an FPGA processor. It should be noted that the method of this embodiment is not limited to data transmission between two processors. In other implementations, data transmission methods that can implement multiple types and multiple transmission paths are all within the protection scope of this embodiment.

[0029] First, it is necessary to establish an interface link channel between two different types of processors. The interface methods currently used between multiple processors mainly include: PCIe (PCI Express, a type of PCI computer bus) front-end bus, LVDS (Low-Voltage Differential Signaling, low voltage differential signal) interface standard, VME (VersaModuleEurocard, a general computer bus), etc. For example, PCIe bus, as a new generation of data transmission bus, adopts end-to-end, differential serial mode for data transmission. PCIe bus, as a high-speed data transmission channel, can directly move data to the memory address without passing through the CPU processor through DMA (Direct Memory Access, direct memory access) technology. However, based on the general driver of the Linux operating system, DMA will generate an interrupt for each packet of data transmitted, and the transmission of massive data will frequently trigger interrupts, resulting in frequent interruptions of the CPU processor, so it is necessary to enter the driver layer to process interrupt requests, thereby failing to fully utilize the transmission performance of the PCIe bus. Therefore, in this embodiment, the interface connection method between the first processor and the second processor is configured as a DMA transmission channel generated by merging multiple channels of PCIe. The specific implementation is: multiple Lanes or channels of PCIe are merged through the second processor to implement parallel transmission. At the same time, from the perspectives of multi-threaded parallel transmission, subsequent interrupt acquisition method, CPU execution efficiency, etc., the transmission rate of the high-speed transmission system is improved. According to the experiments of this embodiment, it can be increased from the original 16Gbps to 20Gbps. At the same time, the robustness of the system is improved, the packet loss rate of transmission is greatly reduced, and stable transmission of the system can be achieved.

[0030] Step 102: Start the interrupt thread of the first processor, poll and monitor the register content information in the second processor to generate multiple interrupt instructions including semaphores.

[0031] Since the interrupt is realized by notifying the application layer through the kernel interrupt when the traditional interrupt mode is adopted, in order to reduce the overhead caused by the kernel notifying the application layer through the interrupt mode, the present application realizes the interrupt response by polling the second processor, that is, the FPGA machine board register. At the same time, according to the number of interrupts, it is determined how many semaphores are released to trigger the interrupt response thread for how many times, so as to avoid the interrupt being lost due to untimely response. The specific implementation is as follows: firstly, the number of interrupts of the interrupt register in the second processor is monitored by polling, and if it is detected that the number of interrupts increases by one unit, that is, there is an accumulation phenomenon / recorded as +1, the interrupt request instruction of the second processor is triggered, and the interrupt request instruction includes the interrupt signal sent by the second processor. In response to the interrupt request instruction, the first processor will release the semaphore of the corresponding working thread, and generate multiple interrupt instructions including the semaphore. Therefore, this polling and reading of the register at the application layer to obtain the number of interrupts, rather than responding to the interrupt at the kernel layer, avoids the interrupt loss caused by untimely interrupt response in high-speed transmission, and improves the robustness of data transmission.

[0032] Step 103: In response to the interrupt instruction, execute multiple working threads of the first processor, and obtain data transmission information of the second processor through the DMA transmission channel.

[0033] The working threads in the first processor CPU are multi-threaded, and multiple working threads are bound to separate processor cores for operation. Specifically, through the CPU core binding technology provided by the kernel, each thread is bound to a separate CPU core for operation, thereby avoiding the overhead of inter-thread competition. In addition, the working threads use large paging units to allocate large memory spaces separately, which greatly reduces the number of page fault interrupts; reduces the frequency of page table lookups, and greatly reduces the overhead of accessing memory. In addition, this type of working thread is bound to a CPU core to run separately, avoiding the problem of memory re-addressing and reloading pages. The speed of data processing is accelerated.

[0034] When the workload of multiple working threads included in the acquisition interrupt instruction is obtained, the corresponding working threads are executed, that is, when the working threads each receive the semaphore transmitted by the interrupt thread, the first processor CPU executes the DMA read instruction, and the data of the second processor FPGA board can be obtained. This method of determining how many semaphores are released and how many times the interrupt response thread is triggered according to the number of interrupts can avoid the interrupt being lost due to untimely response. It is specifically implemented as follows: when the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate a consistent data transmission information output of the second processor. Exemplarily, the working thread of the CPU processor writes the preset FPGA board memory address and the amount of data read that are negotiated in advance, and after receiving the semaphore sent by the interrupt thread, the data transmission information of the second processor is obtained through the DMA transmission channel to start DMA transmission. After starting the transmission, the working thread compares and detects the number of bytes of the second processor received by the DMA transmission channel and the negotiated number of bytes. If it is inconsistent with the negotiated number, the transmission continues. After the negotiation is consistent, the DMA transmission is stopped to complete the high-speed data transmission between the first processor and the second processor.

[0035] Embodiment 2:

[0036] See also Figure 2 , Figure 2 The schematic diagram of the framework of a high-speed data transmission system of a multi-threaded DMA disclosed in an embodiment of the present invention. The high-speed data transmission system of the multi-threaded DMA can be applied to data transmission systems of multiple processors, and the embodiment of the present invention does not limit the application scenario of the high-speed data transmission system of the multi-threaded DMA. Figure 2 As shown, the high-speed data transmission system of the multi-threaded DMA may include:

[0037] The first processor 1; the second processor 3; the DMA transmission channel 2. The first processor and the second processor may include one of a CPU processor, a GPU processor, an FPGA processor, and an ARM processor, and the present embodiment does not limit the type of processor. For example, the first processor 1 is a CPU processor, which can be applied to a Linux operating system, and the second processor 3 is an FPGA processor. In this embodiment, the DMA transmission channel formed by the CPU processor and the FPGA processor based on the PCIe interface constitutes a high-speed data transmission system, the CPU interface is implemented as a PCIe bus interface, the board of the FPGA processor is connected to the CPU through the PCIe bus, and the board of the FPGA processor has a DMA function, which can complete data read and write operations.

[0038] The specific implementation of DMA transmission channel 2 is as follows: multiple Lanes of PCIe, such as Lane0, Lane1, Lane2... as shown in the figure, are merged through the second processor, so that parallel transmission can be implemented. At the same time, from the perspectives of multi-threaded parallel transmission, subsequent interrupt acquisition method, CPU execution efficiency, etc., the transmission rate of the high-speed transmission system is improved. According to the experiments of this embodiment, it can be increased from the original 16Gbps to 20Gbps. At the same time, the robustness of the system is improved, the packet loss rate of transmission is greatly reduced, and stable transmission of the system can be achieved.

[0039] The first processor includes an interrupt thread and a working thread. For the interrupt thread, the interrupt number of the interrupt register in the second processor is first polled and monitored. If the interrupt number is monitored to increase by one unit, that is, an accumulation phenomenon / recorded as +1 occurs, an interrupt request instruction for the second processor is triggered. The interrupt request instruction includes an interrupt signal sent by the second processor. In response to the interrupt request instruction, the first processor releases the semaphore of the corresponding working thread and generates multiple interrupt instructions including the semaphore. Therefore, this method of polling and reading the register at the application layer to obtain the number of interrupts, rather than responding to interrupts at the kernel layer, avoids interrupt loss caused by untimely interrupt response during high-speed transmission, and improves the robustness of data transmission.

[0040] For worker threads, the worker threads in the CPU processor are multi-threaded, and multiple worker threads are bound to separate processor cores for operation. Specifically, through the CPU core binding technology provided by the kernel, each thread is bound to a separate CPU core for operation, thereby avoiding the overhead of inter-thread competition. In addition, by using large paging units, worker threads are allocated large memory spaces separately, which greatly reduces the number of page fault interrupts; reduces the frequency of page table lookups, and greatly reduces the overhead of accessing memory. In addition, this type of worker thread is bound to a CPU core to run separately, avoiding the problem of memory re-addressing and reloading pages. The speed of data processing is accelerated.

[0041] When the workload of multiple working threads included in the acquisition interrupt instruction is obtained, the corresponding working threads are executed, that is, when the working threads each receive the semaphore transmitted by the interrupt thread, the first processor CPU executes the DMA read instruction, and the data of the second processor FPGA board can be obtained. This method of determining how many semaphores are released and how many times the interrupt response thread is triggered according to the number of interrupts can avoid the interrupt being lost due to untimely response. It is specifically implemented as follows: when the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate a consistent data transmission information output of the second processor. Exemplarily, the working thread of the CPU processor writes the preset FPGA board memory address and the amount of data read that are negotiated in advance, and after receiving the semaphore sent by the interrupt thread, the data transmission information of the second processor is obtained through the DMA transmission channel to start DMA transmission. After starting the transmission, the working thread compares and detects the number of bytes of the second processor received by the DMA transmission channel and the negotiated number of bytes. If it is inconsistent with the negotiated number, the transmission continues. After the negotiation is consistent, the DMA transmission is stopped to complete the high-speed data transmission between the first processor and the second processor.

[0042] Embodiment 3

[0043] See also Figure 3 , Figure 3 1 is a schematic diagram of a high-speed data transmission device of a multi-threaded DMA disclosed in an embodiment of the present invention. Figure 3 The described device can be applied to data transmission of various types of processors, and the embodiment of the present invention does not limit the application scenario of the multi-threaded DMA high-speed data transmission device. Figure 3 As shown, the device may include:

[0044] A memory 301 storing executable program codes;

[0045] a processor 302 coupled to the memory 301;

[0046] The processor 302 calls the executable program code stored in the memory 301 to execute the described multi-thread DMA high-speed data transmission method.

[0047] Embodiment 4

[0048] The embodiment of the present invention discloses a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the described multi-thread DMA high-speed data transmission method.

[0049] Embodiment 5

[0050] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute the described multi-thread DMA high-speed data transmission method.

[0051] The embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, i.e., they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without paying creative labor.

[0052] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or partly contributed to the prior art in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0053] Finally, it should be noted that the high-speed data transmission method and system of a multi-threaded DMA disclosed in the embodiment of the present invention discloses only the preferred embodiment of the present invention, which is only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions recorded in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A high-speed data transmission method for multi-threaded DMA, It is characterized in that The method comprises: Configuring an interface connection mode between the first processor and the second processor to generate a DMA transmission channel includes: Merging multiple PCIe channels through a second processor to generate a DMA transmission channel for parallel data transmission; The interrupt thread of the first processor is started, and the register content information in the second processor is polled and monitored to generate multiple interrupt instructions including semaphores, including: Polling and monitoring the interruption number of the interruption register in the second processor; If it is detected that the number of interruptions increases by one unit, an interrupt request instruction of the second processor is generated; In response to the interrupt request instruction, the first processor releases the semaphore of the corresponding working thread and generates a plurality of interrupt instructions including the semaphore; In response to the interrupt instruction, executing multiple working threads of the first processor, and acquiring data transmission information of the second processor through the DMA transmission channel; Wherein, in the first processor, the interrupt thread and the plurality of working threads are respectively bound to separate processor cores for execution.

2. The high-speed data transmission method of multi-threaded DMA according to claim 1, It is characterized in that In response to the interrupt instruction, executing multiple working threads of the first processor, and obtaining data transmission information of the second processor through the DMA transmission channel, including: Obtaining the workload of multiple working threads included in the interrupt instruction, and executing corresponding working threads; When the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate consistent data transmission information output of the second processor.

3. The high-speed data transmission method of multi-threaded DMA according to claim 1 or 2, It is characterized in that The first processor and the second processor include at least one of a CPU processor, a GPU processor, a FPGA processor, and an ARM processor.

4. A multi-threaded DMA high-speed data transmission system, It is characterized in that The system comprises: a first processor; A second processor; A DMA transmission channel is used to generate by configuring the interface connection mode between the first processor and the second processor, including: merging multiple PCIe channels through the second processor to generate a DMA transmission channel for parallel data transmission; Wherein, the first processor comprises: The interrupt thread, when starting the interrupt thread of the first processor, polls and monitors the register content information in the second processor to generate multiple interrupt instructions including semaphores, including: Polling and monitoring the interruption number of the interruption register in the second processor; If it is detected that the number of interruptions increases by one unit, an interrupt request instruction of the second processor is generated; In response to the interrupt request instruction, the first processor releases the semaphore of the corresponding working thread and generates a plurality of interrupt instructions including the semaphore; A plurality of working threads, for executing the plurality of working threads of the first processor in response to the interrupt instruction, and obtaining data transmission information of the second processor through the DMA transmission channel; Wherein, in the first processor, the interrupt thread and the plurality of working threads are respectively bound to separate processor cores for execution.

5. The high-speed data transmission system of multi-threaded DMA according to claim 4, It is characterized in that The working thread includes: Obtaining the workload of multiple working threads included in the interrupt instruction, and executing corresponding working threads; When the first processor executes the working thread, the preset data transmission information of the second processor is compared with the number of bytes of the data transmission information of the second processor obtained through the DMA transmission channel to generate consistent data transmission information output of the second processor.

6. The high-speed data transmission system of multi-threaded DMA according to claim 4 or 5, It is characterized in that The first processor and the second processor include at least one of a CPU processor, a GPU processor, a FPGA processor, and an ARM processor.

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