Geometry processing method, device, equipment and storage medium

Abstract

The present application discloses a geometry processing method, apparatus, device, and storage medium. The method includes configuring multiple GPU cores into one or more core groups based on the number and size of tasks; executing the geometry processing tasks corresponding to the core group in parallel using the cores in the core group; wherein a core group includes one or more cores, and each core group executes one geometry processing task. This allows for better utilization of the computing resources of each core, improving parallel processing capabilities and efficiency.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a geometry processing method, apparatus, device and storage medium. Background Art

[0002] A graphics processing unit (GPU) is a chip specifically designed for drawing images and processing metadata. The GPU rendering process is divided into the geometry phase and the fragment phase. A multi-core GPU integrates multiple GPU cores on a single chip. During use, the GPU cores can be configured as multiple independent GPUs, or multiple GPU cores can be combined into a single GPU, allowing workloads to be processed in parallel across multiple GPU cores. Current multi-core GPUs generally do not support geometry processing; geometry processing can only be performed on a single GPU core, failing to fully utilize the processing power of a multi-core GPU. Summary of the Invention

[0003] In view of this, embodiments of the present application provide at least one geometric processing method, apparatus, device, and storage medium.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a geometry processing method applied to a multi-GPU core system, the method comprising: configuring multiple GPU cores into one or more core groups based on the number and size of tasks; executing the geometry processing tasks corresponding to the core group in parallel through the cores in a core group; wherein a core group includes one or more cores, and a core group executes one geometry processing task.

[0006] In some embodiments, the one or more core groups perform different geometry processing tasks in parallel.

[0007] In some embodiments, the parallel execution of geometric processing tasks corresponding to a core group by cores in a core group includes: determining a task division rule based on the number of cores in the core group, the computing performance of each core in the core group, and the amount of geometric processing tasks to be processed by the core group, the task division rule being used to indicate the subtasks to be processed by each core in the core group; and performing geometric processing on the corresponding subtasks by each core in the core group according to the task division rule.

[0008] In some embodiments, the computing performance includes the task threshold of the core; the task division rule includes the data range of the subtask corresponding to each core in the core group; the task division rule is determined based on the number of cores in the core group, the computing performance of each core in the core group, and the task amount of the geometric processing tasks to be processed by the core group, including: dividing the task amount of the geometric processing tasks to be processed by the core group based on the task threshold of each core and the number of cores in the core group, and obtaining the data range of the subtask corresponding to each core.

[0009] In some embodiments, the task division rule includes the primitive range of the subtask corresponding to each core in the core group; the geometric processing of the corresponding subtask by each core in the core group according to the task division rule includes: judging whether the received primitive belongs to the primitive range corresponding to the subtask by each core in the core group; processing the primitives belonging to the primitive range of the subtask by each core in the core group, and discarding the primitives that do not belong to the primitive range of the subtask.

[0010] In some embodiments, the primitives have an order, and the primitive range is a primitive count range; the determination of whether the received primitives belong to the primitive range corresponding to the subtask by each core in the core group includes: counting the received primitives by the core to obtain a count value of each primitive; and determining whether the count value belongs to the primitive count range corresponding to the subtask.

[0011] In some embodiments, the geometry processing task includes performing geometry processing in units of primitives; the method further includes: receiving control commands and vertex data corresponding to the geometry processing task through the core group; and converting the vertex data into primitives in sequence based on the control commands through each core in the core group.

[0012] In some embodiments, the converting of the vertex data into primitives in sequence based on the control command by each core in the core group includes: extracting the topological type of the primitive from the control instruction, and converting the corresponding vertex data into the primitive based on the topological type.

[0013] In some embodiments, the method further includes: in the process of executing the geometry processing task corresponding to the core group in parallel through the cores in the core group, in response to receiving a target task with a higher priority than the geometry processing task, interrupting the geometry processing task and saving the processing status information of the geometry processing task; executing the target task in parallel through the cores in the core group; in response to completion of execution of the target task, resuming execution of the geometry processing task based on the processing status information of the geometry processing task.

[0014] In some embodiments, the processing status information includes sub-status information of the core; resuming execution of the geometry processing task based on the processing status information of the geometry processing task includes: obtaining sub-status information corresponding to each of the cores; and resuming execution of the geometry processing task based on the sub-status information corresponding to each of the cores.

[0015] In some embodiments, interrupting the geometry processing task and saving the processing status information of the geometry processing task include: obtaining the processing status of each core in the core group for the geometry processing task; the processing status represents the processing progress of the core for the corresponding subtask; when the processing status of the core for the geometry processing task represents that the core has completed the geometry processing of the corresponding subtask, the sub-state information of the core is not saved; when the processing status of the core for the geometry processing task represents that the core has not completed the geometry processing of the corresponding subtask, the sub-state information of the core is saved.

[0016] On the other hand, an embodiment of the present application provides a geometry processing device, comprising: a configuration module for configuring multiple GPU cores into one or more core groups based on the number and size of tasks; and an execution module for executing the geometry processing tasks corresponding to a core group in parallel using the cores in the core group; wherein a core group includes one or more cores, and a core group executes one geometry processing task. In yet another aspect, an embodiment of the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and when the processor executes the program, it implements some or all of the steps of the above method.

[0017] On the other hand, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements some or all of the steps in the above method when executed by a processor.

[0018] In an embodiment of the present application, the multiple GPU cores in the graphics processor are divided into core groups, and the core groups are used to implement the first level of parallel processing of the geometry processing process. Furthermore, within the core group, the geometry processing tasks corresponding to the core group are distributed to the various cores in the core group, thereby implementing the second level of parallel processing of the geometry processing process. Through two levels of parallel processing, the processing speed and efficiency are improved.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0021] Figure 1 A schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application Figure 1 ;

[0022] Figure 2 A schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application Figure 2 ;

[0023] Figure 3 A schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application Figure 3 ;

[0024] Figure 4 A schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application Figure 4 ;

[0025] Figure 5 A schematic diagram of a command processing module provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of a primitive sequence division rule provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of the structure of a geometry processing device provided in an embodiment of the present application;

[0028] Figure 8 A hardware entity diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence of "first / second / third" may be interchanged where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing this application only and are not intended to limit this application.

[0032] The present invention provides a geometry processing method that can be executed by a processor of a computer device. The computer device may include a server, laptop, tablet, desktop computer, smart TV, set-top box, mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), or other device with data processing capabilities.

[0033] Figure 1 A schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the method includes the following steps S101 to S102:

[0034] Step S101: Configure multiple GPU cores into one or more core groups according to the number and size of tasks.

[0035] The above-mentioned geometry processing method is applied to a multi-GPU core system, which includes multiple graphics processing units (GPU cores) for high-performance computing tasks such as graphics rendering and scientific computing.

[0036] Here, the driver corresponding to the graphics processor can receive the geometry processing task generated by the upper-layer application in the computer device and obtain task information of the geometry processing task. The task information may include the task quantity and task size of the geometry processing task. In some embodiments, the task quantity refers to the number of geometry processing tasks, and the task size refers to the amount of data that the geometry processing task needs to process. The data that the geometry processing task needs to process may be tile data, vertex data, and primitive data.

[0037] In some embodiments, a core group includes one or more cores, and a core group performs one geometry processing task. The core group is a combination including at least one GPU core, and the GPU cores included in different core groups do not overlap.

[0038] In some embodiments, the number of cores included in different core groups may be the same or different, and this application does not limit this.

[0039] In some embodiments, configuring multiple GPU cores into one or more core groups based on the number and size of tasks can be achieved by determining the number of cores required for each geometry processing task based on the task size of each geometry processing task, and then allocating a corresponding core to each geometry processing task based on the number of cores required for each geometry processing task to generate a core group for each geometry processing task. For example, if a graphics processor includes eight cores and receives two geometry processing tasks, where the task size corresponding to geometry processing task 1 is three times the task size of geometry processing task 2, six cores can be allocated into one core group to execute geometry processing task 1, and the other two cores can be allocated into another core group to execute geometry processing task 2. Alternatively, a unit task size corresponding to a core can be preset. If the task size corresponding to geometry processing task 1 is three times the unit task size, three cores can be allocated into one core group to execute geometry processing task 1. If the task size corresponding to geometry processing task 2 is one times the unit task size, one additional core can be allocated into a core group to execute geometry processing task 2. In this case, the graphics processor still has four cores remaining for executing subsequent tasks.

[0040] Of course, this application may also use other methods to configure multiple GPU cores into one or more core groups, which will not be described in detail here.

[0041] In some embodiments, when there are geometry processing tasks corresponding to multiple users, multiple GPU cores can be configured into multiple core groups, providing each user with a separate core group to accelerate the execution of their applications. Core groups are isolated from each other, and geometry processing tasks executed in one core group do not affect the cache of another core group. This ensures that individual user tasks can run to completion with predictable throughput and latency.

[0042] In the above embodiment, different numbers of GPU cores can be allocated to each core group based on the workload of different users' geometry processing tasks, with users with larger workloads receiving more GPU cores. Furthermore, after task execution is complete, the number of GPU cores in each core group can be statically adjusted based on the profiling results of each core group. This core group division improves GPU hardware utilization while providing isolation between different users, ensuring that one user does not affect the tasks and scheduling of other users.

[0043] In some embodiments, when there is only a geometry processing task corresponding to a single user, a multi-core GPU can also be divided into multiple core groups. For some tasks (e.g., tasks with relatively simple geometry processing), the benefits of GPU multi-core parallel execution are marginally diminishing. For example, the operating efficiency of a 4-core GPU is significantly improved compared to a single-core GPU, while the operating efficiency of an 8-core GPU is slightly or almost not improved compared to a 4-core GPU. For these simpler tasks, multiple GPU cores can be divided into two 4-core core groups to execute two tasks in parallel, thereby improving overall operating efficiency.

[0044] In an embodiment of the present application, the graphics processor can adaptively divide the multiple cores in the graphics processor according to the number and size of received tasks to obtain core groups that meet the task requirements. Therefore, in the process of using multiple core groups to process multiple tasks in parallel, the computing resource requirements of each task can be met, while at the same time improving the parallelism and processing efficiency of the geometric processing process as a whole.

[0045] Step S102: The cores in a core group execute the geometry processing tasks corresponding to the core group in parallel.

[0046] In some embodiments, when a core group executes a corresponding geometry processing task, each core within the core group executes the corresponding geometry processing task in parallel. That is, the geometry processing task can be divided into multiple subtasks, with each core executing a corresponding subtask in parallel, with different cores executing different subtasks.

[0047] In some embodiments, the one or more core groups execute different geometry processing tasks in parallel. For example, there are geometry processing task 1, geometry processing task 2, and geometry processing task 3. When multiple GPU cores are configured as three core groups, each executing a geometry processing task, core group 1 executes geometry processing task 1, core group 2 executes geometry processing task 2, and core group 3 executes geometry processing task 3 in parallel.

[0048] In an embodiment of the present application, the multiple GPU cores in the graphics processor are divided into core groups, and the core groups are used to implement the first level of parallel processing of the geometry processing process. Furthermore, within the core group, the geometry processing tasks corresponding to the core group are distributed to the various cores in the core group, thereby implementing the second level of parallel processing of the geometry processing process. Through two levels of parallel processing, the processing speed and efficiency are improved.

[0049] Figure 2 This is a schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application. Figure 2 , the method can be executed by a processor of a computer device. Figure 1 , Figure 1 S101 in can be updated to S201 to S202, which will be combined Figure 2 The steps shown are explained.

[0050] Step S201: determine a task division rule based on the number of cores in a core group, the computing performance of each core in the core group, and the amount of geometry processing tasks to be processed by the core group, wherein the task division rule is used to indicate the subtasks to be processed by each core in the core group.

[0051] In some embodiments, considering that different computing cores have different corresponding computing performances, the task division rules corresponding to different computing cores are also different. Accordingly, the task division rules are used to determine the data range that the subtasks of the core need to process based on the computing performance of the core, and to determine whether the data to be processed belongs to the subtask to be processed by the current core based on the data to be processed corresponding to the geometry processing tasks of the current core group and the data range of the subtask to be processed by the current core.

[0052] In some embodiments, the relative proportion between the computing performance corresponding to each core can be determined. Based on the relative proportion corresponding to each core and the task volume corresponding to the geometric processing task (all data that need to be processed), the data range of the subtask that each core needs to process is determined, and then the task division rules corresponding to each core are obtained.

[0053] For example, if the current core group includes core 1, core 2, and core 3, and the number of data items that need to be processed for the geometry processing tasks is 1 to 90, and the relative ratio of the computing performance of cores 1, 2, and 3 is 2:3:4, it can be determined that the number of data items that core 1 needs to process is 20, the number of data items that core 2 needs to process is 30, and the number of data items that core 3 needs to process is 40. Accordingly, the data range corresponding to the data that core 1 needs to process can be a set of 20 values ​​in [1, 90]; the data range corresponding to the data that core 2 needs to process can be a set of 30 values ​​in [1, 90]; and the data range corresponding to the data that core 3 needs to process can be a set of 40 values ​​in [1, 90]. The counting values ​​within the sets can be selected in any manner, but it must be ensured that there is no intersection between the set of data ranges corresponding to the data that core 1 needs to process, the set of data ranges corresponding to the data that core 2 needs to process, and the set of data ranges corresponding to the data that core 3 needs to process, and that the union of the three sets is [1, 90].

[0054] In some embodiments, the computing performance of the core can be quantitatively determined by at least one of the following parameters: the number of computing units present in the core, the geometry processing load in the core, the real-time temperature of the core, etc.

[0055] In some embodiments, the computing performance includes the task threshold of the core; the task division rule includes the data range of the subtask corresponding to each core in the core group; the above-mentioned task division rule can be determined based on the number of cores in the core group, the computing performance of each core in the core group, and the task amount of the geometric processing tasks to be processed by the core group through step S2011.

[0056] Step S2011 : Based on the task threshold of each core and the number of cores in the core group, the task amount of the geometry processing task to be processed by the core group is divided to obtain the data range of the subtask corresponding to each core.

[0057] In some embodiments, the task threshold of a core is used to determine the maximum amount of tasks continuously assigned to the core during geometry processing task distribution. The task threshold corresponding to the core is pre-set based on at least one of the core's computing performance, rendering scene, rendering mode, and other factors. The computing performance can be quantitatively determined by at least one of the following parameters: the number of computing units present in the core, the geometry processing load on the core, the real-time temperature of the core, and the like.

[0058] Step S202: According to the task division rule, each core in the core group performs geometric processing on the corresponding subtask.

[0059] In some embodiments, the geometry processing task corresponding to the core group can be sent to each core in the core group. Each core can determine the subtask to be processed based on the task partitioning rule and then execute the subtask. It is understood that each core executes different subtasks in parallel.

[0060] In some embodiments, the task division rule includes the primitive range of the subtask corresponding to each core in the core group, that is, the data to be processed by the geometry processing task is primitives. Steps S2021 and S2022 can be used to implement the geometry processing of the subtask corresponding to each core in the core group according to the task division rule.

[0061] Step S2021: Each core in the core group determines whether the received primitive belongs to the primitive range corresponding to the subtask.

[0062] In some embodiments, the primitive range is a primitive counting range, and whether the received primitive belongs to the primitive range corresponding to the subtask can be determined in the following manner: the received primitives are counted by the core to obtain the count value of each primitive; and whether the count value belongs to the primitive counting range corresponding to the subtask can be determined.

[0063] In the embodiment of the present application, all cores in a core group receive the same primitives, and each core receives the primitives independently. Accordingly, each core counts each primitive upon receiving it to obtain a corresponding count value for each primitive. The count value for each primitive represents the total number of primitives received by the core at the time it receives the primitive.

[0064] It should be noted that the counting process of each core for the graphics primitives is also independent of each other. That is, different cores may have different counting values ​​at the same time due to different speeds of receiving graphics primitives.

[0065] For example, if the current core group includes cores 1, 2, and 3, and the geometry processing tasks correspond to primitives 1 through 7, cores 1 through 3 will each acquire these 7 primitives and determine the count value for each primitive as they acquire them. For example, when core 1 acquires the first primitive, the count value for that primitive is 1; when core 1 acquires the second primitive, the count value for that primitive is 2, and so on.

[0066] In some embodiments, when the core obtains the primitive and calculates the count value corresponding to the primitive, it determines whether the count value corresponding to the primitive belongs to the primitive count range corresponding to the subtask corresponding to the core.

[0067] In this embodiment of the present application, since each core in the core group receives all primitives, in order to facilitate the distribution of all primitives to each core, this embodiment of the present application predetermines the primitive count range corresponding to each core. Therefore, overall, the primitive count range corresponding to all cores is used to distribute all primitives to each core; locally, the primitive count range corresponding to a core is used to determine the primitives that the core needs to process from all received primitives.

[0068] The counting values ​​corresponding to the primitives to be processed by different cores are different. In this way, the primitives to be processed by different cores will not overlap, thereby reducing the waste of geometric processing resources.

[0069] Step S2022: Process the primitives within the primitive range of the subtask through each core in the core group, and discard the primitives that do not belong to the primitive range of the subtask.

[0070] In some embodiments, when the count value corresponding to the received primitive belongs to the primitive count range corresponding to the subtask, the received primitive is determined to be a primitive belonging to the primitive range of the subtask; when the count value corresponding to the received primitive does not belong to the primitive count range corresponding to the subtask, the primitive is discarded.

[0071] In the above embodiment, after the core receives a primitive, it determines whether the primitive is a primitive that the current core needs to process based on the count value corresponding to the received primitive.

[0072] In some embodiments, the above-mentioned primitive division rule includes the primitive count range of the target primitives that need to be processed by the core, and the primitive division rule is used to determine whether the count value corresponding to each of the primitives belongs to the primitive count range of the target primitive. When the count value corresponding to the received primitive belongs to the primitive count range of the target primitive that needs to be processed by the core, the received primitive is determined as the target primitive that needs to be processed by the core. When the count value corresponding to the received primitive does not belong to the primitive count range of the target primitive that needs to be processed by the core, the received primitive is discarded.

[0073] In the embodiment of the present application, each core needs to process different subtasks, and each core's geometric processing process for the subtask it needs to process is independent of each other.

[0074] Figure 3 This is a schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application. Figure 3 , the method can be executed by a processor of a computer device. Figure 1The geometric processing task includes performing geometric processing on a primitive basis; the method may further include S301 and S302, combining Figure 3 The steps shown are explained.

[0075] Step S301: Receive control commands and vertex data corresponding to the geometry processing task through the core group.

[0076] In some embodiments, the control command is used to determine a conversion rule between vertex data and primitives. For all primitives corresponding to the geometry processing task, the control command includes a conversion rule corresponding to each primitive. Accordingly, the vertex data includes the primitive vertices corresponding to each primitive. Thus, based on the conversion rule corresponding to a primitive, the primitive vertices corresponding to the primitive are converted to obtain the primitive.

[0077] In other embodiments, the above control commands are also used to configure parameters of downstream computing units, thereby determining calculation rules of the computing units.

[0078] Step S302: Convert the vertex data into primitives in sequence based on the control command through each core in the core group.

[0079] In an embodiment of the present application, for all primitives corresponding to the geometry processing task, the core needs to execute the conversion process corresponding to each primitive in sequence according to the processing order of the primitives set by the geometry processing task, and then obtain each primitive in sequence.

[0080] In some embodiments, in response to obtaining a primitive, a counter may be used to record the number of primitives converted by the geometry processing task. Specifically, each time a primitive is obtained, the counter increments by 1. The count value displayed by the counter reflects the number of primitives converted by the current core. Furthermore, the count value may also reflect the relative order / rank of the currently obtained primitive among all primitives corresponding to the geometry processing task.

[0081] In an embodiment of the present application, by obtaining the control commands and corresponding vertex data corresponding to the geometric processing task, the graphics elements corresponding to the geometric processing task can be converted in sequence to facilitate subsequent graphics element division and parallel geometric processing; at the same time, by converting the graphics elements corresponding to the geometric processing task in sequence, the count value obtained can reflect the relative order of the currently obtained graphics element among all graphics elements corresponding to the geometric processing task, thereby realizing the restoration of the original data order during the parallel geometric processing process.

[0082] In some embodiments, step S3021 may be used to implement the above-mentioned conversion of the vertex data into primitives in sequence based on the control command by each core in the core group.

[0083] Step S3021: Extract the topology type of the primitive from the control instruction, and convert the corresponding vertex data into the primitive based on the topology type.

[0084] In some embodiments, the topology type may include, but is not limited to, a point list type, a line list type, a line strip type, a triangle list type, a triangle strip type, and the like.

[0085] In some embodiments, during the primitive conversion process, the topology type of the primitive may be extracted from the control instruction, and the corresponding vertex data may be converted into the primitive based on the topology type. For example, if the topology type of the primitive is a triangle list type, three vertices corresponding to the primitive may be obtained from the vertex data, and the three vertices may be connected based on the vertex connection strategy corresponding to the triangle list type to obtain the primitive.

[0086] Figure 4 This is a schematic diagram of the implementation process of a geometric processing method provided in an embodiment of the present application. Figure 4 , the method can be executed by a processor of a computer device. Figure 1 The method further includes steps S401 to S403, combining Figure 4 The steps shown are explained.

[0087] Step S401: In the process of executing the geometry processing task corresponding to the core group in parallel through the cores in the core group, in response to receiving a target task with a higher priority than the geometry processing task, interrupt the geometry processing task and save the processing status information of the geometry processing task.

[0088] In some embodiments, the priority of the target task is higher than the priority of the geometry processing task. If the graphics processor also assigns the target task to the core group executing the geometry processing task, the core group executing the geometry processing task needs to pause (interrupt) execution of the geometry processing task and save processing status information of the geometry processing task.

[0089] The processing status information of the geometry processing task represents the processing status of the geometry processing task by the core group at the time of interruption. In some embodiments, the processing status information may include sub-state information of each core in the core group.

[0090] In some embodiments, the interruption of the geometry processing task and the saving of the processing status information of the geometry processing task can be achieved through steps S4011 to S4013.

[0091] Step S4011: Obtain the processing status of each core in the core group for the geometry processing task.

[0092] The processing status represents the processing progress of the core on the corresponding subtask.

[0093] In an embodiment of the present application, considering the different processing performances of different cores in a core group, the processing progress of each core for all primitives corresponding to the geometry processing task is also different. Therefore, it is necessary to obtain the processing status of each core for the geometry processing task.

[0094] Step S4012: When the processing state of the core for the geometry processing task indicates that the core has completed geometry processing of the corresponding subtask, the substate information of the core is not saved.

[0095] Step S4013: When the processing status of the core for the geometry processing task indicates that the core has not completed geometry processing of the corresponding subtask, save the substate information of the core.

[0096] In the above embodiment, when the core's processing status for the geometry processing task indicates that the core has completed geometry processing for all target primitives to be processed, this indicates that the core has completed its own geometry processing task (i.e., the task to which the core is assigned when the geometry processing task is divided). When the geometry processing task is subsequently resumed, there is no need to continue executing the related processing procedures of the geometry processing task. Therefore, there is no need to save the core's sub-state information. Accordingly, when the core's processing status for the geometry processing task indicates that the core has not completed geometry processing for all target primitives to be processed, since the core has not completed its own geometry processing task, when the geometry processing task is subsequently resumed, it is necessary to continue executing the related processing procedures of the geometry processing task. Therefore, it is necessary to save the core's sub-state information.

[0097] In an embodiment of the present application, the different processing progress of each core for all graphics elements corresponding to the geometric processing task can be taken into account, and only the core that has not completed the geometric processing of all target graphics elements that need to be processed is allowed to save the core's sub-state information. Then, in the process of subsequent task recovery, only the core that has saved the sub-state information can be controlled to continue to execute the geometric processing task, saving system energy consumption.

[0098] Step S402: Execute the target task in parallel through the cores in the core group.

[0099] In an embodiment of the present application, the process of the core group executing the target task is the same as the process of the core group processing the geometric processing task, including: receiving the primitives corresponding to the target task through the core in the core group, and counting each of the primitives to obtain a corresponding count value; the core group includes at least two cores among the multiple cores; determining the primitives that the core needs to process based on the count value corresponding to each of the primitives and the primitive partitioning rule corresponding to the core; the primitive partitioning rule is used to determine the data range of the subtask that the core needs to process based on the computing performance of the core; and using the core to perform geometric processing on the primitives that need to be processed.

[0100] Step S403: In response to the target task being completed, resuming execution of the geometry processing task based on the processing status information of the geometry processing task.

[0101] In some embodiments, after the core group completes processing of the target task, it will restore to the state at the time of interruption based on the processing status information of the geometry processing task, and then resume execution of the geometry processing task.

[0102] In this embodiment of the present application, upon receiving a higher-priority target task, the currently processing task can be immediately interrupted and its processing status information saved for subsequent resumption. This mechanism ensures that high-priority tasks are processed promptly, improving the system's responsiveness and efficiency. Furthermore, by saving the processing status information of the geometry processing task and resuming execution of the geometry processing task based on this status information after the target task has completed, duplicate geometry processing tasks can be avoided, saving time and resources.

[0103] In some embodiments, the processing status information includes sub-state information of the core; the processing status information based on the geometry processing task can be implemented through steps S4031 to S4032 to resume execution of the geometry processing task.

[0104] Step S4031: Obtain sub-state information corresponding to each core.

[0105] In the embodiment of the present application, considering the different processing performances of different cores within a core group, each core has a different processing progress for all primitives corresponding to the geometry processing task. Therefore, it is necessary to obtain the sub-state information corresponding to each core. The sub-state information corresponding to the core is used to restore the processing progress of the geometry processing task at the time of the interruption. In other words, the sub-state information corresponding to the core is used to determine the primitive that the current core was converting at the time of the interruption of the geometry processing task.

[0106] Step S4032: Resume executing the geometry processing task based on the sub-state information corresponding to each core.

[0107] In an embodiment of the present application, since the sub-state information can determine the primitives that the current core is converting when the execution of the geometry processing task is interrupted, in the process of resuming the execution of the geometry processing task, the core can quickly locate the processed primitives based on the sub-state information corresponding to the core, so as to continue processing the unprocessed primitives.

[0108] In an embodiment of the present application, each core resumes execution of the geometric processing task based on the corresponding sub-state information. From the perspective of the core group, each core continues to process unprocessed primitives, thereby enabling the core group to resume execution of the geometric processing task from the point of interruption.

[0109] In some embodiments, the sub-state information includes a count value corresponding to the primitive at the interruption point; the resumption of execution of the geometry processing task based on the sub-state information corresponding to each of the cores includes: on the basis of the count value corresponding to the primitive at the interruption point, continuing to count the received primitives through the core to obtain the count value of each primitive; judging whether the count value belongs to the primitive count range corresponding to the subtask; processing the primitives belonging to the primitive range of the subtask through each core in the core group, and discarding the primitives that do not belong to the primitive range of the subtask.

[0110] Among them, the sub-state information also includes the vertex data address and control instruction address at the interruption point; based on the count value corresponding to the primitive at the interruption point, the received primitives are continued to be counted by the core to obtain the count value of each primitive, including: the vertex data continued to be obtained is converted by the core based on the control instructions continued to be obtained, and based on the count value corresponding to the primitive at the interruption point, each primitive obtained after the conversion is counted to obtain the corresponding count value.

[0111] In the above embodiment, the sub-state information includes the count value corresponding to the primitive at the interruption, the vertex data address at the interruption, and the control instruction address, and the resuming execution of the geometry processing task by the core based on the corresponding sub-state information includes: continuing to obtain the vertex data of the geometry processing task based on the vertex data address at the interruption by the core; and continuing to obtain the control instruction of the geometry processing task based on the control instruction address at the interruption; converting the vertex data continued to be obtained by the core based on the control instruction continued to be obtained, and counting each primitive obtained after the conversion on the basis of the count value corresponding to the primitive at the interruption to obtain the corresponding count value; determining the target primitive that the core needs to process based on the count value corresponding to each primitive and the primitive division rule corresponding to the core, and using the core to perform geometric processing on the target primitive.

[0112] In the embodiment of the present application, since each core is converted in sequence to obtain each primitive, the sub-state information corresponding to the above core includes the count value corresponding to the current core primitive at the moment of interrupting the execution of the geometry processing task, the vertex data address and the control instruction address at the interruption. Among them, the count value corresponding to the primitive at the interruption is used to determine the count value of the primitive converted after resuming execution, thereby facilitating the determination of whether the primitive converted after resuming execution is the target primitive that the current core needs to process; the vertex data address and the control instruction address at the interruption are used to determine the vertex data and the corresponding control instruction that the current core needs to obtain at the interruption, that is, the vertex data address and the control instruction address at the interruption are used to determine the vertex data and the corresponding control instruction corresponding to the first primitive that needs to be continued to be processed, thereby realizing the conversion of the first primitive.

[0113] The following describes the application of the geometry processing method provided in the embodiments of the present application in actual scenarios, mainly involving the geometry processing process of a multi-core graphics processor.

[0114] In some embodiments, for a multi-core GPU supporting geometry processing, multiple GPU cores read the same primitive sequence and, according to the same rules, divide the read primitive sequence into blocks to obtain multiple primitive data blocks. Each GPU core is responsible for processing a portion of the primitive data blocks and performs geometry processing operations only on the primitive data blocks it is responsible for.

[0115] After research, it was found that the above implementation plan has the following problems:

[0116] (1) The configuration of multi-core GPUs is not flexible enough and can only combine multi-core GPUs into one GPU.

[0117] (2) After each GPU core reads the primitive sequence, the division of the primitive sequence is not flexible enough, and the sizes of the divided primitive data blocks are the same.

[0118] (3) In the case where a task with a higher priority arrives, it is impossible to give priority to this task with a higher priority.

[0119] It can be seen that the above implementation scheme is not flexible enough in configuring the multi-core GPU, and can only form the multi-core GPU into one GPU. Based on this, the present application provides a geometry processing scheme. In the implementation scheme of the present application, N GPU cores can be configured into M GPU groups (GPU Group) through a configuration module, where M < N. Each GPU Group can execute different tasks. Therefore, the software can be flexibly configured according to the number and size of tasks. The software involved in the embodiments of the present application can be understood as the driver of the GPU.

[0120] Please refer to Figure 5 , which shows a schematic diagram of a command processing module. This command processing module can support the parallel processing of geometry by the multi-core GPU, greatly improving the geometry processing performance of the multi-core GPU. Among them, this command processing module 100 includes a configuration module 110, a command reading module 120, a primitive division module 130, and a context switching (ContextSwitch) module 140.

[0121] Among them, the software can divide the multi-core GPU into one or more GPU Groups, and each GPU Group executes the geometry processing task in parallel. The specific method is: the software writes the number of GPU cores in the current GPU Group, the ID of the current GPU core in the GPU Group, and the length of the primitive data block divided by each GPU core (that is, the number of primitives in the primitive data block) into the configuration module 110.

[0122] The configuration module 110 is used to calculate the primitive division rule of the current GPU core according to the number of GPU cores in the GPU Group, the ID of the current GPU core in the GPU Group, and the length of the primitive data block divided by each GPU core, and send it to the primitive division module 130.

[0123] The command reading module 120 is used to read the control command and vertex data from the memory (Memory), and send the control command and vertex data to the primitive division module. Among them, the control command is used to configure the parameters of the downstream arithmetic unit, and further determine the calculation rule of the arithmetic unit.

[0124] The primitive partitioning module 130 is configured to receive control commands and vertex data sent by the command reading module 120, as well as primitive partitioning rules sent by the configuration module 110. The primitive partitioning module 130 extracts primitive topology from the control commands and sends the control commands to the geometry processing module. Based on the primitive topology information, the primitive partitioning module 130 organizes the vertex data into primitives and counts the primitives using a counter. The counter's count value is compared with the primitive partitioning rules sent by the configuration module 110. Primitives that belong to the current GPU core are sent to the geometry processing module, while primitives that do not belong to the current GPU core are discarded.

[0125] The context switching module 140 is used to perform context switching operations. When a higher-priority task arrives, the software triggers a context store operation. Upon receiving a context store request, the context switching module interrupts the current task and saves the current task's status information to memory. The command processing module 100 then begins executing the higher-priority task. After the execution is complete, the software triggers a context resume operation. The command processing module 100 loads back the current task's status information previously saved to memory and continues execution from the previously interrupted location.

[0126] It should be noted that when a higher-priority task arrives, the software will send a context store request to all GPU cores in the GPU Group. Because each GPU core executes tasks at different speeds, GPU cores that have already completed their tasks will not respond to context store requests, meaning no context switch will occur. For GPU cores that have not yet completed their current tasks, a context store operation will be performed, and the status information will be sent to the software. After the software waits for the higher-priority task to complete, it will trigger a context restore operation, allowing the GPU core that previously performed the context store operation to resume executing the current task from the interrupted position.

[0127] In order to facilitate understanding of the embodiments of the present application, the specific implementation methods will be described in detail below.

[0128] First, software can combine multiple GPU cores into a GPU Group based on the number and size of tasks. Multiple GPU cores within a GPU Group can execute geometry processing tasks in parallel. Each GPU core reads the same command sequence (including control commands and vertex data) from memory. The vertex data is then organized into a primitive sequence, and each GPU core performs geometry processing for a segment of that primitive sequence.

[0129] Specifically, the software writes the number of GPU cores in the current GPU Group, the ID of the current GPU core within the GPU Group, and the length of the primitive data block allocated to each GPU core (i.e., the number of primitives in a primitive data block) into the configuration module. Based on this information, the configuration module calculates the primitive data block required for execution by the current GPU core (i.e., the length of the corresponding primitive sequence).

[0130] For example, if there are three GPU cores forming a GPU Group, with GPU core IDs 0, 1, and 2, executing primitives K0, K1, and K2, respectively, then GPU core ID 0 needs to perform geometry processing on primitives numbered 0 to K0-1; GPU core ID 1 needs to perform geometry processing on primitives numbered K0 to K0+K1-1; and GPU core ID 2 needs to perform geometry processing on primitives numbered K0+K1 to K0+K1+K2-1.

[0131] The function of the command reading module is to read control commands and vertex data from the memory and send them to the primitive division module.

[0132] The primitive partitioning module receives control commands and vertex data from the command reading module. It extracts the primitive's topological type from the control command, sends the control command to the geometry processing module, and organizes the vertex data into a primitive sequence based on the primitive's topological type. The primitive partitioning module uses a counter to count primitives and, based on data from the configuration module, determines which primitives belong to the current GPU core. Primitives that belong to the current GPU core are sent to the geometry processing module, while the remaining primitives are discarded.

[0133] For example, if three GPU cores form a GPU Group, the GPU core IDs are 0, 1, and 2, and they execute K0, K1, and K2 primitives respectively. The counter counts cyclically from 0 to K0+K1+K2-1. For the GPU core with ID 0, the primitives with counter values ​​from 0 to K0-1 will be sent to the geometry processing module, and the remaining primitives will not be sent to the geometry processing module; for the GPU core with ID 1, the primitives with counter values ​​from K0 to K0+K1-1 will be sent to the geometry processing module, and the remaining primitives will not be sent to the geometry processing module. For the GPU core with ID 2, the primitives with counter values ​​from K0+K1 to K0+K1+K2-1 will be sent to the geometry processing module, and the remaining primitives will not be sent to the geometry processing module.

[0134] See also Figure 6, which shows a schematic diagram of a primitive sequence division rule. After the command reading module of each GPU core reads the control command and vertex data from the memory, it will send them to the primitive division module in the current core. The primitive division module will group the vertex data into primitives according to the primitive topology information. Figure 6 As shown, the vertex data received by the primitive division module is converted into a primitive sequence, such as primitive sequence 0, primitive sequence 1, and primitive sequence 2 in the figure. For the received control command, the relative position of the control instruction in the vertex data is the same as the relative position of the control instruction in the primitive, such as Figure 6 In the example, control instruction 0 precedes all primitives, and control instruction 1 is between the last primitive in primitive sequence 0 and the first primitive in primitive sequence 1. If the GPU core IDs are 0, 1, and 2, respectively, and they process K0, K1, and K2 primitives, the K0 primitives in primitive sequence 0 are processed by GPU core 0, the K1 primitives in primitive sequence 1 are processed by GPU core 1, and the K2 primitives in primitive sequence 2 are processed by GPU core 2. Furthermore, control instructions 0 and 1 are broadcast to all GPU cores.

[0135] The context switch module performs context switch operations, including context store and context restore. When a higher-priority task arrives, the software sends a context store request, triggering a context store operation. The GPU interrupts the currently executing task, saves the current state, and switches to executing the higher-priority task. When the higher-priority task completes, the software sends a context restore request, triggering a context restore operation. The GPU loads the previously saved state and resumes execution from the point where it was interrupted.

[0136] In some implementation scenarios, when multi-core GPUs perform parallel geometry processing, the software needs to send a context store request to all GPU cores in a GPU Group. Since multiple GPU cores perform parallel geometry processing at different speeds, it is possible that some GPU cores have completed execution while some GPU cores are still executing. When the context switch module of the GPU core receives a context store request, it first needs to determine whether the task of the current GPU core has been completed. If the task has been completed, it will not respond to the context store request. If the task is being executed, it will respond to the context store request, interrupt the current task, and save the status information. After these operations are completed, the software will be notified. During the context recovery phase, the software will only send a context recovery signal to the GPU core that has performed the context store operation. The context switch module of the GPU core that receives the context recovery signal will load back the previously saved status information, and the GPU core will continue execution from the previously interrupted position.

[0137] Based on the above embodiments, the present application can configure multiple GPU cores into one or more GPU Groups according to the number and size of tasks, and the GPU cores in each GPU Group execute the same task in parallel. When executing a large task, all GPU cores can be configured into one GPU Group. When executing multiple small tasks, multiple GPU Groups can be configured, and each GPU Group executes a small task, thereby maximizing the utilization of the GPU and the processing speed of the task. Taking into account that in some cases, the computing units of each GPU core are different, the embodiments of the present application support software configuration when a multi-core GPU executes geometric processing tasks in parallel, so that the GPU core with more computing units executes a larger block of graphic data, thereby achieving load balancing and improving the processing speed of the task. At the same time, the embodiments of the present application also support context switching operations of multi-core GPUs, which can quickly respond to higher priority tasks.

[0138] In some implementations, in addition to the number of primitives, other conditions may be added to the division rules of the primitive data block, for example, the primitive data block ends when the Draw-Call ends; the primitive data block ends when the task ends.

[0139] In some implementations, the configuration module may be combined with the primitive division module, and the software may directly set parameters in the primitive division module to divide the primitive data.

[0140] In some implementations, during a context restore operation, the software sends a context restore request to all GPU cores, but only the GPU core on which the context store operation occurred previously responds to the request and performs the context restore operation.

[0141] Based on the foregoing embodiments, an embodiment of the present application provides a geometry processing device, which includes the various units included and the various modules included in each unit, and can be implemented by a processor in a computer device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0142] Figure 7 A schematic diagram of the structure of a geometric processing device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the geometry processing device 700 includes: a configuration module 710 and an execution module 720, wherein:

[0143] A configuration module 710 is configured to configure multiple GPU cores into one or more core groups based on the number and size of tasks;

[0144] The execution module 720 is configured to execute the geometry processing tasks corresponding to a core group in parallel through the cores in the core group; wherein a core group includes one or more cores, and a core group executes one geometry processing task.

[0145] In some embodiments, the one or more core groups perform different geometry processing tasks in parallel.

[0146] In some embodiments, the execution module 720 is further used to: determine a task division rule based on the number of cores in a core group, the computing performance of each core in the core group, and the amount of geometric processing tasks to be processed by the core group, wherein the task division rule is used to indicate the subtasks to be processed by each core in the core group; and according to the task division rule, perform geometric processing on the corresponding subtasks through each core in the core group.

[0147] In some embodiments, the computing performance includes the task threshold of the core; the task division rule includes the data range of the subtask corresponding to each core in the core group; the execution module 720 is also used to: divide the task amount of the geometric processing task to be processed by the core group based on the task threshold of each core and the number of cores in the core group, and obtain the data range of the subtask corresponding to each core.

[0148] In some embodiments, the task division rule includes the primitive range of the subtask corresponding to each core in the core group; the execution module 720 is also used to: determine whether the received primitive belongs to the primitive range corresponding to the subtask through each core in the core group; process the primitives belonging to the primitive range of the subtask through each core in the core group, and discard the primitives that do not belong to the primitive range of the subtask.

[0149] In some embodiments, the primitives have an order, and the primitive range is a primitive count range; the execution module 720 is also used to: count the received primitives through the core to obtain a count value for each primitive; and determine whether the count value belongs to the primitive count range corresponding to the subtask.

[0150] In some embodiments, the geometry processing task includes performing geometry processing in units of primitives; the execution module 720 is further used to: receive control commands and vertex data corresponding to the geometry processing task through the core group; and convert the vertex data into primitives in sequence based on the control commands through each core in the core group.

[0151] In some embodiments, the execution module 720 is further configured to extract the topology type of the primitive from the control instruction, and convert the corresponding vertex data into the primitive based on the topology type.

[0152] In some embodiments, the execution module 720 is further used to: in the process of executing the geometry processing task corresponding to the core group in parallel through the cores in the core group, in response to receiving a target task with a higher priority than the geometry processing task, interrupt the geometry processing task and save the processing status information of the geometry processing task; execute the target task in parallel through the cores in the core group; in response to completion of execution of the target task, resume execution of the geometry processing task based on the processing status information of the geometry processing task.

[0153] In some embodiments, the processing status information includes sub-status information of the core; the execution module 720 is further used to: obtain sub-status information corresponding to each of the cores; and resume execution of the geometry processing task based on the sub-status information corresponding to each of the cores.

[0154] In some embodiments, the execution module 720 is further used to: obtain the processing status of each core in the core group for the geometric processing task; the processing status represents the processing progress of the core for the corresponding subtask; when the processing status of the core for the geometric processing task represents that the core has completed the geometric processing of the corresponding subtask, the sub-state information of the core is not saved; when the processing status of the core for the geometric processing task represents that the core has not completed the geometric processing of the corresponding subtask, the sub-state information of the core is saved.

[0155] The description of the above device embodiment is similar to the description of the above method embodiment and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the device provided in the embodiments of the present application can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0156] It should be noted that, in the embodiment of the present application, if the above-mentioned geometric processing method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0157] An embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0158] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above method. The computer-readable storage medium may be transient or non-transient.

[0159] An embodiment of the present application provides a computer program, including computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0160] An embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, implements some or all of the steps in the above method. The computer program product can be implemented specifically by hardware, software, or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium. In other embodiments, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0161] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between the various embodiments, and their similarities or similarities can be referenced to each other. The descriptions of the above device, storage medium, computer program, and computer program product embodiments are similar to the descriptions of the above method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the description of the method embodiments of this application for understanding.

[0162] Figure 8 A hardware entity diagram of a computer device provided in an embodiment of the present application is shown as follows: Figure 8 As shown, the hardware entity of the computer device 800 includes: a processor 801 and a memory 802, wherein the memory 802 stores a computer program that can be run on the processor 801, and the processor 801 implements the steps of the method of any of the above embodiments when executing the program.

[0163] The memory 802 stores computer programs that can be run on the processor. The memory 802 is configured to store instructions and applications executable by the processor 801. It can also cache data to be processed or processed by the processor 801 and various modules in the computer device 800 (for example, image data, audio data, voice communication data, and video communication data). This can be implemented through flash memory (FLASH) or random access memory (RAM).

[0164] When the processor 801 executes the program, the steps of any of the above-mentioned geometry processing methods are implemented. The processor 801 generally controls the overall operation of the computer device 800.

[0165] An embodiment of the present application provides a computer storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the geometric processing method of any of the above embodiments.

[0166] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0167] The processor may be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device that implements the functions of the processor may also be other electronic devices, which are not specifically limited in the embodiments of the present application.

[0168] The above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0169] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0170] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0171] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0172] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0173] In addition, the functional units in the embodiments of the present application can all be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the above-mentioned integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units. It can be understood by ordinary technicians in this field that all or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions, and the above-mentioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiments; and the above-mentioned storage medium includes: various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), magnetic disks or optical disks.

[0174] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0175] The above is only an implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A geometric processing method, characterized in that: Applied to a multi-GPU core system, the method includes: configuring the multiple GPU cores into one or more core groups based on the number and size of tasks, wherein the multiple core groups execute different geometry processing tasks in parallel; Determining a task partitioning rule based on the number of cores in the core group, the computing performance of each core in the core group, and the amount of geometry processing tasks to be processed by the core group, wherein the task partitioning rule is used to indicate the subtask to be processed by each core in the core group; According to the task division rule, each core in the core group performs geometric processing on the corresponding subtask; Different core groups may include the same or different numbers of cores, a core group may include one or more cores, and a core group may execute one geometry processing task.

2. The method according to claim 1, characterized in that The computing performance includes the task threshold of the core; the task division rule includes the data range of the subtask corresponding to each core in the core group; The determining of the task partitioning rule based on the number of cores in the core group, the computing performance of each core in the core group, and the amount of geometry processing tasks to be processed by the core group includes: Based on the task threshold of each core and the number of cores in the core group, the task amount of the geometry processing task to be processed by the core group is divided to obtain the data range of the subtask corresponding to each core.

3. The method according to claim 1, characterized in that The task division rule includes a primitive range of a subtask corresponding to each core in the core group; and performing geometric processing on the corresponding subtask by each core in the core group according to the task division rule includes: Determining whether the received primitive belongs to the primitive range corresponding to the subtask by each core in the core group; The primitives belonging to the primitive range of the subtask are processed by each core in the core group, and the primitives not belonging to the primitive range of the subtask are discarded.

4. The method according to claim 3, characterized in that The primitives have an order, the primitive range is a primitive counting range; and the determining, by each core in the core group, whether the received primitive belongs to the primitive range corresponding to the subtask includes: Counting the received primitives by the core to obtain a count value of each primitive; It is determined whether the count value belongs to the primitive count range corresponding to the subtask.

5. The method according to any one of claims 1 to 4, characterized in that The geometry processing task includes performing geometry processing on a primitive basis; the method further includes: receiving, through the core group, control commands and vertex data corresponding to the geometry processing task; The vertex data are converted into primitives in sequence by each core in the core group based on the control command.

6. The method according to claim 5, characterized in that The converting the vertex data into primitives in sequence based on the control command by each core in the core group includes: The topology type of the primitive is extracted from the control command, and the corresponding vertex data is converted into the primitive based on the topology type.

7. The method according to any one of claims 1 to 4, characterized in that The method further comprises: During the parallel execution of the geometry processing tasks corresponding to the core group by the cores in the core group, in response to receiving a target task having a higher priority than the geometry processing task, interrupting the geometry processing task and saving processing state information of the geometry processing task; Execute the target task in parallel through the cores in the core group; In response to completion of execution of the target task, the geometry processing task is resumed based on the processing status information of the geometry processing task.

8. The method according to claim 7, characterized in that The processing state information includes sub-state information of the core; and resuming execution of the geometry processing task based on the processing state information of the geometry processing task includes: Obtaining sub-state information corresponding to each of the cores; The geometry processing task is resumed based on the sub-state information corresponding to each of the cores.

9. The method according to claim 7, characterized in that The interrupting the geometry processing task and saving the processing status information of the geometry processing task includes: Obtaining a processing status of each core in the core group on the geometry processing task; the processing status represents a processing progress of the core on the corresponding subtask; In a case where the processing state of the core for the geometry processing task indicates that the core has completed geometry processing of the corresponding subtask, not saving the substate information of the core; In a case where the processing state of the core on the geometry processing task indicates that the core has not completed geometry processing of the corresponding subtask, substate information of the core is saved.

10. A geometry processing device, characterized in that: The device comprises: a configuration module, configured to configure the multiple GPU cores into one or more core groups according to the number and size of tasks, wherein the multiple core groups execute different geometry processing tasks in parallel; an execution module, configured to determine a task partitioning rule based on the number of cores in a core group, the computing performance of each core in the core group, and the amount of geometry processing tasks to be processed by the core group, wherein the task partitioning rule indicates a subtask to be processed by each core in the core group; and perform geometry processing on the corresponding subtask by each core in the core group according to the task partitioning rule; Different core groups may include the same or different numbers of cores, a core group may include one or more cores, and a core group may execute one geometry processing task.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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