A power supply circuit

Abstract

The present invention relates to the field of communication technology, and discloses a power supply circuit, in which a boost module boosts the voltage of a communication bus to supply power to a chip internal module, thereby solving the problem of insufficient internal voltage margin under low voltage, reducing the design difficulty, and eliminating the need for an external energy storage capacitor, saving costs. At the same time, the boost module power adaptive technology eliminates the need for a power detection module, thereby solving the problem of power consumption waste caused by the response speed of the power detection module.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a power supply circuit. Background Art

[0002] The existing 1WI slave chip can support Class C low-voltage operation, but due to insufficient voltage margin, an external capacitor is required to provide power for the slave chip during the low-level period of single-line communication. At the same time, the chip also requires ultra-low power design, which increases the chip cost and the difficulty of chip design. In addition, the 1WI power detection module is required to provide level detection to control the clock circuit to be turned off during the low-level period of communication and turned on during the high-level period. Since the power detection requires reaction time, the clock circuit cannot be turned off in time, resulting in problems such as the inability to control power consumption at the lowest state. Summary of the invention

[0003] In view of this, the present invention provides a power supply circuit to solve the problem that an external capacitor is needed to provide power to a slave chip during a low level period of single-line communication due to insufficient voltage margin.

[0004] The present invention provides a power supply circuit, which is integrated in a chip. The power supply circuit includes: a pre-charging module, a boosting module, a reference module, a voltage regulator module and an energy storage module, wherein the pre-charging module, a first end of which takes energy from a communication bus, and a second end of which is connected to a first end of the reference module; the chip transmits data with other devices via the communication bus; the boosting module, a first end of which is connected to the communication bus, a second end of which is connected to a second end of the reference module, a third end of which is connected to a first end of the reference module, a first end of the energy storage module and a first end of the voltage regulator module; the voltage regulator module, a second end of which is connected to a second end of the reference module, a third end of which outputs a power supply voltage, and a fourth end of which is connected to the communication bus. The chip is connected by a line, and the power supply voltage is used to power various modules inside the chip; the energy storage module, the second end of which is grounded; when the chip is in a receiving state and the communication bus receives a high level, the pre-charging module pre-charges the reference module, and the reference module outputs a reference voltage, and the boost module boosts the reference voltage to a preset voltage, and the preset voltage enables the voltage regulator module to charge the energy storage module, and the voltage regulator module outputs a power supply voltage based on the reference voltage; when the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the boost module no longer boosts the reference voltage, the energy storage module is a reference module and a voltage regulator module, and the voltage regulator module outputs a power supply voltage based on the reference voltage.

[0005] The present invention boosts the voltage of the communication bus to power the internal modules of the chip, thereby solving the problem of insufficient internal voltage margin under low voltage and reducing the design difficulty; no external energy storage capacitor is required, saving costs; at the same time, the boost module power adaptive technology does not require a power detection module, solving the problem of power consumption waste caused by the response speed of the power detection module.

[0006] In some optional embodiments, the pre-charging module includes: at least one first switch branch, wherein the first end of each first switch branch draws energy from the communication bus, and the second end of each first switch branch is connected to the first end of the reference module; by controlling the number of first switch branches put into operation, the charging speed of the pre-charging of the reference module is controlled.

[0007] In some optional implementations, each switch branch includes: a power electronic switch device.

[0008] In some optional embodiments, the boost module includes: a clock circuit, at least one boost sub-circuit, and a voltage detection circuit, wherein the clock circuit has a first end connected to the communication bus, and a second end and a third end connected to the control end and the control end of the boost sub-circuit, respectively; the first end of all the boost sub-circuits connected in series is connected to the second end of the reference module, and the second end of all the boost sub-circuits connected in series is connected to the first end of the reference module, the first end of the energy storage module, and the first end of the voltage regulator module; the voltage detection circuit has a first end connected to the second end of all the boost sub-circuits connected in series, and a second end connected to the enable end of the clock circuit; when the chip is in a receiving state and the communication bus receives a high level, the clock circuit outputs a clock signal to the boost sub-circuit, and all the boost sub-circuits perform multi-stage boosting on the reference voltage. When the voltage detection circuit detects that the voltage is boosted to a preset voltage, it sends a stop boosting signal, and the clock circuit controls the boost sub-circuit to stop boosting after receiving the stop boosting signal; when the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the clock circuit does not output a clock signal to the boost sub-circuit.

[0009] The clock circuit inside the boost module of the present invention can adapt to different states of the communication bus and the chip, and does not require a power detection module, thereby solving the problem of power consumption waste caused by the response speed of the power detection module.

[0010] In some optional embodiments, the boost subcircuit includes a boost pump.

[0011] In some optional embodiments, the boost module further includes: a filter circuit, a first end of which is connected to the second end of all the boost sub-circuits connected in series, and a second end of which is grounded.

[0012] In some optional implementations, the filtering circuit includes: a filtering capacitor.

[0013] In some optional embodiments, the voltage regulator module includes: a driving circuit, a second switch branch, a first pull-down resistor and a second pull-down resistor, wherein the driving circuit has a first end connected to the third end of the boost module and the first end of the energy storage module, a second end connected to the second end of the reference module, and a third end connected to the control end of the second switch branch; the second switch branch has a first end connected to the communication bus, a second end connected to the first end of the first pull-down resistor, and the second end also outputs the supply voltage; the first pull-down resistor has a second end connected to the fourth end of the driving circuit, and the second end is also connected to the control end of the second switch branch. The second pull-down resistor is grounded; when the chip is in a receiving state and the communication bus receives a high level, the boost module outputs a preset voltage, the preset voltage enables the drive circuit, and after the drive circuit drives the second switch branch to turn on, the second switch branch outputs a supply voltage; when the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the energy storage module supplies power to the reference module and the drive circuit, and after the drive circuit drives the second switch branch to turn on, the second switch branch outputs a supply voltage; the drive circuit is also used to maintain a stable supply voltage based on the second end voltage of the first pull-down resistor.

[0014] In some optional embodiments, the driving circuit includes: an operational amplifier, whose power supply terminal is connected to the third terminal of the boost module and the first terminal of the energy storage module, whose in-phase input terminal is connected to the second terminal of the reference module, whose inverting input terminal is connected to the second terminal of the first pull-down resistor, and whose output terminal is connected to the control terminal of the second switch branch.

[0015] In some optional implementations, the second switch branch includes: an NMOS tube.

[0016] In some optional embodiments, the energy storage module includes: an energy storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a structural block diagram of a power supply circuit according to an embodiment of the present invention;

[0019] Figure 2 is a chip system structure diagram according to an embodiment of the present invention;

[0020] Figure 3 is a structural block diagram of another power supply circuit according to an embodiment of the present invention;

[0021] Figure 4 is a specific circuit structure diagram of a pre-charging module according to an embodiment of the present invention;

[0022] Figure 5 is a structural block diagram of another power supply circuit according to an embodiment of the present invention;

[0023] Figure 6 is a specific circuit structure diagram of a boost module according to an embodiment of the present invention;

[0024] Figure 7 is a structural block diagram of another power supply circuit according to an embodiment of the present invention;

[0025] Figure 8 4 is a specific circuit structure diagram of a voltage regulator module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] In this embodiment, a power supply circuit is provided, and the power supply circuit is integrated in a chip, such as Figure 1 As shown, the power supply circuit includes: a pre-charging module 1 , a boost module 2 , a reference module 3 , a voltage regulator module 4 and an energy storage module 5 .

[0031] like Figure 1 As shown, the pre-charging module 1 has a first end that obtains energy from the communication bus, and a second end that is connected to the first end of the reference module 3; the chip transmits data with other devices via the communication bus.

[0032] Specifically, Figure 2 As shown, the two chips are connected through a 1WI line, which can be used for both power supply and signal transmission between the master chip and the slave chip. The pre-charging module 1 of the present application obtains energy from 1WI and uses the obtained power to power the reference module 3.

[0033] like Figure 1 As shown, the boost module 2 has a first end connected to the communication bus, a second end connected to the second end of the reference module 3, and a third end connected to the first end of the reference module 3, the first end of the energy storage module 5, and the first end of the voltage regulator module 4.

[0034] Specifically, the slave chip draws power from the 1WI line used for communication with the master chip. During data transmission between the two chips, the slave chip may be in a receiving state or a sending state. When the slave chip is in a receiving state and the 1WI bus receives a high level, the high level voltage is not sufficient to support the power supply of the slave chip. Therefore, the high level voltage is increased to a preset voltage by setting a boost module 2. The preset voltage is not only used for power supply, but also can power the energy storage module 5. When the slave chip is in a receiving state and the 1WI bus receives a low level, or when the slave chip is in a sending state, the energy storage module 5 powers the slave chip.

[0035] like Figure 1 As shown, the voltage regulator module 4 has a second end connected to the second end of the reference module 3, a third end outputting a power supply voltage VDD, and a fourth end connected to the communication bus. The power supply voltage VDD is used to power each module inside the chip. The energy storage module 5 has a second end connected to ground.

[0036] Specifically, when the chip is in a receiving state and the communication bus receives a high level, the pre-charging module 1 pre-charges the reference module 3, and the reference module 3 outputs a reference voltage VREF. After the boost module 2 boosts the reference voltage VREF to a preset voltage VMP, the preset voltage VMP enables the voltage regulator module 4 and charges the energy storage module 5. The voltage regulator module 4 outputs a power supply voltage VDD based on the reference voltage VREF. When the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the boost module 2 no longer boosts the reference voltage VREF, the energy storage module 5 is the reference module 3 and the voltage regulator module 4, and the voltage regulator module 4 outputs a power supply voltage VDD based on the reference voltage VREF.

[0037] In an optional embodiment, if Figure 3 As shown, the pre-charging module 1 includes: at least one first switch branch 11, wherein the first end of each first switch branch 11 draws energy from the communication bus, and the second end of each first switch branch 11 is connected to the first end of the reference module 3; by controlling the number of first switch branches 11 put into operation, the charging speed of pre-charging the reference module 3 is controlled.

[0038] Specifically, a plurality of first switch branches 11 connected in parallel are arranged inside the pre-charging module 1. When the first switch branch 11 is turned on, the 1WI bus voltage pre-charges the reference module 3, and the charging speed is controlled by controlling the number of the first switch branches 11. For example, when a large number of first switch branches 11 are put into use, the charging speed is fast.

[0039] Optionally, each switch branch includes: a power electronic switch device. Exemplarily, Figure 4 Taking the two first switch branches 11 as an example, the two first switch branches 11 include power electronic switch devices MY1 and MY2 respectively, wherein the charging speed when only one of MY1 and MY2 is put into operation is lower than the charging speed when both MY1 and MY2 are put into operation at the same time.

[0040] In an optional embodiment, if Figure 5 As shown, the boost module 2 includes: a clock circuit 21 , at least one boost sub-circuit 22 , and a voltage detection circuit 23 .

[0041] like Figure 5 As shown, the clock circuit 21 has a first end connected to the communication bus, and a second end and a third end connected to the control end and the control end of the boost sub-circuit 22 respectively.

[0042] Specifically, the clock circuit 21 is controlled by the communication bus and the voltage detection circuit 23. When the slave chip is in a receiving state and the communication bus receives a high level, the clock circuit 21 outputs a clock signal to each boost sub-circuit 22; when the slave chip is in a receiving state and the communication bus receives a low level, or when the slave chip is in a sending state, the clock circuit 21 automatically stops and the boost module 2 is turned off, thereby reducing system power consumption and discharging the energy storage module 5.

[0043] like Figure 5 As shown, the first end of all the boost sub-circuits 22 connected in series is connected to the second end of the reference module 3, and the second end of all the boost sub-circuits 22 connected in series is connected to the first end of the reference module 3, the first end of the energy storage module 5, and the first end of the voltage regulator module 4. Specifically, the multiple boost sub-circuits 22 perform multi-stage boosting on the reference voltage VREF and then transmit it to the voltage regulator module 4 and the energy storage module 5.

[0044] like Figure 5 As shown, the voltage detection circuit 23 has a first end connected to the second end of all the boost sub-circuits 22 connected in series, and a second end connected to the enable end of the clock circuit 21; specifically, the boost module 2 will not raise the reference voltage VREF indefinitely, and when the voltage detection circuit 23 detects that the voltage rises to the preset voltage VMP, the clock circuit 21 is no longer enabled in time, so that the clock circuit 21 no longer sends a clock signal to the boost sub-circuit 22, and the boost module 2 is turned off.

[0045] Optionally, the voltage detection circuit 23 may be a voltage monitor VD, but this is only an example and is not intended to be limiting.

[0046] Specifically, when the chip is in the receiving state and the communication bus receives a high level, the clock circuit 21 outputs a clock signal to the boost sub-circuit 22, and all the boost sub-circuits 22 perform multi-stage boosting on the reference voltage VREF. When the voltage detection circuit 23 detects that the voltage is boosted to the preset voltage VMP, it sends a stop boosting signal. After receiving the stop boosting signal, the clock circuit 21 controls the boost sub-circuit 22 to stop boosting. When the chip is in the receiving state and the communication bus receives a low level, or when the chip is in the sending state, the clock circuit 21 does not output a clock signal to the boost sub-circuit 22.

[0047] Optionally, the boost subcircuit 22 includes a boost pump. The boost pump structure is as follows: Figure 6 As shown, the boost pump includes: transistors M1, M2, M3, M4, capacitors C1, C2, wherein the boost amplitude can be controlled by controlling the duty cycle of the transistors.

[0048] It should be noted that the boost circuit of this embodiment is not limited to Figure 6The structure shown may also be other circuits with the same boosting function, such as a Boost circuit, etc. This is only an example and is not intended to be limiting.

[0049] In an optional implementation, the boost module 2 further includes: a filter circuit, a first end of which is connected to the second end of all the boost sub-circuits 22 connected in series, and a second end of which is grounded. Figure 6 As shown, the filter circuit includes: a filter capacitor C3.

[0050] On the basis of the above structure, the boost module 2 may further include a voltage stabilizing circuit, and the voltage stabilizing circuit may include a voltage stabilizing tube to achieve the stabilization of the output voltage.

[0051] In an optional embodiment, if Figure 7 As shown, the voltage regulator module 4 includes: a driving circuit 41, a second switch branch 42, a first pull-down resistor R1 and a second pull-down resistor R2.

[0052] like Figure 7 As shown, the first end of the driving circuit 41 is connected to the third end of the boost module 2 and the first end of the energy storage module 5, the second end is connected to the second end of the reference module 3, and the third end is connected to the control end of the second switch branch 42. The second switch branch 42 is connected to the communication bus at the first end, connected to the first end of the first pull-down resistor R1 at the second end, and outputs the power supply voltage VDD; the first pull-down resistor R1 is connected to the fourth end of the driving circuit 41 at the second end, and grounded through the second pull-down resistor R2 at the second end.

[0053] Specifically, when the chip is in a receiving state and the communication bus receives a high level, the boost module 2 outputs a preset voltage VMP, and the preset voltage VMP enables the drive circuit 41. After the drive circuit 41 drives the second switch branch 42 to turn on, the second switch branch 42 outputs the power supply voltage VDD; when the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the energy storage module 5 supplies power to the reference module 3 and the drive circuit 41. After the drive circuit 41 drives the second switch branch 42 to turn on, the second switch branch 42 outputs the power supply voltage VDD.

[0054] Specifically, when the chip is in a receiving state and the communication bus receives a high level, the boost module 2 outputs a preset voltage VMP, and the preset voltage VMP enables the drive circuit 41; when the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the energy storage module 5 is the reference module 3 and the drive circuit 41, wherein, whether the boost module 2 directly enables the drive circuit 41 or the energy storage module 5 is enabled, the voltages output by both are greater than the 1WI bus voltage, thereby ensuring that even in the low-voltage state of the 1WI bus, the second switch branch 42 can still be reliably turned on.

[0055] Specifically, the driving circuit 41 is also used to maintain the stability of the power supply voltage VDD based on the second terminal voltage of the first pull-down resistor R1. The driving circuit 41 collects the output voltage through the first pull-down resistor R1 and the second pull-down resistor R2, and adjusts the control terminal voltage of the second switch branch 42 according to the output voltage amplitude to achieve output voltage stability.

[0056] In an optional embodiment, if Figure 8 As shown, the driving circuit 41 includes: an operational amplifier OPA, whose power supply terminal is connected to the third terminal of the boost module 2 and the first terminal of the energy storage module 5, whose in-phase input terminal is connected to the second terminal of the reference module 3, whose inverting input terminal is connected to the second terminal of the first pull-down resistor R1, and whose output terminal is connected to the control terminal of the second switch branch 42. The operational amplifier OPA compares the reference voltage VREF with the output voltage, and adjusts the voltage level of the control terminal of the second switch branch 42 according to the comparison result, so as to adjust the duty cycle of the second switch branch 42.

[0057] In an optional embodiment, if Figure 8 As shown, the second switch branch 42 includes an NMOS tube, and the output voltage is maintained constant by adjusting the duty cycle of the NMOS tube.

[0058] In an optional implementation, the energy storage module 5 includes: an energy storage capacitor, but this is only an example and is not intended to be limiting.

[0059] For example, in combination Figures 1 to 8 The power supply circuit of this embodiment has the following states:

[0060] (1) The connection line between the pre-charging module 1 and the reference module 3 is pre-charged so that it has an initial voltage VM (VM≤1WI voltage high level) to meet the working conditions of the reference module 3. The reference module 3 outputs a reference voltage VREFVREF.

[0061] (2) After the reference module 3 works, the boost module 2 uses the reference as a reference to increase the reference voltage VREF to VMP (VMP = n times VREF, VMP is much greater than 1WI high level). VMP is required to meet the operation of the voltage regulator and other modules and fully charge the energy storage module 5; the voltage regulator module 4 starts to work under the action of VREF and VMP and outputs a stable logic power supply VDD.

[0062] (3) Communication status, 1WI port will receive and transmit "0" and "1".

[0063] ① When receiving "1", the boost module 2 outputs the preset voltage VMP and fully charges the energy storage module 5; the transceiver module inside the chip demodulates the 1WI signal "1" and transmits it to the logic module for processing.

[0064] ② After 1WI becomes "0", the power supply of the clock circuit 21 of the boost module 2 becomes 0, the clock output of the clock circuit 21 stops automatically, and the boost module 2 outputs VMP in a holding state. The charge consumption of the chip is provided by the energy storage module 5 under VMP. The transceiver module demodulates the 1WI signal "0" and transmits it to the logic module for processing.

[0065] Taking the energy storage module 5 as an energy storage capacitor as an example, the voltage on the energy storage capacitor in the prior art can only be 1WI high level, while the voltage on the energy storage capacitor in this embodiment is VMP, which is much larger than the 1WI voltage. In this way, under the same capacitance size, the energy stored in the energy storage capacitor is much larger than the prior art, so that the capacitor can be made smaller and placed inside the chip; at the same time, the clock circuit 21 automatically stops the clock, and after the boost module 2 stops working, the internal power consumption of the chip is reduced to a minimum, and VMP maintains the normal operation of the internal module.

[0066] ③ The main chip enters the input state, and the chip power supply mode changes from the main chip power supply to the pull-up resistor Rup power supply; when sending "1", it relies on the internal energy storage capacitor to power the internal. The logic module sends "1" to the transceiver module, and the transceiver module sends "1" to the main chip.

[0067] ④The main chip is still in input state, and the chip is powered by the internal energy storage capacitor. The logic module sends "0" to the transceiver module, and the transceiver module sends "0" to the main chip.

[0068] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A power supply circuit, characterized in that: The power supply circuit is integrated in the chip, and includes: a pre-charging module, a boost module, a reference module, a voltage regulator module and an energy storage module, wherein: A pre-charging module, a first end of which takes energy from a communication bus, and a second end of which is connected to a first end of the reference module; the chip performs data transmission with other devices via the communication bus; A boost module, a first end of which is connected to the communication bus, a second end of which is connected to the second end of the reference module, and a third end of which is connected to the first end of the energy storage module, the first end of the reference module, and the first end of the voltage regulator module; a voltage regulator module, a second end of which is connected to the second end of the reference module, a third end of which outputs a power supply voltage, and a fourth end of which is connected to the communication bus, wherein the power supply voltage is used to supply power to each module inside the chip; The energy storage module has a second end grounded; When the chip is in a receiving state and the communication bus receives a high level, after the pre-charging module pre-charges the reference module, the reference module outputs a reference voltage, and after the boost module boosts the reference voltage to a preset voltage, the preset voltage enables the voltage regulator module to charge the energy storage module, and the voltage regulator module outputs the supply voltage based on the reference voltage; When the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the boost module no longer boosts the reference voltage, the energy storage module supplies power to the reference module and the voltage regulator module, and the voltage regulator module outputs the supply voltage based on the reference voltage.

2. The power supply circuit according to claim 1, characterized in that: The pre-charging module comprises: at least one first switch branch, wherein: The first end of each of the first switch branches obtains energy from the communication bus, and the second end of each of the first switch branches is connected to the first end of the reference module; The charging speed of precharging the reference module is controlled by controlling the number of the first switch branches that are switched on.

3. The power supply circuit according to claim 2, characterized in that: Each of the switch branches includes: a power electronic switch device.

4. The power supply circuit according to claim 1, characterized in that: The boost module includes: a clock circuit, at least one boost sub-circuit, and a voltage detection circuit, wherein: A clock circuit, a first end of which is connected to the communication bus, and a second end and a third end of which are connected to the control end and the control end of the boost subcircuit respectively; The first end of all the boost subcircuits connected in series is connected to the second end of the reference module, and the second end of all the boost subcircuits connected in series is connected to the first end of the reference module, the first end of the energy storage module, and the first end of the voltage regulator module; A voltage detection circuit, a first end of which is connected to the second end of all the boost sub-circuits connected in series, and a second end of which is connected to the enable end of the clock circuit; When the chip is in a receiving state and the communication bus receives a high level, the clock circuit outputs a clock signal to the boost subcircuit, and all the boost subcircuits perform multi-stage boosting on the reference voltage. When the voltage detection circuit detects that the voltage has been boosted to a preset voltage, it sends a stop boosting signal. After receiving the stop boosting signal, the clock circuit controls the boost subcircuit to stop boosting. When the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the clock circuit does not output a clock signal to the boost sub-circuit.

5. The power supply circuit according to claim 4, characterized in that: The boost subcircuit includes a boost pump.

6. The power supply circuit according to claim 4, characterized in that: The boost module further comprises: The filter circuit has a first end connected to the second end of all the boost sub-circuits connected in series, and a second end grounded.

7. The power supply circuit according to claim 6, characterized in that: The filter circuit includes: a filter capacitor.

8. The power supply circuit according to claim 1, characterized in that: The voltage regulator module includes: a driving circuit, a second switch branch, a first pull-down resistor and a second pull-down resistor, wherein: a driving circuit, wherein a first end of the driving circuit is connected to the third end of the boost module and the first end of the energy storage module, a second end of the driving circuit is connected to the second end of the reference module, and a third end of the driving circuit is connected to the control end of the second switch branch; A second switch branch, a first end of which is connected to the communication bus, a second end of which is connected to the first end of the first pull-down resistor, and the second end also outputs a supply voltage; a first pull-down resistor, a second end of which is connected to the fourth end of the driving circuit, and a second end of which is also grounded through the second pull-down resistor; When the chip is in a receiving state and the communication bus receives a high level, the boost module outputs a preset voltage, the preset voltage enables the drive circuit, and after the drive circuit drives the second switch branch to turn on, the second switch branch outputs a supply voltage; When the chip is in a receiving state and the communication bus receives a low level, or when the chip is in a sending state, the energy storage module supplies power to the reference module and the drive circuit, and after the drive circuit drives the second switch branch to turn on, the second switch branch outputs a power supply voltage; The driving circuit is further configured to maintain the supply voltage stable based on the voltage at the second end of the first pull-down resistor.

9. The power supply circuit according to claim 8, characterized in that: The driving circuit comprises: An operational amplifier, wherein a power supply end thereof is connected to the third end of the boost module and the first end of the energy storage module, a non-inverting input end thereof is connected to the second end of the reference module, an inverting input end thereof is connected to the second end of the first pull-down resistor, and an output end thereof is connected to the control end of the second switch branch.

10. The power supply circuit according to claim 8, characterized in that: The second switch branch includes: an NMOS tube.

11. The power supply circuit according to claim 1, characterized in that: The energy storage module includes: an energy storage capacitor.

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