A base current compensation circuit for a BJT input stage of an LDO

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a base current compensation circuit for a BJT input stage of an LDO, which comprises a base current sampling circuit and a current operation circuit. OUT The base current sampling circuit comprises a BJT sampling circuit and a clamping circuit, an input end of the base current sampling circuit is connected with an output end V CO of the LDO, and an output end is connected with an input end of the current operation circuit, for generating a current related to the base current of the BJT input stage of the LDO; the current operation circuit converts a compensation current which is equal to the base current of the BJT input stage of the LDO, and outputs the compensation current through a V CO end. The application proposes a base current compensation circuit for a low-noise LDO using a BJT input stage, which eliminates the influence of the base current on the reference voltage without affecting the noise performance of the LDO, and improves the precision of the output voltage of the LDO.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a base current compensation circuit for a BJT input stage of an LDO. BACKGROUND

[0002] With the development of process and manufacturing technology, the feature size of chip manufacturing is continuously reduced, which brings faster speed and lower power supply voltage, and also makes the influence of noise on signals more significant. Compared with a switching converter, an LDO has the advantages of small size, low cost, small output ripple, low noise and high stability, and has been widely used in electronic systems. Especially in applications with high noise performance requirements, the noise of the LDO itself needs to be low enough to provide a relatively clean power supply voltage.

[0003] In a power management chip such as an LDO and a switching DC-DC converter, noise mainly comes from a reference, an error amplifier and a feedback resistor network. In order to reduce the noise of the LDO as much as possible, the main methods are to use unit gain negative feedback, current reference, BJT input stage error amplifier, etc. However, since the BJT has a base current, the current will be extracted from the reference current, so that the generated reference voltage is not accurate, thereby reducing the accuracy of the output voltage. SUMMARY

[0004] In view of the above problems, the application provides a BJT input stage base current compensation circuit for a high-precision and low-noise LDO, which aims to solve the influence of the BJT base current on the output accuracy in the low-noise LDO.

[0005] To achieve the above purpose, the application adopts the following technical scheme:

[0006] A BJT input stage base current compensation circuit for an LDO, comprising a base current sampling circuit and a current operation circuit.

[0007] The base current sampling circuit comprises a BJT sampling circuit and a clamping circuit, the input end of the base current sampling circuit is connected with the output end V OUT of the LDO, and the output end is connected with the input end of the current operation circuit. The BJT sampling circuit is matched with the BJT input stage of the LDO, and the V B end of the BJT sampling circuit and the V OUT end are clamped to the same level by the clamping circuit, so as to obtain an accurate current proportional to the base current of the BJT input stage;

[0008] The current operation circuit is used for proportional operation of the current to obtain a compensation current equal to the size of the base current of the BJT input stage, and the compensation current is output through the V CO end.

[0009] The base current compensation circuit described in this invention is suitable for low-noise LDOs using a BJT input stage and a current reference source. By using the base current compensation circuit, the output accuracy of the low-noise LDO circuit can be improved. A high-precision, low-noise LDO circuit with BJT input stage base current compensation includes a reference circuit, an LDO main loop, and a base current compensation circuit.

[0010] The reference circuit is used to generate a precise reference voltage V. REF This includes a reference current source and an external resistor R. REF With capacitor C REF The reference source generates a reference current I. B And this current is combined with the base compensation current I b After superposition, we get I B +I b The total output current. Of this, Ib flows into the BJT input stage of the error amplifier to compensate for the base current of its input transistors; IB flows through the off-chip resistor R. REF With capacitor C REF The RC filter network forms a reference voltage V. REF ;

[0011] The LDO main loop is used to generate a low-noise output voltage V. OUT This includes an error amplifier, a buffer stage, and a power transistor M. POWER Output capacitor C OUT Equivalent series resistance R ESR With load I LOAD The error amplifier includes a BJT input stage and a gain stage AMP. EA The input terminal of the BJT input stage is connected to the output terminal V via unity-gain negative feedback. OUT The other end is connected to the reference voltage V. REF Gain-stage AMP EA It provides higher loop gain to achieve higher output accuracy and better power supply rejection performance;

[0012] The base current compensation circuit is used to generate the base compensation current I of the BJT input stage. b The base current compensation circuit obtains the base current I of the BJT amplifier through a sampling transistor. b proportional 1 / k·I b And will contain 1 / k·I b The current is proportionally calculated through a current calculation circuit to obtain I, which is equal to the base current of the BJT amplifier. b And through V CO The output is sent to a reference current source to compensate for the base current.

[0013] The BJT input stage circuit comprises a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a first current source I B1 The upper end of the first resistor R1 is connected to a power supply VDD, and the lower end thereof is connected to the collector of the first transistor Q1 and the inverting input end of a gain stage AMP EA The upper end of the second resistor R2 is connected to the power supply VDD, and the lower end thereof is connected to the collector of the second transistor Q2 and the non-inverting input end of the gain stage AMP EA The base of the first transistor Q1 is connected to an output voltage terminal V OUT The emitter thereof is connected to the emitter of the second transistor Q2 and the upper end of the first current source I B1 The base of the second transistor Q2 is connected to a reference voltage terminal V REF The lower end of the first current source I B1 is connected to a ground GND;

[0014] The base current compensation circuit comprises a third resistor R3, a third transistor Q3, an operational amplifier AMP, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M 10 , a second current source I B2 , a third current source I B3 , a fourth current source I B4 , a fifth current source I B5 The upper end of the third resistor R3 is connected to a power supply VDD, and the lower end thereof is connected to the collector of the third transistor Q3; the base of the third transistor Q3 is connected to the non-inverting input end of the operational amplifier AMP, the drain of the third MOS transistor M3 and the upper end of the third current source I B3 The emitter thereof is connected to the upper end of the second current source IB2; the inverting input end of the operational amplifier AMP is connected to an LDO output terminal V OUT The output end thereof is connected to the gate of the third MOS transistor M3; the gate and the drain of the first MOS transistor M1 are short-circuited and connected to the source of the third MOS transistor M3, the source of the fourth MOS transistor M4 and the gate of the second MOS transistor M2, and the source thereof is connected to the power supply VDD; the source of the second MOS transistor M2 is connected to the power supply VDD, and the drain thereof is connected to the source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6; the gate of the fourth MOS transistor M4 is connected to the gate and the drain of the fifth MOS transistor M5 and the upper end of the fifth current source I B5 The drain thereof is connected to the gate of the sixth MOS transistor M6 and the upper end of the fourth current source I B4The upper end; the drain of the sixth MOSFET M6 is connected to the gate and drain of the seventh MOSFET M7 and the gate of the eighth MOSFET M8; the source of the seventh MOSFET M7 is connected to ground GND; the source of the eighth MOSFET M8 is connected to ground GND, and its drain is connected to the gate and drain of the ninth MOSFET M9 and the tenth MOSFET M10. 10 The gate of the ninth MOSFET M9 is connected to the power supply VDD; the source of the tenth MOSFET M... 10 Its source is connected to the power supply VDD, and its drain is connected to the reference current source circuit.

[0015] The beneficial effects of this invention are as follows: This invention proposes a BJT input stage base current compensation circuit for high-precision, low-noise LDOs. For low-noise LDOs that use BJT input stages and current source references, this invention eliminates the influence of the base current generated by the BJT as an input pair on the reference voltage without affecting its noise performance, thereby improving the accuracy of the LDO output voltage to a certain extent. Attached Figure Description

[0016] Figure 1 This is a block diagram of a BJT input stage base current compensation circuit for a high-precision, low-noise LDO proposed in this invention.

[0017] Figure 2 This is a system block diagram of a high-precision, low-noise LDO circuit with BJT input stage base current compensation proposed in this invention;

[0018] Figure 3 This is a circuit diagram of a high-precision, low-noise LDO circuit with BJT input stage base current compensation proposed in this invention.

[0019] Figure 4 This is a circuit diagram of a high-precision, low-noise LDO circuit with BJT input stage base current compensation proposed in this invention.

[0020] Figure 5 This is a comparison chart showing the output voltage of a high-precision, low-noise LDO circuit with BJT input stage base current compensation as a function of the BJT input stage bias current, with and without the base current compensation circuit proposed in this invention. Detailed Implementation

[0021] like Figure 1 As shown, this invention proposes a base current compensation circuit for the input stage of a BJT for a high-precision, low-noise LDO, including a base current sampling circuit and a current calculation circuit.

[0022] The base current sampling circuit is used to generate a current proportional to the BJT base current. It includes a BJT sampling circuit and a clamping circuit, and its input terminal is connected to the output terminal V of the LDO. OUT The output terminal is connected to the input terminal of the current calculation circuit. The BJT sampling circuit is matched to the BJT input stage of the LDO, and the clamping circuit clamps the V of the BJT sampling circuit. B End and V OUT The current is clamped to the same level, thus obtaining a precise current related to the base current of the BJT input stage.

[0023] The current calculation circuit is used to perform proportional calculations on the current to obtain a compensation current equal to the base current of the BJT input stage, and then transmits this compensation current through V. CO Terminal output;

[0024] like Figure 2 As shown, this invention proposes a high-precision, low-noise LDO circuit with BJT input stage base current compensation, which improves output accuracy by using the base current compensation circuit. The LDO circuit includes a reference circuit, an LDO main loop, and a base current compensation circuit. The overall architecture adopts a unity-gain negative feedback structure, eliminating the use of feedback resistors and thus eliminating the noise of the voltage divider resistor network in traditional LDOs.

[0025] The reference circuit is used to generate a precise reference current I. B This includes a reference current source and an external resistor R. REF With capacitor C REF An RC filter network composed of external resistors and capacitors can filter out high-frequency noise, effectively reducing the noise contributed by the reference circuit. The reference source generates a reference current I. B Then, with the base compensation current I b The superposition produces a current I. B +I b A portion flows into the base of the BJT in the error amplifier, i.e., the base current I of the BJT input stage. b A portion of the current flows through the external resistor R. REF With capacitor C REF The generated reference voltage V REF , can be represented as V REF =I B ·R REF .

[0026] The LDO main loop is used to generate a low-noise output voltage V. OUT This includes an error amplifier, a buffer stage, and a power transistor M. POWER Output capacitor C OUT Equivalent series resistance R ESR With load I LOADThe error amplifier adopts a BJT input amplification stage, thereby reducing the noise contributed by the error amplifier and obtaining a lower equivalent output voltage noise. The next stage amplifier of the BJT input stage provides a high loop gain, which is used to obtain a higher power supply rejection ratio and improve the precision of the output voltage. The buffer stage is used to split the error amplifier output pole into a higher frequency pole, thereby improving the stability of the loop.

[0027] The base current compensation circuit provided by the application is suitable for a low-noise LDO using a BJT input stage and a current reference source. The LDO of this structure has good noise performance, but the bias current of the BJT input stage is usually large, and the base current is also large, which will affect the reference voltage. The base current compensation circuit provided by the application can solve the above problems, thereby improving the precision of the output voltage. The circuit structure and connection relationship of each module are described below.

[0028] Figure 3 A BJT input stage circuit is given. The BJT input stage circuit includes a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a first current source I B1 ; the upper end of the first resistor R1 is connected to a power supply VDD, and the lower end is connected to the collector of the first transistor Q1 and the inverting input terminal of a gain stage AMP EA ; the upper end of the second resistor R2 is connected to the power supply VDD, and the lower end is connected to the collector of the second transistor Q2 and the non-inverting input terminal of the gain stage AMP EA ; the base of the first transistor Q1 is connected to an output voltage terminal V OUT , the emitter is connected to the emitter of the second transistor Q2 and the positive terminal of the first current source I B1 ; the base of the second transistor Q2 is connected to a reference voltage terminal V REF ; wherein the current amplification factor of Q1 and Q2 is β, and the base current I b can be represented as: I b1 = I b2 = I b = 1 / β·I B1 . The current of the current source I B1 can be represented as: I B1 = I BIAS When the bias current is large or the current amplification factor of the transistor is small, the base current will be large. In this case, compensation of the base current is particularly needed.

[0029] Figure 4An implementation of a base current compensation circuit is presented. This circuit includes a third resistor R3, a third transistor Q3, an operational amplifier AMP, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a tenth MOSFET M1. 10 Second current source I B2 Third current source I B3 Fourth current source I B4 Fifth current source I B5 The upper end of the third resistor R3 is connected to the power supply VDD, and its lower end is connected to the collector of the third transistor Q3; the base of the third transistor Q3 is connected to the non-inverting input of the operational amplifier AMP, the drain of the third MOSFET M3, and the third current source I. B3 The upper end of the amplifier is connected to the upper end of the second current source IB2; the inverting input of the operational amplifier AMP is connected to the output V of the LDO. OUT Its output terminal is connected to the gate of the third MOSFET M3; the gate and drain of the first MOSFET M1 are shorted and connected to the source of the third MOSFET M3, the source of the fourth MOSFET M4, and the gate of the second MOSFET M2, with its source connected to the power supply VDD; the source of the second MOSFET M2 is connected to the power supply VDD, and its drain is connected to the source of the fifth MOSFET M5 and the source of the sixth MOSFET M6; the gate of the fourth MOSFET M4 is connected to the gate and drain of the fifth MOSFET M5 and the fifth current source I. B5 At its upper end, its drain is connected to the gate of the sixth MOSFET M6 and the fourth current source I. B4 The upper end; the drain of the sixth MOSFET M6 is connected to the gate and drain of the seventh MOSFET M7 and the gate of the eighth MOSFET M8; the source of the seventh MOSFET M7 is connected to ground GND; the source of the eighth MOSFET M8 is connected to ground GND, and its drain is connected to the gate and drain of the ninth MOSFET M9 and the tenth MOSFET M10. 10 The gate of the ninth MOSFET M9 is connected to the power supply VDD; the source of the tenth MOSFET M... 10 The source is connected to the power supply VDD, and its drain is connected to the reference current source circuit.

[0030] Among them, transistor Q3 is matched with transistors Q1 and Q2 in the BJT amplifier stage, resistor R3 is matched with resistors R1 and R2, and current source I... B2 With current source I B1 The transistors Q1, Q2, and Q3 are matched. The current amplification factor is β, and the ratio of their emitter-junction area is k:k:1. The resistance ratio of resistors R1, R2, and R3 is 1:1:k. Current source I... B1 I B2The current ratio of the current source I, I and I is 2k:1.The operational amplifier AMP and the MOS tube M3 form a unit gain negative feedback loop, and the base potential of the transistor Q1 is clamped to the output voltage V OUT , that is, the base potential of the transistors Q1 and Q2.The base, emitter and collector potentials of the transistors Q1, Q2 and Q3 are equal respectively.The base current of the transistor Q3 can be expressed as: b3 =1 / β·I B2 =1 / β·1 / k·I B1 =1 / k·I b The MOS tubes M1 and M2 form a current mirror, and the currents flowing through the MOS tubes M2 and M3 can be expressed as: M1 =I M2 =I b3 +I B3 +I B4 The MOS tubes M4, M5 and M6 form a negative feedback loop, which clamps the source potential of M4 and M5, so that the current flowing through the MOS tubes M1 and M2 is more accurate.The width-length ratio of the MOS tubes M4 and M5 is 1:2, and the current ratio of the current sources I B3 , I B4 and I B5 is 1:1:2.The current flowing through the MOS tube M6 can be expressed as: M6 =I M2 -I M5 =I b3 +I B3 +I B4 -I B5 =I b3 =1 / k·I b The current is equal to the base current of the BJT amplification stage, and the current is sent to the reference current source circuit to realize the base current compensation.

[0031] Figure 5 The simulation results of the high-precision and low-noise LDO output voltage changing with the BJT input stage bias current with and without the base current compensation circuit are given.The figure only represents the simulation results under a certain simulation condition, and the structure proposed in the patent can still have the corresponding effect under the changed simulation condition and circuit parameters, so the changed simulation condition and circuit parameters are still within the protection scope of the application.

[0032] In summary, the application provides a BJT input stage base current compensation circuit for a high-precision and low-noise LDO.The low-noise LDO with a BJT input stage and a current source reference eliminates the influence of the base current generated by the BJT input on the reference voltage without affecting the noise performance, so that the precision of the LDO output voltage is improved.

Claims

1. A base current compensation circuit for the input stage of a BJT in an LDO, comprising a base current sampling circuit and a current calculation circuit, wherein the input terminal of the base current sampling circuit is connected to the output terminal V of the LDO. OUT The output terminal is connected to the input terminal of the current calculation circuit; The base current sampling circuit includes a BJT sampling circuit and a clamping circuit, wherein, The BJT sampling circuit is matched with the BJT input stage of the LDO, and the clamping circuit clamps the output V of the BJT sampling circuit. B With V OUT Clamped to the same level, thereby obtaining a precise current that is proportional to the base current of the BJT input stage; The current calculation circuit is used to perform proportional calculation on the current output by the base current sampling circuit to obtain a compensation current equal to the magnitude of the base current of the BJT input stage. The output terminal V of the current calculation circuit is... CO The obtained compensation current is output to the reference current source in the LDO; The base current compensation circuit includes a third resistor R3, a third transistor Q3, an operational amplifier AMP, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a tenth MOSFET M1. 10 Second current source I B2 Third current source I B3 Fourth current source I B4 and the fifth current source I B5 The upper end of the third resistor R3 is connected to the power supply VDD, and its lower end is connected to the collector of the third transistor Q3; the base of the third transistor Q3 is connected to the non-inverting input of the operational amplifier AMP, the drain of the third MOSFET M3, and the third current source I. B3 At the upper end, the emitter of the third transistor Q3 is connected to the upper end of the second current source IB2; the inverting input of the operational amplifier AMP is connected to the output V of the LDO. OUT The output of the operational amplifier AMP is connected to the gate of the third MOSFET M3; the gate and drain of the first MOSFET M1 are shorted and connected to the source of the third MOSFET M3, the source of the fourth MOSFET M4, and the gate of the second MOSFET M2. The source of the first MOSFET M1 is connected to the power supply VDD; the source of the second MOSFET M2 is connected to the power supply VDD, and its drain is connected to the source of the fifth MOSFET M5 and the source of the sixth MOSFET M6; the gate of the fourth MOSFET M4 is connected to the gate and drain of the fifth MOSFET M5 and the fifth current source I. B5 At the upper end, the drain of the fourth MOSFET M4 is connected to the gate of the sixth MOSFET M6 and the fourth current source I. B4 The upper end; the drain of the sixth MOSFET M6 is connected to the gate and drain of the seventh MOSFET M7 and the gate of the eighth MOSFET M8; the source of the seventh MOSFET M7 is connected to ground GND; the source of the eighth MOSFET M8 is connected to ground GND, and its drain is connected to the gate and drain of the ninth MOSFET M9 and the tenth MOSFET M10. 10 The gate of the ninth MOSFET M9 is connected to the power supply VDD; the source of the tenth MOSFET M... 10 The source is connected to the power supply VDD, and its drain is the output terminal of the base current compensation circuit.

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