A low process variation voltage reference source circuit based on on-chip auto-tuning

Abstract

This invention discloses a voltage reference source circuit with low process deviation based on on-chip automatic adjustment, including a reference source, a core voltage reference source, an adjustment circuit, a comparator, and a digital execution logic circuit. The reference source and the core voltage reference source are respectively connected to the two input terminals of the comparator. The output terminal of the comparator is connected to the input terminal of the adjustment circuit through the digital execution logic circuit, and the output terminal of the adjustment circuit is connected to the core voltage reference source. The comparator compares the output voltage value of the core voltage reference source with a K-fold value of the output voltage value of the reference source, and controls the digital execution logic circuit to automatically adjust the output voltage of the core voltage reference source. This invention uses an additional reference source to calibrate the original design, reducing the impact of CMOS process deviation on the output voltage reference. In addition, the automatic adjustment achieved through the adjustment circuit reduces the complexity of the adjustment process, greatly reduces configuration complexity, and improves flexibility.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of reference circuit, and particularly relates to a voltage reference source circuit with low process deviation based on on-chip automatic trimming. BACKGROUND

[0002] The voltage reference source provides a stable voltage reference for other circuits, which is not affected by process, voltage, temperature (PVT) changes, and is widely used in switching power supply, analog-to-digital converter, linear voltage regulator and other circuits. The voltage reference source composed of CMOS is widely studied because it can work in a lower voltage environment and has better integration. However, the threshold voltage in CMOS is greatly affected by process deviation, and the deviation under different process angles is generally 10% to 20%, which makes the consistency of the reference voltage source generated according to the threshold voltage worse than that of the bandgap reference source. At the same time, in view of the deviation of the output of the reference source under different processes, an additional trimming circuit is needed to correct the temperature coefficient. Most trimming circuits generally manually correct the trimming bits after testing the voltage changes at different temperatures, and generally require multiple processes to obtain the optimal output value. With the increase of trimming bits, the configuration complexity is further increased, which is not conducive to the productization of the reference source. SUMMARY

[0003] The technical problem solved by the application is that the application provides a voltage reference source circuit with low process deviation based on on-chip automatic trimming, which uses an additional reference source to calibrate the original design, reduces the influence of CMOS process deviation on the output voltage reference, and further realizes automatic trimming through a trimming circuit, reduces the complexity of the trimming process, greatly reduces the configuration complexity, and improves flexibility.

[0004] Technical scheme

[0005] A voltage reference source circuit with low process deviation based on on-chip automatic trimming, the voltage reference source circuit comprising a reference source, a core voltage reference source, a trimming circuit, a comparator and a digital execution logic circuit.

[0006] The output end of the reference source and the output end of the core voltage reference source are respectively connected with two input ends of the comparator, the output end of the comparator is connected with the input end of the trimming circuit through the digital execution logic circuit, and the output end of the trimming circuit is connected with the core voltage reference source.

[0007] The comparator compares the output voltage value of the core voltage reference source and the K times value of the output voltage value of the reference source, controls the digital execution logic circuit to output a corresponding trimming control signal to the trimming circuit according to the comparison result, automatically trims the output voltage of the core voltage reference source, and locks the output voltage of the core voltage reference source after trimming.

[0008] Further, the reference source comprises NMOS transistor MN1, NMOS transistor MN2, MOS transistor MN3 and NMOS transistor MN4; wherein the drain of NMOS transistor MN1 is connected to a power supply, the gate is connected to the output of the reference source, and the source is connected to the drain of NMOS transistor MN2; the gate of NMOS transistor MN2 is connected to ground, and the source is connected to the output of the reference source; the drain and the gate of NMOS transistor MN3 are connected to the output of the reference source, and the source is connected to the drain of NMOS transistor MN4; the gate of NMOS transistor MN4 is connected to the output of the reference source, and the source is connected to ground; and the output of the reference source is connected to the comparator through a multiplication circuit.

[0009] Further, NMOS transistor MN1 and NMOS transistor MN2 are intrinsic NMOS transistors, NMOS transistor MN3 is a standard threshold voltage NMOS transistor, and NMOS transistor MN4 is a high threshold voltage NMOS transistor.

[0010] Further, the output voltage V B of the reference source is:

[0011]

[0012] wherein V th-high and V th-native are the threshold voltages of NMOS transistor MN4 and NMOS transistor MN2; m N and m n are the sub-threshold conduction coefficients of NMOS transistor MN4 and NMOS transistor MN2, respectively; K N and K n are the products of the mobility and the oxide capacitance and the width-length ratio of NMOS transistor MN4 and NMOS transistor MN2, respectively.

[0013] Further, the core voltage reference source comprises PMOS transistor MP1, PMOS transistor MP2 and PMOS transistor MP3; the sources and the substrates of PMOS transistor MP1, PMOS transistor MP2 and PMOS transistor MP3 are shorted; the gate and the drain of PMOS transistor MP1 are connected to ground, and the source is connected to the drain and the gate of PMOS transistor MP2; the source of PMOS transistor MP2 is connected to the drain and the gate of PMOS transistor MP3; and the source of PMOS transistor MP3 is connected to the output of the core voltage reference source.

[0014] The trimming circuit comprises: NMOS tubes MNa0, MNa1, MNa2, MNa3, MNa4, MNa5, MNa6, MNa7, MNa8, MNa9, MNa10, MNal1, MNa12, MNa13, MNa14, MNa15; NMOS tubes MNb0, MNb1, MNb2, MNb3, MNb4, MNb5, MNb6, MNb7, MNb8, MNb9, MNb10, MNb11, MNb12, MNb13, MNb14, MNb15; PMOS tubes MPa0, MPa1, MPa2, MPa3, MPa4, MPa5, MPa6, MPa7, MPa8, MPa9, MPa10, MPa11, MPa12, MPa13, MPa14, MPa15;

[0015] The source terminals of the NMOS tubes MNa0 to MNa15 are connected with the output terminal of the core voltage reference source, the gate terminals are connected with the drain terminals of the PMOS tube MP3, and the drain terminals are connected with the source terminals of the NMOS tubes MNb0 to MNb15 in one-to-one correspondence respectively; the gate terminals of the NMOS tubes MNb0 to MNb15 are connected with the output terminal of the core voltage reference source, and the drain terminals are connected with the drain terminals of the PMOS tubes MPa0 to MPa15 in one-to-one correspondence respectively; the gate terminals of the PMOS tubes MPa0 to MPa15 are connected with the control signal output terminals Y0 to Y15 of the digital execution logic circuit in one-to-one correspondence respectively, and the source terminals are connected with the power supply.

[0016] Further, the PMOS tubes MP1, MP2, MP3, MPa0 to MPa15 are all standard threshold voltage PMOS tubes, and the NMOS tubes MNa0 to MNa15 and MNb0 to MNb15 are all intrinsic NMOS tubes.

[0017] Further, the output voltage V REF of the core voltage reference source is:

[0018]

[0019] Among them, V thp V represents the threshold voltage of PMOS transistors MP1, MP2, and MP3. thn V represents the threshold voltage of NMOS transistors MNa0 to MNa15, m1 represents the subthreshold conduction coefficient of NMOS transistors MNa0 to MNa15, m2 represents the subthreshold conduction coefficient of PMOS transistors MP1, MP2, and MP3, and V represents the threshold voltage of NMOS transistors MP0 to MP15. T Where μ is the thermal voltage, μ1 is the mobility of NMOS transistors MNa0 to MNa15, μ2 is the mobility of PMOS transistors MP1, MP2, and MP3, and C is the thermal voltage. OX1 For NMOS transistors MNa0 to MNa15, C is the oxide capacitance. oX2 The oxide layer capacitances of PMOS transistors MP1, MP2, and MP3 are shown; W1 and L1 are the width and length of NMOS transistors MNa0 to MNa15, respectively; and W2 and L2 are the width and length of PMOS transistors MP1, MP2, and MP3, respectively.

[0020] Furthermore, the digital execution logic circuit includes a four-bit register and a decoder. The output of the comparator is connected to the input of the four-bit register, and the output of the four-bit register is connected to the tuning circuit through the decoder.

[0021] The comparator outputs 0 or 1 based on the comparison result, controls the four-bit register to generate a four-bit count result, and converts it into 16 control signals through the decoder to control the width-to-length ratio of NMOS transistors MNa0 to MNa15 and the conduction state of PMOS transistors MPa0 to MPa15, thereby adjusting the output voltage and temperature coefficient of the core voltage reference source.

[0022] Furthermore, the process by which the digital execution logic circuit adjusts the output voltage and temperature coefficient of the core voltage reference source includes the following steps:

[0023] S1, set the gate width and gate length of NMOS transistors MNa0 and MNa15, wherein the gate width of NMOS transistors MNa0 to MNa15 increases arithmetically in successive steps; in the initial control signal, only Y0 outputs a low potential, which turns on the branch controlled by PMOS transistor MPa0, and turns off the other PMOS transistors MPa1 to MPa15.

[0024] S2, the comparator compares the output voltage A of the core voltage reference source with the output voltage B of the reference source by a factor of K. If A < KB, the comparator outputs 1 to a four-bit register. When the rising edge of the enable terminal of the four-bit register arrives, the register is incremented by one, and the signal is converted by the decoder to provide the corresponding control signal. The adjustment circuit is shifted and adjusted so that the branch controlled by PMOS transistor MPa1 is turned on and the other PMOS transistors are turned off, and the output voltage A of the core voltage reference source rises.

[0025] S3. Repeat step S2, sequentially control one of the PMOS transistors MPa0 to MPa15 to turn on until the output voltage A of the core voltage reference source rises to meet the following condition: A > KB. After the comparator judges, it outputs 0 to the four-bit register. The four-bit register is latched to complete the adjustment process and lock the value of the output voltage A of the core voltage reference source.

[0026] Secondly, the present invention discloses a voltage reference source chip with low process deviation based on on-chip automatic adjustment, wherein the voltage reference source chip includes the voltage reference source circuit as described above.

[0027] Beneficial effects:

[0028] First, the voltage reference source circuit of the present invention, which achieves low process deviation based on on-chip automatic adjustment, reduces the process deviation of the CMOS voltage reference source by using an additional low process deviation reference source to correct the core voltage reference source.

[0029] Secondly, the voltage reference source circuit of the present invention, which achieves low process deviation based on on-chip automatic adjustment, realizes automatic adjustment of the output voltage through comparators, registers and decoders, avoiding manual adjustment, greatly reducing configuration complexity and improving flexibility.

[0030] Third, the voltage reference source circuit of the present invention, which achieves low process deviation based on on-chip automatic adjustment, adopts a MOS transistor array adjustment structure, which effectively reduces the influence of PVT and solves the problem of the influence of CMOS fluctuations in the process on the output voltage reference. Attached Figure Description

[0031] Figure 1 This is a block diagram of the voltage reference source circuit based on on-chip automatic adjustment to achieve low process deviation according to the present invention.

[0032] Figure 2 This is a schematic diagram of the circuit structure of the voltage reference source circuit based on on-chip automatic adjustment to achieve low process deviation according to the present invention;

[0033] Figure 3 It is a logic control block diagram of a digital execution logic circuit;

[0034] Figure 4 The results are simulation results using Cadence. (a) is the 500th iteration of the reference source results for the device mismatch model, (b) is the 500th iteration of the core voltage reference source results for the device mismatch model, and (c) is a schematic diagram of the reference source and core voltage reference source results under different process angles (SS\TT\FF\SF\FS).

[0035] Figure 5 This is a schematic diagram of the register and reference voltage output results in a transient simulation using Cadence;

[0036] Figure 6 This is a schematic diagram of the temperature characteristic curve of the core voltage reference source output reference voltage after adjustment at 27℃ using Cadence simulation of different process angles (SS, TT, FF). Detailed Implementation

[0037] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0038] See Figure 1 This invention discloses a voltage reference source circuit that achieves low process deviation based on on-chip automatic trimming. The voltage reference source circuit includes a reference source, a core voltage reference source, a trimming circuit, a comparator, and a digital execution logic circuit.

[0039] The output of the reference source and the output of the core voltage reference source are respectively connected to the two inputs of the comparator. The output of the comparator is connected to the input of the trimming circuit through a digital execution logic circuit. The output of the trimming circuit is connected to the core voltage reference source.

[0040] The comparator compares the output voltage value of the core voltage reference source with a value that is K times the output voltage value of the reference source. Based on the comparison result, it controls the digital execution logic circuit to output a corresponding adjustment control signal to the adjustment circuit, automatically adjusts the output voltage of the core voltage reference source, and locks the output voltage of the core voltage reference source after the adjustment is completed.

[0041] This invention first compares the core voltage reference source with a reference source at a ratio of K (K is a user-defined value, depending on the target output voltage value to be adjusted; in this case, K is set to 577.7mV). The comparator outputs 0 or 1, and through a register and decoder, the 4-bit adjustment network is adjusted to correct the core voltage reference source, ultimately achieving the core reference output voltage (V). REF (Process deviation calibration)

[0042] See Figure 2The circuit structure of each module and the connection relationship between the modules of the voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation in this invention are as follows:

[0043] The reference source consists of NMOS transistors MN1, MN2, MN3, and MN4. NMOS transistors MN1 and MN2 are intrinsic NMOS transistors, NMOS transistor MN3 is a standard threshold voltage NMOS transistor, and NMOS transistor MN4 is a high threshold voltage NMOS transistor used in the input / output module. The drain of NMOS transistor MN1 is connected to the power supply, its gate is connected to the reference output, and its source is connected to the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is grounded, and its source is connected to the reference output. The drain and gate of NMOS transistor MN3 are connected to the reference output, and its source is connected to the drain of NMOS transistor MN4. The gate of NMOS transistor MN4 is connected to the reference output source and grounded. This invention provides a reference source with a voltage value unaffected by voltage and process variations, serving as a reference for the core voltage reference source to calibrate against the effects of process variations. At a fixed temperature, such as room temperature of 27°C, the output voltage of the core voltage reference source is calibrated through an automatic adjustment control network.

[0044] The core voltage reference source consists of PMOS transistors MP1, MP2, MP3, NMOS transistors MNa0 to MNa15, NMOS transistors MNb0 to MNb15, and PMOS transistors MPa0 to MPa15. PMOS transistors MP1, MP2, MP3, and MPa0 to MPa15 are PMOS transistors with standard threshold voltages, while NMOS transistors MNa0 to MNa15 and MNb0 to MNb15 are intrinsic NMOS transistors. The sources and substrates of PMOS transistors MP1, MP2, and MP3 are shorted. The gate and drain of PMOS transistor MP1 are grounded, and its source is connected to the drain and gate of PMOS transistor MP2. The source of PMOS transistor MP2 is connected to the drain and gate of PMOS transistor MP3. The source of PMOS transistor MP3 is connected to the core voltage reference source output. The sources of NMOS transistors MNa0 to MNa15 are connected to the core voltage reference source output, and their gates are connected to the drain of PMOS transistor MP3. Their drains are connected to the sources of NMOS transistors MNb0 to MNb15. The gates of NMOS transistors MNb0 to MNb15 are connected to the core voltage reference source output, and their drains are connected to the drains of PMOS transistors MPa0 to MPa15. The gates of PMOS transistors MPa0 to MPa15 are connected to control signals Y0 to Y15, and their sources are connected to the power supply. Low temperature coefficient is achieved by utilizing the threshold voltage difference between intrinsic NMOS and PMOS transistors, which has a negative temperature coefficient.

[0045] Adjustment circuit: The NMOS transistors MNa0, MNa15, MNb0 to MNb15, and PMOS transistors MPa0 and MPa15 in the core voltage reference source are adjustment modules. By setting different width-to-length ratios of NMOS transistors MNa0 to MNa15 and controlling the conduction of PMOS transistors MPa0 to MPa15, the output reference voltage and temperature coefficient can be adjusted.

[0046] Comparator: The comparator in the analog circuit unit compares the value between the core voltage reference source and a reference source of K times, and outputs 0 or 1 to provide input for digital execution logic.

[0047] Digital execution logic circuit: A 4-bit counting function is implemented through a register, and the result is converted into a control signal through a decoder to control the conduction of the tuning network.

[0048] like Figure 2 As shown, the reference source first reduces the impact of process deviations on the threshold voltage by using the difference between different threshold voltages. However, this still increases as the process changes from FF to SS. Then, an additional intrinsic NMOS transistor is used for correction. The gate of this intrinsic NMOS transistor is grounded, and its source is connected to the reference source output. Its threshold voltage also increases as it changes from FF to SS, thus reducing the impact of process deviations on the final output. Furthermore, since all reference sources use NMOS transistors, the impact of PMOS transistors does not need to be considered due to process deviations. The output of the reference source (V...) B )for:

[0049]

[0050] Where V th-high and V th-native The threshold voltages of NMOS transistors MN4 and MN2; m N and m n K represents the subthreshold conduction coefficients of NMOS transistors MN4 and MN2, respectively; N and K n These are the products of the mobility, oxide capacitance, and aspect ratio of NMOS transistors MN4 and MN2, respectively. The threshold voltage and K are variables that vary with process variations. By adjusting the dimensions of NMOS transistors MN4 and MN2, the variation of VB at different process corners can be reduced, thus achieving a process-independent reference source.

[0051] The core voltage reference source used is a low-power voltage reference source employing subthreshold conduction. It utilizes the threshold voltage difference between different subthreshold conduction coefficients to achieve a reference source that does not change with temperature. Its output V REF for:

[0052]

[0053] Among them, V thp V represents the threshold voltage of PMOS transistors MP1, MP2, and MP3. thn V represents the threshold voltage of NMOS transistors MNa0 to MNa15, m1 represents the subthreshold conduction coefficient of NMOS transistors MNa0 to MNa15, m2 represents the subthreshold conduction coefficient of PMOS transistors MP1, MP2, and MP3, and V represents the threshold voltage of NMOS transistors MP0 to MP15. T Where μ is the thermal voltage, μ1 is the mobility of NMOS transistors MNa0 and MNa15, μ2 is the mobility of PMOS transistors MP1, MP2, and MP3, and C is the thermal voltage. OX1 For NMOS transistors MNa0 to MNa15, C is the oxide capacitance. OX2 Here, W1 represents the oxide layer capacitance of PMOS transistors MP1, MP2, and MP3; W1 and L1 represent the width and length of NMOS transistors MNa0 to MNa15, respectively; and W2 and L2 represent the width and length of PMOS transistors MP1, MP2, and MP3, respectively. As shown in the formula, this invention can obtain a temperature-independent output reference voltage V. REF Furthermore, the power supply rejection capability and linear sensitivity of the output reference are improved by using NMOS transistors MNb0 to MNb15.

[0054] The process by which digital execution logic circuits adjust the output voltage and temperature coefficient of the core voltage reference source includes the following steps:

[0055] S1, set the gate width to gate length ratio of NMOS transistor MNa0 to 0.55um / 1um, and increase the gate width of NMOS transistors MNa0 to MNa15 by equal increments, with adjacent gate widths increasing by 60nm (e.g., set the gate width to gate length ratio of MNa1 to 0.61um / 1um). Initially, A < KB (A is the output voltage of the core voltage reference source, and B is the output voltage of the reference source). After the comparator determines the voltage, it outputs "1" to the next stage (the initial signal is 1111 1111 1111 1110, that is, only Y0 is at a low potential, and the branch controlled by its PMOS MPa0 is turned on, while the others are turned off).

[0056] S2, when the rising edge of the enable terminal of the four-bit register arrives, since the signal input from the comparator is "1", the register is incremented by one, and the 4-to-16 signal is converted through the decoder to provide the corresponding control signal to shift and adjust the trimming circuit. (If the previous signal was the initial signal, the signal now becomes 1111 1111 1111 1101, that is, only Y1 is at a low potential, and the branch controlled by its PMOS MPa1 is turned on, while the others are turned off. Because the gate width of MNa1 is 60nm larger than the gate width of MNa0, the output voltage A of the core voltage reference source will rise.)

[0057] S3. Repeat step S2 until A > KB. After the comparator judges, it outputs "0" to the next stage. At this time, the four-bit register performs latching processing to complete the adjustment process and lock the value of the output voltage A of the core voltage reference source.

[0058] See Figure 3 First, select the V to be corrected. REF The target value is achieved by adjusting the reference source (KB) by a scaling factor K. Initially, the NMOS transistor MNa0 in the adjustment network is set to the minimum width-to-length ratio, and then progressively increases arithmetically up to NMOS transistor MNa15. Therefore, initially A < KB. When the rising edge of the enable terminal (EN) arrives, the execution register is incremented, and the conversion is achieved through the decoder, adjusting the adjustment network. At this time, the NMOS transistor turned on changes from MNa0 to MNa1. Since MNa1 has a larger gate width, A increases. Then the above logic is repeated until A > KB, and then the register is held. At this time, the output voltage stabilizes at the required voltage value. Since the reference source has a low process deviation, the final corrected V REF It exhibits very low process tolerance. However, due to the temperature-dependent influence of the reference source, automatic calibration must be performed at a fixed temperature, such as 27°C. After the calibration process is complete, the enable pin is turned off, and the calibration is finished. Based on this method, a voltage reference source operating from 0°C to 160°C can be realized. A 4-bit calibration network covers all process corners, meaning output calibration can be achieved in a maximum of 16 clock cycles. The width difference between the calibration MOS bits is set to increase arithmetically, with a width-to-length ratio ranging from 0.55u / 1u to 1.45u / 1u, and a width difference of 60nm. Simulation results show that the voltage impact of two adjacent bits on the core reference output is between 1.5mV and 2.5mV. Therefore, the maximum deviation between the calibrated reference source and the reference source is less than 2.5mV, i.e., the least significant bit (LSB) = 2.5mV. The specific deviation effect is shown in the following formula:

[0059]

[0060] Where ΔV thp，process The deviation of the threshold voltages of MP1, MP2, and MP3 from process variations; ΔVthn，process The deviation of the threshold voltage of MNa0 to MNa15 from the process variation; Δβ 1，process and Δβ 2，process They are respectively:

[0061]

[0062]

[0063] Therefore, the W1 value is obtained when it is unaffected by process deviation:

[0064]

[0065] W is set according to the deviation under different processes. 1，trim The value is determined by arranging the bits in an arithmetic progression to achieve the desired adjustment, resulting in V. REF The relationship between output deviation and adjustment accuracy is as follows:

[0066]

[0067] The initial value is set at the FF process corner. The adjustment circuit (adjustment network) is designed based on the process error between the FF and SS process corners. Therefore, the theoretical slowest time for automatic adjustment to reach stability is 16 clock cycles. That is, at the SS process corner, it will take 16 cycles to stabilize at the output value.

[0068] Figure 4 The diagram illustrates the simulation results using a 65nm CMOS process. (a) shows the results of 500 simulations of the Cadence mismatch error model with the reference source; (b) shows the results of 500 simulations of the Cadence mismatch error model with the core voltage reference source; and (c) shows the results of the reference source and core voltage reference source under different process angles. The results show that the ratio of the standard deviation to the mean of the reference source, σ / μ = 0.589%, is a significant improvement over the ratio of the standard deviation to the mean of the core voltage reference source, σ / μ = 1.833%. Simulation results under different process angles also demonstrate that the reference source effectively suppresses the influence of process deviations. The process deviation (Max-MIN) / MAX ratio for SS, TT, FF, SF, and FS is only 0.5825%, a significant improvement over the 22.567% of the core reference source, proving that this invention has a good ability to eliminate the influence of process deviations.

[0069] Figure 5This is the result of transient simulation using Cadence with a 65nm CMOS process, involving the enable signal (EN), registers (Q0, Q1, Q2, Q3), and reference voltage output at the SS process corner. At 27°C, the register enable switch is turned on. At this point, the input of the JK flip-flop is the comparator output. Since A < KB, the comparator output is 1, and the register performs a counting function, incrementing by one. An automatic adjustment is implemented using a 4-to-16 decoder. The above logic repeats in the next enable cycle. Until A > KB, the JK flip-flop input becomes 0, implementing a latching function. At this point, the core output reference source completes calibration, locking the output value to the reference value. Then, after the output stabilizes, the switch is turned off, completing the entire automatic adjustment process. Simulation results show that its digital automatic adjustment module can automatically correct the output voltage of the core voltage reference source to 577.7mV. According to the simulation results, after 15 clock cycles, or 15ms, the output power supply stabilizes to the reference source voltage. At this time, the output of its core voltage reference source is 578.4mV, which is 0.7mV less than the set 577.7mV, within the set error range.

[0070] Figure 6 This is a simulation result of the temperature characteristic curve of the core voltage reference source output voltage at different process angles (SS, TT, FF) under 27℃ adjustment using Cadence simulation of a 65nm CMOS process. The results show that, within the range of 0℃ to 160℃, the temperature coefficients at different process angles are 18.7ppm / ℃ for TT, 20.9ppm / ℃ for SS, and 17.1ppm / ℃ for FF. This indicates that it has excellent temperature coefficients, and at 27℃, the power consumption of the overall automatically adjusted reference source is below nW at the TT process angle.

[0071] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A voltage reference source circuit with low process deviation based on on-chip automatic trimming, characterized in that, The voltage reference source circuit includes a reference source, a core voltage reference source, a trimming circuit, a comparator, and a digital execution logic circuit. The output of the reference source and the output of the core voltage reference source are respectively connected to the two inputs of the comparator. The output of the comparator is connected to the input of the trimming circuit through a digital execution logic circuit. The output of the trimming circuit is connected to the core voltage reference source. The comparator compares the output voltage value of the core voltage reference source with a value that is K times the output voltage value of the reference source. Based on the comparison result, it controls the digital execution logic circuit to output the corresponding adjustment control signal to the adjustment circuit, automatically adjusts the output voltage of the core voltage reference source, and locks the output voltage of the core voltage reference source after the adjustment is completed. The core voltage reference source includes PMOS transistors MP1, MP2, and MP3; the source terminals of PMOS transistors MP1, MP2, and MP3 are shorted to the substrate; the gate and drain terminals of PMOS transistor MP1 are grounded, and its source terminal is connected to the drain and gate terminals of PMOS transistor MP2; the source terminal of PMOS transistor MP2 is connected to the drain and gate terminals of PMOS transistor MP3; and the source terminal of PMOS transistor MP3 is connected to the output terminal of the core voltage reference source. The adjustment circuit includes: NMOS transistors MNa0, MNa1, MNa2, MNa3, MNa4, MNa5, MNa6, MNa7, MNa8, MNa9, MNa10, MNa11, MNa12, MNa13, MNa14, and MNa15; and NMOS transistors MNb0, MNb1, MNb2, MNb3, MNb4, MNb5, MNb6, and MNb...

7. NMOS transistors MNb8, MNb9, MNb10, MNb11, MNb12, MNb13, MNb14, MNb15; PMOS transistors MPa0, MPa1, MPa2, MPa3, MPa4, MPa5, MPa6, MPa7, MPa8, MPa9, MPa10, MPa11, MPa12, MPa13, MPa14, MPa15; The source terminals of NMOS transistors MNa0 to MNa15 are all connected to the output terminal of the core voltage reference source, and their gate terminals are connected to the drain terminals of PMOS transistor MP3. The drain terminals are respectively connected to the source terminals of NMOS transistors MNb0 to MNb15. The gate terminals of NMOS transistors MNb0 to MNb15 are all connected to the output terminal of the core voltage reference source, and their drain terminals are respectively connected to the drain terminals of PMOS transistors MPa0 to MPa15. The gate terminals of PMOS transistors MPa0 to MPa15 are respectively connected to the control signal output terminals Y0 to Y15 of the digital execution logic circuit, and their source terminals are all connected to the power supply. Furthermore, the digital execution logic circuit includes a four-bit register and a decoder. The output of the comparator is connected to the input of the four-bit register, and the output of the four-bit register is connected to the tuning circuit through the decoder. The comparator outputs 0 or 1 based on the comparison result, controls the four-bit register to generate a four-bit count result, and converts it into 16 control signals through the decoder to control the width-to-length ratio of NMOS transistors MNa0 to MNa15 and the conduction state of PMOS transistors MPa0 to MPa15, thereby adjusting the output voltage and temperature coefficient of the core voltage reference source.

2. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation as described in claim 1, characterized in that, The reference source comprises NMOS transistors MN1, MN2, MN3, and MN4. The drain of NMOS transistor MN1 is connected to a power supply, its gate is connected to the reference source output, and its source is connected to the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is grounded, and its source is connected to the reference source output. The drain and gate of NMOS transistor MN3 are connected to the reference output, and its source is connected to the drain of NMOS transistor MN4. The gate of NMOS transistor MN4 is connected to the reference source output, and its source is grounded. The reference source output is connected to a comparator via a multiplier circuit.

3. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation as described in claim 2, characterized in that, The NMOS transistors MN1 and MN2 are intrinsic NMOS transistors, MN3 is a standard threshold voltage NMOS transistor, and MN4 is a high threshold voltage NMOS transistor.

4. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation as described in claim 2, characterized in that, The output voltage of the reference source for: ； in and The threshold voltages of NMOS transistors MN4 and MN2 are given. and These are the subthreshold conduction coefficients of NMOS transistors MN4 and MN2, respectively. and These are the products of the mobility of NMOS transistor MN4 and NMOS transistor MN2, the oxide capacitance, and the aspect ratio, respectively. This is thermal voltage.

5. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation as described in claim 1, characterized in that, The PMOS transistors MP1, MP2, MP3, and MPa0 to MPa15 are all PMOS transistors with standard threshold voltages, while the NMOS transistors MNa0 to MNa15 and MNb0 to MNb15 are all intrinsic NMOS transistors.

6. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation according to claim 1, characterized in that, The output voltage of the core voltage reference source for: ； in, The threshold voltages of PMOS transistors MP1, MP2, and MP3; The threshold voltages of NMOS transistors MNa0 to MNa15 The subthreshold conduction coefficients of NMOS transistors MNa0 to MNa15 are given. The subthreshold conduction coefficients of PMOS transistors MP1, MP2, and MP3 are given. Thermoelectric voltage, The mobility of NMOS transistors MNa0 to MNa15 The mobility of PMOS transistors MP1, MP2, and MP3. The oxide layer capacitance of NMOS transistors MNa0 to MNa15 The oxide layer capacitances of PMOS transistors MP1, MP2, and MP3 are shown; W1 and L1 are the width and length of NMOS transistors MNa0 to MNa15, respectively; and W2 and L2 are the width and length of PMOS transistors MP1, MP2, and MP3, respectively.

7. The voltage reference source circuit based on on-chip automatic trimming to achieve low process deviation according to claim 6, characterized in that, The process by which the digital execution logic circuit adjusts the output voltage and temperature coefficient of the core voltage reference source includes the following steps: S1, set the gate width and gate length of NMOS transistors MNa0 to MNa15, wherein the gate width of NMOS transistors MNa0 to MNa15 increases arithmetically in successive steps; in the initial control signal, only Y0 outputs a low potential, which turns on the branch controlled by PMOS transistor MPa0, and turns off the other PMOS transistors MPa1 to MPa15; S2. The comparator compares the output voltage A of the core voltage reference source with K times the output voltage B of the reference source. If A < KB, the comparator outputs 1 to the four-bit register. When the rising edge of the enable terminal of the four-bit register arrives, the register is incremented, and signal conversion is performed through the decoder to provide the corresponding control signal to perform a shift adjustment on the trimming circuit, causing the branch controlled by the PMOS transistor MPa1 to conduct and other PMOS transistors to turn off, and the output voltage A of the core voltage reference source to rise. S3. Repeat step S2 to sequentially control one of the PMOS transistors MPa0 to MPa15 to conduct until the output voltage A of the core voltage reference source rises to meet the following condition: A > KB. After the comparator makes a judgment, it outputs 0 to the four-bit register, and the four-bit register performs a latch operation to complete the trimming process and lock the value of the output voltage A of the core voltage reference source.

8. A voltage reference source chip with low process deviation based on on-chip automatic adjustment, characterized in that, The voltage reference source chip includes the voltage reference source circuit as described in any one of claims 1-7.

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