A three-level topology positive and negative bus voltage balancing circuit and inverter

Abstract

The invention relates to a three-level topology positive and negative bus voltage balancing circuit and an inverter. The circuit comprises a bus capacitor Cp, a bus capacitor Cn, an output filter capacitor Cf, a capacitor C1, a capacitor C2, a switch tube S1, a switch tube S2, a switch tube S3, a switch tube S4, a diode D1, a diode D2, a diode D3, a diode D4, an inductor L1 and an inductor L2; the gate of the switch tube S1 is used to access a first pulse signal, the gate of the switch tube S2 is used to access a second pulse signal, the gate of the switch tube S3 is used to access a third pulse signal, and the gate of the switch tube S4 is used to access a fourth pulse signal; the invention utilizes an LC oscillation circuit in combination with a unidirectional conduction function of a diode to achieve lossless transfer of positive and negative bus electric energy; when the bus capacitor Cp voltage charges the capacitor C1, the electric energy in the charged capacitor C1 is transferred to the bus capacitor Cn; when the bus capacitor Cn charges the capacitor C2, the electric energy in the capacitor C2 is transferred to the bus capacitor Cp, thereby achieving balance of positive and negative bus voltages.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to a three-level topology positive and negative bus voltage balancing circuit and an inverter. Background Art

[0002] Multilevel inverters have become a hot spot for medium and high voltage high power applications. Three-level inverters have the advantages of low voltage stress, low switching loss, and low harmonic content of the output voltage of the power switch tube, and have been widely used. Compared with two-level inverters, three-level inverters have the advantages of smaller dv / dt, that is, the rate of change of voltage, lower harmonic distortion rate of voltage and current, and power loss. Typical three-level inverters such as midpoint clamped type, flying capacitor type and cascaded H-bridge type topology have been widely used in medium and high voltage industrial applications. Diode midpoint clamped converter is a widely used multilevel inverter. NPC type three-level inverter is one of the most widely used structures. However, NPC type three-level inverter has an inherent disadvantage, that is, the midpoint voltage balance problem, which is mainly manifested as midpoint voltage fluctuation and midpoint potential offset, which will affect the output waveform quality and even cause harm to the system. Summary of the invention

[0003] In order to solve the technical problems such as midpoint potential offset of an NPC type three-level inverter in the prior art, the present invention provides a three-level topology positive and negative bus voltage balancing circuit and an inverter.

[0004] The technical solution of the present invention to solve the above technical problems is as follows:

[0005] A three-level topology positive and negative bus voltage balancing circuit, including a bus capacitor Cp, a bus capacitor Cn, an output filter capacitor Cf, a capacitor C1, a capacitor C2, a switch tube S1, a switch tube S2, a switch tube S3, a switch tube S4, a diode D1, a diode D2, a diode D3, a diode D4, an inductor L1 and an inductor L2;

[0006] The positive electrode of the bus capacitor Cp is electrically connected to the source electrode of the switch tube S1, the negative electrode of the bus capacitor Cp is electrically connected to the positive electrode of the bus capacitor Cn, and the negative electrode of the bus capacitor Cn is electrically connected to the drain electrode of the switch tube S4; the drain electrode of the switch tube S1 is electrically connected to one end of the inductor L1 and the source electrode of the switch tube S2 respectively, the other end of the inductor L1 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to the positive electrode of the diode D3, and the negative electrode of the diode D3 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn;

[0007] The drain of the switch tube S2 is electrically connected to the source of the switch tube S3 and one end of the output filter capacitor Cf, respectively, and the other end of the output filter capacitor Cf is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn; the drain of the switch tube S3 is electrically connected to the source of the switch tube S4 and one end of the inductor L2, respectively, and the other end of the inductor L2 is electrically connected to one end of the capacitor C2, and the other end of the capacitor C2 is electrically connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is electrically connected to the positive electrode of the bus capacitor Cp;

[0008] The positive electrode of the diode D2 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn, and the negative electrode of the diode D2 is electrically connected to the other end of the capacitor C2 or the positive electrode of the diode D1; the positive electrode of the diode D4 is electrically connected to the negative electrode of the bus capacitor Cn or the drain of the switch tube S4, and the negative electrode of the diode D4 is electrically connected to the other end of the capacitor C1 or the positive electrode of the diode D3;

[0009] The gate of the switch tube S1 is used to access the first pulse signal, the gate of the switch tube S2 is used to access the second pulse signal, the gate of the switch tube S3 is used to access the third pulse signal, and the gate of the switch tube S4 is used to access the fourth pulse signal; the rising edge of the first pulse signal is at the same position as the rising edge of the second pulse signal, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal, the rising edges of the third pulse signal and the fourth pulse signal are both located at the falling edge of the second pulse signal, and the pulse width of the third pulse signal is greater than the pulse width of the fourth pulse signal.

[0010] The beneficial effects of the present invention are as follows: by utilizing the LC oscillation circuit in combination with the unidirectional conduction function of the diode, the lossless transfer of positive and negative bus electric energy is realized; when the bus capacitor Cp voltage charges the capacitor C1, the electric energy in the charged capacitor C1 is transferred to the bus capacitor Cn; when the bus capacitor Cn charges the capacitor C2, the electric energy in the charged capacitor C2 is transferred to the bus capacitor Cp, thereby realizing the function of balancing the positive and negative bus voltages.

[0011] Based on the above technical solution, the present invention can also be improved as follows.

[0012] Furthermore, it also includes a diode D5 and a diode D6, the positive electrode of the diode D5 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn, and the negative electrode of the diode D5 is electrically connected to the drain of the switch tube S1; the positive electrode of the diode D6 is electrically connected to the drain of the switch tube S3, and the negative electrode of the diode D6 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn.

[0013] Furthermore, an inductor Lf is included, one end of the inductor Lf is electrically connected to the drain of the switch tube S2, and the other end of the inductor Lf is electrically connected to one end of the output filter capacitor Cf.

[0014] Furthermore, the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal are all high-level pulse signals.

[0015] Furthermore, the switch tube S1 , the switch tube S2 , the switch tube S3 , and the switch tube S4 are all MOS tubes.

[0016] Furthermore, the MOS transistor is a P-channel enhancement mode MOS transistor.

[0017] Furthermore, a parasitic diode is connected to the P-channel enhancement mode MOS transistor, an anode of the parasitic diode is electrically connected to the drain of the P-channel enhancement mode MOS transistor, and a cathode of the parasitic diode is electrically connected to the source of the P-channel enhancement mode MOS transistor.

[0018] Furthermore, a parasitic capacitor is connected to the P-channel enhancement mode MOS transistor, one end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement mode MOS transistor, and the other end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement mode MOS transistor.

[0019] In order to solve the above technical problems, the present invention also provides an inverter, and its specific technical contents are as follows:

[0020] An inverter comprises the above three-level topology positive and negative bus voltage balancing circuit.

[0021] Furthermore, the inverter is an I-type half-bridge three-level inverter or an I-type three-level half-bridge LLC resonant DC / DC inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a circuit schematic diagram of a three-level topology positive and negative bus voltage balancing circuit in an embodiment of the present invention;

[0023] Figure 2 1 is a waveform diagram of the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0025] like Figure 1As shown, this embodiment provides a three-level topology positive and negative bus voltage balancing circuit, including a bus capacitor Cp, a bus capacitor Cn, an output filter capacitor Cf, a capacitor C1, a capacitor C2, a switch tube S1, a switch tube S2, a switch tube S3, a switch tube S4, a diode D1, a diode D3, an inductor L1 and an inductor L2, a diode D2, a diode D4, a diode D5, a diode D6 and an inductor Lf.

[0026] The positive electrode of the bus capacitor Cp is electrically connected to the source electrode of the switch tube S1, the negative electrode of the bus capacitor Cp is electrically connected to the positive electrode of the bus capacitor Cn, and the negative electrode of the bus capacitor Cn is electrically connected to the drain electrode of the switch tube S4; the drain electrode of the switch tube S1 is electrically connected to one end of the inductor L1 and the source electrode of the switch tube S2, respectively, the other end of the inductor L1 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to the positive electrode of the diode D3, and the negative electrode of the diode D3 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn.

[0027] The drain of the switch tube S2 is electrically connected to the source of the switch tube S3 and one end of the output filter capacitor Cf, respectively, and the other end of the output filter capacitor Cf is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn; the drain of the switch tube S3 is electrically connected to the source of the switch tube S4 and one end of the inductor L2, respectively, and the other end of the inductor L2 is electrically connected to one end of the capacitor C2, and the other end of the capacitor C2 is electrically connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is electrically connected to the positive electrode of the bus capacitor Cp.

[0028] By utilizing the LC oscillation circuit in combination with the unidirectional conduction function of the diode, the lossless transfer of positive and negative bus electric energy is achieved; when the bus capacitor Cp voltage charges the capacitor C1, the electric energy in the charged capacitor C1 is transferred to the bus capacitor Cn; when the bus capacitor Cn charges the capacitor C2, the electric energy in the charged capacitor C2 is transferred to the bus capacitor Cp, thus achieving the function of balancing the positive and negative bus voltages.

[0029] Specifically, the positive electrode of the diode D2 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn, and the negative electrode of the diode D2 is electrically connected to the other end of the capacitor C2 or the positive electrode of the diode D1; the positive electrode of the diode D4 is electrically connected to the negative electrode of the bus capacitor Cn or the drain of the switch tube S4, and the negative electrode of the diode D4 is electrically connected to the other end of the capacitor C1 or the positive electrode of the diode D3.

[0030] The positive electrode of the diode D5 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn, and the negative electrode of the diode D5 is electrically connected to the drain of the switch tube S1; the positive electrode of the diode D6 is electrically connected to the drain of the switch tube S3, and the negative electrode of the diode D6 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn. One end of the inductor Lf is electrically connected to the drain of the switch tube S2, and the other end of the inductor Lf is electrically connected to one end of the output filter capacitor Cf.

[0031] In some embodiments, the switch tube S1, the switch tube S2, the switch tube S3 and the switch tube S4 can be triodes; when the switch tube S1, the switch tube S2, the switch tube S3 and the switch tube S4 are triodes, the gate is the base of the triode, the source is the collector of the triode, and the drain is the emitter of the triode.

[0032] When the switch tube S1, the switch tube S2, the switch tube S3 and the switch tube S4 are all MOS tubes, the MOS tubes are preferably P-channel enhancement-type MOS tubes. The P-channel enhancement-type MOS tube is connected with a parasitic diode and a parasitic capacitor, the anode of the parasitic diode is electrically connected to the drain of the P-channel enhancement-type MOS tube, and the cathode of the parasitic diode is electrically connected to the source of the P-channel enhancement-type MOS tube. One end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement-type MOS tube, and the other end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement-type MOS tube.

[0033] like Figure 2 As shown, the gate of the switch tube S1 is used to access the first pulse signal, the gate of the switch tube S2 is used to access the second pulse signal, the gate of the switch tube S3 is used to access the third pulse signal, and the gate of the switch tube S4 is used to access the fourth pulse signal; the rising edge of the first pulse signal is at the same position as the rising edge of the second pulse signal, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal, the rising edges of the third pulse signal and the fourth pulse signal are both located at the falling edge of the second pulse signal, and the pulse width of the third pulse signal is larger than the pulse width of the fourth pulse signal. Wherein, the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal are all high-level pulse signals or square wave signals.

[0034] In this embodiment, when the switch tube S1 and the switch tube S2 are turned on, the positive end of the bus capacitor Cp passes through the switch tube S1, the inductor L1, the capacitor C1, and the diode D3, and returns to the negative end of the bus capacitor Cp. The voltage on the bus capacitor Cp is transferred to C1 through the inductor L1 and the capacitor C1. At this time, the voltage on the capacitor C1 is negative on the left and positive on the right; when the switch tube S1 is turned off and S2 continues to be turned on, the capacitor C1 discharges and charges the bus capacitor Cn at the same time, and the electric energy in the capacitor C1 is transferred to the bus capacitor Cn. The discharge circuit is capacitor C1, inductor L1, switch tube S2, inductor Lf, capacitor Cf, capacitor Cn, and diode D4. Similarly, when the switch tube S3 and the switch tube S4 are turned on, the voltage on the capacitor Cn is charged to the capacitor C2, and the electric energy is stored in C2. When the switch tube S4 is turned off and the switch tube S3 continues to be turned on, the electric energy in C2 is transferred to the capacitor Cp. The voltage of capacitor Cp charges capacitor C1, and the electric energy in capacitor C1 is transferred to capacitor Cn. Capacitor Cn charges capacitor C2, and the electric energy in capacitor C2 is transferred to capacitor Cp, so as to balance the positive and negative bus voltages.

[0035] In some other embodiments, an inverter is further provided, wherein the inverter comprises the above-mentioned three-level topology positive and negative bus voltage balancing circuit, wherein the inverter is an I-type half-bridge three-level inverter or an I-type three-level half-bridge LLC resonant DC / DC inverter.

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-level topology positive and negative bus voltage balancing circuit, characterized in that: Including bus capacitor Cp, bus capacitor Cn, output filter capacitor Cf, capacitor C1, capacitor C2, switch tube S1, switch tube S2, switch tube S3, switch tube S4, diode D1, diode D2, diode D3, diode D4, inductor L1 and inductor L2; The positive electrode of the bus capacitor Cp is electrically connected to the source electrode of the switch tube S1, the negative electrode of the bus capacitor Cp is electrically connected to the positive electrode of the bus capacitor Cn, and the negative electrode of the bus capacitor Cn is electrically connected to the drain electrode of the switch tube S4; the drain electrode of the switch tube S1 is electrically connected to one end of the inductor L1 and the source electrode of the switch tube S2 respectively, the other end of the inductor L1 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to the positive electrode of the diode D3, and the negative electrode of the diode D3 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn; The drain of the switch tube S2 is electrically connected to the source of the switch tube S3 and one end of the output filter capacitor Cf, respectively, and the other end of the output filter capacitor Cf is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn; the drain of the switch tube S3 is electrically connected to the source of the switch tube S4 and one end of the inductor L2, respectively, and the other end of the inductor L2 is electrically connected to one end of the capacitor C2, and the other end of the capacitor C2 is electrically connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is electrically connected to the positive electrode of the bus capacitor Cp; The positive electrode of the diode D2 is electrically connected to the negative electrode of the bus capacitor Cp or the positive electrode of the bus capacitor Cn, and the negative electrode of the diode D2 is electrically connected to the other end of the capacitor C2 or the positive electrode of the diode D1; the positive electrode of the diode D4 is electrically connected to the negative electrode of the bus capacitor Cn or the drain of the switch tube S4, and the negative electrode of the diode D4 is electrically connected to the other end of the capacitor C1 or the positive electrode of the diode D3; The gate of the switch tube S1 is used to receive the first pulse signal, the gate of the switch tube S2 is used to receive the second pulse signal, the gate of the switch tube S3 is used to receive the third pulse signal, and the gate of the switch tube S4 is used to receive the fourth pulse signal; The rising edge of the first pulse signal is at the same position as the rising edge of the second pulse signal, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal, the rising edges of the third pulse signal and the fourth pulse signal are both located at the falling edge of the second pulse signal, and the pulse width of the third pulse signal is greater than the pulse width of the fourth pulse signal.

2. The three-level topology positive and negative bus voltage balancing circuit according to claim 1, characterized in that: It also includes a diode D5 and a diode D6, wherein the anode of the diode D5 is electrically connected to the cathode of the bus capacitor Cp or the cathode of the bus capacitor Cn, and the cathode of the diode D5 is electrically connected to the drain of the switch tube S1; the anode of the diode D6 is electrically connected to the drain of the switch tube S3, and the cathode of the diode D6 is electrically connected to the cathode of the bus capacitor Cp or the cathode of the bus capacitor Cn.

3. The three-level topology positive and negative bus voltage balancing circuit according to claim 1, characterized in that: It also includes an inductor Lf, one end of which is electrically connected to the drain of the switch tube S2, and the other end of which is electrically connected to one end of the output filter capacitor Cf.

4. The three-level topology positive and negative bus voltage balancing circuit according to claim 1, characterized in that: The first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal are all high-level pulse signals.

5. The three-level topology positive and negative bus voltage balancing circuit according to claim 1, characterized in that: The switch tube S1 , the switch tube S2 , the switch tube S3 , and the switch tube S4 are all MOS tubes.

6. The three-level topology positive and negative bus voltage balancing circuit according to claim 5, characterized in that: The MOS tube is a P-channel enhancement type MOS tube.

7. The three-level topology positive and negative bus voltage balancing circuit according to claim 6, characterized in that: A parasitic diode is connected to the P-channel enhancement mode MOS transistor, the anode of the parasitic diode is electrically connected to the drain of the P-channel enhancement mode MOS transistor, and the cathode of the parasitic diode is electrically connected to the source of the P-channel enhancement mode MOS transistor.

8. The three-level topology positive and negative bus voltage balancing circuit according to claim 7, characterized in that: A parasitic capacitor is connected to the P-channel enhancement mode MOS transistor, one end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement mode MOS transistor, and the other end of the parasitic capacitor is electrically connected to the drain of the P-channel enhancement mode MOS transistor.

9. An inverter, characterized in that: It comprises the three-level topology positive and negative bus voltage balancing circuit as claimed in any one of claims 1 to 8.

10. The inverter according to claim 9, characterized in that: The inverter is an I-type half-bridge three-level inverter or an I-type three-level half-bridge LLC resonant DC / DC inverter.

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