Split floating diffusion pixel layout design

Abstract

This application relates to split floating diffusion pixel layout design. A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusion regions that receive charge from first and third photodiodes through first and third transfer transistors and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of the first transfer transistors of the first and second pixel circuits. A third shared gate structure includes gates of the third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of the second transfer transistors of the first and third pixel circuits. A fourth shared gate structure includes gates of the fourth transfer transistors of the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusion regions and the third and fourth split floating diffusion regions to merge charge in the first, second, third, and fourth floating diffusion regions.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, webcams, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like by device architecture design and image acquisition processing in as many ways as possible, such as resolution, power consumption, dynamic range, and the like. The technology for manufacturing image sensors is constantly advancing. For example, the demand for higher resolution and lower power consumption has prompted these devices to be further miniaturized and integrated.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having a photosensitive element, such as a photodiode, that absorbs a portion of the incident image light and photo generates image charge after absorbing the image light. The image charge photo generated by a pixel is measurable as an analog output image signal on a column bit line that varies in accordance with the incident image light. In other words, the amount of photo generated image charge is proportional to the intensity of the image light, which is read out as an analog signal from the column bit line and converted to a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] Standard image sensors have a limited dynamic range of about 60 to 70 dB. However, the luminance dynamic range of real-world scenes is much greater. For example, natural scenes often span a range of 90 dB and more. To capture details in both bright and dim light at the same time, high dynamic range (HDR) techniques have been used in image sensors to increase the captured dynamic range. SUMMARY

[0005] In one aspect, the present disclosure provides a pixel array comprising: a plurality of pixel circuits arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits includes: first, second, third, and fourth photodiodes disposed in a semiconductor material and configured to photogenerate charges in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first, second, third, and fourth split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charges photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, wherein the second split floating diffusion region is coupled to receive the charges photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure comprises a gate of the first transfer transistor of the first pixel circuit and a gate of a first transfer transistor of a second pixel circuit of the plurality of pixel circuits, wherein the third shared gate structure comprises a gate of the third transfer transistor of the first pixel circuit and a gate of a third transfer transistor of the second pixel circuit, wherein the second shared gate structure comprises a gate of the second transfer transistor of the first pixel circuit and a gate of a second transfer transistor of a third pixel circuit of the plurality of pixel circuits, wherein the fourth shared gate structure comprises a gate of the fourth transfer transistor of the first pixel circuit and a gate of a fourth transfer transistor of the third pixel circuit; and a dual floating diffusion transistor coupled between the first and second split floating diffusion regions and the third and fourth split floating diffusion regions, wherein the dual floating diffusion transistor is configured to turn on to merge charges in the first, second, third, and fourth floating diffusion regions.

[0006] In another aspect, the present disclosure provides an imaging system, comprising: a pixel array including a plurality of pixel circuits arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits includes: first, second, third, and fourth photodiodes disposed in a semiconductor material and configured to photogenerate charges in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first, second, third, and fourth split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charges photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, wherein the second split floating diffusion region is coupled to receive the charges photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure includes a gate of the first transfer transistor of the first pixel circuit and a gate of a first transfer transistor of a second pixel circuit of the plurality of pixel circuits, wherein the third shared gate structure includes a gate of the third transfer transistor of the first pixel circuit and a gate of a third transfer transistor of the second pixel circuit, wherein the second shared gate structure includes a gate of the second transfer transistor of the first pixel circuit and a gate of a second transfer transistor of a third pixel circuit of the plurality of pixel circuits, wherein the fourth shared gate structure includes a gate of the fourth transfer transistor of the first pixel circuit and a gate of a fourth transfer transistor of the third pixel circuit; and a dual floating diffusion transistor coupled between the first and second split floating diffusion regions and the third and fourth split floating diffusion regions, wherein the dual floating diffusion transistor is configured to turn on to merge charges in the first, second, third, and fourth floating diffusion regions; a control circuit coupled to the pixel array to control operation of the pixel array; and a readout circuit coupled to the pixel array to read out image data from the pixel array.

[0007] In another aspect, the disclosure provides a pixel array comprising: a plurality of pixel circuits arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits includes: first, second, third, and fourth photodiodes disposed in a semiconductor material and configured to photogenerate charges in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first and second split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charges photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, wherein the second split floating diffusion region is coupled to receive the charges photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure comprises a gate of the first transfer transistor of the first pixel circuit and a gate of a first transfer transistor of a second pixel circuit of the plurality of pixel circuits, wherein the third shared gate structure comprises a gate of the third transfer transistor of the first pixel circuit and a gate of a third transfer transistor of the second pixel circuit, wherein the second shared gate structure comprises a gate of the second transfer transistor of the first pixel circuit and a gate of a second transfer transistor of a third pixel circuit of the plurality of pixel circuits, wherein the fourth shared gate structure comprises a gate of the fourth transfer transistor of the first pixel circuit and a gate of a fourth transfer transistor of the third pixel circuit; a first source follower transistor disposed in the semiconductor material between the first and second split floating diffusion regions; a first row select transistor having a drain region coupled to a source region of the first source follower transistor; and a second row select transistor having a drain region coupled to the source region of the first source follower transistor. BRIEF DESCRIPTION OF DRAWINGS

[0008] Non-limiting and non-exhaustive examples of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views.

[0009] Figure 1 An example of an imaging system including an array of pixel circuits organized in various different color patterns is described in accordance with the teachings of the present disclosure.

[0010] Figure 2A A plan view showing an example layout of an arrangement of pixel circuits having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of the present disclosure.

[0011] Figure 2BA schematic diagram showing an exemplary arrangement of pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure.

[0012] Figure 3A A timing diagram illustrating exemplary transfer control signals associated with a readout sequence for exemplary pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure.

[0013] Figure 3B A first readout period for an exemplary pixel array of pixel circuitry having shared gate structures and split floating diffusion regions in accordance with the teachings of this disclosure is described.

[0014] Figure 3C A second readout period for an exemplary pixel array of pixel circuitry having shared gate structures and split floating diffusion regions in accordance with the teachings of this disclosure is described.

[0015] Figure 4 A cross-sectional view showing an exemplary pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure.

[0016] Figure 5 Various exemplary patterns for a color filter array disposed on a pixel array including an arrangement of pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure are described.

[0017] Figure 6A A plan view showing another exemplary layout for an arrangement of pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure.

[0018] Figure 6B A schematic diagram showing another exemplary arrangement of pixel circuitry having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure.

[0019] In all of the several views of the drawings, corresponding reference symbols indicate corresponding components. A skilled artisan understands that the elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements for clarity and to help promote understanding of the various embodiments of the application. Furthermore, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present application. DETAILED DESCRIPTION

[0020] Examples described herein relate to imaging systems having pixel circuits with shared gate structures and split floating diffusion regions included in a pixel array, in accordance with the teachings of this disclosure. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspect(s) that are not related to the presently disclosed technology.

[0021] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present technology. Thus, the appearances of the phrase "in one example" or "in an example" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0022] For purposes of the description hereinafter, spatial or directional terms, such as "below," "above," "left," "right," "upper," "lower," "upward," "downward," "vertical," "horizontal," and the like, can be used where applicable to describe the illustrated embodiment. Unless otherwise stated as applied to the operation and functioning of the preferred embodiment of the application, such terms are not intended to imply a fixed or absolute spatial orientation of the apparatus. It will be appreciated that the apparatus can be oriented in any direction and the described references can be similarly oriented.

[0023] In this specification, several technical terms are used. Such terms will take their ordinary meaning in the art unless otherwise defined herein or the context of their use clearly dictates otherwise. It is noted that element names and symbols can be used interchangeably in this document (e.g., Si vs. silicon); however, both have the same meaning.

[0024] As will be discussed, various examples of imaging systems are disclosed that include a pixel array having pixel circuits with shared gate structures and split floating diffusion regions. In various examples, each pixel circuit includes at least first, second, third, and fourth photodiodes disposed in a semiconductor material configured to photo generate charges in response to incident light. At least first, second, third, and fourth transfer transistors are coupled to the first, second, third, and fourth photodiodes, respectively, and at least a first split floating diffusion region and a second split floating diffusion region are disposed in the semiconductor material. As such, the first split floating diffusion region is coupled to receive charges photo generated by the first and third photodiodes through the first and third transfer transistors, respectively, and the second split floating diffusion region is coupled to receive charges photo generated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively.

[0025] Each pixel circuit also includes at least first, second, third, and fourth shared gate structures. The first shared gate structure includes a gate of the first transfer transistor of a first pixel circuit of the plurality of pixel circuits and a gate of the first transfer transistor of a second pixel circuit. The third shared gate structure includes a gate of the third transfer transistor of the first pixel circuit and a gate of the third transfer transistor of the second pixel circuit. The second shared gate structure includes a gate of the second transfer transistor of the first pixel circuit of the plurality of pixel circuits and a gate of the second transfer transistor of a third pixel circuit. The fourth shared gate structure includes a gate of the fourth transfer transistor of the first pixel circuit and a gate of the fourth transfer transistor of the third pixel circuit. In various examples, the first pixel circuit is disposed in the semiconductor material between the second pixel circuit and the third pixel circuit such that the first, second, and third pixel circuits are adjacent pixel circuits in the pixel array. In examples, each pixel circuit further includes a source follower transistor disposed in the semiconductor material between the first and second split floating diffusion regions. As such, each pixel circuit also includes a conductor disposed over the gate of the source follower transistor and the first and second split floating diffusion regions such that the gate of the source follower transistor is coupled to the first and second split floating diffusion regions through the conductor.

[0026] Accordingly, it should be appreciated that a pixel circuit according to the teachings of this disclosure features a pixel design that splits the floating diffusion region surrounded by four adjacent transfer transistors into two portions. Using a shared gate structure, the gates of the transfer transistors of the pixel circuit have a merged TX gate between adjacent pixel circuits (e.g., a shared transfer gate structure between multiple transfer transistors) that enables a single metal interconnect of the transfer control signal to be shared between adjacent pixel circuits. Thus, metal routing complexity is reduced and routing flexibility is also provided. For example, wider metal pitch is provided to benefit pixel scaling. In one example, pixel size can be reduced to 0.5 um. Using a source follower transistor disposed in semiconductor material between the first and second split diffusion regions, according to the teachings of this disclosure, the conductor path length from the first split floating diffusion region to the gate of the source follower transistor to the second split floating diffusion region can be reduced, which enables pitch reduction of the pixel circuit design while still allowing shared pixel structures such as 2x2, 2x4, or higher. Additionally, the pixel design provides flexibility that allows high dynamic range, switchable multiple conversion gain, multiple pixel merging, phase detection autofocus, high speed readout via multiple bit lines, and dual row select configurations.

[0027] As will be discussed, in some examples, the pixel circuit can also include a dual floating diffusion transistor coupled between the third and fourth split floating diffusion regions and the first and second split floating diffusion regions that provides switchable conversion gain and switchable multiple merging (e.g., 2x2, 2x4, etc.) of the pixel circuit. For example, as will be discussed, when the dual floating diffusion transistor is on, lower conversion gain and / or 2x4 merging readout can be achieved. In examples, when the dual floating diffusion transistor is off, higher conversion gain and / or 2x2 merging readout can be achieved.

[0028] As will be discussed, in other examples, the pixel circuit can also include a dual row select transistor coupled to one or both source follower transistors. For example, in various examples, the dual row select transistor can be applied to 2x4 or higher shared pixel circuit structures by connecting more 2x2 shared cell pixels with metal routing that supports switchable conversion gain. In various examples, the dual row select pixel circuit example can be used based on 2x4 shared split floating diffusion pixel circuits by connecting the dual row select transistor to a separate row control line down to, for example, 0.5 um wide pixel circuits.

[0029] To illustrate, Figure 1Generally described, one example of a complementary metal-oxide-semiconductor (CMOS) imaging system 100 in accordance with an embodiment of the present disclosure includes a pixel array 102 having an array of pixel circuits with dual row select pixels for fast pixel binning. As shown in the depicted example, the imaging system 100 includes an image sensor having the pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array of pixel circuits.

[0030] In examples, the pixel circuits included in the pixel array 102 can be organized in one of a variety of different color patterns. For example, the color pixel circuit array 104A illustrates an example of a 1C Bayer (RGB) color filter pattern, which can be used for high resolution still image capture. Similarly, the color pixel circuit array 104B illustrates an example of a 4C (2x2) Bayer color filter pattern of red (R), green (G), and blue (B) color filters, as shown. The color pixel circuit array 104C illustrates an example of a 16C (4x4) Bayer (RGB) color filter pattern. It should be noted that in the depicted example, the color pixel circuit 104C is organized in adjacent pairs of 2x4 pixel circuits to form a 4x4 16C Bayer (RGB) color filter pattern. The color pixel circuit array 104D illustrates another example of a 16C (4x4) Bayer (RGB) color filter pattern, which can be used, for example, for high speed HD video capture.

[0031] In the depicted example, the pixel circuits included in the pixel array 102 are arranged in rows and columns to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc. After a photodiode in a pixel circuit of the pixel array 102 acquires its image charge, the corresponding analog image signal is read out by the readout circuitry 106 through the column bit lines 112. In various examples, the pixel circuits included in the pixel array 102 can also be configured to provide a high dynamic range (HDR) image signal, in which case image charge generated by one or more photodiodes in bright lighting conditions can also be transferred to a lateral overflow integrated capacitor (LOFIC) and / or an additional floating diffusion region to store image charge. For example, each pixel circuit 104 can include a LOFIC configured to store excess image charge that overflows from the coupled one or more photodiodes during an integration period. In various examples, the readout circuitry 106 can include a current source, routing circuitry, and a comparator that can be included in an analog-to-digital converter or other.

[0032] In various examples, the readout circuit 106 includes an analog-to-digital conversion (ADC) circuit coupled to convert analog image signals received from the pixel circuit 104 over the bit line 112 into digital image signals, which can then be transferred to the functional logic 108. The functional logic 108 can merely store the digital image data or even manipulate the digital image data by applying post-image effects such as cropping, rotation, red-eye removal, adjusting brightness, adjusting contrast, or others.

[0033] In one example, the control circuit 110 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with an illumination effect such as a flash.

[0034] In one example, the imaging system 100 is implemented on a single semiconductor wafer. In another example, the imaging system 100 is on stacked semiconductor wafers. For example, the pixel array 102 is implemented on a pixel wafer and the readout circuit 106, control circuit 110, and functional logic 108 are implemented on an application specific integrated circuit (ASIC) wafer, where the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). For another example, the pixel array 102 and control circuit 110 are implemented on a pixel wafer and the readout circuit 106 and functional logic 108 are implemented on an ASIC wafer, where the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs).

[0035] In one example, the imaging system 100 can be included in a digital device, a cell phone, a laptop, an endoscope, a camera, or an imaging device for a car, or the like. Additionally, the imaging system 100 can be coupled to other hardware such as a processor (general purpose or otherwise), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, and the like), illumination / flash, electrical inputs (keyboard, touch display, touchpad, mouse, microphone, and the like), and / or a display. The other hardware can communicate instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0036] Figure 2A A plan view showing an example layout of an arrangement of pixel circuits 204_N, 204_N-2, 204_N+2, 204_N+4, and the like having shared gate structures and split floating diffusion regions included in a pixel array according to the teachings of this disclosure is shown. It should be appreciated that, Figure 2Apixel circuits 204_N, 204_N-2, 204_N+2, 204_N+4, etc. can be substantially similar to one another. Thus, it should be understood that the description of features and functions in the first pixel circuit 204_N can apply to corresponding features and functions in other pixel circuits included in the pixel array, including the second pixel circuit 204_N-2 and the third pixel circuit 204_N+2, etc. Figure 1 The example of adjacent pixel circuits included in the pixel array 102 shown in FIG. 2A is similarly coupled and operates as follows. In various examples, the first pixel circuit 204_N, the second pixel circuit 204_N-2, and the third pixel circuit 204_N+2 are substantially similar to one another. Thus, it should be understood that the description of features and functions in the first pixel circuit 204_N can apply to corresponding features and functions in other pixel circuits included in the pixel array, including the second pixel circuit 204_N-2 and the third pixel circuit 204_N+2, etc.

[0037] As shown in FIG. 2A, the pixel circuit 204_N includes a photodiode 202_N, a transfer transistor 206_N, a reset transistor 208_N, a source follower transistor 210_N, a row select transistor 212_N, and a floating diffusion node 214_N. The pixel circuit 204_N also includes a storage capacitor 216_N. The pixel circuit 204_N is coupled to a row select line 218_N, a reset line 220_N, a transfer line 222_N, a source follower line 224_N, and a storage capacitor line 226_N. Figure 2AAs shown in the example depicted in FIG, the first pixel circuit 204_N is disposed in a semiconductor material 260 (e.g., a silicon substrate material) between the second pixel circuit 204_N-2 and the third pixel circuit 204_N+2. In the depicted example, the widths of the first pixel circuit 204_N, the second pixel circuit 204_N-2, and the third pixel circuit 204_N+2 can have a pixel pitch in the sub-micron range, such as 0.5 μm or less. As shown, the first pixel circuit 204_N includes at least first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 disposed in the semiconductor material 260 and configured to photogenerate charge in response to incident light. At least first, second, third, and fourth transfer transistors TX1 216-1, TX2 216-2, TX3 216-3, and TX4 216-4 are coupled to first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4, respectively. At least first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 included in first pixel circuit 204_N are disposed in semiconductor material 260. First split floating diffusion region FD_1 218-1 is coupled to receive charge photogenerated by first and third photodiodes PD1 214-1 and PD3 214-3 through first and third transfer transistors TX1 216-1 and TX3 216-3, respectively. First split floating diffusion region FD_1 218-1 may be disposed in semiconductor material 260 proximate to first and third transfer transistors TX1 216-1 and TX3 216-3 in first pixel circuit 204_N. Similarly, second split floating diffusion region FD_2 218-2 is coupled to receive charge photogenerated by second and fourth photodiodes PD2 214-2 and PD4 214-4 through second and fourth transfer transistors TX2 216-2 and TX4 216-4, respectively. Second split floating diffusion region FD_2 218-2 may be disposed in semiconductor material 260 proximate to second and fourth transfer transistors TX2 216-2 and TX4 216-4 in first pixel circuit 204_N.

[0038] continue Figure 2AThe first pixel circuit 204_N also includes at least a first, second, third, and fourth shared gate structure 230-1, 230-2, 230-3, and 230-4 in the depicted example. The first shared gate structure 230-1 includes a gate (e.g., gate electrode) of a first transfer transistor TX1 216-1 of the first pixel circuit 204_N and a gate (e.g., gate electrode) of a first transfer transistor TX1 216-1 of an adjacent second pixel circuit 204_N-2. The gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the first pixel circuit 204_N and the gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the adjacent second pixel circuit 204_N-2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the first pixel circuit 204_N is configured to couple the first photodiode PD1 214-1 to a first split floating diffusion FD_1 218-1 of the first pixel circuit 204_N. The gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the adjacent second pixel circuit 204_N-2 is configured to couple the first photodiode PD1 214-1 of the adjacent second pixel circuit 204_N-2 to a respective first split floating diffusion FD_1 of the adjacent second pixel circuit 204_N-2. The first shared gate structure 230-1 enables the gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the first pixel circuit 204_N and the gate (e.g., gate electrode) of the first transfer transistor TX1 216-1 of the adjacent second pixel circuit 204_N-2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a first transfer control signal.

[0039] The third shared gate structure 230-3 includes a gate (e.g., a gate electrode) of a third transfer transistor TX3 216-3 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of a third transfer transistor TX3 216-3 of an adjacent second pixel circuit 204_N-2. The gate (e.g., a gate electrode) of the third transfer transistor TX3 216-3 of the first pixel circuit 204_N and the gate (e.g., a gate electrode) of the third transfer transistor TX3 216-3 of the adjacent second pixel circuit 204_N-2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate (e.g., a gate electrode) of the third transfer transistor TX3 216-3 of the first pixel circuit 204_N is configured to couple the third photodiode PD3 214-3 to a first split floating diffusion region FD_1 218-1 of the first pixel circuit 204_N. The gate (e.g., a gate electrode) of the third transfer transistor TX1 216-1 of the adjacent second pixel circuit 204_N-2 is configured to couple a respective third photodiode PD3 214-3 of the adjacent second pixel circuit 204_N-2 to a respective first split floating diffusion region FD_1. The third shared gate structure 230-3 enables the gate (e.g., a gate electrode) of the third transfer transistor TX3 216-3 of the first pixel circuit 204_N and the gate (e.g., a gate electrode) of the third transfer transistor TX3 216-3 of the adjacent second pixel circuit 204_N-2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a third transfer control signal.

[0040] The second shared gate structure 230-2 includes a gate (e.g., a gate electrode) of a second transfer transistor TX2 216-2 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of a second transfer transistor TX2 216-2 of an adjacent third pixel circuit 204_N+2. The gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the first pixel circuit 204_N and the gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the adjacent third pixel circuit 204_N+2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the first pixel circuit 204_N is configured to couple the second photodiode PD2 214-2 to a second split floating diffusion FD_2 218-2 of the first pixel circuit 204_N. The gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the adjacent third pixel circuit 204_N+2 is configured to couple a respective second photodiode PD2 214-2 of the adjacent third pixel circuit 204_N+2 to a respective second split floating diffusion FD_2 of the adjacent third pixel circuit 204_N+2. The second shared gate structure 230-2 enables the gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the first pixel circuit 204_N and the gate (e.g., a gate electrode) of the second transfer transistor TX2 216-2 of the adjacent third pixel circuit 204_N+2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a second transfer control signal.

[0041] The fourth shared gate structure 230-4 includes a gate (e.g., a gate structure) of a fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N and a gate (e.g., a gate structure) of a fourth transfer transistor TX4 216-4 of an adjacent third pixel circuit 204_N+2. The gate (e.g., a gate structure) of the fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N and the gate (e.g., a gate structure) of the fourth transfer transistor TX4 216-4 of the adjacent third pixel circuit 204_N+2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate (e.g., a gate electrode) of the fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N is configured to couple the fourth photodiode PD4 214-4 to a second split floating diffusion region FD_2 218-2. The gate (e.g., a gate electrode) of the fourth transfer transistor TX4 216-4 of the adjacent third pixel circuit 204_N+2 is configured to couple a respective fourth photodiode PD4 214-4 of the adjacent third pixel circuit 204_N+2 to a respective second split floating diffusion region FD_2 of the adjacent third pixel circuit 204_N+2. The fourth shared gate structure 230-4 enables the gate (e.g., a gate structure) of the fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N and the gate (e.g., a gate structure) of the fourth transfer transistor TX4 216-4 of the adjacent third pixel circuit 204_N+2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a fourth transfer control signal.

[0042] As shown in the depicted example, the first pixel circuit 204_N also includes a first source follower transistor SF 220-1 disposed in the semiconductor material 260 between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. A first conductor 232-1 is disposed over and coupled to the gate of the first source follower transistor SF 220-1 and the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 by respective contacts. As such, the gate of the first source follower transistor SF 220-1 is coupled to the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 by the first conductor 232-1. It should be appreciated that since the gate of the first source follower transistor SF 220-1 is in relatively close proximity to the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 (as shown), the routing of the first conductor 232-1 is relatively short and simple, which helps to allow a relatively small pitch of the pixel circuit. For example, in one example, the width of each of the first, second, and third pixel circuits 204_N, 204_N-2, 204_N+2 is approximately only 0.5um. In other examples, it should be appreciated that the pitch of the first, second, and third pixel circuits 204_N, 204_N-2, 204_N+2 can have different values. Additionally, it should be appreciated that the shorter length and lower parasitic capacitance of the first conductor 232-1 associated with the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 provides, in accordance with the teachings of this disclosure, for the first pixel circuit 204_N to have a higher conversion gain. Continuing with the depicted example, the first pixel circuit 204_N also includes a first row select transistor RS 222-1 coupled to the first source follower transistor SF 220-1 such that the first source follower transistor SF 220-1 and the first row select transistor RS 222-1 are coupled between the power line AVDD and the bit line BL 212. The first row select transistor RS 222-1 can be disposed in the semiconductor material 260 between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. The first source follower transistor SF 220-1 and the first row select transistor RS 222-1 can be arranged in a vertical direction (e.g., y-direction) in the region between the first and third photodiodes PD1 214-1, PD3 214-3 and the second and fourth photodiodes PD2 214-2, PD4 214-4 of the first pixel circuit 204_N.

[0043] In Figure 2AIn the depicted example, the first pixel circuit 204_N also includes a first reset transistor RST 224-1 coupled between the power line AVDD and the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. As shown, the first conductor 232-1 is further coupled between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 and to the gate of the first source follower transistor SF 220-1 and the source of the first reset transistor RST 224-1.

[0044] Continuing Figure 2A In the depicted example, the first pixel circuit 204_N further includes fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 disposed in the semiconductor material 260 and configured to photo generate charges in response to incident light. As shown in the example, fifth, sixth, seventh, and eighth transfer transistors TX5 216-5, TX6 216-6, TX7 216-7, and TX8 216-8 are coupled to the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8, respectively. The third split floating diffusion region FD_3 218-3 is coupled to receive charges photo generated by the fifth and seventh photodiodes PD5 214-5 and PD7 214-7 by the fifth and seventh transfer transistors TX5 216-5 and TX7 216-7, respectively. Similarly, the fourth split floating diffusion region FD_4 218-4 is coupled to receive charges photo generated by the sixth and eighth photodiodes PD6 214-6 and PD8 214-8 by the sixth and eighth transfer transistors TX6 216-6 and TX8 216-8, respectively.

[0045] As shown in the depicted example, the first pixel circuit 204_N further includes a fifth, a sixth, a seventh, and an eighth shared gate structure 230-5, 230-6, 230-7, and 230-8. The fifth shared gate structure 230-5 includes a gate of a fifth transfer transistor TX5 216-5 of the first pixel circuit 204_N and a gate of a fifth transfer transistor TX5 216-5 of an adjacent second pixel circuit 204_N-2. The gate of the fifth transfer transistor TX5 216-5 of the first pixel circuit 204_N and the gate of the fifth transfer transistor TX5 216-5 of the adjacent second pixel circuit 204_N-2 can be formed from a single gate structure, such as a monolithic gate structure. The gate of the fifth transfer transistor TX5 216-5 of the first pixel circuit 204_N is configured to couple a fifth photodiode PD5 214-5 to a third split floating diffusion FD_3 218-3 of the first pixel circuit 204_N. The gate of the fifth transfer transistor TX5 216-5 of the adjacent second pixel circuit 204_N-2 is configured to couple a respective fifth photodiode PD5 214-5 to a respective third split floating diffusion FD_3 218-3 of the adjacent second pixel circuit 204_N-2. The fifth shared gate structure 230-5 enables the gate of the fifth transfer transistor TX5 216-5 of the first pixel circuit 204_N and the gate of the fifth transfer transistor TX5 216-5 of the adjacent second pixel circuit 204_N-2 to share a single metal interconnect, such as a signal metal 1 interconnect, coupled to receive a fifth transfer control signal.

[0046] The seventh shared gate structure 230-7 includes a gate of a seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N and a gate of a seventh transfer transistor TX7 216-7 of an adjacent second pixel circuit 204_N-2. The gate of the seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N and the gate of the seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate of the seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N is configured to couple a seventh photodiode PD7 214-7 to a third split floating diffusion FD_3 218-3 of the first pixel circuit 204_N. The gate of the seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2 is configured to couple a respective seventh photodiode PD7 214-7 to a respective third split floating diffusion FD_3 218-3 of the adjacent second pixel circuit 204_N-2. The seventh shared gate structure 230-7 enables the gate of the seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N and the gate of the seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a seventh transfer control signal.

[0047] The sixth shared gate structure 230-6 includes a gate of a sixth transfer transistor TX6 216-6 of the first pixel circuit 204_N and a gate of a sixth transfer transistor TX6 216-6 of a third pixel circuit 204_N+2. The gate (e.g., gate electrode) of the sixth transfer transistor TX6 216-6 of the first pixel circuit 204_N and the gate of the sixth transfer transistor TX6 216-6 of the adjacent third pixel circuit 204_N+2 can be formed from a single gate structure (e.g., a monolithic gate structure). The gate (e.g., gate electrode) of the sixth transfer transistor TX6 216-6 of the first pixel circuit 204_N is configured to couple a sixth photodiode PD6 214-6 to a fourth split floating diffusion FD_4 218-4 of the first pixel circuit 204_N. The gate of the sixth transfer transistor 216-6 of the adjacent third pixel circuit 204_N+2 is configured to couple a respective sixth photodiode PD6 214-6 to a respective fourth split floating diffusion FD_4 218-4 of the adjacent third pixel circuit 204_N+2. The sixth shared gate structure 230-6 enables the gate (e.g., gate electrode) of the sixth transfer transistor TX6 216-6 of the first pixel circuit 204_N and the gate of the sixth transfer transistor 216-6 of the adjacent third pixel circuit 204_N+2 to share a single metal interconnect (e.g., a signal metal 1 interconnect) coupled to receive a sixth transfer control signal.

[0048] The eighth shared gate structure 230-8 includes a gate of the eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N and a gate of the eighth transfer transistor TX8 216-8 of the third pixel circuit 204_N+2. The gate of the eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N and the gate of the eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2 can be formed from a single gate structure, such as a monolithic gate structure. The gate of the eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N is configured to couple the eighth photodiode PD8 214-8 to the fourth split floating diffusion region FD_4 218-4 of the first pixel circuit 204_N. The gate of the eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2 is configured to couple the respective eighth photodiode PD8 214-8 to the respective fourth split floating diffusion region FD_4 218-4 of the third pixel circuit 204_N+2. The eighth shared gate structure 230-8 enables the gate of the eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N and the gate of the eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2 to share a single metal interconnect (such as a signal metal 1 interconnect) coupled to receive an eighth transfer control signal.

[0049] Figure 2A The example depicted in FIG. 2B shows that the first pixel circuit 204_N further includes a second source follower transistor SF2 220-2 disposed in the semiconductor material 260 between the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. A second conductor 232-2 is disposed over the gate of the second source follower transistor SF2 220-2 and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 by respective contacts. The gate of the second source follower transistor is coupled to the third and fourth split floating diffusion regions by the second conductor 232-2. As such, the gate of the second source follower transistor SF2 220-2 is coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 by the second conductor 232-2. It will be appreciated that because the gate of the second source follower transistor SF2 220-2 is in relatively close proximity to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 (as shown), the routing of the second conductor 232-2 is relatively short and simple, which helps to allow a relatively small pitch of the pixel circuit and reduces parasitic capacitance associated with the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4, which is beneficial for high conversion gain operation associated with the first pixel circuit 204_N.

[0050] Continuing with the depicted example, the first pixel circuit 204_N also includes a second row select transistor RS 222-2 coupled to a second source follower transistor SF 220-2. The second source follower transistor SF 220-2 and the second row select transistor RS 222-2 are coupled between the power line AVDD and the bit line 212. In an example, a second reset transistor RST 224-2 is coupled between the power line AVDD and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. In an example, a second conductor 232-2 is further coupled between the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 and the second reset transistor RST 224-2. The second row select transistor RS 222-2 can be disposed in the semiconductor material 260 between the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. The second source follower transistor SF 220-2 and the second row select transistor RS 222-2 can be arranged in a vertical direction (e.g., y-direction) in a region between the fifth and seventh photodiodes PD5 214-5, PD7 214-7 and the sixth and eighth photodiodes PD6 214-6, PD8 214-8 of the first pixel circuit 204_N.

[0051] As Figure 2A As shown in the example depicted in FIG. 2, the first pixel circuit 204_N further includes a dual floating diffusion transistor 226 coupled between the first conductor 232-1 and the second conductor 232-2. As such, the dual floating diffusion transistor 226 is coupled between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Thus, when the dual floating diffusion transistor 226 is off, the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are not coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4, and when the dual floating diffusion transistor 226 is on, the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4.

[0052] Thus, when the dual floating diffusion transistor 226 is turned on, the charge in the first, second, third, and fourth split floating diffusion regions FD_1 218-1, FD_2 218-2, D_3 218-3, and FD_4 218-4 is merged because the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Accordingly, a low conversion gain readout can be obtained from the first pixel circuit 204_N when the dual floating diffusion transistor 226 is turned on. Further, in various examples, a 2x2 or 2x4 merged readout of the first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 and / or the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 can be obtained from the first pixel circuit 204_N when the dual floating diffusion transistor 226 is turned on.

[0053] Further, when the dual floating diffusion transistor 226 is turned off, the charge in the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 is not merged with the charge in the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Accordingly, a high conversion gain 2x2 readout of the first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 or the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 can be obtained from the first pixel circuit 204_N when the dual floating diffusion transistor 226 is turned off.

[0054] Figure 2B FIGS. 1-3 illustrate example pixel circuits 204_N, 204_N-2, 204_N+2, 204_N+4, etc. having shared gate structures and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure. It should be appreciated that the pixel circuits 204_N, 204_N-2, 204_N+2, 204_N+4, etc. of FIGS. 1-3 correspond to the pixel circuits 204_N, 204_N-2, 204_N+2, 204_N+4, etc. depicted in FIGS. 1-3, which can also be included in the pixel array 202 of FIG. 1. Figure 2B Figure 2A Figure 1 ​​The example shown in FIG. 2A is illustrative of a first pixel circuit 204_N in a pixel array 102. Accordingly, like-named and numbered elements described above are similarly coupled and operate below. As can be observed in various examples, the first pixel circuit 204_N, the second pixel circuit 204_N-2, and the third pixel circuit 204_N+2 are substantially similar to one another. As such, it should be appreciated that the description of features and functions in the first pixel circuit 204_N can apply to corresponding features and functions in other pixel circuits included in the pixel array, including the second pixel circuit 204_N-2 and the third pixel circuit 204_N+2.

[0055] As Figure 2B As shown in the example depicted in FIG. 2A, the first pixel circuit 204_N is disposed in a semiconductor material 260 between the second pixel circuit 204_N-2 and the third pixel circuit 204_N+2. As shown, the first pixel circuit 204_N includes at least first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 disposed in the semiconductor material 260 and configured to photo generate charges in response to incident light. At least first, second, third, and fourth transfer transistors TX1 216-1, TX2 216-2, TX3 216-3, and TX4 216-4 are coupled to the first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4, respectively. At least first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are disposed in the semiconductor material 260. The first split floating diffusion region FD_1 218-1 is coupled to receive charges photo generated by the first and third photodiodes PD1 214-1 and PD3 214-3 through the first and third transfer transistors TX1 216-1 and TX3 216-3, respectively. Similarly, the second split floating diffusion region FD_2 218-2 is coupled to receive charges photo generated by the second and fourth photodiodes PD2 214-2 and PD4 214-4 through the second and fourth transfer transistors TX2 216-2 and TX4 216-4, respectively.

[0056] Continuing Figure 2BThe first pixel circuit 204_N also includes at least first, second, third, and fourth shared gate structures SGS 230-1, 230-2, 230-3, and 230-4 in the depicted example. The first shared gate structure SGS 230-1 includes a gate (e.g., gate electrode) of a first transfer transistor TX1 216-1 of the first pixel circuit 204_N and a gate (e.g., gate electrode) of a first transfer transistor TX1 216-1 of an adjacent second pixel circuit 204_N-2. The third shared gate structure SGS 230-3 includes a gate (e.g., gate electrode) of a third transfer transistor TX3 216-3 of the first pixel circuit 204_N and a gate (e.g., gate electrode) of a third transfer transistor TX3 216-3 of the adjacent second pixel circuit 204_N-2. The second shared gate structure SGS 230-2 includes a gate (e.g., gate electrode) of a second transfer transistor TX2 216-2 of the first pixel circuit 204_N and a gate (e.g., gate electrode) of a second transfer transistor TX2 216-2 of an adjacent third pixel circuit 204_N+2. The fourth shared gate structure SGS 230-4 includes a gate (e.g., gate structure) of a fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N and a gate (e.g., gate structure) of a fourth transfer transistor TX4 216-4 of the adjacent third pixel circuit 204_N+2.

[0057] As shown in the depicted example, the first pixel circuit 204_N also includes a first source follower transistor SF 220-1 disposed in the semiconductor material 260 between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. A first conductor 232-1 is coupled to a gate of the first source follower transistor SF 220-1 and the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. In an example, the first pixel circuit 204_N also includes a first row select transistor RS 222-1 coupled to the first source follower transistor SF 220-1 such that the first source follower transistor SF 220-1 and the first row select transistor RS 222-1 are coupled between a power line AVDD and a bit line BL 212. The first pixel circuit 204_N also includes a first reset transistor RST 224-1 coupled between the power line AVDD and the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2. As shown, the first conductor 232-1 is further coupled between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 and to the gate of the first source follower transistor SF 220-1 and the first reset transistor RST 224-1 (e.g., a source of the first reset transistor RST 224-1).

[0058] Continuing Figure 2B As shown in the depicted example, the first pixel circuit 204_N further includes fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 disposed in the semiconductor material 260 and configured to photogenerate charges in response to incident light. As shown in the example, fifth, sixth, seventh, and eighth transfer transistors TX5 216-5, TX6 216-6, TX7 216-7, and TX8 216-8 are coupled to the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8, respectively. A third split floating diffusion region FD_3 218-3 is coupled to receive charges photogenerated by the fifth and seventh photodiodes PD5 214-5 and PD7 214-7 by the fifth and seventh transfer transistors TX5 216-5 and TX7 216-7, respectively. Similarly, a fourth split floating diffusion region FD_4 218-4 is coupled to receive charges photogenerated by the sixth and eighth photodiodes PD6 214-6 and PD8 214-8 by the sixth and eighth transfer transistors TX6 216-6 and TX8 216-8, respectively.

[0059] As shown in the depicted example, the first pixel circuit 204_N further includes fifth, sixth, seventh, and eighth shared gate structures SGS 230-5, 230-6, 230-7, and 230-8. The fifth shared gate structure SGS 230-5 includes a gate (e.g., a gate electrode) of the fifth transfer transistor TX5 216-5 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of the fifth transfer transistor TX5 216-5 of the adjacent second pixel circuit 204_N-2. The seventh shared gate structure SGS 230-7 includes a gate (e.g., a gate electrode) of the seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of the seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2. The sixth shared gate structure SGS 230-6 includes a gate (e.g., a gate electrode) of the sixth transfer transistor TX6 216-6 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of the sixth transfer transistor TX6 216-6 of the adjacent third pixel circuit 204_N+2. The eighth shared gate structure SGS 230-8 includes a gate (e.g., a gate electrode) of the eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N and a gate (e.g., a gate electrode) of the eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2.

[0060] Figure 2B The depicted example shows that the first pixel circuit 204_N further includes a second source follower transistor SF 220-2 disposed in semiconductor material 260 between the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. A second conductor 232-2 is disposed over the gate of the second source follower transistor SF 220-2 and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 by a respective contact. The gate of the second source follower transistor is coupled to the third and fourth split floating diffusion regions by the second conductor 232-2. As such, the gate of the second source follower transistor SF 220-2 is coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 by the second conductor 232-2. It should be appreciated that because the gate of the second source follower transistor SF 220-2 is in relatively close proximity to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 (as shown), the routing of the second conductor 232-2 is relatively short and simple, which helps to allow a relatively small pitch of the pixel circuit and reduces parasitic capacitance associated with the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4, which is beneficial for high conversion gain operation associated with the first pixel circuit 204_N.

[0061] Continuing with the depicted example, the first pixel circuit 204_N also includes a second row select transistor RS 222-2 coupled to the second source follower transistor SF 220-2. The second source follower transistor SF 220-2 and the second row select transistor RS 222-2 are coupled between the power line AVDD and the bit line 212. In an example, a second reset transistor RST 224-2 is coupled between the power line AVDD and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. In an example, the second conductor 232-2 is further coupled between the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 and the second reset transistor RST 224-2 (e.g., the source of the second reset transistor RST 224-2).

[0062] As Figure 2BAs shown in the example depicted in the middle, the first pixel circuit 204_N further includes a double-floated diffusion transistor 226 coupled between the first conductor 232-1 and the second conductor 232-2. As such, the double-floated diffusion transistor 226 is coupled between the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 and the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Thus, when the double-floated diffusion transistor 226 is off, the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are not coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4, and when the double-floated diffusion transistor 226 is on, the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4.

[0063] As such, when the double-floated diffusion transistor 226 is on, the charge in the first, second, third, and fourth split floating diffusion regions FD_1 218-1, FD_2 218-2, D_3 218-3, and FD_4 218-4 is merged because the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 are coupled to the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Thus, a low conversion gain readout can be obtained from the first pixel circuit 204_N when the double-floated diffusion transistor 226 is on. Further, in various examples, a 2x2 or 2x4 merged readout of the first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 and / or the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 can be obtained from the first pixel circuit 204_N when the double-floated diffusion transistor 226 is on.

[0064] In addition, when the dual floating diffusion transistor 226 is turned off, the charge in the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 does not merge with the charge in the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4. Thus, a high conversion gain 2x2 readout of the first, second, third, and fourth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, and PD4 214-4 or the fifth, sixth, seventh, and eighth photodiodes PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8 can be obtained from the first pixel circuit 204_N when the dual floating diffusion transistor 226 is turned off.

[0065] In the illustrated example, the first shared gate structure SGS 230-1 is coupled to receive a first transfer control signal TX_N_O 234-1. In an example, the first transfer control signal TX_N_O 234-1 is coupled to be received by shared gate structures (e.g., SGS 230-1, etc.) in "odd" columns of shared gate structures in the pixel array in the same row as the first and second shared gate structures SGS 230-1 and SGS 230-2. Similarly, the second shared gate structure SGS 230-2 is coupled to receive a second transfer control signal TX_N_E 234-2. In an example, the second transfer control signal TX_N_E 234-2 is coupled to be received by shared gate structures (e.g., SGS 230-2, etc.) in "even" columns of shared gate structures in the pixel array in the same row as the first and second shared gate structures SGS 230-1 and SGS 230-2.

[0066] Continuing with the depicted example, the third shared gate structure SGS 230-3 is coupled to receive a third transfer control signal TX_N+1_O 234-3. In the depicted example, the third transfer control signal TX_N+1_O 234-3 is coupled to be received by shared gate structures (e.g., SGS 230-3, etc.) in "odd" columns of shared gate structures in the pixel array in the same row as the third and fourth shared gate structures SGS 230-3 and SGS 230-4. In an example, the fourth shared gate structure SGS 230-4 is coupled to receive a fourth transfer control signal TX_N+1_E 234-4. In the depicted example, the fourth transfer control signal TX_N+1 234-4 is coupled to be received by shared gate structures (e.g., SGS 230-4, etc.) in even columns of shared gate structures in the pixel array in the same row as the third and fourth shared gate structures SGS 230-3 and SGS 230-4.

[0067] Continuing with the depicted example, the fifth shared gate structure SGS 230-5 is coupled to receive a fifth transfer control signal TX_N+2_0 234-5. In an example, the fifth transfer control signal TX_N+2_0 234-5 is coupled to be received by shared gate structures in "odd" columns of shared gate structures in the pixel array in the same row as the fifth and sixth shared gate structures SGS 230-5 and SGS 230-6 (e.g., SGS 230-5, etc.). Similarly, the sixth shared gate structure SGS 230-6 is coupled to receive a sixth transfer control signal TX_N+2_E 234-6. In an example, the sixth transfer control signal TX_N+2_E 234-6 is coupled to be received by shared gate structures in "even" columns of shared gate structures in the pixel array in the same row as the fifth and sixth shared gate structures SGS 230-5 and SGS 230-6 (e.g., SGS 230-6, etc.).

[0068] Continuing with the depicted example, the seventh shared gate structure SGS 230-7 is coupled to receive a seventh transfer control signal TX_N+3_0 234-7. In the depicted example, the seventh transfer control signal TX_N+3_0 234-7 is coupled to be received by shared gate structures in "odd" columns of shared gate structures in the pixel array in the same row as the seventh and eighth shared gate structures SGS 230-7 and SGS 230-8 (e.g., SGS 230-7, etc.). In an example, the eighth shared gate structure SGS 230-8 is coupled to receive an eighth transfer control signal TX_N+3_E 234-8. In the depicted example, the eighth transfer control signal TX_N+3_E 234-8 is coupled to be received by shared gate structures in even columns of shared gate structures in the pixel array in the same row as the seventh and eighth shared gate structures SGS 230-7 and SGS 230-8 (e.g., SGS 230-8, etc.).

[0069] Thus, the first transfer transistor TXI 216-1 of the first pixel circuit 204_N (and the first transfer transistor TXI 216-1 of the adjacent second pixel circuit 204_N-2) is coupled to be controlled in response to a first transfer control signal TX_N_O 234-1. During a readout operation, charge photo-generated in the first photodiode PD1 214-1 is configured to be transferred from the first photodiode PD1 214-1 through the first transfer transistor TXI 216-1 to the first split floating diffusion region FD_1 218-1 in response to the first transfer control signal TX_N_O 234-1. The second transfer transistor TX2 216-2 of the first pixel circuit 204_N (and the second transfer transistor TX2 216-2 of the adjacent third pixel circuit 204_N+2) is coupled to be controlled in response to a second transfer control signal TX_N_E 234-2. During a readout operation, charge photo-generated in the second photodiode PD2 214-2 is configured to be transferred from the photodiode PD2 214-2 through the second transfer transistor TX2 216-2 to the second split floating diffusion region FD_2 218-2 in response to the second transfer control signal TX_N_E 234-2.

[0070] Similarly, the third transfer transistor TX3 216-3 of the first pixel circuit 204_N (and the third transfer transistor TX3 216-3 of the adjacent second pixel circuit 204_N-2) is coupled to be controlled in response to a third transfer control signal TX_N+1_O 234-3. During a readout operation, charge photo-generated in the third photodiode PD3 214-3 is configured to be transferred from the third photodiode PD3 214-3 through the third transfer transistor TX3 216-3 to the first split floating diffusion region FD_1 218-1 in response to the third transfer control signal TX_N+1_O 234-3. The fourth transfer transistor TX4 216-4 of the first pixel circuit 204_N (and the fourth transfer transistor TX4 216-4 of the adjacent third pixel circuit 204_N+2) is coupled to be controlled in response to a fourth transfer control signal TX_N+1_E 234-4. During a readout operation, charge photo-generated in the fourth photodiode PD4 214-4 is configured to be transferred from the fourth photodiode PD4 214-4 through the fourth transfer transistor TX4 216-4 to the second split floating diffusion region FD_2 218-2 in response to the fourth transfer control signal TX_N+1_E 234-4.

[0071] Similarly, a seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N (and a seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2) is coupled to be controlled in response to a seventh transfer control signal TX_N+3_0 234-7. During a readout operation, charge photo-generated in a seventh photodiode PD7 214-7 is configured to be transferred from the seventh photodiode PD7 214-7 through the seventh transfer transistor TX7 216-7 to the third split floating diffusion region FD_3 218-3 in response to the seventh transfer control signal TX_N+3_0 234-7. An eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N (and an eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2) is coupled to be controlled in response to an eighth transfer control signal TX_N+3_E 234-8. During a readout operation, charge photo-generated in an eighth photodiode PD8 214-8 is configured to be transferred from the eighth photodiode PD8 214-8 through the eighth transfer transistor TX8 216-8 to the fourth split floating diffusion region FD_4 218-4 in response to the eighth transfer control signal TX_N+3_E 234-8.

[0072] Similarly, a seventh transfer transistor TX7 216-7 of the first pixel circuit 204_N (and a seventh transfer transistor TX7 216-7 of the adjacent second pixel circuit 204_N-2) is coupled to be controlled in response to a seventh transfer control signal TX_N+3_0 234-7. During a readout operation, charge photo-generated in a seventh photodiode PD7 214-7 is configured to be transferred from the seventh photodiode PD7 214-7 through the seventh transfer transistor TX7 216-7 to the third split floating diffusion region FD_3 218-3 in response to the seventh transfer control signal TX_N+3_0 234-7. An eighth transfer transistor TX8 216-8 of the first pixel circuit 204_N (and an eighth transfer transistor TX8 216-8 of the adjacent third pixel circuit 204_N+2) is coupled to be controlled in response to an eighth transfer control signal TX_N+3_E 234-8. During a readout operation, charge photo-generated in an eighth photodiode PD8 214-8 is configured to be transferred from the eighth photodiode PD8 214-8 through the eighth transfer transistor TX8 216-8 to the fourth split floating diffusion region FD_4 218-4 in response to the eighth transfer control signal TX_N+3_E 234-8.

[0073] According to the teachings of this disclosure, in operation, the dual floating diffusion transistor 226 can be turned off and the first row select transistor RS 222-1 is coupled to output a high conversion gain signal (e.g., image data) from the first source follower transistor SF 220-1 of the first pixel circuit 204_N to the bit line BL 212 in response to a row select control signal and charges in the first and second split floating diffusion regions FD_1 218-1 and FD_2 218-2 coupled to the gate of the first source follower transistor SF 220-1 by the first conductor 232-1. Similarly, according to the teachings of this disclosure, the dual floating diffusion transistor 226 can be turned off and the second row select transistor RS 222-2 is coupled to output a high conversion gain signal (e.g., image data) from the second source follower transistor SF 220-2 of the first pixel circuit 204_N to the bit line BL 212 in response to a row select control signal and charges in the third and fourth split floating diffusion regions FD_3 218-3 and FD_4 218-4 coupled to the gate of the second source follower transistor SF 220-2 by the second conductor 232-2.

[0074] In another example, according to the teachings of this disclosure, the dual floating diffusion transistor 226 can be turned on which merges the charges in the first, second, third, and fourth split floating diffusion regions FD_1 218-1, FD_2 218-2, FD_3 218-3, and FD_4 218-4 to provide a low conversion gain signal (e.g., image data) from the first source follower transistor SF 220-1 or the second source follower transistor SF 220-2 in response to the charges in the first, second, third, and fourth split floating diffusion regions FD_1 218-1, FD_2 218-2, FD_3 218-3, and FD_4 218-4 received from any one or more of the first, second, third, fourth, fifth, sixth, seventh, and / or eighth photodiodes PD1 214-1, PD2 214-2, PD3 214-3, PD4 214-4, PD5 214-5, PD6 214-6, PD7 214-7, and / or PD8 214-8.

[0075] Figure 3A A timing diagram illustrating example transfer control signals associated with a readout sequence for an example pixel circuit having a shared gate structure and split floating diffusion regions included in a pixel array according to the teachings of this disclosure is illustrated. It should be appreciated that the transfer control signals and readout sequence depicted in FIGS. 1A-1B can be Figure 3A Examples of transfer control signals and readout sequences for the pixel circuits depicted in FIGS. 2A-2B are illustrated in FIGS. 3A-3B, respectively, and the similarly named and numbered elements described above are similarly coupled and operate below. Figure 1 , 2A Examples of transfer control signals and readout sequences for the pixel circuits depicted in FIGS. 2A-2B are illustrated in FIGS. 3A-3B, respectively, and the similarly named and numbered elements described above are similarly coupled and operate below.

[0076] As shown in the depicted example, a first transfer control signal TX N O 334-1 is configured to read out the pixel circuits in a first readout period, and then a second transfer control signal TX N E 334-2 is configured to read out the pixel circuits in a second readout period, and then a third transfer control signal TX N+1 O 334-3 is configured to read out the pixel circuits in a third readout period, and then a fourth transfer control signal TX N+1 E 334-4 is configured to read out the pixel circuits in a fourth readout period, and so on. It will be appreciated that, for brevity, Figure 3A only four readout periods are depicted in the example shown in FIG. 2B, and fifth, sixth, seventh, eighth, etc. readout periods can thus follow. As shown, the second readout period occurs after the first readout period, and the third readout period occurs after the second readout period, and the fourth readout period occurs after the third readout period. In one example, the cycle of readout periods repeats to read out the pixel circuits included in the pixel array. In one example, the first and third transfer control signals TX N O 334-1 and TX N+1 O 334-3 are configured to control readout of the first and third photodiodes (e.g., PD1, PD3) in odd columns of the pixel array, and the second and fourth transfer control signals TX N E 334-2 and TX N+1 E 334-4 are configured to control readout of the second and fourth photodiodes (e.g., PD2, PD4) in even columns of the pixel array. In one example, it will be appreciated that the fifth and seventh transfer control signals TX N+2 O 334-5 and TX N+3 O 334-7 are configured to control readout of the fifth and seventh photodiodes (e.g., PD5, PD7) in odd columns of the pixel array, and the sixth and eighth transfer control signals TX N+2 E 334-6 and TX N+3 E 334-8 are configured to control readout of the sixth and eighth photodiodes (e.g., PD6, PD8) in even columns of the pixel array.

[0077] To illustrate, Figure 3B A first readout period of an example pixel array 302 having pixel circuits with shared gate structures and split floating diffusion regions in accordance with the teachings of this disclosure is illustrated. It will be appreciated that, Figure 3B The pixel array 302 depicted in FIG. 2A can be Figure 1 One example of the pixel array 102 depicted in FIG. 1A, and the pixel circuits included in the pixel array 302 can be Figure 1 , 2A The example pixel circuits depicted in FIGS. 2A-2B, and the above similarly named and numbered elements are similarly coupled and operate below.

[0078] For example, as Figure 3BAs shown in FIG. 3, pixel array 302 includes an array of pixel circuits including pixel circuit 304_N disposed between neighboring pixel circuits 304_N-2 and 304_N+2. In an example, each of pixel circuits 304_N-2, 304_N, 304_N+2 includes eight photodiodes labeled 1, 2, 3, 4, 5, 6, 7, and 8 (which correspond to Figure 2A to 2B PD1 214-1, PD2 214-2, PD3 214-3, PD4 214-4, PD5 214-5, PD6 214-6, PD7 214-7, and PD8 214-8) in FIG. 3. In an example, photodiodes 1, 3, 5, and 7 in each of pixel circuits 304_N-2, 304_N, 304_N+2 are configured to be controlled in response to odd transfer control signals TX_N_O 334-1, TX_N+1_O 334-3, TX_N+2_O 334-5, TX_N+3_O 334-7, and photodiodes 2, 4, 6, and 8 in each of pixel circuits 304_N-2, 304_N, 304_N+2 are configured to be controlled in response to even transfer control signals TX_N_E 334-2, TX_N+1_E 334-4, TX_N+2_E 334-6, TX_N+3_E 334-8.

[0079] Figure 3B The example depicted in FIG. 3 illustrates a first readout period during which first photodiode 1 (e.g., PD1 214-1) of each of pixel circuits 304_N-2, 304_N, 304_N+2 is configured to be read out in response to first transfer control signal TX_N_O 334-1, as described above Figure 3A with respect to FIG. 2. It should be appreciated that each first photodiode 1 (e.g., PD1 214-1) of each pixel circuit 304_N-2, 304_N, 304_N+2 is read out in synchronization with the corresponding first photodiode 1 (e.g., PD1 214-1) of the neighboring pixel circuit 304_N-2, 304_N, 304_N+2 according to the teachings of this disclosure because the shared gate structure (e.g., SGS 230-1) is coupled to control the first transfer transistor TX1 (e.g., TX1 216-1) of the neighboring pixel circuit 304_N-2, 304_N, 304_N+2.

[0080] Figure 3C illustrates a second readout period of example pixel array 302 having pixel circuits with shared gate structures and split floating diffusion regions according to the teachings of this disclosure. Similar to Figure 3B , it should be appreciated that, Figure 3C pixel array 302 depicted in FIG. 3 is also Figure 1One example of the pixel array 102 depicted in FIG. 1A, and the pixel circuits included in the pixel array 302 can be Figure 1 , 2A the pixel circuit depicted in FIG. 2B, and the above similarly named and numbered elements are similarly coupled and operate below.

[0081] Figure 3C A second readout period of the example pixel array 302 having pixel circuits with shared gate structures and split floating diffusion regions in accordance with the teachings of this disclosure is illustrated. As shown, during the second readout period, the second photodiode 2 (e.g., PD2 214-2) of each of the pixel circuits 304_N-2, 304_N, 304_N+2 is configured to be read out in response to a second transfer control signal TX_N_E 334-2 as described above Figure 3A in FIG. 2B. As shown, it should be appreciated that in accordance with the teachings of this disclosure, each second photodiode 2 (e.g., PD2 214-2) of each pixel circuit 304_N-2, 304_N, 304_N+2 is read out in synchronization with the corresponding second photodiode 2 (e.g., PD2 214-2) of the adjacent pixel circuits 304_N-2, 304_N, 304_N+2 because the shared gate structure (e.g., SGS 230-2) is coupled to control the second transfer transistor TX2 (e.g., TX2 216-2) of the adjacent pixel circuits 304_N-2, 304_N, 304_N+2. It should be appreciated that each third photodiode 3 (e.g., PD3 214-3), fourth photodiode 4 (e.g., PD4 214-4), fifth photodiode 5 (e.g., PD5 214-5), sixth photodiode 6 (e.g., PD6 214-6), seventh photodiode 7 (e.g., PD7 214-7), and eighth photodiode 8 (e.g., PD8 214-8) are similarly read out in response to a third transfer control signal TX_N+1_O 334-3, a fourth transfer control signal TX_N+1_E 334-4, a fifth transfer control signal TX_N+2_O 334-5, a sixth transfer control signal TX_N+2_E 334-6, a seventh transfer control signal TX_N+3_O 334-7, and an eighth transfer control signal TX_N+3_E 334-8 during the third, fourth, fifth, sixth, seventh, and eighth readout periods, respectively, that follow.

[0082] Figure 4 A cross-sectional view of an example pixel circuit 404 having a shared gate structure and split floating diffusion regions included in a pixel array in accordance with the teachings of this disclosure is illustrated. It should be appreciated that the pixel circuit 404 depicted in FIG. 4 can be the pixel circuit 404 described above in FIG. 3 Figure 4 , Figure 1 2A ​2B, 3B to 3C, and similarly named and numbered elements described above are similarly coupled and operate below.

[0083] In particular, it should be understood that the cross-sectional view of the example pixel circuit 404 depicted in the cross-sectional view of the example pixel circuit 404 is taken along Figure 2A The cross-sectional view of the dotted line A-A' is shown in FIG. Figure 4 , pixel circuit 404 includes a plurality of photodiodes including a first photodiode PD1 414-1 and a second photodiode PD2 414-2 disposed in a semiconductor substrate or semiconductor material 460. In one example, first photodiode PD1 414-1 and second photodiode PD2 414-2 include N-type doped semiconductor material. In the example, first photodiode PD1 414-1 and second photodiode PD2 414-2 are configured to photogenerate charge in response to incident light.

[0084] A first split floating diffusion region FD_1 418-1 and a second split floating diffusion region FD_2 418-2 are disposed in semiconductor material 460 and are configured to store charge photogenerated in the first photodiode PD1 414-1 and the second photodiode PD2 414-2, respectively. In the depicted example, charge photogenerated in the first photodiode PD1 414-1 is configured to be transferred to the first split floating diffusion region FD_1 418-1 via a first transfer transistor TX1 416-1, and charge photogenerated in the second photodiode PD2 414-2 is configured to be transferred to the second split floating diffusion region FD_2 418-2 via a second transfer transistor TX2 416-2.

[0085] As shown in the depicted example, the first shared gate structure SGS 430-1 includes the gate electrode of the first transfer transistor TX1 416-1 and the second shared gate structure SGS 430-2 includes the gate electrode of the second transfer transistor TX2 416-2. In the depicted example, the gate electrode of the first transfer transistor TX1 416-1 and the gate electrode of the second transfer transistor TX2 416-2 are disposed on a surface of the semiconductor material 460. As shown in the depicted example, the first source follower transistor SF 420-1 is disposed in the semiconductor material 460 between the first split floating diffusion region FD_1 418-1 and the second split floating diffusion region FD_2 418-2. In the depicted example, the gate electrode of the first source follower transistor SF 420-1 is also disposed on a surface of the semiconductor material 460. In an example, a thin gate oxide 440 is disposed between the gate electrodes of the first and second transfer transistors TX1 416-1 and TX2 416-2 and the gate electrode of the first source follower transistor SF 420-1 and the surface of the semiconductor material 460. In one example, the thin gate oxide 440 has a thickness of about 30 to 80 Angstroms.

[0086] In the depicted example, the first conductor 432-1 is disposed over the gate of the first source follower transistor SF 420-1, the first split floating diffusion region FD_1 418-1, and the second split floating diffusion region FD_2 418-2, as shown. In an example, the first conductor 432-1 is implemented by a metal 1 interconnect disposed in an interlayer dielectric 438, which is disposed over the gate electrodes of the transistors and the surface of the semiconductor material 460, as shown. In an example, the first conductor 432-1 is coupled to the gate of the first source follower transistor SF 420-1, the first split floating diffusion region FD_1 418-1, and the second split floating diffusion region FD_2 418-2 by the interlayer dielectric 438, by the contacts 442, as shown. As such, the gate of the first source follower transistor SF 420-1 is coupled to the first and second split floating diffusion regions FD_1 418-1 and FD2 418-2 by their respective contacts 442 and the first conductor 432-1. In some embodiments, the first conductor 432-1 can not be disposed as a metal 1 interconnect, but can be a metal interconnect in other metal layers (e.g., metal 2) or within the interlayer dielectric 438. In some embodiments, the first conductor 432-1 can be a polysilicon-based interconnect embedded in the interlayer dielectric 438, such as an extension of the gate of the first source follower transistor SF 420-1. In the depicted example, the first shared gate structure SGS 430-1 is coupled to receive the first transfer control signal TX_N_O 434-1 and the second shared gate structure SGS 430-2 is coupled to receive the second transfer control signal TX_N_E 434-2 by the contacts 442, by the interlayer dielectric 438, as shown.

[0087] As shown in the depicted example, the pixel circuit 404 also includes a plurality of isolation structures. For example, as shown in the depicted example, the pixel circuit 404 includes a first isolation structure 440-1 and a second isolation structure 440-2. In an example, the first isolation structure 440-1 is disposed between the first source follower transistor SF 420-1 and the second source follower transistor SF 420-2, as shown. In an example, the second isolation structure 440-2 is disposed between the first source follower transistor SF 420-1 and the second source follower transistor SF 420-2, as shown. Figure 4, a first isolation structure is disposed in semiconductor material 460 between first split floating diffusion region FD_1 418-1 and the source / drain (e.g., S / D) regions of first source follower transistor SF 420-1, comprising a shallow trench isolation (e.g., STI) structure 444 disposed in well isolation region 436. A second isolation structure is also disposed in semiconductor material 460 between second split floating diffusion region FD_2 418-2 and the source / drain (e.g., S / D) regions of first source follower transistor SF 420-1, comprising a shallow trench isolation (e.g., STI) structure 444 disposed in well isolation region 436. In the example, shallow trench isolation (e.g., STI) structure 444 is disposed proximate a front side of semiconductor material 460. The depth of each shallow trench isolation (e.g., STI) structure 444 relative to a surface (e.g., a front surface) of the semiconductor material 460 may be greater than the junction depth of the first split floating diffusion region FD_1 418-1 or the second split floating diffusion region FD_2 418-2. The depth of each shallow trench isolation (e.g., STI) structure 444 may be greater than the junction depth of the source / drain regions of the first source follower transistor SF 420-1.

[0088] In the depicted example, additional isolation structures are also disposed in the semiconductor material 460 to isolate the photodiodes (including the first photodiode PD1 414-1 and the second photodiode PD2 414-2) from surrounding circuit elements. Figure 4 , a third isolation structure is disposed in semiconductor material 460 proximate to first photodiode PD1 414-1, which includes a deep trench isolation (e.g., DTI) structure 446 disposed in well isolation region 448, and a fourth isolation structure is disposed in semiconductor material 460 proximate to second photodiode PD2 414-2, which also includes a deep trench isolation (e.g., DTI) structure 446 disposed in well isolation region 448. In an example, deep trench isolation (e.g., DTI) structure 446 is disposed proximate to the back side of semiconductor material 460. Figure 4 In the example shown, photodiodes (e.g., PD1 414-1 and PD2 414-2) are disposed between a DTI structure 446 and respective first and second split floating diffusion regions FD_1 418-1 and FD2 418-2. Well isolation regions 436 and 448 are doped well regions having a conductivity type opposite to that of the photodiodes (e.g., PD1 414-1 and PD2 414-2), the source / drain (e.g., S / D) regions of the first source follower transistor SF 420-1, and the first split floating diffusion region FD_1 418-1 or the second split floating diffusion region FD_2 418-2. In the example, well isolation regions 436 and 448 include P-type doped semiconductor material.

[0089] Figure 5 Various example patterns of a color filter array disposed over pixel array 502, including an arrangement of pixel circuits having a shared gate structure and a split floating diffusion region, are illustrated in accordance with the teachings of the present invention. Figure 5 The example pixel array 502 and pixel circuitry depicted in FIG. 5 may be the same as those described above. Figure 1 、 2A 2B, 3B to 3C, 4, and similarly named and numbered elements described above are similarly coupled and operate below.

[0090] like Figure 5 As shown in the example depicted in , pixel array 502 includes an array of pixel circuits including pixel circuits 504_N, 504_N+2, 505_N, and 505_N+2. It should be understood that each of pixel circuits 504_N, 504_N+2, 505_N, and 505_N+2 is substantially similar to the pixel circuits discussed above. Thus, Figure 5 2, 505_N+2, 506_N+3, and 506_N+4. Each of the pixel circuits 504_N, 504_N+2, 505_N, and 505_N+2 shown in FIG. 5 includes a 2×4 arrangement of eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8, as shown. In an example, a color filter array is disposed above pixel array 502 such that each of the photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8 of each pixel circuit 504_N, 504_N+2, 505_N, and 505_N+2 is configured to be illuminated by incident light passing through a respective one of the color filters in the color filter array disposed above pixel array 502. In various examples, the color pixel array includes a mosaic of color filters arranged in a pattern, such as, for example, a Bayer filter, or the like.

[0091] exist Figure 5 In the illustrated example, the color filter array disposed over pixel array 502 includes a first color filter 550R disposed over pixel circuit 505_N, a second color filter 550G1 disposed over pixel circuit 505_N+2, a third color filter 550G2 disposed over pixel circuit 504_N, and a fourth color filter 550B disposed over pixel circuit 504_N+2. In the depicted example, first color filter 550R is a red (R) filter, and second and third color filters 550G1 and 550G2 are green filters. In one example, fourth color filter 550B may be a blue (B) filter. In another example, fourth color filter 550B may be a clear (CLR) filter. In yet another example, fourth color filter 550B may be an infrared (IR) filter.

[0092] It should be understood that in Figure 5 In each of the depicted examples, all eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8 of each respective pixel circuit 504_N, 504_N+2, 505_N, and 505_N+2 are configured to receive incident light that passes through the same respective one of the color filters 550G2, 550B, 550R, or 550G1. Thus, in the example where the fourth color filter 550B is a blue (B) color filter, all eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8 of the pixel circuit 504_N+2 are configured to receive incident light that has been filtered by the blue color filter 550B. Similarly, all eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8 of the pixel circuit 505_N are configured to receive incident light that has been filtered by the red color filter 550R. Similarly, all eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7 and PD8 of pixel circuit 504_N and all eight photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7 and PD8 of pixel circuit 504_N+2 are configured to receive incident light that has been filtered by green filters 550G1 and 550G2.

[0093] Figure 6A A plan view showing another exemplary layout of an arrangement of pixel circuits 604_N, 604_N-2, 604_N+2, 604_N+4 with a shared gate structure and a split floating diffusion region included in a pixel array according to the teachings of the present invention is shown. It should be understood that Figure 6A The pixel circuits 604_N, 604_N-2, 604_N+2, 604_N+4, etc. may also be included in Figure 1 , and similarly named and numbered elements are similarly coupled and operate hereinafter. In various examples, the first pixel circuit 604_N, the second pixel circuit 604_N-2, the third pixel circuit 604_N+2, and so on are substantially similar to each other. Thus, it should be understood that the description of features and functions in the first pixel circuit 604_N can be applied to corresponding features and functions in other pixel circuits included in the pixel array (including the second pixel circuit 604_N-2 and the third pixel circuit 604_N+2, and so on).

[0094] like Figure 6AAs shown in the depicted example, the first pixel circuit 604_N is disposed in the semiconductor material 660 between the second pixel circuit 604_N-2 and the third pixel circuit 604_N+2. In the depicted example, the width of the first pixel circuit 604_N, the second pixel circuit 604_N-2, and the third pixel circuit 604_N+2 can have a pixel pitch of 0.5 um. As shown, the first pixel circuit 604_N includes at least first, second, third, and fourth photodiodes PD1 614-1, PD2 614-2, PD3 614-3, and PD4 614-4 disposed in the semiconductor material 660 and configured to photo generate charges in response to incident light. At least first, second, third, and fourth transfer transistors TX1 616-1, TX2 616-2, TX3 616-3, and TX4 616-4 are coupled to the first, second, third, and fourth photodiodes PD1 614-1, PD2 614-2, PD3 614-3, and PD4 614-4, respectively. At least first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 are disposed in the semiconductor material 660. The first split floating diffusion region FD_1 618-1 is coupled to receive charges photo generated by the first and third photodiodes PD1 614-1 and PD3 614-3 through the first and third transfer transistors TX1 616-1 and TX3 616-3, respectively. Similarly, the second split floating diffusion region FD_2 618-2 is coupled to receive charges photo generated by the second and fourth photodiodes PD2 614-2 and PD4 614-4 through the second and fourth transfer transistors TX2 616-2 and TX4 616-4, respectively.

[0095] Continuing Figure 6AIn the example depicted in FIG. 6A, the first pixel circuit 604_N further includes at least first, second, third, and fourth shared gate structures 630-1, 630-2, 630-3, and 630-4. The first shared gate structure 630-1 includes a gate (e.g., gate electrode) of the first transfer transistor TX1 616-1 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of the first transfer transistor TX1 616-1 of the adjacent second pixel circuit 604_N-2. The third shared gate structure 630-3 includes a gate (e.g., gate electrode) of the third transfer transistor TX3 616-3 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of the third transfer transistor TX3 616-3 of the adjacent second pixel circuit 604_N-2. The second shared gate structure 630-2 includes a gate (e.g., gate electrode) of the second transfer transistor TX2 616-2 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of the second transfer transistor TX2 616-2 of the adjacent third pixel circuit 604_N+2. The fourth shared gate structure 630-4 includes a gate (e.g., gate structure) of the fourth transfer transistor TX4 616-4 of the first pixel circuit 604_N and a gate (e.g., gate structure) of the fourth transfer transistor TX4 616-4 of the adjacent third pixel circuit 604_N+2.

[0096] As shown in the depicted example, the first pixel circuit 604_N also includes a first source follower transistor SF 620-1 disposed in semiconductor material 660 between the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2. A first conductor 632-1 is disposed over and coupled to the gate of the first source follower transistor SF 620-1 and the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 by respective contacts. As such, the gate of the first source follower transistor SF 620-1 is coupled to the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 by the first conductor 632-1. It should be appreciated that since the gate of the first source follower transistor SF 620-1 is in relatively close proximity to the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 (as shown), the routing of the first conductor 632-1 is relatively short and simple, which helps to allow a relatively small pitch of the pixel circuit and to reduce parasitic capacitance associated with the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2. For example, in one example, the width (e.g., pixel width) of each of the first, second, and third pixel circuits 604_N, 604_N-2, 604_N+2 is about 0.5um or less. In other examples, it should be appreciated that the pitch of the first, second, and third pixel circuits 604_N, 604_N-2, 604_N+2 can have different values.

[0097] Continuing with the depicted example, the first pixel circuit 604_N also includes a first row select transistor RS0 622-1 coupled to the first source follower transistor SF 620-1 such that the first source follower transistor SF 620-1 and the first row select transistor RS0 622-1 are coupled between the power line AVDD and the first bit line BL 612-1. In various examples, the first row select transistor RS0 622-1 has a drain region coupled to a source region of the first source follower transistor SF 620-1. The first pixel circuit 604_N further includes a second row select transistor RS1 622-2 coupled to the first source follower transistor SF 620-1 such that the first source follower transistor SF 620-1 and the second row select transistor RS1 622-2 are coupled between the power line AVDD and the second bit line BL 612-2. In various examples, the second row select transistor RS1 622-2 has a drain region that is also coupled to a source region of the first source follower transistor SF 620-1.

[0098] Accordingly, both the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 are coupled to the source region of the first source follower transistor SF 620-1. In one example, the source region of the first source follower transistor SF 620-1 is a split source junction region that is split into the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2. In other words, the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 share a common junction 623 in the semiconductor material 660 with the split source junction region of the first source follower transistor SF 620-1. Accordingly, the drain region of the first row select transistor RS0 622-1 and the drain region of the second row select transistor RS1 622-2 are shared and coupled together and coupled to the source region of the first source follower transistor 620-1 through the semiconductor material 660 of the common junction 623.

[0099] Continuing Figure 6A In the example depicted in FIG. 6B, the first pixel circuit 604_N further includes a fifth, a sixth, a seventh, and an eighth photodiode PD5 614-5, PD6 614-6, PD7 614-7, and PD8 614-8 disposed in the semiconductor material 660 and configured to photo generate charges in response to incident light. As shown in the example, a fifth, a sixth, a seventh, and an eighth transfer transistor TX5 616-5, TX6 616-6, TX7 616-7, and TX8 616-8 are coupled to the fifth, the sixth, the seventh, and the eighth photodiode PD5 614-5, PD6 614-6, PD7 614-7, and PD8 614-8, respectively. A third split floating diffusion region FD_3 618-3 is coupled to receive charges photo generated by the fifth and the seventh photodiode PD5 614-5 and PD7 614-7 through the fifth and the seventh transfer transistor TX5 616-5 and TX7 616-7, respectively. Similarly, a fourth split floating diffusion region FD_4 618-4 is coupled to receive charges photo generated by the sixth and the eighth photodiode PD6 614-6 and PD8 614-8 through the sixth and the eighth transfer transistor TX6 616-6 and TX8 616-8, respectively.

[0100] As shown in the depicted example, the first pixel circuit 604_N further includes fifth, sixth, seventh, and eighth shared gate structures 630-5, 630-6, 630-7, and 630-8. The fifth shared gate structure 630-5 includes the gate of the fifth transfer transistor TX5 616-5 of the first pixel circuit 604_N and the gate of the fifth transfer transistor TX5 616-5 of the second pixel circuit 604_N-2. The seventh shared gate structure 630-7 includes the gate of the seventh transfer transistor TX7 616-7 of the first pixel circuit 604_N and the gate of the seventh transfer transistor TX7 616-7 of the second pixel circuit 604_N-2. The sixth shared gate structure 630-6 includes the gate of the sixth transfer transistor TX6 616-6 of the first pixel circuit 604_N and the gate of the sixth transfer transistor 616-6 of the third pixel circuit 604_N+2. The eighth shared gate structure 630-8 includes the gate of the eighth transfer transistor TX8 616-8 of the first pixel circuit 604_N and the gate of the eighth transfer transistor TX8 616-8 of the third pixel circuit 604_N+2.

[0101] Figure 6A The example depicted in FIG. 6A shows that the first pixel circuit 604_N further includes a second source follower transistor SF 620-2 disposed in semiconductor material 660 between the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4. A second conductor 632-2 is disposed over the gate of the second source follower transistor SF 620-2 and the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 by respective contacts. The gate of the second source follower transistor SF 620-2 is coupled to the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 by the second conductor 632-2. As such, the gate of the second source follower transistor SF 620-2 is coupled to the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 by the second conductor 632-2. It will be appreciated that because the gate of the second source follower transistor SF 620-2 is in relatively close proximity to the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 (as shown), the routing of the second conductor 632-2 is relatively short and simple, which helps to allow the pitch of the pixel circuit to be relatively small.

[0102] In various examples, the source region of the second source follower transistor SF 620-2 is also coupled to the drain region of the first row select transistor RS0 622-1 and the drain region of the second row select transistor RS1 622-2. Thus, the second source follower transistor SF 620-2 and the first row select transistor RS0 622-1 are coupled between the power line AVDD and the first bit line BL 612-1. In addition, the second source follower transistor SF 620-2 and the second row select transistor RS1 622-2 are also coupled between the power line AVDD and the second bit line BL 612-2.

[0103] In various examples, the source region of the second source follower transistor SF 620-2 is also a split source junction region that is split into the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2. In other words, the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 also share a common junction 623 in the semiconductor material 660 with the split source junction region of the second source follower transistor SF 620-2. Thus, the drain region of the first row select transistor RS0 622-1 and the drain region of the second row select transistor RS1 622-2 are shared and coupled together and coupled to the source regions of the first and second source follower transistors 620-1 and 620-2 through the semiconductor material 660 of the common junction 623.

[0104] In various examples, the first conductor 632-1 is coupled to the second conductor 632-2. Figure 6A , the first conductor 632-1 is further coupled between the gate electrodes of the first and second source follower transistors 620-1 and 620-2. In another example, it should be understood that the second conductor 632-2 can be further coupled between the gate electrodes of the first and second source follower transistors 620-1 and 620-2. Thus, it should be understood that the gate electrodes of the first and second source follower transistors 620-1 and 620-2 and the first, second, third, and fourth split floating diffusion regions FD_1 618-1, FD_2 618-2, FD_3 618-3, and FD_4 618-4 are coupled together.

[0105] In the depicted example, the first pixel circuit 604_N also includes a reset transistor RST 624 coupled between the power line AVDD and the first and second conductors 632-1 and 632-2. Thus, the reset transistor RST 624 is coupled between the power line AVDD and the first, second, third, and fourth split floating diffusion regions FD_1 618-1, FD_2 618-2, FD_3 618-3, and FD_4 618-4 through the first and second conductors 632-1 and 632-2.

[0106] like Figure 6A , the first pixel circuit 604_N further includes a dual floating diffusion transistor 626 coupled between the second conductor 632-2 and the reset transistor 624. In one example, a capacitor can be coupled to the node between the reset transistor 624 and the dual floating diffusion transistor 626 to store charge for low conversion gain readout when the dual floating diffusion transistor is turned on. When the dual floating diffusion transistor is turned off, a high conversion gain readout can be provided by the first pixel circuit 604_N.

[0107] Figure 6B A schematic diagram showing another exemplary arrangement of pixel circuits 604_N, 604_N-2, 604_N+2, 604_N+4, etc., having a shared gate structure and a split floating diffusion region included in a pixel array according to the teachings of the present invention is shown. It should be understood that Figure 6B The pixel circuits 604_N, 604_N-2, 604_N+2, 604_N+4, etc. are Figure 6A The pixel circuits 604_N, 604_N-2, 604_N+2, 604_N+4, etc. depicted in FIG. 6 correspond to the plan views, which may also be included in FIG. Figure 1 . Therefore, similarly named and numbered elements described above are similarly coupled and operate hereinafter. As can be observed in various examples, the first pixel circuit 604_N, the second pixel circuit 604_N-2, and the third pixel circuit 604_N+2 are substantially similar to each other. Thus, it should be understood that the description of features and functions in the first pixel circuit 604_N can be applied to corresponding features and functions in other pixel circuits included in the pixel array (including the second pixel circuit 604_N-2 and the third pixel circuit 604_N+2).

[0108] like Figure 6BAs shown in the example depicted in the middle, the first pixel circuit 604_N is disposed in the semiconductor material 660 between the second pixel circuit 604_N-2 and the third pixel circuit 604_N+2. In the depicted example, the width (e.g., pixel width) of the first pixel circuit 604_N, the second pixel circuit 604_N-2, and the third pixel circuit 604_N+2 can have a pixel pitch of 0.5um or less. As shown, the first pixel circuit 604_N includes at least first, second, third, and fourth photodiodes PD1 614-1, PD2 614-2, PD3 614-3, and PD4 614-4 disposed in the semiconductor material 660 and configured to photo generate charges in response to incident light. At least first, second, third, and fourth transfer transistors TX1 616-1, TX2 616-2, TX3 616-3, and TX4 616-4 are coupled to the first, second, third, and fourth photodiodes PD1 614-1, PD2 614-2, PD3 614-3, and PD4 614-4, respectively. At least first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 are disposed in the semiconductor material 660. The first split floating diffusion region FD_1 618-1 is coupled to receive charges photo generated by the first and third photodiodes PD1 614-1 and PD3 614-3 through the first and third transfer transistors TX1 616-1 and TX3 616-3, respectively. Similarly, the second split floating diffusion region FD_2 618-2 is coupled to receive charges photo generated by the second and fourth photodiodes PD2 614-2 and PD4 614-4 through the second and fourth transfer transistors TX2 616-2 and TX4 616-4, respectively.

[0109] Continuing Figure 6BThe first pixel circuit 604_N also includes at least first, second, third, and fourth shared gate structures SGS 630-1, 630-2, 630-3, and 630-4 in the depicted example. The first shared gate structure SGS 630-1 includes a gate (e.g., gate electrode) of a first transfer transistor TX1 616-1 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of a first transfer transistor TX1 616-1 of an adjacent second pixel circuit 604_N-2. The third shared gate structure SGS 630-3 includes a gate (e.g., gate electrode) of a third transfer transistor TX3 616-3 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of a third transfer transistor TX3 616-3 of the adjacent second pixel circuit 604_N-2. The second shared gate structure SGS 630-2 includes a gate (e.g., gate electrode) of a second transfer transistor TX2 616-2 of the first pixel circuit 604_N and a gate (e.g., gate electrode) of a second transfer transistor TX2 616-2 of an adjacent third pixel circuit 604_N+2. The fourth shared gate structure SGS 630-4 includes a gate (e.g., gate structure) of a fourth transfer transistor TX4 616-4 of the first pixel circuit 604_N and a gate (e.g., gate structure) of a fourth transfer transistor TX4 616-4 of the adjacent third pixel circuit 604_N+2.

[0110] As shown in the depicted example, the first pixel circuit 604_N also includes a first source follower transistor SF 620-1 disposed in semiconductor material 660 between the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2. A first conductor 632-1 is disposed over and coupled to the gate of the first source follower transistor SF 620-1 and the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 by respective contacts. As such, the gate of the first source follower transistor SF 620-1 is coupled to the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 by the first conductor 632-1. It will be appreciated that because the gate of the first source follower transistor SF 620-1 is in relatively close proximity to the first and second split floating diffusion regions FD_1 618-1 and FD_2 618-2 (as shown), the routing of the first conductor 632-1 is relatively short and simple, which helps to allow for a relatively small pitch of the pixel circuits.

[0111] Continuing with the depicted example, the first pixel circuit 604_N also includes a first row select transistor RS0 622-1 coupled to the first source follower transistor SF 620-1, such that the first source follower transistor SF 620-1 and the first row select transistor RS0 622-1 are coupled between the power line AVDD and the first bit line BL 612-1. In various examples, the first row select transistor RS0 622-1 has a drain region coupled to a source region of the first source follower transistor SF 620-1. The first pixel circuit 604_N further includes a second row select transistor RS1 622-2 coupled to the first source follower transistor SF 620-1, such that the first source follower transistor SF 620-1 and the second row select transistor RS1 622-2 are coupled between the power line AVDD and the second bit line BL 612-2. In various examples, the second row select transistor RS1 622-2 has a drain region that is also coupled to the source region of the first source follower transistor SF 620-1.

[0112] Thus, both the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 are coupled to the source region of the first source follower transistor SF 620-1. In one example, the source region of the first source follower transistor SF 620-1 is a split source junction region split into the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2. In other words, the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 share a common junction 623 in the semiconductor material 660 with the split source junction region of the first source follower transistor SF 620-1. Thus, the drain region of the first row select transistor RS0 622-1 and the drain region of the second row select transistor RS1 622-2 share and are coupled together and to the source region of the first source follower transistor 620-1 through the semiconductor material 660 of the common junction 623.

[0113] Continuing Figure 6BIn the depicted example, the first pixel circuit 604_N further includes fifth, sixth, seventh, and eighth photodiodes PD5 614-5, PD6 614-6, PD7 614-7, and PD8 614-8 disposed in the semiconductor material 660 and configured to photogenerate charges in response to incident light. As shown in the example, fifth, sixth, seventh, and eighth transfer transistors TX5 616-5, TX6 616-6, TX7 616-7, and TX8 616-8 are coupled to the fifth, sixth, seventh, and eighth photodiodes PD5 614-5, PD6 614-6, PD7 614-7, and PD8 614-8, respectively. A third split floating diffusion region FD_3 618-3 is coupled to receive charges photogenerated by the fifth and seventh photodiodes PD5 614-5 and PD7 614-7 by the fifth and seventh transfer transistors TX5 616-5 and TX7 616-7, respectively. Similarly, a fourth split floating diffusion region FD_4 618-4 is coupled to receive charges photogenerated by the sixth and eighth photodiodes PD6 614-6 and PD8 614-8 by the sixth and eighth transfer transistors TX6 616-6 and TX8 616-8, respectively.

[0114] As shown in the depicted example, the first pixel circuit 604_N further includes fifth, sixth, seventh, and eighth shared gate structures SGS 630-5, SGS 630-6, SGS 630-7, and SGS 630-8. The fifth shared gate structure SGS 630-5 includes the gate of the fifth transfer transistor TX5 616-5 of the first pixel circuit 604_N and the gate of the fifth transfer transistor TX5 616-5 of the adjacent second pixel circuit 604_N-2. The seventh shared gate structure SGS 630-7 includes the gate of the seventh transfer transistor TX7 616-7 of the first pixel circuit 604_N and the gate of the seventh transfer transistor TX7 616-7 of the adjacent second pixel circuit 604_N-2. The sixth shared gate structure SGS 630-6 includes the gate of the sixth transfer transistor TX6 616-6 of the first pixel circuit 604_N and the gate of the sixth transfer transistor 616-6 of the adjacent third pixel circuit 604_N+2. The eighth shared gate structure SGS 630-8 includes the gate of the eighth transfer transistor TX8 616-8 of the first pixel circuit 604_N and the gate of the eighth transfer transistor TX8 616-8 of the adjacent third pixel circuit 604_N+2.

[0115] Figure 6BThe example depicted in FIG. 6A shows that the first pixel circuit 604_N further includes a second source follower transistor SF 620-2 disposed in the semiconductor material 660 between the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4. A second conductor 632-2 is disposed over the gate of the second source follower transistor SF 620-2 and the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 by respective contacts. The gate of the second source follower transistor SF 620-2 is coupled to the third and fourth split floating diffusion regions by the second conductor 632-2. Thus, the gate of the second source follower transistor SF 620-2 is coupled to the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 by the second conductor 632-2. It should be appreciated that since the gate of the second source follower transistor SF 620-2 is in relatively close proximity to the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4 (as shown), the routing of the second conductor 632-2 is relatively short and simple, which helps to allow a relatively small pitch of the pixel circuit and also reduces the parasitic capacitance associated with the third and fourth split floating diffusion regions FD_3 618-3 and FD_4 618-4.

[0116] In various examples, the source region of the second source follower transistor SF 620-2 is also coupled to the drain region of the first row select transistor RS0 622-1 and the drain region of the second row select transistor RS1 622-2. Thus, the second source follower transistor SF 620-2 and the first row select transistor RS0 622-1 are coupled between the power line AVDD and the first bit line BL 612-1. In addition, the second source follower transistor SF 620-2 and the second row select transistor RS1 622-2 are also coupled between the power line AVDD and the second bit line BL 612-2.

[0117] In various examples, the source region of the second source follower transistor SF 620-2 is also split into split source junction regions of the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2. In other words, the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 also share a common junction 623 in the semiconductor material 660 with the split source junction regions of the second source follower transistor SF 620-2. Thus, the drain regions of the first row select transistor RS0 622-1 and the second row select transistor RS1 622-2 share and are coupled together and coupled to the source regions of the first and second source follower transistors 620-1 and 620-2 by the semiconductor material 660 of the common junction 623.

[0118] In various examples, the first conductor 632-1 is coupled to the second conductor 632-2. Figure 6B , the first conductor 632-1 is further coupled between the gate electrodes of the first and second source follower transistors 620-1 and 620-2. In another example, it should be understood that the second conductor 632-2 can be further coupled between the gate electrodes of the first and second source follower transistors 620-1 and 620-2. Thus, it should be understood that the gate electrodes of the first and second source follower transistors 620-1 and 620-2 and the first, second, third, and fourth split floating diffusion regions FD_1 618-1, FD_2 618-2, FD_3 618-3, and FD_4 618-4 are coupled together.

[0119] In the depicted example, the first pixel circuit 604_N also includes a reset transistor RST 624 coupled between the power line AVDD and the first and second conductors 632-1 and 632-2. Thus, the reset transistor RST 624 is coupled between the power line AVDD and the first, second, third, and fourth split floating diffusion regions FD_1 618-1, FD_2 618-2, FD_3 618-3, and FD_4 618-4 through the first and second conductors 632-1 and 632-2.

[0120] like Figure 6B , the first pixel circuit 604_N further includes a dual floating diffusion transistor 626 coupled between the second conductor 632-2 and the reset transistor 624. In one example, a capacitor CAP can be coupled to a node between the reset transistor 624 and the dual floating diffusion transistor 626 to store charge for low conversion gain readout when the dual floating diffusion transistor is turned on. When the dual floating diffusion transistor is turned off, a high conversion gain readout can be provided by the first pixel circuit 604_N.

[0121] The above description of illustrative examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Those skilled in the art will recognize that, although specific examples of the invention are described herein for illustration, various modifications are possible within the scope of the invention.

[0122] These modifications may be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A pixel array comprising: A plurality of pixel circuits are arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits comprises: first, second, third, and fourth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first, second, third, and fourth split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charge photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, and wherein the second split floating diffusion region is coupled to receive the charge photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure includes a gate of the first transfer transistor of the first pixel circuit and a gate of the first transfer transistor of a second pixel circuit among the plurality of pixel circuits, wherein the third shared gate structure includes a gate of the third transfer transistor of the first pixel circuit and a gate of the third transfer transistor of the second pixel circuit, wherein the second shared gate structure includes a gate of the second transfer transistor of the first pixel circuit and a gate of the second transfer transistor of a third pixel circuit among the plurality of pixel circuits, wherein the fourth shared gate structure includes a gate of the fourth transfer transistor of the first pixel circuit and a gate of the fourth transfer transistor of the third pixel circuit; and A double floating diffusion transistor is coupled between the first and second split floating diffusion regions and the third and fourth split floating diffusion regions, wherein the double floating diffusion transistor is configured to be turned on to merge the charge in the first, second, third, and fourth floating diffusion regions. 2 . The pixel array of claim 1 , wherein the first pixel circuitry is disposed in the semiconductor material between the second pixel circuitry and the third pixel circuitry. 3 . The pixel array of claim 1 , wherein the first pixel circuit further comprises a first source follower transistor disposed in the semiconductor material between the first and second split floating diffusion regions.

4. The pixel array according to claim 3, wherein the first pixel circuit further comprises: a first isolation structure disposed in the semiconductor material between the first split floating diffusion region and the first source follower transistor; and A second isolation structure is disposed in the semiconductor material between the second split floating diffusion region and the first source follower transistor.

5. The pixel array of claim 4 , wherein each of the first and second isolation structures comprises: a well isolation region disposed in the semiconductor material proximate to the first source follower transistor; and A shallow trench isolation (STI) structure is disposed in the well isolation region near the front side of the semiconductor material.

6. A pixel array according to claim 5, wherein the first pixel circuit further includes a first conductor disposed above the gate of the first source follower transistor and the first and second split floating diffusion regions, wherein the gate of the first source follower transistor is coupled to the first and second split floating diffusion regions through the first conductor.

7. The pixel array according to claim 6, wherein the first pixel circuit further comprises: a first row select transistor coupled to the first source follower transistor, wherein the first source follower transistor and the first row select transistor are coupled between a power line and a bit line; and A first reset transistor is coupled between the power line and the first and second split floating diffusion regions, wherein the first conductor is further coupled between the first and second split floating diffusion regions and the first reset transistor.

8. The pixel array according to claim 1 , wherein the first pixel circuit further comprises: fifth, sixth, seventh, and eighth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; fifth, sixth, seventh, and eighth transfer transistors coupled to the fifth, sixth, seventh, and eighth photodiodes, respectively, wherein the third split floating diffusion region is coupled to receive the charges photogenerated by the fifth and seventh photodiodes through the fifth and seventh transfer transistors, respectively, wherein the fourth split floating diffusion region is coupled to receive the charges photogenerated by the sixth and eighth photodiodes through the sixth and eighth transfer transistors, respectively; and Fifth, sixth, seventh and eighth shared gate structures, wherein the fifth shared gate structure includes the gate of the fifth transfer transistor of the first pixel circuit and the gate of the fifth transfer transistor of the second pixel circuit among the multiple pixel circuits, wherein the seventh shared gate structure includes the gate of the seventh transfer transistor of the first pixel circuit and the gate of the seventh transfer transistor of the second pixel circuit, wherein the sixth shared gate structure includes the gate of the sixth transfer transistor of the first pixel circuit and the gate of the sixth transfer transistor of the third pixel circuit among the multiple pixel circuits, and wherein the eighth shared gate structure includes the gate of the eighth transfer transistor of the first pixel circuit and the gate of the eighth transfer transistor of the third pixel circuit.

9. The pixel array of claim 8, wherein the first pixel circuit further comprises a second source follower transistor disposed in the semiconductor material between the third and fourth split floating diffusion regions.

10. The pixel array of claim 9 , wherein the first pixel circuit further comprises a second conductor disposed above the gate of the second source follower transistor and the third and fourth split floating diffusion regions, wherein the gate of the second source follower transistor is coupled to the third and fourth split floating diffusion regions through the second conductor.

11. The pixel array according to claim 10, wherein the first pixel circuit further comprises: a second row select transistor coupled to the second source follower transistor, wherein the second source follower transistor and the second row select transistor are coupled between a power line and a bit line; and A second reset transistor is coupled between the power line and the third and fourth split floating diffusion regions, wherein the second conductor is further coupled between the third and fourth split floating diffusion regions and the second reset transistor.

12. The pixel array of claim 8, wherein the first, second, third, fourth, fifth, sixth, seventh, and eighth photodiodes are configured to be illuminated by the incident light through a first color filter in a color filter array disposed above the pixel array.

13. The pixel array of claim 12, wherein the first color filter in the color filter array is disposed over the first pixel circuit.

14. The pixel array according to claim 1, wherein the first shared gate structure is coupled to receive a first transfer control signal, wherein the first transfer control signal is coupled to be received by shared gate structures in odd columns of the shared gate structures in the pixel array in the same row as the first and second shared gate structures, wherein the second shared gate structure is coupled to receive a second transfer control signal, wherein the second transfer control signal is coupled to be received by shared gate structures in even columns of the shared gate structures in the pixel array in the same row as the first and second shared gate structures, wherein the third shared gate structure is coupled to receive a third transfer control signal, wherein the third transfer control signal is coupled to be received by shared gate structures in odd columns of the shared gate structures in the pixel array in the same row as the third and fourth shared gate structures, wherein the fourth shared gate structure is coupled to receive a fourth transfer control signal, wherein the fourth transfer control signal is coupled to be received by shared gate structures in even columns of the shared gate structures in the pixel array in the same row as the third and fourth shared gate structures.

15. The pixel array according to claim 14, wherein the first transfer control signal is configured to read out the first photodiode before the second transfer control signal is configured to read out the second photodiode, wherein the second transfer control signal is configured to read out the second photodiode before the third transfer control signal is configured to read out the third photodiode, Wherein the third transfer control signal is configured to read out the third photodiode before the fourth transfer control signal is configured to read out the fourth photodiode.

16. The pixel array according to claim 15, wherein the first photodiode is configured to be read out during a first readout period in response to the first transfer control signal, wherein the second photodiode is configured to be read out during a second readout period in response to the second transfer control signal, wherein the second readout period occurs after the first readout period, wherein the third photodiode is configured to be read out during a third readout period in response to the third transfer control signal, wherein the third readout period occurs after the second readout period, The fourth photodiode is configured to be read out during a fourth readout period in response to the fourth transfer control signal, wherein the fourth readout period occurs after the third readout period.

17. An imaging system comprising: A pixel array comprising a plurality of pixel circuits arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits comprises: first, second, third, and fourth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first, second, third, and fourth split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charge photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, and wherein the second split floating diffusion region is coupled to receive the charge photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure includes a gate of the first transfer transistor of the first pixel circuit and a gate of the first transfer transistor of a second pixel circuit among the plurality of pixel circuits, wherein the third shared gate structure includes a gate of the third transfer transistor of the first pixel circuit and a gate of the third transfer transistor of the second pixel circuit, wherein the second shared gate structure includes a gate of the second transfer transistor of the first pixel circuit and a gate of the second transfer transistor of a third pixel circuit among the plurality of pixel circuits, wherein the fourth shared gate structure includes a gate of the fourth transfer transistor of the first pixel circuit and a gate of the fourth transfer transistor of the third pixel circuit; and a double floating diffusion transistor coupled between the first and second split floating diffusion regions and the third and fourth split floating diffusion regions, wherein the double floating diffusion transistor is configured to be turned on to combine charge in the first, second, third, and fourth floating diffusion regions; a control circuit coupled to the pixel array to control operation of the pixel array; and Readout circuitry is coupled to the pixel array to read out image data from the pixel array.

18. The imaging system of claim 17, further comprising functional logic coupled to the readout circuitry to store the image data read out from the pixel array.

19. The imaging system of claim 17, wherein the first pixel circuitry is disposed in the semiconductor material between the second pixel circuitry and the third pixel circuitry.

20. The imaging system of claim 17, wherein the first pixel circuit further comprises a first source follower transistor disposed in the semiconductor material between the first and second split floating diffusion regions.

21. The imaging system of claim 20, wherein the first pixel circuit further comprises: a first isolation structure disposed in the semiconductor material between the first split floating diffusion region and the first source follower transistor; and A second isolation structure is disposed in the semiconductor material between the second split floating diffusion region and the first source follower transistor.

22. The imaging system of claim 21 , wherein each of the first and second isolation structures comprises: a well isolation region disposed in the semiconductor material proximate to the first source follower transistor; and A shallow trench isolation (STI) structure is disposed in the well isolation region near the front side of the semiconductor material.

23. An imaging system according to claim 22, wherein the first pixel circuit further includes a first conductor disposed above the gate of the first source follower transistor and the first and second split floating diffusion regions, wherein the gate of the first source follower transistor is coupled to the first and second split floating diffusion regions through the first conductor.

24. The imaging system of claim 23, wherein the first pixel circuit further comprises: a first row select transistor coupled to the first source follower transistor, wherein the first source follower transistor and the first row select transistor are coupled between a power line and a bit line; and A first reset transistor is coupled between the power line and the first and second split floating diffusion regions, wherein the first conductor is further coupled between the first and second split floating diffusion regions and the first reset transistor.

25. The imaging system of claim 17, wherein the first pixel circuit further comprises: fifth, sixth, seventh, and eighth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; fifth, sixth, seventh, and eighth transfer transistors coupled to the fifth, sixth, seventh, and eighth photodiodes, respectively, wherein the third split floating diffusion region is coupled to receive the charges photogenerated by the fifth and seventh photodiodes through the fifth and seventh transfer transistors, respectively, wherein the fourth split floating diffusion region is coupled to receive the charges photogenerated by the sixth and eighth photodiodes through the sixth and eighth transfer transistors, respectively; and Fifth, sixth, seventh and eighth shared gate structures, wherein the fifth shared gate structure includes the gate of the fifth transfer transistor of the first pixel circuit and the gate of the fifth transfer transistor of the second pixel circuit among the multiple pixel circuits, wherein the seventh shared gate structure includes the gate of the seventh transfer transistor of the first pixel circuit and the gate of the seventh transfer transistor of the second pixel circuit, wherein the sixth shared gate structure includes the gate of the sixth transfer transistor of the first pixel circuit and the gate of the sixth transfer transistor of the third pixel circuit among the multiple pixel circuits, and wherein the eighth shared gate structure includes the gate of the eighth transfer transistor of the first pixel circuit and the gate of the eighth transfer transistor of the third pixel circuit.

26. The imaging system of claim 25, wherein the first pixel circuit further comprises a second source follower transistor disposed in the semiconductor material between the third and fourth split floating diffusion regions.

27. An imaging system according to claim 26, wherein the first pixel circuit further includes a second conductor disposed above the gate of the second source follower transistor and the third and fourth split floating diffusion regions, wherein the gate of the second source follower transistor is coupled to the third and fourth split floating diffusion regions through the second conductor.

28. The imaging system of claim 27, wherein the first pixel circuit further comprises: a second row select transistor coupled to the second source follower transistor, wherein the second source follower transistor and the second row select transistor are coupled between a power line and a bit line; and A second reset transistor is coupled between the power line and the third and fourth split floating diffusion regions, wherein the second conductor is further coupled between the third and fourth split floating diffusion regions and the second reset transistor.

29. The imaging system of claim 25, wherein the first, second, third, fourth, fifth, sixth, seventh, and eighth photodiodes are configured to be illuminated by the incident light through a first color filter in a color filter array disposed above the pixel array.

30. The imaging system of claim 29, wherein the first color filter in the color filter array is disposed over the first pixel circuit.

31. The imaging system of claim 17, wherein the first shared gate structure is coupled to receive a first transfer control signal, wherein the first transfer control signal is coupled to be received by shared gate structures in odd columns of the shared gate structures in the pixel array in the same row as the first and second shared gate structures, wherein the second shared gate structure is coupled to receive a second transfer control signal, wherein the second transfer control signal is coupled to be received by shared gate structures in even columns of the shared gate structures in the pixel array in the same row as the first and second shared gate structures, wherein the third shared gate structure is coupled to receive a third transfer control signal, wherein the third transfer control signal is coupled to be received by shared gate structures in odd columns of the shared gate structures in the pixel array in the same row as the third and fourth shared gate structures, wherein the fourth shared gate structure is coupled to receive a fourth transfer control signal, wherein the fourth transfer control signal is coupled to be received by shared gate structures in even columns of the shared gate structures in the pixel array in the same row as the third and fourth shared gate structures.

32. The imaging system according to claim 31 , wherein the first transfer control signal is configured to read out the first photodiode before the second transfer control signal is configured to read out the second photodiode, wherein the second transfer control signal is configured to read out the second photodiode before the third transfer control signal is configured to read out the third photodiode, Wherein the third transfer control signal is configured to read out the third photodiode before the fourth transfer control signal is configured to read out the fourth photodiode.

33. The imaging system according to claim 32, wherein the first photodiode is configured to be read out during a first readout period in response to the first transfer control signal, wherein the second photodiode is configured to be read out during a second readout period in response to the second transfer control signal, wherein the second readout period occurs after the first readout period, wherein the third photodiode is configured to be read out during a third readout period in response to the third transfer control signal, wherein the third readout period occurs after the second readout period, The fourth photodiode is configured to be read out during a fourth readout period in response to the fourth transfer control signal, wherein the fourth readout period occurs after the third readout period.

34. A pixel array comprising: A plurality of pixel circuits are arranged in rows and columns, wherein a first pixel circuit of the plurality of pixel circuits comprises: first, second, third, and fourth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively; first and second split floating diffusion regions disposed in the semiconductor material, wherein the first split floating diffusion region is coupled to receive the charge photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, and wherein the second split floating diffusion region is coupled to receive the charge photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; first, second, third, and fourth shared gate structures, wherein the first shared gate structure includes a gate of the first transfer transistor of the first pixel circuit and a gate of the first transfer transistor of a second pixel circuit among the plurality of pixel circuits, wherein the third shared gate structure includes a gate of the third transfer transistor of the first pixel circuit and a gate of the third transfer transistor of the second pixel circuit, wherein the second shared gate structure includes a gate of the second transfer transistor of the first pixel circuit and a gate of the second transfer transistor of a third pixel circuit among the plurality of pixel circuits, and wherein the fourth shared gate structure includes a gate of the fourth transfer transistor of the first pixel circuit and a gate of the fourth transfer transistor of the third pixel circuit; a first source follower transistor disposed in the semiconductor material between the first and second split floating diffusion regions; a first row select transistor having a drain region coupled to a source region of the first source follower transistor; and A second row select transistor has a drain region coupled to the source region of the first source follower transistor.

35. A pixel array according to claim 34, wherein the pixel array further includes a common junction in the semiconductor material disposed between the gate of the first row selection transistor and the gate of the second row selection transistor, wherein the drain region of the first row selection transistor and the drain region of the second row selection transistor are shared and coupled together by the semiconductor material of the common junction.

36. A pixel array according to claim 35, wherein the source region of the first source follower transistor includes a split source junction region, and the split source junction region is contained in the semiconductor material of the common junction, so that the split source junction region of the first source follower transistor, the drain region of the first row selection transistor and the drain region of the second row selection transistor are shared and coupled together through the semiconductor material of the common junction.

37. The pixel array of claim 36, wherein the first source follower transistor and the first row select transistor are coupled between a power line and a first bit line, wherein the first source follower transistor and the second row select transistor are coupled between the power line and a second bit line.

38. The pixel array of claim 37, wherein the first pixel circuitry is disposed in the semiconductor material between the second pixel circuitry and the third pixel circuitry.

39. A pixel array according to claim 38, wherein the first pixel circuit further includes a first conductor disposed above the gate of the first source follower transistor and the first and second split floating diffusion regions, wherein the gate of the first source follower transistor is coupled to the first and second split floating diffusion regions through the first conductor.

40. The pixel array of claim 39, wherein the first pixel circuit further comprises: fifth, sixth, seventh, and eighth photodiodes disposed in the semiconductor material and configured to photogenerate charge in response to incident light; fifth, sixth, seventh, and eighth transfer transistors coupled to the fifth, sixth, seventh, and eighth photodiodes, respectively, third and fourth split floating diffusion regions disposed in the semiconductor material, wherein the third split floating diffusion region is coupled to receive the charge photogenerated by the fifth and seventh photodiodes through the fifth and seventh transfer transistors, respectively, and wherein the fourth split floating diffusion region is coupled to receive the charge photogenerated by the sixth and eighth photodiodes through the sixth and eighth transfer transistors, respectively; and Fifth, sixth, seventh and eighth shared gate structures, wherein the fifth shared gate structure includes the gate of the fifth transfer transistor of the first pixel circuit and the gate of the fifth transfer transistor of the second pixel circuit among the multiple pixel circuits, wherein the seventh shared gate structure includes the gate of the seventh transfer transistor of the first pixel circuit and the gate of the seventh transfer transistor of the second pixel circuit, wherein the sixth shared gate structure includes the gate of the sixth transfer transistor of the first pixel circuit and the gate of the sixth transfer transistor of the third pixel circuit among the multiple pixel circuits, and wherein the eighth shared gate structure includes the gate of the eighth transfer transistor of the first pixel circuit and the gate of the eighth transfer transistor of the third pixel circuit.

41. The pixel array of claim 40, wherein the first pixel circuit further comprises a second source follower transistor disposed in the semiconductor material between the third and fourth split floating diffusion regions.

42. The pixel array according to claim 41 , wherein the drain region of the first row select transistor is further coupled to the source region of the second source follower transistor, wherein the drain region of the second row select transistor is further coupled to the source region of the second source follower transistor, The source region of the second source follower transistor includes a split source junction region, and the split source junction region is contained in the semiconductor material of the common junction, so that the split source junction region of the second source follower transistor, the drain region of the first row selection transistor, the drain region of the second row selection transistor and the split source junction region of the first source follower transistor are shared and coupled together through the semiconductor material of the common junction.

43. The pixel array of claim 42, wherein the second source follower transistor and the first row select transistor are coupled between the power line and a first bit line, wherein the second source follower transistor and the second row select transistor are coupled between the power line and a second bit line.

44. A pixel array according to claim 43, wherein the first pixel circuit further includes a second conductor disposed above the gate of the second source follower transistor and the third and fourth split floating diffusion regions, wherein the gate of the second source follower transistor is coupled to the third and fourth split floating diffusion regions through the second conductor.

45. The pixel array of claim 44, wherein the second conductor is coupled to the first conductor, wherein the first pixel circuit further comprises a reset transistor coupled between a power line and the first and second conductors.

46. ​​The pixel array of claim 45, wherein the first pixel circuit further comprises a dual floating diffusion transistor coupled between the reset transistor and the first and second conductors.

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