A circuit manufacturing method, device and electronic equipment

Abstract

The application provides a circuit manufacturing method and device and electronic equipment, and relates to the field of integrated circuits. When designing a circuit, standard cells are placed in corresponding working areas according to different types, so that resource utilization is improved, instead of dividing a unified sacrifice area for all standard cells and prohibiting the placement of standard cells in the sacrifice area. The method comprises the following steps: obtaining type and position information of the standard cells, wherein the position information comprises an angle and a distance, the distance is the distance from the center of the standard cell to the center of a through silicon via (TSV), and the angle is the included angle between the line connecting the center of the TSV and the center of the standard cell and the horizontal line of the center of the standard cell. Whether the standard cell is located in a working area is determined according to the position information and a pre-set position information table, if not, the position information of the standard cell after position updating is obtained for re-determination until the standard cell falls into the working area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a circuit manufacturing method and device and electronic equipment. BACKGROUND

[0002] With the continuous progress of chip nanometer process technology, the transistor density of a wafer gradually approaches the physical limit in a two-dimensional plane, and therefore higher demands are placed on the density and performance of integrated packaging. One method of three-dimensional packaging is to vertically integrate wafers based on through silicon via (TSV) technology and stacking. Three-dimensional packaging can achieve smaller size, higher bandwidth, lower latency and higher performance. TSV technology is a new interconnection technology used in high-density microelectronic packaging, which forms a micro via by etching a silicon wafer, then fills the micro via with copper by electroplating, and forms a micro via by annealing and thinning the silicon wafer. The upper and lower surfaces of the chip are electrically connected to the packaging structure through a redistribution process.

[0003] In the above processes such as electroplating and annealing, the use of TSV technology can easily generate high stress in the electroplated copper material. In addition, three-dimensional packaging based on TSV technology needs to withstand the coupling effects of temperature, humidity, current / voltage, vibration, etc. during its manufacture and use, and these stress coupling effects can affect the mobility and threshold voltage of the surrounding standard cells, thereby causing the failure of the flipping characteristics of the standard cells. The prior art usually defines a sacrifice area outside the process clearance area of the TSV according to the process manufacturing rules. The process clearance area is a region planned according to the process manufacturing rules, in which standard cells are prohibited. The sacrifice area is located outside the process clearance area and is a region planned according to the principle that the impact of TSV on standard cells decreases with increasing distance. Since the standard cells are located outside the sacrifice area, the distance between the TSV and the standard cells increases, so the impact of TSV stress can be reduced.

[0004] However, because different standard cells can work or fail in different regions, defining the same sacrifice area for different standard cells and prohibiting the placement of any standard cells in the sacrifice area can cause a waste of design resources. SUMMARY

[0005] The embodiments of the present application provide a circuit manufacturing method and device and electronic equipment to improve the problem of waste of design resources caused by the TSV stress defining a uniform sacrifice area around the TSV.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] In a first aspect, a circuit manufacturing method is provided. The method comprises: obtaining type and position information of a standard cell, the position information comprising an angle and a distance, wherein the distance is a distance from a center of a through silicon via (TSV) to a center of the standard cell, and the angle is an included angle between a line from the center of the TSV to the center of the standard cell and a horizontal line of the center of the standard cell; determining whether the standard cell is in an active area according to the type, the distance, the angle, and a pre-set position information table, the position information table storing boundary information of the active area of different types of standard cells, the boundary information comprising a first included angle and a first distance, the first included angle being the included angle between the line from the center of the TSV to the center of the standard cell and the horizontal line of the center of the standard cell, and the first distance being a minimum working distance from the center of the standard cell corresponding to the first included angle to the center of the TSV; comparing the angle and the distance of the standard cell with the first included angle and the first distance stored in the position information table corresponding to the type of the standard cell, and determining that the standard cell is in the active area if the distance of the standard cell is greater than the first distance corresponding to the first included angle matched with the angle, and obtaining position information of the standard cell after the position of the standard cell is updated until the standard cell is in the active area if the standard cell is outside the active area.

[0008] In the scheme provided by the embodiments of the present application, the boundary information of the active area of different types of standard cells is stored in the position information table, instead of uniformly defining a sacrifice area for all standard cells. Thus, whether the standard cell is in the active area is determined by obtaining the position information of the standard cell and the boundary information of the active area of the standard cell in the position information table, and the position information of the standard cell after the position of the standard cell is updated is obtained again for determination until the standard cell is in the active area corresponding to the standard cell. Compared with the scheme of defining a sacrifice area in which no standard cell of any type is placed, the scheme provided by the embodiments of the present application sets the active area for different types of standard cells, and thus different standard cells can be placed in their respective active areas to achieve efficient use of resources when a circuit layout is designed.

[0009] In a possible implementation, after the standard cell is in the active area, the method further comprises: determining whether a delay of the standard cell belongs to a pre-set range according to the position information and based on a pre-set standard cell timing table; obtaining the position information of the standard cell after the position of the standard cell is updated until the delay is in the pre-set range if the delay is out of the pre-set range.

[0010] In the embodiment of the present application, the working state of the standard cell in the work area meets the design requirements, but the position of the standard cell changes, and the order of signal transmission of the metal interconnection line connecting multiple standard cells changes due to the different positions. Different positions have different delays. The position of the standard cell is determined whether it meets the order of signal transmission or the delay requirement through the standard cell position and the standard cell timing table. If it does not meet the requirement, the position information of the standard cell after the position is updated is obtained for re-determination. Until the delay of the standard cell is within the set range, it is ensured that the timing of signal transmission of each standard cell meets the requirement.

[0011] In a possible implementation, before determining whether the standard cell is in the work area according to the type, distance, angle, and position information table, the method further includes: determining the position information table. The position information table stores the range of the work area corresponding to different types of standard cells. The position information table is established in advance. When the circuit is made, it can be ensured that each standard cell is placed in the work area according to the position information table.

[0012] In a possible implementation, determining the position information table includes: calling a device model of any type of standard cell representing TSV stress, establishing a simulation structure of the standard cell with TSV; wherein the model is used to indicate the corresponding relationship between the delay and the flip characteristics of the transistor inside the standard cell and the position information of the standard cell; adjusting the position of the standard cell, determining the first distance of the standard cell corresponding to each first angle, and determining each first angle and the first distance corresponding to the first angle as the boundary information of the work area of the standard cell; and establishing the position information table according to the type and the boundary information of the work area.

[0013] In a possible implementation, adjusting the position of the standard cell and determining the first distance of the standard cell corresponding to each first angle includes: setting the first angle of the standard cell as a starting angle and the distance from the center of the standard cell to the center of the TSV as an initial distance, increasing the distance from the center of the standard cell to the center of the TSV by a set distance step, until the minimum working distance that meets the preset requirements of the delay and the flip characteristics at the starting angle is determined, wherein the initial distance is the radius of the process clearance area; adjusting the first angle of the standard cell by a set angle step, determining the minimum working distance that meets the preset requirements of the delay and the flip characteristics after adjusting the first angle, until the first angle of the standard cell is adjusted to a terminal angle, and the sum of the starting angle and the terminal angle is 2π. The boundary of the work area at the angle is determined by the method of fixing the angle and increasing the distance by a step, and the boundary of the work area at the new angle is determined by the method of fixing the angle and increasing the distance by a step after the angle is transformed by a step, until the terminal angle is reached. In this way, the minimum working distance that meets the requirements of the delay and the flip characteristics of the standard cell at each angle, that is, the boundary information of the work area of the standard cell, can be determined.

[0014] In a possible implementation, the determining whether the standard cell is in the work area according to the type, the distance, the angle, and the pre-set position information table comprises: determining boundary information of the work area corresponding to the type in the position information table according to the type of the standard cell; determining a first distance corresponding to a first included angle matching the angle in the boundary information of the work area according to the angle; and determining that the standard cell is in the work area if the distance is greater than or equal to the first distance. Each type of standard cell is determined to be in the work area according to the above determination method. When a circuit layout is made, different standard cells are respectively arranged in their respective work areas, so that the resources can be efficiently utilized.

[0015] In a possible implementation, before the determining whether the delay of the standard cell belongs to the pre-set range according to the updated position information and based on the pre-set standard cell timing table, the method further comprises: determining the standard cell timing table. The delay of the standard cell corresponding to each position is determined before a circuit is made, and the standard cell timing table is determined, so that the timing of each standard cell can meet the requirements when the circuit is designed, and the efficiency of circuit design is improved.

[0016] In a possible implementation, the method for creating the standard timing table comprises: calling a device model of any type of standard cell representing TSV stress, and establishing a simulation structure of the standard cell with TSV; wherein the standard cell model is used to indicate a corresponding relationship between the delay of the type of standard cell and the position information of the standard cell; determining the delay of the standard cell under the influence of TSV at the current position, and determining an influence factor at the position as a ratio of the delay to an initial delay of the standard cell, wherein the initial delay refers to the delay of the standard cell under the influence of TSV; adjusting the position of the standard cell, determining the influence factor after the position is adjusted, and storing the corresponding relationship between the position and the influence factor corresponding to the position into the standard cell timing table.

[0017] In a possible implementation, the determining whether the delay of the standard cell belongs to the pre-set range according to the updated position information and based on the pre-set standard cell timing table comprises: determining an influence factor according to the position information and the standard cell timing table; multiplying the influence factor and the initial delay of the standard cell to determine the delay of the standard cell under the influence of TSV; and determining whether the delay of the standard cell under the influence of TSV belongs to the pre-set range. The pre-set range can be a timing range based on a signal flow relationship required to be met by a specific function of a digital chip, for example, the delay of different standard cells is determined according to the relationship of the signal flow directions of different standard cells.

[0018] In a second aspect, a circuit design apparatus is provided, which comprises an obtaining module and a processing module. The obtaining module is configured to obtain type and position information of a standard cell, the position information comprising an angle and a distance, the distance being a distance from a center of a through-silicon via (TSV) to a center of the standard cell, and the angle being an included angle between a line connecting the center of the TSV to the center of the standard cell and a horizontal line of the center of the standard cell. The processing module is configured to determine whether the standard cell is in an active region according to the type, the distance, the angle, and a pre-set position information table, the position information table storing boundary information of the active region of different types of standard cells, the boundary information comprising a first included angle and a first distance. The first included angle is an included angle between a line connecting the center of the TSV to the center of the standard cell and a horizontal line of the center of the standard cell, and the first distance is a minimum working distance from the center of the TSV to the center of the standard cell corresponding to the first included angle. If the standard cell is outside the active region, the obtaining module is further configured to obtain position information of the standard cell after the position of the standard cell is updated until the standard cell is in the active region.

[0019] In a third aspect, a computer readable storage medium is provided, which stores computer instructions. When the instructions are executed by a processor, the processor is enabled to perform the method provided in any of the embodiments of the first aspect.

[0020] In a fourth aspect, a chip is provided, which stores computer instructions. When the computer instructions are executed by a processor, the method provided in any of the embodiments of the first aspect is implemented.

[0021] In a fifth aspect, an electronic device is provided, which comprises a processor and a memory. The processor is configured to execute computer instructions stored in the memory to implement the method provided in any of the embodiments of the first aspect.

[0022] The technical effects of the second aspect, the third aspect, the fourth aspect, and the fifth aspect can be referred to the above description of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A schematic diagram of a three-dimensional packaging structure provided by an embodiment of the present application;

[0024] Figure 2 A schematic diagram of another three-dimensional packaging structure provided by an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a correspondence between input and output of a standard cell and time under the influence of a TSV provided by an embodiment of the present application;

[0026] Figure 4 A schematic diagram of a change of noise margin of a standard cell under the influence of a TSV provided by an embodiment of the present application;

[0027] Figure 5 A standard cell with TSV provided for an embodiment of the present application;

[0028] Figure 6 An electronic device structure provided for an embodiment of the present application;

[0029] Figure 7 A flowchart of a circuit manufacturing method provided for an embodiment of the present application;

[0030] Figure 8 A signal flow diagram provided for an embodiment of the present application;

[0031] Figure 9 A flowchart of another circuit manufacturing method provided for an embodiment of the present application;

[0032] Figure 10 A flowchart of another circuit manufacturing method provided for an embodiment of the present application;

[0033] Figure 11 A flowchart of another circuit manufacturing method provided for an embodiment of the present application;

[0034] Figure 12a A diagram of the influence of TSV stress on the transistor mobility inside a standard cell provided for an embodiment of the present application;

[0035] Figure 12b A diagram of the influence of TSV stress on the transistor threshold voltage variation inside a standard cell provided for an embodiment of the present application;

[0036] Figure 13a A diagram of the influence of TSV stress on the transistor saturation current inside a standard cell provided for an embodiment of the present application;

[0037] Figure 13b A diagram of the influence of TSV stress on the transistor threshold voltage inside a standard cell provided for an embodiment of the present application;

[0038] Figure 14a A diagram of the delay of a standard cell provided for an embodiment of the present application;

[0039] Figure 14b A diagram of the flip characteristics of a standard cell provided for an embodiment of the present application;

[0040] Figure 15 A flowchart of another circuit manufacturing method provided for an embodiment of the present application;

[0041] Figure 16 A flowchart of another circuit manufacturing method provided for an embodiment of the present application;

[0042] Figure 17 A standard cell layout schematic diagram provided for the embodiment of the present application;

[0043] Figure 18 Another standard cell layout schematic diagram provided for the embodiment of the present application;

[0044] Figure 19 Two standard cell layout schematic diagrams provided for the embodiment of the present application;

[0045] Figure 20 A circuit design device function block diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments of the present application.

[0047] Hereinafter, the terms "first", "second", and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features.

[0048] In addition, in the present application, the orientation terms such as "up", "down", "left", "right", "horizontal", and "vertical" are defined with respect to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the orientation of the components in the drawings.

[0049] In the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood broadly, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium.

[0050] Packaging is to install a shell for chip integrated circuit, and the shell plays multiple roles such as fixing, sealing, protecting the chip, and enhancing heat dissipation. Packaging also plays the role of a bridge between the internal and external circuits of the chip, so packaging is divided into internal packaging and external packaging. With the continuous progress of nanometer process technology of chips, the transistor density on the two-dimensional plane of the wafer gradually approaches the physical limit, so there is a higher demand for the density and performance of integrated packaging, and three-dimensional packaging based on through silicon via (TSV) technology emerges as the times require.

[0051] TSV technology is formed by etching a micro-hole that penetrates the substrate longitudinally and filling the micro-hole with a conductive material (such as copper). The TSV can be used to provide electrical connections between semiconductor circuits on the back side of a semiconductor substrate and the opposite side of the substrate, or to provide electrical connections between semiconductor circuits on stacked chips.

[0052] 3D packaging based on TSV technology can stack multiple functional chips within a single package, enabling a single package to perform more functions. Taking memory chips as an example, 3D packaging based on TSV technology can stack multiple memory chips within a single package, thereby doubling the storage capacity.

[0053] like Figure 1 The diagram illustrates a back-to-face (BtF) integration method for 3D packaging based on TSV technology. This means that the front side of the first device wafer 001 is bonded or connected to the back side of the second device wafer 003. The surface of the first substrate 002 in the first device wafer 001 is the back side, and... Figure 1 The through-silicon via 005 shown is connected at one end to the front metal 006 inside the second device wafer 003, and at the other end to the rear metal 007 located above the second substrate 004 of the second device wafer 003.

[0054] like Figure 2 The diagram illustrates a face-to-face (FTF) integration method for 3D packaging based on TSV technology. Specifically, the front side of the first device wafer 011 is connected to the front side of the second device wafer 013. The surface of the first device wafer 011 containing the first substrate 012 is the back side, and the surface of the second device wafer 013 containing the second substrate 014 is the back side. Figure 2 The through-silicon via 015 shown is connected at one end to the front metal 016 inside the second device wafer 013, and at the other end to the rear metal 017 located below the second substrate 014 of the second device wafer 013. The resulting wafer stack is not like a standard wafer, meaning that different integration processes are required for the other layers of the multilayer stack. The main advantage of this process flow is that it does not require processing thin wafers.

[0055] Theoretically, three-dimensional packaging based on TSV technology can make chips directly interconnected, faster signal transmission and less interference. However, due to the heat residual caused by high temperature processing when manufacturing TSV and the need to withstand temperature, humidity, current, voltage, vibration and other multi-stress coupling effects during use, the standard cells arranged around the TSV may be affected by the TSV and cannot work normally. Among them, the standard cell (STD cell) refers to a standard device composed of transistors, such as a gate circuit capable of providing Boolean logic function or a device with storage function. The standard cell can be a general logic gate circuit, such as an AND gate, an OR gate, a NOT gate, a NAND gate, and a NOR gate, and the standard cell can also be a flip-flop, a latch and the like.

[0056] In the embodiments of the present application, the transistor can adopt a metal-oxide-semiconductor field effect transistor (MOSFET), including a negative-channel-mental-oxide semiconductor (NMOS) and a positive-channel-mental-oxide semiconductor (PMOS), wherein the NMOS is also called an N-type transistor, and the PMOS is also called a P-type transistor. The transistor includes a source, a drain and a gate, and the conduction or turn-off of the transistor can be controlled by controlling the level of the input transistor gate. When the transistor is turned on, the source and the drain are turned on to generate a conduction current, and when the gate level of the transistor is different, the size of the conduction current generated between the source and the drain is also different; when the transistor is turned off, the source and the drain will not be turned on and no current will be generated. In addition, the N-type transistor is turned on when the level of the control end is high, the first end and the second end are turned on, and a conduction current is generated between the first end and the second end; the N-type transistor is turned off when the level of the control end is low, the first end and the second end are not turned on, and no current is generated. The P-type transistor is turned on when the level of the control end is low, the first end and the second end are turned on, and a conduction current is generated; the P-type transistor is turned off when the level of the control end is high, the first end and the second end are not turned on, and no current is generated.

[0057] Figure 3 The input and output of a standard cell under the influence of TSV are shown in the corresponding relationship diagram of time, the horizontal coordinate is time, and the vertical coordinate is input or output (voltage), Figure 3The upper graph is a schematic diagram of the input of the standard cell versus time, and the lower graph is a schematic diagram of the output of the standard cell versus time. Taking a standard cell as a NOT gate as an example, in general, a high-level signal is input to the standard cell, and correspondingly, a low-level signal is output from the standard cell; a low-level signal is input to the standard cell, and correspondingly, a high-level signal is output from the standard cell. This corresponding change relationship between the input and the output is referred to as the flip characteristic of the standard cell.

[0058] Figure 3 The abscissa shown is divided into six intervals by T1, T2, T3, T4, T5 and T6. In the interval of 0-T1, the input of the standard cell is a high level; in the interval of T1-T4, the input of the standard cell is converted to a low level; and in the interval of T4-T6, the input of the standard cell is converted to a high level. In general, in the interval of 0-T1, the output of the standard cell should be a low level; in the interval of T1-T4, the output of the standard cell should be a high level; and in the interval of T4-T6, the output of the standard cell should be a high level.

[0059] However, because the stress of the TSV will affect the standard cells around the TSV, the mobility of the standard cells will fluctuate, and then the saturation current of the standard cells will be affected, leading to a delay in the flip of the standard cells, such as Figure 3 As shown in the lower graph, at the time T2, the input of the standard cell has been converted from a high level to a low level, but the output of the standard cell is converted from a low level to a high level until T3. The time period from T2 to T3 is the delay of the flip of the standard cell. The flip of the output signal is delayed relative to the change of the input signal. When the saturation current of the standard cell is affected by the TSV and becomes smaller, the delay of the standard cell increases.

[0060] The threshold voltage of the transistor refers to the pinch-off voltage of the depletion-mode transistor or the turn-on voltage of the enhancement-mode transistor. When the transistor is depletion-mode, the threshold voltage is a negative value, and the transistor is pinched off when the voltage is less than the threshold voltage. When the transistor is enhancement-mode, the threshold voltage is a positive value, and the transistor is turned on when the voltage is greater than the threshold voltage. Therefore, the standard cell can only work when the input voltage is greater than the threshold voltage.

[0061] The change of the threshold voltage of the transistor will affect the noise margin of the standard cell. The noise margin refers to the maximum noise amplitude allowed to ensure that the next stage can normally operate under the worst output quality of the previous stage. The noise margin can reflect the anti-interference performance of the standard cell. The greater the noise margin, the stronger the anti-interference performance.

[0062] Figure 4The figure shows the schematic diagram of the noise margin change of the standard cell under the influence of TSV. Taking the high level noise as an example, for the transistor, if the output of the previous stage is greater than V2, it is high level, recorded as "1" output, and the output range is V2-V1, while for the input of the next stage, the input is high level when it is greater than V5, recorded as "1" input, and for the transistor, V5 is the threshold voltage.

[0063] Without the influence of TSV stress, the noise margin is the difference between the minimum value of the output of the previous stage and the threshold voltage of the transistor of the next stage, recorded as V3, and then V3 is the difference between V2 and V5. Then for the transistor of the next stage, without the influence of TSV stress, the "1" input is the difference between the maximum value of the output of the previous stage and the threshold voltage of the transistor of the next stage, recorded as V7, and then V7 is the difference between V1 and V5.

[0064] Under the influence of TSV stress, the threshold voltage of the transistor is increased from V5 to V6, and in this case, the noise margin is recorded as V4, and V4 is the difference between V2 and V6. Since V6 is greater than V5, the noise margin is reduced under the influence of TSV stress. The range of "1" input is also reduced from V7 to V8, where V8 is the difference between V1 and V6.

[0065] Therefore, compared with the noise margin V3 of the standard cell without TSV influence, the noise margin V4 of the standard cell under the influence of TSV is smaller, and the anti-interference ability is worse.

[0066] In order to avoid the influence of TSV stress on the standard cell leading to abnormal operation of the standard cell, an embodiment of the present application provides a possible implementation, which sets a sacrifice area outside the process keep out zone (KoZ). As shown in the figure, Figure 5 According to the process manufacturing rules, the sacrifice area 008 is defined outside the KoZ009. The process keep out zone 009 is a region planned outside the TSV according to the process manufacturing rules, and the standard cell 010 is prohibited to be arranged in this region. The sacrifice area 008 is a region reserved by estimating the factors affected by TSV stress, such as the change in carrier mobility, through numerical simulation or experiment. Because the influence of TSV stress on the standard cell 010 is positively correlated with the distance, the farther the distance between the standard cell 010 and the TSV, the smaller the influence of the stress. Therefore, the sacrifice area is defined outside the KoZ, the standard cell 010 is prohibited to be arranged in the sacrifice area 008, and the standard cell 010 can be arranged outside the sacrifice area 008, so as to reduce the influence of TSV stress on the standard cell by increasing the distance.

[0067] While setting a sacrificial region outside the KoZ can mitigate the impact of TSV stress on the mobility and threshold voltage of standard cells, this design places all standard cells outside the same sacrificial region, prohibiting any standard cells within it. In reality, different standard cells have different operational regions within the sacrificial region. For example, assuming two different types of standard cells: an AND gate and an OR gate, the AND gate cannot function properly at a distance of d1 from the TSV, while the OR gate can. Therefore, the boundaries of the operational regions outside the KoZ for the AND and OR gates are different. This approach of uniformly placing all standard cells outside the same sacrificial region to mitigate TSV stress increases the circuit area and the length of the metal interconnects connecting the standard cells, resulting in a significant waste of resources.

[0068] The circuit fabrication method provided in this application can be applied to electronic devices, for example, see [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device 020 provided in an embodiment of this application, as shown below. Figure 6 As shown, the electronic device 020 may include a processor 021, a communication line 022, and a communication interface 023.

[0069] For example, the electronic device 020 may further include a memory 024. The processor 021, memory 024, and communication interface 023 can be connected via a communication line 022. The processor 021 may be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device, or any combination thereof. The processor 021 may also be other devices with processing functions, such as circuits, devices, or software modules.

[0070] Communication line 022 is used to transmit information between various components of electronic device 020.

[0071] Communication interface 023 is used for communication with other devices or communication networks. This communication network can be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. Communication interface 023 can be an interface circuit, pins, RF module, transceiver, or any device capable of enabling communication.

[0072] Memory 024 is used to store instructions. These instructions can be computer programs for executing the circuit fabrication method provided in the embodiments of this application. Memory 024 can be a read-only memory (ROM) or other type of static storage device capable of storing static information and / or instructions; it can also be a random access memory (RAM) or other type of dynamic storage device capable of storing information and / or instructions; or it can be an electrically erasable programmable read-only memory (EEPROM), a compact optical disc (CD-ROM), or other optical disc storage, optical disk storage, magnetic disk storage media, or other magnetic storage devices. Optical disc storage includes compressed optical discs, laser discs, optical discs, universal digital optical discs, or Blu-ray discs, etc.

[0073] It should be noted that the memory 024 can exist independently of the processor 021, or it can be integrated with the processor 021. The memory 024 can be used to store instructions, program code, or some data, etc. The memory 024 can be located inside or outside the electronic device 020, without limitation. The processor 021 is used to execute the instructions stored in the memory 024 to implement the circuit fabrication method provided in the following embodiments of this application.

[0074] In one example, processor 021 may include one or more CPUs, for example Figure 6 CPU0 and CPU1 in the CPU.

[0075] As an optional implementation, electronic device O20 includes multiple processors, for example, besides Figure 6 In addition to processor 021, it may also include processor 027.

[0076] As an optional implementation, the electronic device 020 also includes an output device 025 and an input device 026. Exemplarily, the input device 026 may be a keyboard, mouse, microphone, or joystick, etc., and the output device 025 may be a display screen, speaker, etc. It should be noted that the electronic device 020 may be a desktop computer, laptop, network server, mobile phone, tablet computer, wireless terminal, embedded device, chip system, or other similar device. Figure 6 Electronic devices with similar structures. Furthermore... Figure 6 The structural composition shown herein does not constitute a limitation on the processing device, except that Figure 6In addition to the components shown, the electronic device 020 may include more or fewer components than those shown, or combine certain components, or have different component arrangements.

[0077] based on Figure 6 The illustrated electronic device 020 illustrates a circuit fabrication method provided in this application embodiment to address the resource waste problem caused by sacrificial region design in existing technologies. For example, the circuit fabrication method provided in this application embodiment can be applied to processing devices or electronic devices capable of implementing three-dimensional packaging design. Specifically, some or all of the workflow of the circuit fabrication method provided in this application embodiment can be implemented using electronic design automation (EDA) tools or other layout design and simulation tools configured in the electronic device; this application does not specifically limit this approach.

[0078] The method provided in this application embodiment is to identify the working boundaries of each standard unit, divide different working areas for different standard units, and set different standard units in their respective working areas when designing the circuit layout to achieve efficient utilization of resources.

[0079] For example, in combination Figure 7 , Figure 7 The diagram shown is a schematic flowchart of a circuit fabrication method provided in an embodiment of this application. The circuit fabrication method provided in this embodiment includes:

[0080] S110: Obtain the type and location information of the standard unit, including the angle and distance.

[0081] Location information includes distance and angle. The distance is the distance from the center of the standard element to the center of the TSV, and the angle is the angle between the line connecting the center of the TSV to the center of the standard element and the horizontal line connecting the center of the standard element. Standard elements are divided into different types based on their internal structure. Different types of standard elements have different structures and are affected differently by TSV stress, so different standard elements have different working areas. Therefore, to determine the working area of ​​each standard element, it is necessary to first know its type and location information. In practical applications, when a user sets a standard element at a certain location using simulation tools or EDA tools, the type, distance, and angle parameters of the standard element can be obtained by parsing the type parameters of the standard element and its relative position to the TSV.

[0082] S130: Determine whether the standard unit is within the working area based on the type, distance, angle, and a pre-set position information table.

[0083] The working area is the region where each standard unit can function normally in the sacrificial area. Within this region, the function of each standard unit meets the design requirements.

[0084] The location information table stores boundary information for the working areas of different types of standard cells. This boundary information includes a first included angle and a first distance. The first included angle is the angle between the line connecting the center of the TSV to the center of the standard cell and the horizontal line connecting the center of the standard cell. The first distance is the minimum working distance from the center of the standard cell to the center of the TSV corresponding to the first included angle. For example, at angle A, the minimum working distance required for the standard cell to meet the requirements is d. This point is the boundary corresponding to angle A. At angle A, if the distance from the center of the standard cell to the center of the TSV is greater than d, the standard cell can function normally; if the distance is less than d, the standard cell cannot function normally.

[0085] Furthermore, different types of standard cells have different structures, and the minimum working distance from the center of the corresponding standard cell to the center of the TSV also varies. The location information table can store the boundary information of the working area corresponding to different types of standard cells.

[0086] After determining the type, distance, and angle of the standard cell, based on the distance and angle of the standard cell and the boundary information of the work area corresponding to the standard cell stored in the location information table, it is determined whether the standard cell is located within the work area.

[0087] S150: If the standard cell is outside the working area, obtain the position information of the standard cell after the position is updated, until the standard cell is inside the working area.

[0088] When the standard cell is located outside the working area, for example, if the standard cell is too close to the TSV, the standard cell cannot work properly, and the designed circuit may not meet the design requirements. Therefore, it is necessary to adjust the position of the standard cell and move the standard cell. In general, the angle of the standard cell and the distance from the center of the standard cell to the center of the TSV can be changed. Since the influence of the standard cell on the TSV is positively correlated with the distance from the center of the standard cell to the center of the TSV, one approach is to increase the distance without changing the angle; another approach is to adjust the angle without changing the distance; or both the angle and the distance can be adjusted.

[0089] After the standard cell's position is adjusted, the updated position information of the standard cell is obtained, and it is determined again whether it is within the work area. If it is within the work area, the position adjustment is stopped. If it is still outside the work area, the position of the standard cell can be adjusted again, and the determination is repeated until the standard cell is within the work area.

[0090] This application embodiment determines the working boundary line of the standard cell within the area enclosed by the sacrificial region and KoZ by repeatedly using controlled variables. This boundary line consists of numerous minimum distances, each with a corresponding angle. Because the types of standard cells differ, each type has a working boundary line. The area facing the sacrificial region from the working boundary line is the interior of the working region; placing the standard cell within this region allows it to function normally. Compared to methods that prohibit the placement of standard cells throughout the entire sacrificial region, placing standard cells within the working region still meets requirements such as delay and flip-flop characteristics. However, the locations of these standard cells may have originally been designated as sacrificial regions where their placement was prohibited. Therefore, the solution provided by this application embodiment can reduce the waste of design resources.

[0091] In the example above, the system determines whether the standard cell is within the working area based on its location and a pre-stored location information table. If the standard cell is outside the working area, the user is prompted to change its location, obtain the updated location information, and the system checks again until the standard cell is within its working area. However, as mentioned in the previous example, the delay of the standard cell varies depending on its location, the stress of the TSV, and the length of the metal interconnect connecting it to other standard cells, causing changes in the timing of the digital chip.

[0092] Digital chips consist of numerous standard units connected by metal interconnects. They are designed with specific functions, and to meet these specific requirements, the order of signal flow must be accurate. Different standard units at different locations have different delays, and these delays affect the order of signal flow.

[0093] The sequence of signal flows required for specific functions of a digital chip has a time range. (See also...) Figure 8 The digital chip consists of standard unit A, standard unit B, and standard unit C. Standard unit A and standard unit C are connected by a metal connecting wire; standard unit B is connected to standard unit C by a metal connecting wire. Signal 1 is transmitted to C through A, and signal 2 is transmitted to C through B. To ensure the functionality of this digital chip, C must process signal 1 first.

[0094] Since the transmission times of signal one and signal two are almost the same, the timing of signal A's output signal needs to be earlier than that of signal B's output signal; in other words, the delay of A must be less than the delay of B. Assuming the delay of B is 0.2 picoseconds, then the delay of A needs to be controlled below 0.2 picoseconds, which is the delay range that standard unit A should meet. If the delay of A is greater than 0.2 picoseconds, then the delay of A is outside the set delay range. Since different positions will result in different delays, the position of standard unit A can be continuously adjusted to find a position that meets the set delay range.

[0095] To ensure that the delay of the standard unit meets the set requirements, for example, refer to... Figure 9 After determining that the standard cell is within the working area, the circuit fabrication method provided in this application embodiment further includes:

[0096] S170: Based on the location information, determine whether the delay of the standard cell is within the set range according to the pre-set standard cell timing table.

[0097] The standard cell timing table stores the type of the standard cell, its location information, and the corresponding influence factor. Multiplying the influence factor by the delay of the standard cell without TSV stress yields the delay of the standard cell under TSV stress. To ensure the sequential order of signal flow required for specific functions of the digital chip, the delay of the standard cell needs to be within a set range. Taking standard cells A, B, and C as an example again, to ensure the timing requirement of signal priority from A to C, the delay range of standard cell A must be smaller than that of standard cell B.

[0098] After determining the type, distance, angle, and corresponding initial delay of the standard element, the delay of the standard element under the influence of TSV stress is calculated based on the distance, angle, initial delay, and influence factor of the standard element stored in the standard element timing table, and it is determined whether the delay of the standard element meets the requirements.

[0099] S190: If the delay of the standard unit is outside the set range, obtain the position information of the standard unit after the position is updated, until the delay is within the set range.

[0100] Standard cells within the set delay range meet timing requirements, while standard cells outside the set timing range do not. Taking standard cells A, B, and C as examples, if the delay range of standard cell A is greater than that of B, the signal transmission priority changes to standard cell B first, then standard cell C. There will be a lag in the transmission from standard cell A to standard cell C, which will cause changes in the timing of the digital chip and thus affect its functionality. In this case, it is necessary to adjust the position of the standard cells within the working area to ensure that the timing meets the set range.

[0101] When the standard cell is outside the set range, its delay cannot meet the requirements, and the designed circuit may not meet the design requirements. Therefore, it is necessary to adjust the position of the standard cell. Since the delay of the standard cell is related to its position, it can be adjusted by changing its position within the working area. Generally, this can be achieved by changing the angle of the standard cell and the distance from its center to the center of the TSV. One approach is to increase the distance without changing the angle; another is to adjust the angle without changing the distance; or, alternatively, both the angle and distance can be adjusted.

[0102] After the position of the standard unit is adjusted, the position information of the updated standard unit and the delay corresponding to the updated position information are obtained. It is then determined whether the position is within the set range. If it is within the set range, the position adjustment is stopped. If it is still outside the set range, the position of the standard unit can be adjusted again, and the determination is repeated until the delay of the standard unit meets the set range.

[0103] This application embodiment determines the set range within which the standard unit meets the delay requirement by repeatedly controlling variables. Within this set range, the standard unit's delay meets the requirement; outside the set range, the delay requirement cannot be met. This application embodiment uses a location information table to determine the working range of the standard unit. The functional requirements of the standard unit are met at any position within the working area. However, the standard units are connected by metal interconnects, and the different positions of the standard units lead to varying interconnect lengths, which may ultimately result in timing discrepancies in the digital chip or difficulty in timing optimization. Further testing with a standard unit timing table after confirming the standard unit's working area ensures that the digital chip's timing meets the requirements. Compared to methods that prohibit the placement of standard units throughout the entire sacrificial region, this method allows for the placement of standard units in positions within the working area that meet timing requirements, shortening the interconnect distance and improving resource utilization.

[0104] However, before utilizing the location information table, it is necessary to pre-establish the location information table and the standard cell timing table. For example, the method provided in this application, before determining whether the standard cell is within the working area based on type, distance, angle, and the location information table, refers to... Figure 10 The methods also include:

[0105] S101: Determine the location information table.

[0106] By calling the device model in computer software that can characterize TSV stress, the relationship between the delay and switching characteristics of the transistor inside the standard cell and the distance from the center of the TSV is obtained. The simulation structure of the standard cell with TSV is designed, and the simulation is continuously performed from the KoZ boundary to obtain the positional relationship between the delay and switching characteristic requirements set for production and the TSV. The working area is divided according to the minimum working distance.

[0107] Figure 11 A flowchart of another circuit fabrication method provided in an embodiment of this application is shown. (See attached document.) Figure 11 S101 includes:

[0108] S101-a: Call the device model of any type of standard cell that characterizes TSV stress to establish the simulation structure of the standard cell with TSV; the model is used to indicate the correspondence between the delay and switching characteristics of the transistor inside the standard cell and the position information of the standard cell.

[0109] like Figure 12a The diagram illustrates the effect of TSV stress on the transistor mobility within a standard cell. Figure 12b The diagram shows the effect of TSV stress on the threshold voltage change of the transistor inside the standard cell. Figure 12a , Figure 12b The horizontal axis in the figure represents the distance from the center of the standard cell to the center of the TSV. Figure 12a The vertical axis represents mobility. It can be seen that as the distance between the transistor and the center of the TSV increases, the rate of increase in mobility is first large and then small. Figure 12b The vertical axis represents the change in threshold voltage. The left side of the dashed line represents the process clearance area, where there is no threshold voltage because no standard cell is set. The right side of the dashed line shows the change in the threshold voltage of the transistor as the distance from the center of the standard cell to the center of the TSV increases, with the rate decreasing from large to small.

[0110] Figure 13a A schematic diagram illustrating the effect of TSV stress on the saturation current of transistors within a standard cell is shown. Figure 13b This is a schematic diagram illustrating the effect of TSV stress on the threshold voltage of the transistor inside the standard cell, provided as an embodiment of this application. Figure 13a ,Figure 13b The horizontal axis represents the distance from the center of the standard cell to the center of the TSV. Figure 13a The vertical axis represents the saturation current. The area to the left of the dashed line represents the process clearance area, where there is no saturation current because no standard units are set up. The area to the right of the dashed line shows that the saturation current increases with increasing distance, and the rate of increase decreases. Figure 13b The vertical axis represents the threshold voltage. The left side of the dashed line represents the process clearance area. Since no standard cells are set in the process clearance area, there is no threshold voltage. The right side of the dashed line indicates that the threshold voltage of the transistor increases with the increase of distance, and the rate decreases from fast to slow.

[0111] S101-b: Adjust the position of the standard element and determine the first distance corresponding to each first included angle of the standard element.

[0112] S101-c: Determine the working area boundary information of each first included angle and the first distance corresponding to the first included angle.

[0113] In one possible implementation, the first included angle of the standard cell is set as the starting angle, and the distance to the center of the TSV is set as the initial distance. The distance from the center of the standard cell to the center of the TSV is increased by a set distance step until the minimum working distance at the starting angle that satisfies the preset requirements for delay and flip characteristics is determined. The minimum working distance is set as the first distance, where the initial distance is the radius of the process clearance area.

[0114] Then, adjust the first included angle of the standard cell in a set angular step size. Determine the minimum working distance at which the delay and flip characteristics meet preset requirements after adjusting the first included angle, until the first included angle of the standard cell is adjusted to the termination angle. Determine the first distance corresponding to the termination angle; the sum of the termination angle and the starting angle is 2π. Define the first distance corresponding to the first included angle of the standard cell as the boundary information of the working area. (See also...) Figure 14a and Figure 14b , Figure 14a This is a schematic diagram of the delay of a standard unit provided in an embodiment of this application. Figure 14b This is a schematic diagram illustrating the flipping characteristics of a standard unit provided in an embodiment of this application. Figure 14a This reflects the relationship between the delay of the standard cell and its distance from the center of the TSV. The horizontal axis represents the distance from the center of the standard cell to the center of the TSV, and the vertical axis represents the delay of the standard cell. The dashed line L2 represents a pre-set delay threshold. To the left of dashed line L2, the delay of the standard cell does not meet the pre-set requirement; to the right of dashed line L2, the delay of the standard cell meets the pre-set requirement. The working area that meets the delay requirement of the standard cell is defined by the delay threshold represented by the dashed line.

[0115] Figure 14bThis reflects the switching characteristics of the standard cell. The horizontal axis represents the input voltage, and the vertical axis represents the output voltage. Without the influence of TSV, the switching characteristics of the standard cell are as shown by the dashed line L3, where the output voltage changes from high to low through L3. Due to TSV stress, as the distance from the center of the standard cell to the center of the TSV increases, the dashed line L3 shifts to the left and right, forming a region abcd between the two solid lines. Within this region abcd, the switching characteristics of the standard cell are satisfied, thus defining the working area that meets the switching characteristics of the standard cell. The switching characteristic requirements are determined by the constraints of the register setup and hold times.

[0116] S101-d: Establish the location information table based on the type and the boundary information of the work area.

[0117] The type of standard cell and the corresponding boundary information of that type of standard cell are stored in a location information table. For example, if there are multiple different types of standard cells, then there may be boundary information for the work area corresponding to multiple different types of standard cells.

[0118] For example, S130 includes determining whether the standard unit is located within the work area. For example, the boundary information of the work area corresponding to the type in the location information table is determined based on the type of the standard unit to determine whether the standard unit is located within its corresponding work area.

[0119] First, determine the first included angle between the boundary information center of the work area corresponding to the standard cell and the angle based on the angle of the standard cell. Then, compare the distance of the standard cell with the first distance corresponding to the first included angle. If the distance of the standard cell is greater than or equal to the first distance, it is determined that the standard cell is within the work area; otherwise, it is determined that the standard cell is outside the work area.

[0120] Before using the standard cell timing table, a timing table needs to be created in advance. Before determining whether the delay of the standard cell falls within the set range based on the updated position information and the pre-defined standard cell timing table, please refer to [the relevant documentation / reference]. Figure 15 The method provided in this application embodiment further includes:

[0121] S102: Determine the timing table for the standard cell.

[0122] For example, determining the standard cell timing table S102 can be done as follows: Figure 15 As shown, before obtaining the type and location information of the standard unit, including the type distance and angle S110, it can also be done in any step before determining whether the delay of the standard unit is within the set range based on the pre-set standard unit timing table according to the updated location information S170.

[0123] Figure 16 A flowchart of another circuit fabrication method provided in an embodiment of this application is shown. (See attached document.) Figure 16 S102 includes:

[0124] S102-a: Call up any type of device model that characterizes TSV stress; establish a simulation structure with standard cells containing TSV; wherein the device model is used to indicate the correspondence between the delay of the standard cell and the position information of the standard cell.

[0125] S102-b: Determine the delay of the standard cell under the influence of TSV at the current location, and determine the ratio of the delay to the initial delay of the standard cell as the influence factor at that location. The initial delay refers to the delay of the standard cell without the influence of TSV.

[0126] Determine the delay of the standard cell under the influence of TSV at the current position, and determine the ratio of this delay to the initial delay of the standard cell as the influence factor at that position. The initial delay refers to the delay of the standard cell without the influence of TSV. This delay can be directly obtained from simulation by any type of device model without TSV.

[0127] S102-c: Adjust the position of the standard unit, determine the impact factor after the adjustment, and establish a time series table of the standard unit based on the correspondence between the position and the impact factor corresponding to the position.

[0128] In one possible implementation, the angle of the standard cell is set as the starting angle, and the distance to the center of the TSV is set as the initial distance. The distance from the center of the standard cell to the center of the TSV is increased in a set distance step until the minimum distance at the starting angle that satisfies the preset requirements for delay and flip characteristics is determined. Here, the initial distance is the radius of the process clearance area.

[0129] The angle of the standard cell is adjusted by a set angle step. After the adjustment angle is determined, the delay and flip characteristics meet the minimum distance required by the preset requirements until the angle of the standard cell is adjusted to the termination angle. The sum of the termination angle and the starting angle is 2π.

[0130] Then, simulations are performed based on various process angle models to obtain the delay of various types of standard cells under the influence of TSV stress at different angles and / or distances. The ratio of this delay to the initial delay is determined as the influence factor at that angle and / or distance. Each standard cell at a specific location has a specific influence factor. Using the influence factor, it is no longer necessary to design a simulation structure for standard cells with TSV stress based on the device model; only the device model of any type without TSV stress is needed to simulate the initial delay and then calculate the delay of the standard cell under the influence of TSV stress. Furthermore, calculating the delay of standard cells under the superposition of multiple TSV stresses using the method of multiplying the initial delay is more convenient.

[0131] For example, S170 further includes determining whether the standard unit is within a set delay range, confirming information stored in the location information table that matches the type of the standard unit based on its type, confirming the influence factor at that location, and obtaining the delay at that location under the influence of TSV by multiplying the influence factor by the initial delay. There is a delay range based on the sequential relationship of signal flows required by the specific function of the digital chip. Whether the delay of the standard unit meets this range is determined.

[0132] EDA tools are design software aids and programmable chip aids. They have powerful functions and can generally be used for circuit design and simulation. They can also perform automatic placement and routing of chip layouts, and output various netlist files for interconnection with third-party software. EDA tools can be broadly classified into three categories: chip design aids, programmable chip design aids, and system design aids.

[0133] For example, when implementing the circuit fabrication method provided in the embodiments of this application using EDA tools, for each standard cell, a working area will be obtained after the above method, such as... Figure 17 As shown, the standard unit 330 is located within the work area 322.

[0134] The boundary line is established by the minimum distance at each preset step angle. (See also...) Figure 18 For standard cells, setting them in the process clearance area 310 poses a manufacturing risk. Therefore, EDA tools are prohibited from setting standard cells in the process clearance area 310. For example, it is prohibited to set standard cells in... Figure 18 The position d shown in the figure.

[0135] Outside the process clearance area 310, for each standard cell, the traditional sacrificial area 320 is divided into a working area 322 and a failure area 321. The delay and toggle characteristics of the standard cells in the working area 322 meet the design requirements, while the delay and toggle characteristics of the standard cells in the failure area 321 may not meet the design requirements. Therefore, standard cells are also prohibited from being placed in the failure area 321. For example, it is prohibited to place standard cells in... Figure 18 The position c is shown in the figure.

[0136] Standard cells can be prevented from being located within work area 322, for example... Figure 18 The position shown is either a or b, but it is also necessary to determine whether the delay of the standard cell meets the requirements. For example, if the delay of the standard cell at position a (R,θ) does not meet the requirements, the position of the standard cell is updated until the standard cell moves to position b (R',θ') where the timing meets the requirements and then stops moving.

[0137] For example, the following is a portion of the code used by EDA to determine the working area boundary of a standard cell:

[0138]

[0139]

[0140] The following is a portion of the code used by EDA to determine the timing table of a standard cell:

[0141]

[0142] First, the `spacing R angleθlayer TSV` statement is used in the EDA TechFile to configure each standard cell according to the final configuration rules obtained in the circuit fabrication method. Here, `R` and `θ` represent the minimum distance and the angle corresponding to that minimum distance, respectively. Second, simulation is used to obtain the timing influence factor of a single TSV stress on each different standard cell in the working region.

[0143] For example, the influence factor is calculated based on the ratio of the simulation structure of the standard cell in the working area of ​​the device model design to the simulation structure of the standard cell with TSV in the working area to meet the timing requirement boundary value. Each determined θ and R corresponds to a determined influence factor.

[0144] In one possible implementation, the influence factors for power consumption and noise can also be calculated in the same manner and added to the timing statement in a lookup table format. Determining the influence factors facilitates the direct calculation of the impact of multiple TSVs on timing, power consumption, and noise. For example, for multiple TSVs, the EDA tool can multiply the influence factors to calculate the timing, power consumption, and noise characteristics after the stress of multiple TSVs is superimposed.

[0145] See Figure 19 The diagrams show two different circuit designs. Figure 19 As shown in the left-middle figure, in traditional circuit design schemes, a unified sacrificial region 320 is defined outside the process clearance area 310 for different standard cells 330. The standard cells 330 can only be placed outside the sacrificial region 320, which leads to a waste of design resources. According to the circuit fabrication method provided in the embodiments of this application, as follows... Figure 19 As shown in the middle right figure, a device model characterizing TSV stress is used to divide the sacrificial region 320 into a working region 322 and a failure region 321 through simulation. Standard cells 330 can be placed within the working region 322, and placement rules for each type of standard cell 330 are established, i.e., different working regions 322 are assigned to different standard cells 330. Placing different standard cells 330 within different working regions 322 improves the rational utilization of resources.

[0146] This application also provides a circuit design apparatus, such as... Figure 20 As shown, the device 500 includes an acquisition module 501 and a processing module 502.

[0147] The acquisition module 501 is used to acquire the type and location information of the standard cell. The location information includes angle and distance. The distance is the distance from the center of the standard cell to the center of the through silicon via (TSV). The angle is the angle between the line connecting the center of the TSV to the center of the standard cell and the horizontal line of the center of the standard cell.

[0148] The processing module 502 is used to determine whether the standard unit is within the working area based on the type, distance, angle and a pre-set position information table. The position information table stores the boundary information of the working area of ​​different types of standard units. The boundary information includes a first included angle and a first distance. The first included angle is the angle between the line connecting the center of the TSV to the center of the standard unit and the horizontal line of the center of the standard unit. The first distance is the minimum working distance from the center of the standard unit to the center of the TSV corresponding to the first included angle.

[0149] The acquisition module 501 is also used to acquire the position information of the standard unit after the standard unit is updated when the standard unit is outside the work area, until the standard unit is inside the work area.

[0150] This application also provides a computer-readable storage medium storing computer instructions that, when executed by a computer or processor, enable the computer or processor to perform a method characterizing TSV technology stress.

[0151] This application also provides a chip that stores computer instructions. When the computer instructions are executed by a processor, they can perform a method to characterize the stress of TSV technology.

[0152] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0153] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0154] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of fabricating a circuit, characterized by, The method comprises: acquiring type and position information of a standard cell, the position information comprising an angle and a distance, the distance being a distance from a center of a through silicon via to a center of the standard cell, and the angle being an included angle between a line connecting the center of the through silicon via and the center of the standard cell and a horizontal line passing through the center of the standard cell; determining whether the standard cell is in a working area according to the type, the distance, the angle, and a pre-set position information table, the position information table storing boundary information of the working area of the standard cell of different types, the boundary information comprising a first included angle and a first distance, the first included angle being an included angle between a line connecting the center of the through silicon via and the center of the standard cell and a horizontal line passing through the center of the standard cell, and the first distance being a minimum working distance from the center of the standard cell corresponding to the first included angle to the center of the through silicon via; if the standard cell is outside the working area, acquiring position information of the standard cell after the position of the standard cell is updated until the standard cell is in the working area.

2. The method of claim 1, wherein if the standard cell is outside the working area, acquiring position information of the standard cell after the position of the standard cell is updated until the standard cell is in the working area, the method further comprising: determining whether a delay of the standard cell belongs to a pre-set range according to the position information and based on a pre-set standard cell timing table; if the delay is outside the pre-set range, acquiring position information of the standard cell after the position of the standard cell is updated until the delay is within the pre-set range.

3. The method of claim 1 or 2, wherein before determining whether the standard cell is in the working area according to the type, the distance, the angle, and the position information table, the method further comprising: determining the position information table.

4. The method of claim 3, wherein the determination of the position information table comprising: calling a device model of any type of standard cell representing stress of a through silicon via to establish a simulation structure of the standard cell with the through silicon via, wherein the model is used to indicate a corresponding relationship between a delay and a flip characteristic of a transistor inside the standard cell of the type and position information of the standard cell; adjusting the position of the standard cell to determine the standard cell at each first distance corresponding to each first included angle; determining each first included angle and the first distance corresponding to the first included angle as boundary information of the working area of the standard cell of the type; establishing the position information table according to the type and the boundary information of the working area.

5. The method of claim 4, wherein the adjustment of the position of the standard cell to determine the standard cell at each first distance corresponding to each first included angle comprising: setting the first included angle of the standard cell as a starting angle and a distance from the center of the standard cell to the center of the through silicon via as an initial distance, increasing the distance from the center of the standard cell to the center of the through silicon via by a pre-set distance step until a minimum working distance at which the delay and the flip characteristic meet pre-set requirements is determined at the starting angle, wherein the initial distance is a radius of a process clearance area; adjusting a first included angle of the standard cell by a set angle step, determining a minimum working distance after adjusting the first included angle, wherein the delay and the flip characteristics meet preset requirements, until the first included angle of the standard cell is adjusted to a terminal angle, and a sum of the terminal angle and the initial angle is 2π.

6. The method of fabricating a circuit according to claim 1 or 2, wherein The determining whether the standard cell is in the working area according to the type, the distance, the angle, and a preset position information table includes: determining boundary information of a working area corresponding to the type in the position information table according to the type of the standard cell; determining the first distance corresponding to the first included angle matching the angle in the boundary information of the working area according to the angle; if the distance is greater than or equal to the first distance, the standard cell is in the working area.

7. The method of claim 2, wherein Before determining whether the delay of the standard cell belongs to a set range based on a preset standard cell timing table according to the position information after the position is updated, the method further includes: determining the standard cell timing table.

8. The method of claim 2, wherein: The method for creating the standard cell timing table includes: calling a device model of any type of standard cell representing a through silicon via stress, establishing a simulation structure of the standard cell with the through silicon via; wherein the standard cell model is used to indicate a corresponding relationship between the delay of the type of standard cell and the position information of the standard cell; determining the delay of the standard cell under the influence of the through silicon via at the current position, determining an influence factor at the position as a ratio of the delay to an initial delay of the standard cell, wherein the initial delay refers to the delay of the standard cell without the influence of the through silicon via; adjusting the position of the standard cell, determining the influence factor after adjusting the position, and establishing the standard cell timing table by establishing a corresponding relationship between the position and the influence factor corresponding to the position.

9. The method of claim 2, wherein The standard cell timing table stores a corresponding relationship between the position information of the standard cell and the influence factor of the through silicon via on the delay of the standard cell, and the determining whether the timing of the standard cell belongs to a set range based on the preset standard cell timing table according to the position information after the position is updated includes: determining the influence factor according to the position information and the standard cell timing table; multiplying the influence factor and the initial delay of the standard cell to determine the delay of the standard cell under the influence of the through silicon via; determining whether the delay of the standard cell under the influence of the through silicon via belongs to a set range.

10. A circuit design apparatus, characterized by comprising: The device includes: an acquisition module, which acquires a type and position information of a standard cell, wherein the position information includes an angle and a distance, the distance is a distance from a center of the standard cell to a center of a through silicon via, and the angle is an included angle between a line connecting the center of the through silicon via to the center of the standard cell and a horizontal line of the center of the standard cell; The processing module determines whether the standard cell is in the working area according to the type, the distance, the angle, and a preset position information table. The position information table stores boundary information of the working area of the standard cell of different types. The boundary information includes a first included angle and a first distance. The first included angle is an included angle between a line connecting a center of the through silicon via and a center of the standard cell and a horizontal line of the center of the standard cell. The first distance is a minimum working distance from the center of the standard cell corresponding to the first included angle to the center of the through silicon via. If the standard cell is outside the working area, the acquisition module is further configured to acquire position information of the standard cell after the standard cell updates the position until the standard cell is in the working area.

11. A computer readable storage medium characterized by, The computer readable storage medium stores computer instructions. When the instructions are executed by the processor, the processor can execute the method in any one of claims 1-9.

12. A chip, characterized by The chip stores computer instructions. When the instructions are executed by the processor, the method in any one of claims 1-9 is implemented.

13. An electronic device, comprising: The electronic device includes: a processor and a memory; The processor is configured to execute computer instructions stored in the memory to implement the method in any one of claims 1-9.

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