Semiconductor device and manufacturing method thereof, and electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, belonging to the field of semiconductor technology, the semiconductor device comprising: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; the transistor comprising a gate electrode and a semiconductor layer; a bit line extending along a direction perpendicular to the substrate and connected to the plurality of semiconductor layers of the plurality of transistors; a word line extending along a first direction parallel to the substrate, comprising the gate electrode and a connecting electrode distributed in the first direction, the connecting electrode extending along the first direction and contacting the gate electrode; the semiconductor layer is an annular semiconductor layer, the sidewall of the annular semiconductor layer extending along a second direction parallel to the substrate, the gate electrode surrounding the outer sidewall of the semiconductor layer and being insulated from the semiconductor layer, the first direction intersecting the second direction. The semiconductor device is conducive to improving device density.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a semiconductor device, including:

[0006] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate; the transistors include a gate electrode and a semiconductor layer;

[0007] A bit line extending in a direction perpendicular to the substrate and connected to the plurality of semiconductor layers of the plurality of transistors;

[0008] A word line extending in a first direction parallel to the substrate, comprising the gate electrode and a connecting electrode distributed in the first direction, wherein the connecting electrode extends along the first direction and contacts the gate electrode;

[0009] The semiconductor layer is an annular semiconductor layer, the sidewall of the annular semiconductor layer extends along a second direction parallel to the substrate, the gate electrode surrounds the outer sidewall of the semiconductor layer and is insulated from the semiconductor layer, and the first direction intersects with the second direction.

[0010] In some embodiments, the semiconductor layer includes two ends opposite to each other in the second direction, and the bit line contacts at least one of one of the ends, an inner sidewall adjacent to the end, and an outer sidewall adjacent to the end of the semiconductor layer.

[0011] In some embodiments, a protrusion is disposed on a sidewall of the bit line, and the protrusion extends into an inner sidewall of the semiconductor layer and is connected to the inner sidewall.

[0012] In some embodiments, the plurality of semiconductor layers of the plurality of transistors are separated by a first insulating layer.

[0013] In some embodiments, the transistor further includes a first source / drain electrode, the first source / drain electrode contacts the inner side wall of the annular semiconductor layer, and the area on the annular semiconductor layer between the first source / drain electrode and the bit line is a channel area of ​​the transistor.

[0014] In some embodiments, the inner sidewall of the annular semiconductor layer includes a first source / drain electrode contact region and a bit line contact region, and the space enclosed by the inner sidewall of the annular semiconductor layer in the channel region is filled with a dielectric material;

[0015] The dielectric material and the bit line contact region of the semiconductor layer form an opening, and the protrusion of the bit line is filled in the opening;

[0016] The dielectric material and the first source / drain electrode contact region of the semiconductor layer form a hole, and the first source / drain electrode is located on the inner side wall of the hole.

[0017] In some embodiments, the orthographic projection of the first source / drain electrode on the substrate is located outside the orthographic projection of the gate electrode on the substrate.

[0018] In some embodiments, an orthographic projection of the gate electrode on the substrate does not overlap with an orthographic projection of the bit line on the substrate.

[0019] In some embodiments, the semiconductor device further comprises: a capacitor, the capacitor comprising a first electrode and a second electrode, the first electrode and the first source / drain electrode sharing a same electrode;

[0020] The second electrode is insulated from the first source / drain electrode by a dielectric layer, and the second electrode includes a first portion filling the hole where the first source / drain electrode is located.

[0021] In some embodiments, the semiconductor device further includes: a groove arranged between first source / drain electrodes adjacent to each other along a direction perpendicular to the substrate, and an opening of the groove faces away from the bit line, and the second pole further includes a second part filling the groove; the first part and the second part of the second pole are an integrated structure.

[0022] In some embodiments, a first insulating layer is provided between the stacked transistors, and the grooves are respectively provided in two first insulating layers adjacent to the first source / drain electrodes, and the two grooves extend in the first insulating layer toward the channel region and extend to the end of the gate electrode.

[0023] In some embodiments, the semiconductor device includes: a multi-layer memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array includes multiple rows and columns of memory cells distributed along the first direction and the second direction respectively, the memory cell includes the transistor and the capacitor, the multiple transistors are multiple transistors at the same position in different layers of memory cell arrays, the transistor and the capacitor of the same memory cell are arranged along the second direction, and the gate electrodes of any two adjacent transistors in the same row are connected through the connecting electrode.

[0024] In some embodiments, the semiconductor device includes a stacked first insulating layer and a sacrificial layer, the sacrificial layer is a conductive layer, the sacrificial layer has a through hole extending along the second direction, the through hole separates the sacrificial layer into a first connecting electrode and a second connecting electrode both extending in the first direction, the sidewall of the through hole includes an end of the first connecting electrode, an end of the second connecting electrode and two adjacent first insulating layers, the gate electrode is formed on the sidewall of the through hole and connected to the first connecting electrode and the second connecting electrode, and the semiconductor layer is formed on the sidewall of the through hole and insulated from the gate electrode.

[0025] In some embodiments, in the same column of memory cells, every two adjacent transistors are arranged facing each other, a bit line is provided between the two transistors, and the bit line is connected to the semiconductor layers of the two transistors at the same time.

[0026] In some embodiments, multiple semiconductor layers of memory cells in the same row are respectively connected to different bit lines.

[0027] In some embodiments, the different bit lines are located in the same trench and are spaced apart in the first direction and insulated from each other.

[0028] The present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, wherein the transistors comprise a gate electrode and a semiconductor layer; a bit line extending along a direction perpendicular to the substrate; and a word line comprising the gate electrode and connecting electrodes located on both sides of the gate electrode. The manufacturing method comprises:

[0029] Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate, wherein the sacrificial layers are conductive layers;

[0030] A plurality of grooves extending along a first direction are formed on the stack structure, the stack between any two adjacent grooves comprises a transistor region, and a word line region connecting the transistors and extending along the first direction, the word line region comprises a gate electrode region of the transistor region and two connection regions located on both sides of the gate electrode region, the connection regions extending along the first direction; an isolation layer penetrating the first insulating layer and the sacrificial layer and extending to the groove is provided between the two connection regions and the groove; the isolation layer of the groove exposes the first insulating layer and the sacrificial layer of the transistor region and shields the two connection regions;

[0031] Using the isolation layer as an etching barrier layer in the two trenches, etching the exposed sacrificial layers, so that the sacrificial layer between two adjacent trenches in the transistor region is etched to form a through hole, wherein the through hole disconnects the sacrificial layer and exposes the end of the sacrificial layer;

[0032] A gate electrode, a gate insulating layer and a semiconductor layer surrounding the side wall of each through hole are sequentially formed in each through hole, and the gate electrode is connected to the end of the disconnected sacrificial layer.

[0033] In some embodiments, forming a gate electrode surrounding the sidewall of each through hole in sequence in each through hole includes: depositing a gate electrode film covering the sidewall of each through hole and the two grooves; and dry etching to remove the gate electrode film covering the two grooves, so that the gate electrode films of different transistors are disconnected.

[0034] In some embodiments, sequentially forming a gate insulating layer and a semiconductor layer surrounding the sidewall of each through hole in each through hole comprises:

[0035] After forming mutually disconnected gate electrode films, sequentially depositing a gate insulating film, a semiconductor film, and a dielectric film covering the sidewalls of each through hole and the two trenches, wherein the dielectric film fills the through hole;

[0036] The dielectric film and the semiconductor film in the two grooves are removed by dry etching, so that the semiconductor films of different transistors are disconnected, and the remaining semiconductor film is the semiconductor layer of the transistor.

[0037] In some embodiments, the manufacturing method further includes: filling a dielectric layer in one of the grooves, patterning the dielectric layer to form a plurality of bit line grooves spaced apart in a first direction and extending in a direction perpendicular to the substrate, the bit line grooves exposing ends of the through holes, laterally etching back the dielectric film in the through holes in the bit line grooves to expose the inner side walls of the semiconductor layer as bit line contact areas, and filling the bit line grooves with conductive material to form bit lines connected to the inner side walls of the semiconductor layer.

[0038] In some embodiments, after forming the bit line, the method further includes: wet etching a gate electrode film in the through hole in another of the trenches to form the gate electrode;

[0039] The method further includes: after forming the gate electrode, etching back the dielectric film in the through hole in the other groove until it is close to the end of the gate electrode to form a hole; forming a conductive layer on the inner side wall of the semiconductor layer exposed by the removed dielectric film, the conductive layer being the first electrode of the capacitor; and forming a second electrode insulated from the first electrode on the inner side wall of the hole in which the first electrode is formed.

[0040] In some embodiments, when the through hole is formed, the sacrificial layer in the word line region is separated by the through hole to serve as a connecting electrode of the word line.

[0041] An embodiment of the present application provides an electronic device, including the semiconductor device provided by any of the above embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device.

[0042] The semiconductor device provided in the embodiment of the present application has a design structure that facilitates high-density device integration.

[0043] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0044] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0046] Figure 1A A top view of a semiconductor device is provided for an exemplary embodiment. Figure 1B For along Figure 1A Cross-sectional view along the BB direction, Figure 1C For along Figure 1A Cross-section view in the CC direction; Figure 1D A cross-sectional view of a semiconductor device along the BB direction provided for another exemplary embodiment;

[0047] Figure 2A A top view after replacing the sacrificial layer is provided for another exemplary embodiment; Figure 2B For along Figure 2A Cross-section view along the AA direction; Figure 2C For along Figure 2ACross-section along the BB direction; Figure 2D For along Figure 2A Cross-section view in the CC direction;

[0048] Figure 3A A top view of a plurality of stacked structures provided by an exemplary embodiment; Figure 3B For along Figure 3A Cross-section view along the AA direction;

[0049] Figure 4A A top view after a preset pattern is formed provided for an exemplary embodiment; Figure 4B For along Figure 4A Cross-section view along the AA direction;

[0050] Figure 5A A top view after forming a second trench and a third trench is provided for an exemplary embodiment; Figure 5B For along Figure 5A Cross-section view along the AA direction;

[0051] Fig. 6A A top view after lateral etching of a sacrificial layer is provided for an exemplary embodiment; Figure 6B For along Fig. 6A Cross-section along the BB direction;

[0052] Fig. 7A A top view after forming a gate electrode and a first dummy layer provided for an exemplary embodiment; Figure 7B For along Fig. 7A Cross-section along the BB direction;

[0053] Fig. 8A A top view after disconnecting the gate electrode and removing the first dummy layer provided in an exemplary embodiment; Figure 8B For along Fig. 8A Cross-section along the BB direction;

[0054] Fig.9A A top view after forming a gate insulating layer, a semiconductor layer and a third insulating layer provided for an exemplary embodiment; Fig. 9B For along Fig.9A Cross-section along the BB direction;

[0055] Fig. 10A A top view after a semiconductor layer is cut off provided for an exemplary embodiment; Fig. 10B For along Fig. 10A Cross-section along the BB direction;

[0056] Fig.11A A top view after forming a bit line is provided for an exemplary embodiment; Fig. 11B For along Fig.11A Cross-section along the BB direction;

[0057] Fig. 12A A top view of an exemplary embodiment after etching away a gate electrode located in a capacitor region; Fig. 12B For along Fig. 12A Cross-section along the BB direction;

[0058] Fig.13A A top view after exposing the semiconductor layer is provided for an exemplary embodiment; Fig. 13B For along Fig.13A Cross-section along the BB direction;

[0059] Fig.14A A top view after forming a first source / drain electrode and a second dummy layer provided for an exemplary embodiment; Fig. 14B For along Fig.14A Cross-section along the BB direction;

[0060] Fig.15A A top view after disconnecting the first source / drain electrode provided by an exemplary embodiment; Fig. 15B For along Fig.15A Cross-section along the BB direction;

[0061] Fig.16A A top view after forming a dielectric layer and a second pole is provided for an exemplary embodiment; Fig. 16B For along Fig.16A Cross-section view in the CC direction;

[0062] Fig.17 A top view after replacing the sacrificial layer provided for an exemplary embodiment;

[0063] Fig.18A A schematic cross-sectional view of a semiconductor device with exposed semiconductor layers provided by another exemplary embodiment;

[0064] Fig.18B A schematic cross-sectional view of a semiconductor device provided for another exemplary embodiment;

[0065] Fig.19A A top view of a semiconductor layer after being cut off is provided for an exemplary embodiment. Fig.19B For along Fig.19A Cross-section along the BB direction;

[0066] Fig. 20A A top view after forming a bit line is provided for an exemplary embodiment. Fig. 20B For along Fig. 20A Cross-section along the BB direction;

[0067] Fig.21A A top view after exposing the third groove is provided for an exemplary embodiment. Fig.21B For along Fig.21A Cross-section along the BB direction;

[0068] Fig.22A A top view of an exemplary embodiment after etching away the gate electrode and the first insulating layer located in the capacitor region. Fig. 22B For along Fig.22A Cross-section along the BB direction;

[0069] Fig.23A A top view after forming a third dummy layer is provided for an exemplary embodiment. Fig. 23B For along Fig.23A Cross-section along the BB direction;

[0070] Fig.24A A top view after exposing the semiconductor layer is provided for an exemplary embodiment; Fig. 24B For along Fig.24A Cross-section along the BB direction;

[0071] Fig.25A A top view after forming a first source / drain electrode and a second dummy layer provided for an exemplary embodiment; Fig.25B For along Fig.25A Cross-section along the BB direction;

[0072] Fig.26A A top view after disconnecting the first source / drain electrode provided by an exemplary embodiment; Fig.26B For along Fig.26A Cross-section along the BB direction; Fig.26C for Fig.26B A magnified view of the middle area 400;

[0073] Fig.27A A top view after the second dummy layer and the third dummy layer are removed by etching provided for an exemplary embodiment; Fig.27B For along Fig.27A Cross-section along the BB direction;

[0074] Fig.28A A top view after forming a dielectric layer and a second pole is provided for an exemplary embodiment; Fig.28B For along Fig.28A Cross-sectional view along CC direction. DETAILED DESCRIPTION

[0075] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0076] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0077] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0078] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0079] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0080] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0081] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0082] In the present disclosure, the first source / drain electrode may be a drain electrode and the second source / drain electrode may be a source electrode, or the first source / drain electrode may be a source electrode and the second source / drain electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0083] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0084] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0085] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0086] Figure 1A A schematic cross-sectional view or a top view of a semiconductor device is provided for an exemplary embodiment. Figure 1B For along Figure 1A Cross-sectional view along the BB direction, Figure 1C For along Figure 1A Cross-sectional view along CC direction. Figures 1A to 1C As shown, an embodiment of the present disclosure provides a semiconductor device, which may include a multi-layer memory cell array vertically stacked on a substrate 1, and the memory cell array may include a plurality of bit lines 30, a plurality of word lines 40, and a plurality of memory cells, and the plurality of memory cells may be arrayed along a first direction X and a second direction Y. The bit lines 30 may extend in a direction perpendicular to the substrate 1, the word lines 40 may extend in a first direction X in a plane parallel to the substrate, a plurality of word lines 40 in the same layer may be spaced apart in the second direction Y, and word lines 40 in different layers may be stacked and arranged on the substrate 1, extending in the same direction and spaced apart from each other. The first direction X and the second direction Y intersect, such as at 90 degrees.

[0087] The memory cell may be a 1T memory cell, or a 2T memory cell including a read transistor and a write transistor, such as a 2T0C or 2T1C memory cell. The 1T memory cell may be a FeFET ferroelectric memory, i.e., it includes a transistor and the gate insulating layer of the transistor is a ferroelectric layer. The 1T memory cell may be a 1T1C memory cell. If the memory cell is a 2T, the stacked transistors described in the embodiment of the present application may be a stack of read transistors or write transistors in a 2T memory cell in a 3D direction. Of course, other types of memory cells may also be used, and this application does not make specific limitations.

[0088] In the above embodiments, the semiconductor device at least includes a plurality of transistors stacked in a direction perpendicular to the substrate 1, each of which may include a gate electrode 26, a first source / drain electrode 51, a second source / drain electrode 52 and a semiconductor layer 23. The second source / drain electrode 52 may be a part of the bit line 30.

[0089] Taking the multiple transistors as different transistors in different layers of memory cell arrays as an example, the second source / drain electrodes 52 of each transistor at the same position on the two-dimensional plane of the different layers of memory cell arrays can be different regions of the same bit line 30. The gate electrode 26 can be a part of the word line 40, and the gate electrodes 26 of the transistors in the same row distributed along the first direction X can be different regions of the same word line 40. The gate electrodes 26 of the transistors in the same layer and row can be connected through the connecting electrode 27 to form a word line 40 extending along the first direction X.

[0090] In some embodiments, the memory cell includes a capacitor, the transistor and the capacitor of the same memory cell may be arranged along the second direction Y, and the capacitor may include a first electrode 41 and a second electrode 42, and a dielectric layer 43 disposed between the first electrode 41 and the second electrode 42. The first source / drain electrode 51 and the first electrode 41 may be the same electrode.

[0091] In some embodiments, in the memory cells of the same layer and the same column, every two memory cells are periodically distributed as a group, and the transistors of the memory cells of each group are close to each other, and the capacitors are far away from each other. This method can make the bit line shared between two adjacent transistors, that is, each group of memory cells shares a bit line 30. It can be understood that every two adjacent transistors are placed facing each other, and a bit line 30 is arranged between the two transistors, and the bit line 30 is connected to the semiconductor layer 23 of the two transistors at the same time.

[0092] Figure 1A , the semiconductor layers 23 of the transistors of a group of memory cells are connected to the same bit line 30. Since the semiconductor layers 23 of the transistors at the same position in different layers are connected to the same bit line 30, at this time, two memory cells adjacent to each other in the second direction Y in the same layer are connected to the same bit line 30.

[0093] In some embodiments, a plurality of semiconductor layers 23 of the same row of memory cells are respectively connected to different bit lines 30, such as Figure 1A As shown, the semiconductor layer 23 of the memory cells in the same row distributed along the first direction X is connected to different bit lines 30 extending in the longitudinal direction, and a plurality of bit lines 30 respectively connected to the semiconductor layer 23 of the memory cells in the same row are located in a trench extending along the first direction X, and different bit lines 30 are arranged at intervals in the trench.

[0094] In some embodiments, different bit lines 30 are located in different bit line trenches, which extend in a direction perpendicular to the substrate 1 . Different bit line trenches are formed by filling an insulating layer in the trenches and then etching openings or grooves. Different bit line trenches are spaced apart in the first direction X.

[0095] The following description is made by taking a semiconductor device including a plurality of memory cells stacked at the same position as an example, and taking a 1T1C memory cell as an example.

[0096] like Figures 1A to 1C As shown, an embodiment of the present disclosure provides a semiconductor device, which may include:

[0097] Multiple transistors are distributed in different layers and stacked in a direction perpendicular to the substrate 1; it can be understood that multiple transistors are stacked in a direction perpendicular to the substrate 1 to form a vertical storage cell column, and are insulated from each other in the direction perpendicular to the substrate 1;

[0098] A bit line 30, penetrating through the different layers and extending in a direction perpendicular to the substrate 1; one bit line 30 is connected to the plurality of transistors;

[0099] The transistor comprises a gate electrode 26 and a semiconductor layer 23, wherein the semiconductor layer 23 is an annular semiconductor layer extending along a second direction Y parallel to the substrate 1, and a sidewall of the annular semiconductor layer extends along the second direction Y;

[0100] The gate electrode 26 extends along the second direction Y and surrounds the outer sidewall of the semiconductor layer 23, and the gate electrode 26 forms a ring-shaped gate electrode; the sidewall of the ring-shaped gate electrode extends along the second direction Y; the semiconductor layer 23 includes an inner sidewall and an outer sidewall of the ring-shaped semiconductor layer, and two end surfaces connecting the inner sidewall and the outer sidewall, and one bit line 30 is simultaneously connected to the multiple semiconductor layers 23 of the multiple transistors;

[0101] The word line 40 extends along a first direction X parallel to the substrate 1, and includes the gate electrodes 26 and the connecting electrodes 27 distributed in the first direction X, and the connecting electrodes 27 extend along the first direction X and contact the gate electrodes 26; taking a row of memory cells as an example, a word line 40 includes the gate electrodes 26 alternately distributed in the first direction X and the connecting electrodes 27 connecting adjacent gate electrodes 26, and each of the connecting electrodes 27 extends along the first direction X and contacts the adjacent gate electrodes 26.

[0102] In the semiconductor device provided in this embodiment, the gate electrode of the word line is arranged around the outer wall of the semiconductor layer, and the bit line extends perpendicular to the substrate direction. Compared with the solution in which the bit line extends parallel to the substrate, since the total thickness of the stacked film layers is relatively small and the intervals between the bit lines are relatively large, it is convenient to reduce the coupling capacitance between the bit lines, reduce the capacitance of the bit lines, and help increase the device density.

[0103] The semiconductor device comprises a first insulating layer 10 and a third insulating layer 14 stacked in a direction perpendicular to a substrate 1 , and the plurality of semiconductor layers 23 of the plurality of transistors are separated by the first insulating layer 10 .

[0104] like Figure 1A The semiconductor device may include a plurality of memory cell regions 500 distributed at intervals. The memory cell region 500 may include a transistor region 501 and a capacitor region 200. Figure 1A The memory cell region 500 identified in FIG. 5 only includes the electrode region of the transistor and the capacitor connected to the transistor, and does not completely include the region where the other electrode of the capacitor is located.

[0105] The semiconductor layer 23 is distributed in the memory cell area 500 and is an annular semiconductor layer extending along the second direction Y. The semiconductor layer 23 surrounds the third insulating layer 14. The third insulating layer 14 is a dielectric material that fills the holes surrounded by the annular semiconductor layer 23 and is located in the channel area.

[0106] In some embodiments, the semiconductor layers 23 of the stacked transistors are disconnected from each other by the first insulating layer 10 or the gate insulating layer to ensure that they are not connected, that is, the semiconductor layers 23 of transistors in different layers are physically disconnected.

[0107] like Figure 1BThe transistor may further include a gate insulating layer 24, the gate insulating layer 24 surrounds the outer side wall of the semiconductor layer 23, and the gate electrode 26 surrounds the outer side wall of the gate insulating layer 24. The cross-sections of the semiconductor layer 23 and the gate electrode 26 are both closed rings, and the rings may be rectangular, square, circular or elliptical. The through hole formed in the annular semiconductor layer of the present application is realized by etching the sacrificial layer between adjacent first insulating layers 10, so the upper and lower surfaces of the through hole are planes, and the other two surfaces of the through hole are the morphology formed by wet etching the sacrificial layer.

[0108] like Figure 1B The sidewall of the annular semiconductor layer 23 extends in a direction parallel to the substrate 1, and includes two ends in the extending direction; it also includes a first source / drain electrode contact region and a bit line contact region close to the two ends, and a channel region between the first source / drain electrode contact region and the bit line contact region, and the annular semiconductor layer 23 in the channel region is filled with a dielectric material, that is, a third insulating layer 14. The third insulating layer 14 extends to the bit line 30 and the first source / drain electrode 51.

[0109] In some embodiments, the gate electrode 26 may be distributed in the channel region of the transistor region 501, but not in the capacitor region 200. In some embodiments, the gate electrode 26 may extend to the first source / drain electrode contact region, but not overlap the second electrode 42 of the capacitor, so as to avoid forming a large parasitic capacitance with the capacitor.

[0110] In some embodiments, the bit line 30 is connected to or in contact with at least one of one of the ends, the inner sidewall adjacent to the end, and the outer sidewall of the semiconductor layer 23 .

[0111] In some embodiments, the inner side wall of the annular semiconductor layer includes a first source / drain electrode contact area and a bit line contact area, and the space enclosed by the inner side wall of the annular semiconductor layer in the channel area is filled with a dielectric material; the dielectric material and the bit line contact area of ​​the semiconductor layer 23 form an opening, and the protrusion of the bit line 30 is filled in the opening; the dielectric material and the first source / drain electrode contact area of ​​the semiconductor layer 23 form a hole, and the first source / drain electrode 51 is located on the inner side wall of the hole.

[0112] like Figure 1D As shown, the side wall of the bit line 30 may be provided with a protrusion, which extends into the inner side wall of the semiconductor layer 23 and is connected to the inner side wall, and the protrusion is also connected to the third insulating layer 14 formed of a dielectric material, that is, the third insulating layer 14 and the semiconductor layer 23 in the bit line contact area form an opening, and the protrusion of the bit line 30 is located in the opening. Figure 1DAs shown, the bit line 30 can be connected to the inner side wall of the semiconductor layer 23 close to the end surface. In this embodiment, the protrusion can increase the contact area between the bit line 30 and the semiconductor layer 23, and can reduce the contact resistance. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the orthographic projection of the bit line 30 on the substrate 1 and the orthographic projection of the semiconductor layer 23 on the substrate 1 do not overlap, that is, the bit line 30 has no protrusion and is connected to the end of the semiconductor layer 23 only through the side wall of the bit line 30.

[0113] In some embodiments, the orthographic projection of the bit line 30 on the substrate 1 does not overlap with the orthographic projection of the semiconductor layer 23 on the substrate 1, and the gate electrode 26 extends to the gate insulating layer 24 to be insulated from the bit line 30, and the orthographic projection on the substrate 1 does not overlap with the orthographic projection of the bit line 30 on the substrate 1. The solution provided in this embodiment can reduce the coupling capacitance between the gate electrode 26 and the bit line 30.

[0114] In some embodiments, the protrusion of the bit line 30 is located in the opening, and the gate electrode 26 extends to the gate insulation layer 24 to be insulated from the bit line 30. In the actual manufacturing process, the projections of the gate electrode 26 and the protrusion on the bit line 30 on the substrate 1 may partially overlap.

[0115] In some embodiments, the size of the bit line 30 along the first direction X may be larger than the size of the bit line 30 along the second direction Y. Compared with the solution in which the size of the bit line 30 along the second direction Y is larger than the size along the first direction X, the coupling capacitance of adjacent bit lines can be further reduced.

[0116] In some embodiments, the transistor may further include a first source / drain electrode 51, the first source / drain electrode 51 may be disposed on the inner side wall of the annular semiconductor layer 23 and connected to a portion of the inner side wall of the semiconductor layer 23, the first source / drain electrode 51 is disposed near an end of the annular semiconductor layer 23 away from the bit line 30 and is located on the inner side wall of the annular semiconductor layer 23. For example, the first source / drain electrode 51 is connected to the inner side wall of the semiconductor layer 23 located in the capacitor region 200. The contact area between the first source / drain electrode 51 and the semiconductor layer 23 is the first source / drain electrode contact area, and the first source / drain electrode contact area is the inner side wall of the semiconductor layer 23. The first source / drain electrode 51 is a hollow cylindrical structure with an opening away from the bit line 30. The first source / drain electrode 51 is also connected to the third insulating layer 14, that is, the third insulating layer 14 and the first source / drain electrode contact area of ​​the semiconductor layer 23 form a hole, and the first source / drain electrode 51 may be located on the inner side wall of the hole.

[0117] In some embodiments, the gate electrode 26 has two ends in the sidewall extension direction, and the first source / drain electrode 51 can be disposed at one end of the gate electrode 26 away from the bit line 30. Figure 1A As shown, the gate electrode 26 is distributed in the transistor region 501 , the first source / drain electrode 51 is distributed in the capacitor region 200 , and the bit line 30 is located at one end of the gate electrode 26 away from the first source / drain electrode 51 .

[0118] In some embodiments, the orthographic projection of the first source / drain electrode 51 on the substrate 1 is located outside the orthographic projection of the gate electrode 26 on the substrate 1. For example, the first source / drain electrode 51 is shared with an electrode of a capacitor, the gate electrode 26 is distributed in the channel region of the transistor region 501, and the first source / drain electrode 51 is distributed in the capacitor region 200. In the solution provided in this embodiment, the orthographic projections of the gate electrode 26 and the first source / drain electrode 51 do not overlap, which can reduce the coupling capacitance between the gate electrode 26 and the first source / drain electrode 51.

[0119] In some embodiments, the orthographic projection of the first source / drain electrode 51 on the substrate 1 may overlap with the orthographic projection of the gate electrode 26 on the substrate 1. For example, the gate electrode 26 may be distributed in the entire memory cell area 500 in the second direction Y. It can be understood that the gate electrode 26 may surround the outer sidewall of the entire semiconductor layer 23, or extend around the channel region of the semiconductor layer 23 and the contact region of the first source / drain electrode 51, covering all or part of the contact region of the first source / drain electrode 51 (referred to as the first source / drain electrode contact region); the first source / drain electrode 51 is distributed in the capacitor area 200, that is, distributed on the inner sidewall of the semiconductor layer 23, extending from the channel region to one end of the semiconductor layer 23 until it extends to the end of the semiconductor layer 23. The length of the first pole of the capacitor area 200 is related to the depth of the first source / drain electrode 51 extending into the inner sidewall of the annular semiconductor layer 23, and the length can be set according to requirements.

[0120] In the solution provided by this embodiment, the gate electrode 26 extends to the capacitor region 200 to cover the contact area of ​​the first source / drain electrode 51 in the semiconductor layer 23. The gate electrode 26 can shield the signal between the adjacent first source / drain electrodes 51 along the direction perpendicular to the substrate 1, thereby reducing the coupling capacitance between the adjacent first source / drain electrodes 51 along the direction perpendicular to the substrate 1.

[0121] In some embodiments, the first source / drain electrode 51 may be provided with a first groove (also understood as a hole) with an opening facing away from the bit line 30. For example, the first source / drain electrode 51 is cylindrical with a bottom and sidewalls. The semiconductor device may also include: a capacitor, the capacitor includes a second electrode 42, the second electrode 42 includes a first part and a second part, the first part is insulated from the first source / drain electrode 51 by a dielectric layer 43 and fills the first groove. In this case, the first source / drain electrode 51 also serves as the first electrode 41 of the capacitor. The first source / drain electrode 51 may be provided with a first groove with an opening facing away from the bit line 30. The first groove may be realized by film deposition. For example, the semiconductor layer 23 is provided on a laterally extending column, the column is retracted relative to the semiconductor layer 23 to form a cavity, a conductive layer is deposited on the inner sidewall of the cavity, the conductive layer on the inner sidewall of the cavity contacts the semiconductor layer 23 and the end of the column, and the conductive layer forms a first groove according to the shape of the cavity.

[0122] In some embodiments, the semiconductor device may further include: a second groove whose opening is away from the bit line 30 and is arranged between the first source / drain electrodes 51 of adjacent transistors along a direction perpendicular to the substrate 1. Two second grooves are formed between each transistor and two adjacent transistors. The two second grooves are located in different layers of the first insulating layer, and the second grooves of different layers extend only in the first insulating layer and are not connected to each other. The second part of the second electrode 42 fills the second groove, and the orthographic projection of the second groove on the substrate 1 overlaps with the orthographic projection of the first source / drain electrode 51 on the substrate 1, and the first part of the second electrode 42 filled in the hollow first source / drain electrode 51 is connected to the second part of the second electrode 42 filled in the second groove to form an integrated structure.

[0123] In the solution provided in this embodiment, since the second electrode 42 is also arranged in the second groove, the second electrode 42 can shield the adjacent first source / drain electrodes 51, reduce the coupling capacitance between the adjacent first source / drain electrodes 51, and improve the stability of the device. In addition, compared with the second electrode 42 being only arranged on the inner side wall of the first electrode 41, that is, in the first groove, the second electrode 42 is also arranged on the outer side wall of the first electrode 41, thereby increasing the capacitance value.

[0124] In some embodiments, the orthographic projection of the second groove on the substrate 1 may overlap with the orthographic projection of the first source / drain electrode 51 on the substrate 1. Compared with the solution with only the first groove, the solution provided in this embodiment increases the capacitance without increasing the substrate area occupied by the capacitor. For example, the orthographic projection of the first source / drain electrode 51 on the substrate 1 may overlap with the capacitor area 200, and the orthographic projection of the second groove on the substrate 1 may overlap with the capacitor area 200. And the second groove is located in the first insulating layer between two adjacent transistors. The first groove and the second groove extend toward the channel region in the first insulating layer to the end of the gate electrode 26, respectively.

[0125] In some embodiments, the bottom of the second groove extends to the end of the gate electrode 26, and has no overlap with the gate electrode 26 in the longitudinal direction (perpendicular to the substrate 1), and the dielectric layer 43 is also distributed in the second groove, and the second electrode 42 is insulated from the gate electrode 26 by the dielectric layer 43. In this embodiment, the sidewall of the second groove along the direction perpendicular to the substrate 1 exposes the first insulating layer 10 and the gate electrode 26, and the dielectric layer 43 covers the first insulating layer 10 and the gate electrode 26.

[0126] The second groove is obtained by etching back the first insulating layer and the gate electrode, and the second groove exposes the semiconductor layers of two adjacent transistors.

[0127] In some embodiments, the second electrode 42 further fills the trenches penetrating the different layers between the memory cells adjacent along the second direction Y. That is, the second electrode 42 may include a third portion filling the trenches penetrating the different layers between two rows of memory cells adjacent along the second direction Y, and the third portion connects the second electrodes of the capacitors stacked at different layers.

[0128] In some embodiments, the gate electrode 26 is an annular electrode, and the cross-sectional sizes of different regions on the sidewall of the annular electrode are different, and there are two outward protrusions in the region contacting the connection electrode 27. Accordingly, the semiconductor layer 23 forms a similar structure according to the shape of the gate electrode.

[0129] like Figure 1A As shown, the gate electrode 26 is distributed in the transistor region 501, that is, the orthographic projection of the gate electrode 26 on the substrate 1 presents the shape of the transistor region 501, and the portion where the gate electrode 26 is connected to the connection electrode 27 protrudes outward relative to the portion not connected to the connection electrode 27, forming a cross-shaped structure. However, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the gate electrode 26 on the substrate 1 may be a straight line with the same width along the first direction X.

[0130] In some embodiments, the maximum distance of the gate electrode 26 along the first direction X is smaller than the maximum distance of the first source / drain electrode 51 along the first direction X. That is, the maximum size of the transistor region 501 along the first direction X is smaller than the maximum size of the capacitor region 200 along the first direction X.

[0131] In some embodiments, the semiconductor device comprises a first insulating layer 10 and a sacrificial layer stack, the sacrificial layer having a through hole extending laterally along the second direction Y, the through hole separating the sacrificial layer into a first connecting electrode and a second connecting electrode both extending in the first direction X; side walls of the first connecting electrode and the second connecting electrode extending along the first direction, and ends at both ends of the side walls; the side wall of the through hole comprises an end of the first connecting electrode and an end of the second connecting electrode and two adjacent first insulating layers; the side wall of the through hole also comprises ends of two adjacent second insulating layers 13 arranged in sequence in the first direction X;

[0132] The gate electrode 26 is located on each side wall of the through hole and is connected to the first connection electrode and the second connection electrode. The gate insulation layer 24 and the semiconductor layer 23 are sequentially formed on each side wall of the through hole. The dielectric material fills the area of ​​the through hole corresponding to the channel area.

[0133] FIG. 2A to FIG. 2D A schematic diagram of a semiconductor device is provided for another exemplary embodiment. In this embodiment, the memory cell comprises 1T1C, and the electrode area of ​​the capacitor is smaller than the electrode area of ​​the capacitor in the previous embodiment. FIG. 2A to FIG. 2D As shown, in this embodiment, the second groove is not provided, and the area where the second groove is located is filled with the first insulating film layer, such as the first insulating layer 10 and the gate insulating layer 24 stacked in sequence, and the gate insulating layer 24 is provided on the side of the first insulating layer 10 close to the substrate 1. In this embodiment, the second electrode 42 may include a portion filled in the grooves that penetrate the different layers between two rows of memory cells adjacent along the second direction Y, and a portion extending to the first grooves of different layers. The structure of the transistor can refer to the previous embodiment and will not be repeated.

[0134] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0135] In an exemplary embodiment, FIG. 2A to FIG. 2D The manufacturing process of the semiconductor device shown may include:

[0136] 101) forming a stacking structure;

[0137] The forming of the stacked structure may include: Figure 3B , providing a substrate 1, depositing a sacrificial layer film and a first insulating film alternately on the substrate 1 in sequence, forming a plurality of stacked structures by a patterning process, and forming a hard mask layer 9 on the formed plurality of stacked structures, such as Figure 3A and Figure 3B As shown, Figure 3A A top view of a plurality of stacked structures is provided for an exemplary embodiment. Figure 3B For along Figure 3A The cross-sectional view along the AA direction. Figure 3B As shown, the stacking structure may include a stack of alternating sacrificial layers 11 and first insulating layers 10, that is, a first insulating layer 10 is arranged on the sacrificial layer 11 to form a stacking structure, and multiple stacking structures are stacked in a vertical direction. Multiple stacking structures are understood as multiple sacrificial layers and first insulating layers being alternately and cyclically distributed.

[0138] It is understandable that the sacrificial layer does not mean that the entire layer needs to be sacrificed and removed, and at least a part of the layer may be sacrificed. The sacrificial layer may be an insulating layer or a conductive layer.

[0139] In some embodiments, substrate 1 may be a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0140] In some embodiments, the first insulating film and the sacrificial layer film may be deposited by chemical vapor deposition.

[0141] In some embodiments, the first insulating film may be a low-K dielectric layer used for isolation between storage units, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0142] In some embodiments, the sacrificial layer film may be a conductive material or a non-conductive material that is not used for the first insulating film. The sacrificial layer film may be, for example, the following conductive materials:

[0143] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals; or, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials; or, it may be doped conductive polysilicon, silicon, germanium, silicon germanium, etc.

[0144] In some embodiments, the hard mask layer 9 includes but is not limited to at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0145] Figure 3B The three stacked structures shown in the figure include three first insulating layers 10 and three sacrificial layers 11, which are only examples. In other embodiments, the stacked structures may include more or fewer first insulating layers 10 and sacrificial layers 11 that are alternately arranged.

[0146] 102) etching the plurality of stacked structures to form a preset pattern, including:

[0147] like Figure 4A As shown in the top view, the plurality of stacked structures are etched to form a plurality of first trenches T1 penetrating the plurality of stacked structures; each of the first trenches T1 enables the first insulating layer 10 and the sacrificial layer 11 to form a preset pattern;

[0148] A storage cell region is defined between every four adjacent first trenches T1, wherein the four first trenches T1 include two straight trenches spaced apart in the first direction X, and two T-shaped trenches spaced apart in the first direction X;

[0149] A straight groove and a T-shaped groove are arranged alternately in the second direction, the T-shaped groove includes a straight groove extending in the first direction X and a groove extending in the second direction Y, and the straight grooves in the T-shaped groove are adjacent to each other;

[0150] The above-mentioned grooves are arranged at intervals, and the interval area is a stacked sacrificial layer 11 and a first insulating layer 10. There is an interval area between two T-shaped grooves, and there is an interval area between adjacent straight grooves and T-shaped grooves. In other words, the interval area between the above-mentioned four grooves is distributed in an integrated manner, and the area between the two straight grooves and the adjacent area of ​​the T-shaped groove is the word line area. The adjacent two groups of four grooves are distributed in a mirror image.

[0151] The above structural features can also be understood through the following content: the area between two first trenches T1 spaced apart in the first direction (x direction) is a transistor area or a storage unit area; the area between two first trenches T1 spaced apart in the second direction (y direction) is a connection area connecting the gate of the transistor.

[0152] The preset pattern is a pattern complementary to the four grooves, specifically including: Figure 4A As shown, a plurality of word line regions 100 extending along a first direction X, a plurality of capacitor regions 200 spaced apart along the first direction X, a plurality of isolation regions 300 extending along the first direction X, the word line region 100 includes a plurality of connection regions 401 and a plurality of transistor regions 501, the plurality of connection regions 401 are spaced apart by the transistor regions 501, and spaced apart along the first direction X, the word line region 100, the isolation region 300, and the capacitor region 200 are separated by a first trench T1; the isolation region 300 includes a plurality of bit line regions 301; and a bit line 30 is subsequently formed in the bit line region 301;

[0153] A second insulating film is deposited in each first trench T1 and polished to form a second insulating layer 13 filling the first trench T1; the second insulating layer 13 may be flush with the hard mask layer 9. Figure 4A and Figure 4B As shown, Figure 4A A top view after forming a preset pattern is provided for an exemplary embodiment. Figure 4B For along Figure 4A The second insulating layers 13 corresponding to the four trenches isolate the multiple memory cells formed subsequently.

[0154] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0155] 103) forming a second trench T2 and a third trench T3, comprising:

[0156] Etching Figure 4A The multiple stacked structures are formed as follows Figure 5A The second trench T2 and the third trench T3 shown running through the plurality of stacked structures, the second trench T2 extends along the first direction X, the third trench T3 extends along the first direction X, the second trench T2 and the third trench T3 are spaced apart along the second direction Y; the second trench T2 exposes the second insulating layer 13 filled in the first trench T1, the first insulating layer 10 and the sacrificial layer 11 of the stacked structure. The third trench T3 exposes the second insulating layer 13 filled in the first trench T1, the first insulating layer 10 and the sacrificial layer 11 of the stacked structure.

[0157] A row of memory cells is included between the second trench T2 and the third trench T3, and two rows of mirror-distributed memory cells can be included between the two third trenches T3. The second trench T2 and the third trench T3 are used to isolate adjacent memory cells of different rows and form a common bit line in this area. In addition, the manufacture of transistors also requires opening a through hole in the sacrificial layer 11 between the second trench T2 and the third trench T3, and depositing the gate electrode, gate insulation layer and semiconductor layer of the transistor in sequence in the through hole.

[0158] like Figure 5A and Figure 5B As shown, Figure 5A A top view after forming the second trench T2 and the third trench T3 is provided for an exemplary embodiment. Figure 5B For along Figure 5A The sacrificial layer 11 can be subsequently wet-etched laterally in the second trench T2 and the third trench T3 using the first insulating layer and the second insulating layer as etching barriers. The second trench T2 is the region where the isolation region 300 is located.

[0159] 104) Laterally etching the sacrificial layer 11;

[0160] The lateral etching of the sacrificial layer 11 includes: simultaneously performing wet lateral etching of the sacrificial layer 11 in the second trench T2 and the third trench T3, etching back the sacrificial layer 11 exposed between the first insulating layer 10 and the second insulating layer, until the sacrificial layer between the second trench T2 and the third trench T3 is removed, and a through hole K1 connected to the second trench T2 and the third trench T3 is formed; it can be understood that the sacrificial layer 11 located in the capacitor area 200 and the transistor area 501 is removed, and the sacrificial layer 11 forms a plurality of disconnected connecting sub-portions 111 distributed along the first direction, and the connecting sub-portions 111 are separated by the transistor area 501, such as Fig. 6A and Figure 6B As shown, Fig. 6A A top view of an exemplary embodiment after lateral etching of the sacrificial layer 11 is provided. Figure 6B For along Fig. 6A Cross-sectional view along the BB direction. The BB direction is parallel to the AA direction.

[0161] In some embodiments, on a plane parallel to the substrate 1, the cross section of the through hole K1 may include two parts, a first part located in the capacitor region 200 and a second part located in the transistor region 501. The first part may be a square, etc., and the second part may be a square, or the second part may be a structure with two side walls facing the connection electrode and protrusions facing the connection electrode. The size of the second part along the first direction X may be smaller than the size of the first part along the first direction X. Fig. 6A The shape of the through hole K1 shown is only an example and other shapes are possible.

[0162] It can be understood that the first part of the through hole is located between the two T-shaped grooves, exposing the second insulating layer 13 of the T-shaped grooves;

[0163] Specifically, the first portion is located outside the inline region (lateral portion of the T) of the two T-shaped grooves, that is, located between the second insulating layers 13 extending along the second direction Y.

[0164] The second portion is the portion of the through hole excluding the first portion, and includes not only the portion between two disconnected sacrificial layers 11, but also the portion between the second insulating layers 13 of two adjacent I-shaped grooves, and the portion between the second insulating layers 13 of the I-shaped regions of two adjacent T-shaped grooves.

[0165] 105) forming a gate electrode 26 and a first dummy layer 61;

[0166] The forming of the gate electrode 26 and the first dummy layer 61 may include: depositing a first conductive film and a first dummy layer film in sequence on the substrate 1 where the through hole K1, the second trench T2 and the third trench T3 are formed, to form the gate electrode 26 and the first dummy layer 61, wherein the first dummy layer 61 fills the second trench T2, the third trench T3 and the through hole K1. Fig. 7A and Figure 7B As shown, Fig. 7A A top view after forming the gate electrode 26 and the first dummy layer 61 is provided for an exemplary embodiment. Figure 7B For along Fig. 7A Cross-sectional view along the BB direction.

[0167] In an exemplary embodiment, the first conductive film and the first dummy layer film may be deposited by an atomic layer deposition (ALD) method.

[0168] In some embodiments, the first conductive film may be a conductive material as follows:

[0169] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0170] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0171] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0172] In an exemplary embodiment, the first dummy layer film may be an insulating layer such as SiN.

[0173] The subsequent conductive film material is similar to the first conductive film material and will not be described in detail.

[0174] 106) disconnecting the gate electrodes 26 of different transistors and removing the first dummy layer 61;

[0175] The disconnecting the gate electrode 26 and removing the first dummy layer 61 may include: removing the first dummy layer 61 and the gate electrode 26 in the second trench T2 and the third trench T3 by dry etching. At this time, the gate electrode 26 located in the through hole K1 is protected by the first dummy layer 61 .

[0176] The first dummy layer 61 in the through hole K1 is removed by lateral etching. At this time, the entire first dummy layer 61 has been etched away. Fig. 8A and Figure 8B As shown, Fig. 8A A top view of an exemplary embodiment after disconnecting the gate electrode 26 and removing the first dummy layer 61 is provided. Figure 8B For along Fig. 8A Cross-sectional view along the BB direction.

[0177] 107) forming a gate insulating layer 24, a semiconductor layer 23 and a third insulating layer 14;

[0178] The forming of the gate insulating layer 24, the semiconductor layer 23 and the third insulating layer 14 may include: depositing a gate insulating film, a semiconductor film and a third insulating film (dielectric material) on the substrate 1 formed with the aforementioned structure in sequence to form the gate insulating layer 24, the semiconductor layer 23 and the third insulating layer 14, wherein the third insulating layer 14 fills the second trench T2, the third trench T3 and the through hole K1, as shown in FIG. Fig.9A and Fig. 9B As shown, Fig.9A A top view after forming a gate insulating layer 24, a semiconductor layer 23 and a third insulating layer 14 is provided for an exemplary embodiment. Fig. 9B For along Fig.9A Cross-sectional view along the BB direction.

[0179] In some embodiments, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material, or may be a low-K material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO 2 ) and other high-K materials.

[0180] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0181] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0182] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0183] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0184] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0185] In some embodiments, the third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0186] 108) disconnecting the semiconductor layers 23 of different transistors;

[0187] The disconnection of the semiconductor layer 23 may include: etching and removing the third insulating layer 14 and the semiconductor layer 23 located on the sidewalls and bottom walls of the second trench T2 and the third trench T3 to disconnect the semiconductor layers 23 of different layers and retain the gate insulating layer; in some embodiments, the third insulating layer 14 and the semiconductor layer 23 in the second trench T2 and the third trench T2 may be removed by dry etching, at which time, the semiconductor layers of transistors of different layers are physically disconnected. The semiconductor layer 23 located in the through hole K1 is protected by the third insulating layer 14;

[0188] A portion of the third insulating layer 14 is laterally etched to expose a portion of the inner sidewall of the semiconductor layer, and the inner sidewall and the third insulating layer 14 form an opening connected to the second trench T2; so that the width d2 of the second trench T2 located in the second sub-trench of the third insulating layer 14 along the direction parallel to BB is enlarged (greater than the width d1 of the second trench T2 located in the first sub-trench of the first insulating layer 10 along the direction parallel to BB), so that the contact area between the subsequently formed bit line 30 and the semiconductor layer 23 is larger, as shown in FIG. Fig. 10A and Fig. 10B As shown, Fig. 10A A top view of a semiconductor layer 23 after being disconnected is provided for an exemplary embodiment. Fig. 10B For along Fig. 10A The width of the sub-trench of the third trench T3 located in the third insulating layer 14 along the direction parallel to the BB direction may also be enlarged. However, the disclosed embodiment is not limited thereto. In another exemplary embodiment, the third insulating layer 14 may not be laterally etched, or the third insulating layer 14 may not be laterally etched in step 108, and the third insulating layer 14 may be laterally etched in step 109.

[0189] 109) forming a bit line 30;

[0190] The forming of the bit lines 30 may include: depositing a second conductive film on the substrate 1 forming the aforementioned structure, patterning to form a plurality of bit lines 30 extending in a direction perpendicular to the substrate 1 and a fourth trench T4 spacing adjacent bit lines 30; the bit lines 30 are located in the second trenches T2, and the plurality of bit lines 30 respectively connected to a plurality of transistors in the same row are spaced apart along the first direction X.

[0191] Depositing a fourth insulating film to form a fourth insulating layer 15, wherein the fourth insulating layer 15 fills the fourth trench T4 and the third trench T3;

[0192] Alternatively, a fourth insulating film is deposited on the substrate forming the aforementioned structure to form a fourth insulating layer 15, and the fourth insulating layer 15 fills the second trench T2 and the third trench T3;

[0193] The fourth insulating layer 15 is grooved to form a plurality of spaced bit line grooves, each of which exposes the end of the through hole K1, and the fourth insulating layer 15 is laterally etched back in the bit line groove (when the third insulating layer 14 is not laterally etched in step 108, the third insulating layer 14 may be laterally etched here) to expose the inner side wall of the semiconductor layer 23, and a second conductive film is deposited in the plurality of bit line grooves to form a plurality of bit lines 30 extending in a direction perpendicular to the substrate 1, the bit lines 30 are located in the bit line grooves, and the plurality of bit lines 30 respectively connected to the plurality of transistors in the same row are arranged at intervals along the first direction X. Fig.11A and Fig. 11BAs shown, Fig.11A FIG. 1 is a top view of an exemplary embodiment after a bit line 30 is formed. Fig. 11B For along Fig.11A Cross-sectional view along the BB direction.

[0194] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0195] 110) etching and removing the gate electrode 26 located in the through hole K1 of the capacitor region 200;

[0196] After the gate electrodes of transistors in different layers are disconnected and before the gate insulating layer is deposited, the etching and removal of the gate electrode 26 in the through hole K1 of the capacitor region 200 may include:

[0197] Dry etching to remove the fourth insulating layer 15 and the gate insulating layer 24 in the third trench T3, exposing the gate electrode 26 facing the side wall of the third trench T3;

[0198] The gate electrode 26 in the through hole K1 of the capacitor region 200 is removed by wet lateral etching; the capacitor region 200 extends from the third trench T3 to the lateral extension portion of the second insulating layer 13 in the T-shaped trench in the second direction Y (the lateral region of the T), and the gate electrode 26 between the lateral extension portions of the second insulating layer 13 in the T-shaped trench is retained.

[0199] A gate insulating film is deposited to fill the region where the gate electrode 26 is laterally etched; however, the embodiment of the present disclosure is not limited thereto, and other insulating film layers may be deposited to fill the region where the gate electrode 26 is laterally etched.

[0200] A fifth insulating film is deposited to form a fifth insulating layer 16 filling the third trench T3. Fig. 12A and Fig. 12B As shown, Fig. 12A A top view of an exemplary embodiment after etching away the gate electrode 26 located in the capacitor region 200 is provided. Fig. 12B For along Fig. 12A Cross-sectional view along the BB direction.

[0201] In some embodiments, the fifth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0202] 111) exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24;

[0203] The step of exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24 comprises: etching and removing the fifth insulating layer 16 in the third trench T3, and etching and removing the third insulating layer 14 located in the through hole K1 of the capacitor region 200 to form a first groove A1, thereby exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24, such as Fig.13A and Fig. 13B As shown, Fig.13A A top view of an exemplary embodiment after the semiconductor layer 23 is exposed is provided. Fig. 13B For along Fig.13A A cross-sectional view along the BB direction. It can be seen that the bottom wall of the third trench T3 exposes the substrate 1.

[0204] 112) forming a first source / drain electrode 51 and a second dummy layer 62;

[0205] The forming of the first source / drain electrode 51 and the second dummy layer 62 may include: depositing a third conductive film and a second dummy layer film on the substrate 1 forming the aforementioned structure in sequence to form the first source / drain electrode 51 and the second dummy layer 62, wherein the second dummy layer 62 fills the third trench T3 and the first groove A1, as shown in FIG. Fig.14A and Fig. 14B As shown, Fig.14A A top view after forming a first source / drain electrode 51 and a second dummy layer 62 is provided for an exemplary embodiment. Fig. 14B For along Fig.14A The first source / drain electrode 51 also serves as the first electrode 41 of the capacitor.

[0206] In some embodiments, the second dummy layer film may be SiN or the like.

[0207] 113) disconnecting the first source / drain electrodes 51 of different transistors;

[0208] The disconnecting the first source / drain electrodes 51 of different transistors may include: etching and removing the second dummy layer film and the first source / drain electrode 51 on the sidewall and bottom wall of the third trench T3 to disconnect the first source / drain electrodes 51 of different layers;

[0209] The second dummy layer 62 in the first groove A1 is removed by lateral etching. The first groove A1 can be understood as a hole. Fig.15A and Fig. 15B As shown, Fig.15A A top view after disconnecting the first source / drain electrode 51 is provided for an exemplary embodiment. Fig. 15B For along Fig.15A Cross-sectional view along the BB direction.

[0210] In some embodiments, the second dummy layer 62 and the first source / drain electrode 51 in the third trench T3 may be removed by dry etching.

[0211] 114) forming a dielectric layer 43 and a second electrode 42;

[0212] The forming of the dielectric layer 43 and the second electrode 42 may include:

[0213] A dielectric layer film and a fourth conductive film are sequentially deposited on the substrate 1 having the aforementioned structure to form a dielectric layer 43 and a second electrode 42. The dielectric layer 43 covers the sidewalls and bottom wall of the third trench T3 and the inner sidewall of the first groove A1. The second electrode 42 fills the third trench T3 and the first groove A1. Fig.16A , Figure 2C and Fig. 16B As shown, Fig.16A A top view of a dielectric layer 43 and a second electrode 42 after forming an exemplary embodiment is provided. Fig. 16B For along Fig.16A Cross-sectional view along CC direction.

[0214] In some embodiments, the dielectric layer 43 may be a High-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO 2 ) and other high-K materials.

[0215] When the sacrificial layer 11 is an insulating material, the sacrificial layer 11 is replaced with a conductive material to connect the gate electrodes 26 of the same layer distributed along the same direction X, that is, the following step 115) is performed; when the sacrificial layer 11 is a conductive material, the connecting sub-part 111 can directly connect the gate electrodes 26 of the same layer distributed along the same direction X, which is equivalent to the connecting electrode 27 of the aforementioned embodiment, and there is no need to perform step 115).

[0216] 115) forming a connecting electrode 27;

[0217] The forming of the connection electrode 27 may include: etching the plurality of stacked structures to form a fifth trench T5 penetrating the plurality of stacked structures, wherein the fifth trench T5 exposes a side wall of the sacrificial layer 11 parallel to the first direction X, and may expose only one side wall, or expose both side walls;

[0218] Wet lateral etching to remove the sacrificial layer 11 (ie, etching to remove the connecting sub-portion 111);

[0219] Depositing a fifth conductive film to fill the area where the connecting sub-portion 111 is located, and etching away the fifth conductive film in the fifth trench T5 to form a connecting electrode 27; the connecting electrode 27 is connected to the gate electrode 26, and the gate electrodes 26 in the same layer and row are connected through the connecting electrode 27 to form a word line 40 distributed along the first direction X;

[0220] Deposit a sixth insulating film to fill the fifth trench T5, forming Fig.17 , Figure 2B , Figure 2C and Figure 2D As shown, Fig.17 A top view after forming the connection electrode 27 is provided for an exemplary embodiment.

[0221] In some embodiments, the sixth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0222] The manufacturing method of the semiconductor device provided in this embodiment can form the word lines and semiconductor layers of multi-layer storage cells at one time, as well as the bit lines of multi-layer storage cells at one time, which is convenient for 3D stacking, and the spacing between the bit lines can be controlled to be a larger distance relative to the horizontally extending bit lines, which is convenient for reducing the coupling capacitance between the bit lines and enhancing the device performance.

[0223] In another exemplary embodiment, step 110) may not be performed, and the gate electrode 26 located in the through hole K1 of the capacitor region 200 is not etched and removed. In this embodiment, after step 109) is performed, the following steps are performed:

[0224] 110 ′) exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24;

[0225] The step of exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24 comprises: etching and removing the fourth insulating layer 15 in the third trench T3, and etching and removing the third insulating layer 14 located in the capacitor region 200 to form a first groove A1, thereby exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24, such as Fig.18A As shown, 18A is a cross-sectional view of a semiconductor device provided by an exemplary embodiment after the semiconductor layer is exposed along the BB direction.

[0226] 111') to 114'), similar to step 112) to step 115), forming a first source / drain electrode 51, a dielectric layer 43, a second electrode 42, and a connecting electrode 27, including:

[0227] A third conductive film and a second dummy layer film are sequentially deposited on the substrate 1 having the aforementioned structure to form a first source / drain electrode 51 and a second dummy layer 62, wherein the second dummy layer 62 fills the third trench T3 and the first groove A1;

[0228] The first source / drain electrode 51 on the sidewall and bottom wall of the third trench T3 is removed by etching to disconnect the first source / drain electrodes 51 of different layers, and the second dummy layer 62 located in the third trench T3 is removed by etching;

[0229] The second dummy layer 62 in the first groove A1 is removed by laterally etching;

[0230] Depositing a dielectric layer film and a fourth conductive film in sequence to form a dielectric layer 43 and a second electrode 42, wherein the dielectric layer 43 covers the sidewalls and bottom wall of the third trench T3 and the inner sidewall of the first groove A1, and the second electrode 42 fills the third trench T3 and the first groove A1;

[0231] Replace the connecting sub-portion 111 with the connecting electrode 27 to form Fig.18B The semiconductor device shown. Fig.18B The cross-sectional view of the semiconductor device provided in this embodiment along the BB direction. In this embodiment, the gate electrode 26 is also distributed in the through hole K1 of the capacitor area 200, that is, the gate electrode 26 is distributed in the entire memory cell area 500, and the rest is similar to the previous embodiment and will not be repeated. In the scheme provided in this embodiment, the gate electrode 26 can shield the first source / drain electrode 51, reduce the coupling capacitance between the adjacent first source / drain electrodes 51 in the direction perpendicular to the substrate 1, and improve the stability of the device.

[0232] In an exemplary embodiment, Figures 1A to 1C The manufacturing process of the semiconductor device shown may include:

[0233] 201)~207), same as steps 101)~107);

[0234] 208) disconnecting the semiconductor layer 23;

[0235] The disconnection of the semiconductor layer 23 may include: etching and removing the semiconductor layer 23 located on the sidewalls and bottom walls of the second trench T2 and the third trench T3 to disconnect the semiconductor layers 23 of different layers, and etching and removing the third insulating layer 14 located in the second trench T2 and the third trench T3; in some embodiments, the semiconductor layer 23 and the third insulating layer 14 in the second trench T2 and the third trench T2 may be removed by dry etching, at which time, the semiconductor layers of transistors of different layers are disconnected. The semiconductor layer 23 located in the through hole K1 is protected by the third insulating layer 14; Fig.19A and Fig.19B As shown, Fig.19AA top view of a semiconductor layer 23 after being disconnected is provided for an exemplary embodiment. Fig.19B For along Fig.19A Cross-sectional view along the BB direction.

[0236] In this embodiment, the width d2 of the second trench T2 located in the second sub-trench of the third insulating layer 14 along the direction parallel to BB is equal to the width d1 of the first sub-trench of the second trench T2 located in the first insulating layer 10 along the direction parallel to BB. However, the disclosed embodiment is not limited thereto, and the third insulating layer 14 may be laterally etched so that the width d2 of the second trench T2 located in the second sub-trench of the third insulating layer 14 along the direction parallel to BB may be greater than the width d1 of the first sub-trench of the second trench T2 located in the first insulating layer 10 along the direction parallel to BB, thereby making the contact area between the subsequently formed bit line 30 and the semiconductor layer 23 larger.

[0237] 209) forming a bit line 30;

[0238] The forming of the bit lines 30 may include: depositing a second conductive film on the substrate 1 forming the aforementioned structure, patterning to form a plurality of bit lines 30 extending in a direction perpendicular to the substrate 1 and fourth trenches T4 spacing adjacent bit lines 30; the bit lines 30 are located in the second trenches T2, and the plurality of bit lines 30 are spaced apart in the first direction X.

[0239] Depositing a fourth insulating film to form a fourth insulating layer 15, wherein the fourth insulating layer 15 fills the fourth trench T4 and the third trench T3;

[0240] Alternatively, a fourth insulating film is deposited on the substrate forming the aforementioned structure to form a fourth insulating layer 15, and the fourth insulating layer 15 fills the fourth trench T4 and the third trench T3;

[0241] The fourth insulating layer 15 is grooved to form a plurality of spaced bit line grooves, each of which is located at the end of a through hole K1, and the fourth insulating layer 15 is laterally etched back in the bit line groove to expose the inner side wall of the semiconductor layer 23, and a second conductive film is deposited in the plurality of bit line grooves to form a plurality of bit lines 30 extending in a direction perpendicular to the substrate 1, and the bit lines 30 are located in the bit line grooves, and the plurality of bit lines 30 respectively connected to the plurality of transistors in the same row are spaced apart along the first direction X. Fig. 20A and Fig. 20B As shown, Fig. 20A FIG. 1 is a top view of an exemplary embodiment after a bit line 30 is formed. Fig. 20B For along Fig. 20A Cross-sectional view along the BB direction.

[0242] 210) exposing the third trench T3;

[0243] Exposing the third trench T3 may include: etching away the fourth insulating layer 15 and the gate insulating layer 24 on the bottom wall and side wall of the third trench T3, exposing the side wall of the gate electrode 26 facing the third trench T3 and the side wall of the first insulating layer 10 facing the third trench T3, such as Fig.21A and Fig.21B As shown, Fig.21A A top view after exposing the third trench T3 is provided for an exemplary embodiment. Fig.21B For along Fig.21A The cross-sectional view along the BB direction. At this time, the film layers in the third trench T3 are all removed. The film layers in the third trench T3 can be removed by dry etching from the top layer to the bottom layer (stopping on the substrate 1).

[0244] 211) etching and removing the gate electrode 26 and the first insulating layer 10 located in the through hole K1 of the capacitor region 200;

[0245] The etching and removing of the gate electrode 26 and the first insulating layer 10 in the through hole K1 of the capacitor region 200 may include:

[0246] The gate electrode 26 and the first insulating layer 10 in the through hole K1 of the capacitor region 200 are removed by wet lateral etching to form a second groove A2. The gate electrode 26 in the second groove A2 is removed by etching to reduce the coupling capacitance between the gate electrode 26 and the first source / drain electrode 51 formed subsequently. The second electrode 42 of the capacitor can be deposited in the second groove A2 to increase the electrode area of ​​the capacitor. Fig.22A and Fig. 22B As shown, Fig.22A A top view after etching away the gate electrode 26 and the first insulating layer 10 in the through hole K1 of the capacitor region 200 provided in an exemplary embodiment, Fig. 22B For along Fig.22A Cross-sectional view along the BB direction.

[0247] 212) forming a third dummy layer 63;

[0248] The forming of the third dummy layer 63 may include: depositing a third dummy layer thin film on the substrate 1 having the aforementioned structure, patterning to form the third dummy layer 63, wherein the third dummy layer 63 fills the second groove A2 and is not disposed in the third trench T3, as shown in FIG. Fig.23A and Fig. 23B As shown, Fig.23A FIG. 1 is a top view after forming the third dummy layer 63 provided by an exemplary embodiment. Fig. 23B For along Fig.23A Cross-sectional view along the BB direction.

[0249] In some embodiments, the third dummy layer film may be an insulating layer such as SiN.

[0250] 213) exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24;

[0251] The step of exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24 comprises: etching and removing the third insulating layer 14 located in the through hole K1 of the capacitor region 200 to form a first groove A1, thereby exposing the surface of the semiconductor layer 23 located in the through hole K1 of the capacitor region 200 away from the gate insulating layer 24, such as Fig.24A and Fig. 24B As shown, Fig.24A A top view of an exemplary embodiment after the semiconductor layer 23 is exposed is provided. Fig. 24B For along Fig.24A Cross-sectional view along the BB direction.

[0252] 214) forming a first source / drain electrode 51 and a second dummy layer 62;

[0253] The forming of the first source / drain electrode 51 and the second dummy layer 62 may include: depositing a third conductive film and a second dummy layer film on the substrate 1 having the aforementioned structure in sequence to form the first source / drain electrode 51 and the second dummy layer 62, wherein the first source / drain electrode 51 covers the sidewall of the third trench T3 and the inner sidewall of the first groove A1, and the second dummy layer 62 fills the third trench T3 and the first groove A1. Fig.25A and Fig.25B As shown, Fig.25A A top view after forming a first source / drain electrode 51 and a second dummy layer 62 is provided for an exemplary embodiment. Fig.25B For along Fig.25A The first source / drain electrode 51 also serves as the first electrode 41 of the capacitor.

[0254] 215) disconnecting the first source / drain electrodes 51 of different transistors;

[0255] The disconnecting of the first source / drain electrodes 51 of different transistors may include: etching and removing the first source / drain electrodes 51 on the sidewalls and bottom wall of the third trench T3 to disconnect the first source / drain electrodes 51 of different layers, and etching and removing the second dummy layer 62 located in the third trench T3. Fig.26A , Fig.26B and Fig.26C As shown, Fig.26A A top view after disconnecting the first source / drain electrode 51 is provided for an exemplary embodiment. Fig.26B For along Fig.26A Cross-sectional view along the BB direction, Fig.26C for Fig.26BA magnified view of area 400.

[0256] In some embodiments, the second dummy layer 62 and the first source / drain electrode 51 in the third trench T3 may be removed by dry etching.

[0257] 216) etching and removing the second dummy layer 62 and the third dummy layer 63;

[0258] The etching and removing of the second dummy layer 62 and the third dummy layer 63 may include: laterally etching the second dummy layer 62 in the first groove A1 and the third dummy layer 63 in the second groove A2 by wet etching, such as Fig.27A and Fig.27B As shown, Fig.27A A top view of an exemplary embodiment after the second dummy layer 62 and the third dummy layer 63 are removed by etching. Fig.27B For along Fig.27A Cross-sectional view along the BB direction.

[0259] 217) forming a dielectric layer 43 and a second electrode 42;

[0260] The forming of the dielectric layer 43 and the second electrode 42 may include:

[0261] A dielectric layer film and a fourth conductive film are sequentially deposited on the substrate 1 having the aforementioned structure to form a dielectric layer 43 and a second electrode 42. The dielectric layer 43 covers the sidewalls and bottom wall of the third trench T3, the inner sidewall of the first groove A1, and the inner sidewall of the second groove A2. The second electrode 42 fills the third trench T3, the first groove A1, and the second groove A2. Fig.28A , Figure 1B and Fig.28B As shown, Fig.28A A top view of a dielectric layer 43 and a second electrode 42 after forming an exemplary embodiment is provided. Fig.28B For along Fig.28A Cross-sectional view along CC direction.

[0262] When the sacrificial layer 11 is an insulating material, the sacrificial layer 11 is replaced with a conductive material to connect the gate electrodes 26 of the same layer distributed along the first direction X, that is, the following step 218 is performed; when the sacrificial layer 11 is a conductive material, the sacrificial layer 11 can directly connect the gate electrodes 26 of the same layer distributed along the first direction X, without performing step 218).

[0263] 218) forming a connecting electrode 27;

[0264] The forming of the connection electrode 27 may include:

[0265] The plurality of stacked structures are etched to form a fifth trench T5 penetrating the plurality of stacked structures, wherein the fifth trench T5 exposes the sidewall of the sacrificial layer 11 parallel to the first direction X, and may expose only one sidewall of the sacrificial layer 11 parallel to the first direction X, or expose both sidewalls, and the position of the fifth trench T5 is referenced to Fig.17 ;

[0266] Wet lateral etching to remove the sacrificial layer 11 (ie, etching to remove the connecting sub-portion 111);

[0267] Depositing a fifth conductive film to fill the area where the connecting sub-portion 111 is located, etching and removing the fifth conductive film in the fifth trench T5 to form a connecting electrode 27; the connecting electrode 27 is connected to the gate electrode 26, and the gate electrodes 26 in the same layer and row are connected through the connecting electrode 27 to form a word line 40;

[0268] Deposit a sixth insulating film to fill the fifth trench T5, forming Figure 1A , Figure 1B , Figure 1C The structure shown.

[0269] The manufacturing method of the semiconductor device provided in this embodiment can form the connecting electrode of the word line of the multi-layer storage unit at one time through the conductive sacrificial layer, form the semiconductor layer of the transistors of different layers in one process, disconnect the semiconductor layer of the transistors of different layers in one process to remove the parasitic MOS, and form the bit line groove of each bit line in one process, and form each bit line extending vertically to the substrate in one process, which is convenient for 3D stacking, and the interval between the bit lines can be controlled to be a larger distance relative to the horizontally extending bit lines, which is convenient for reducing the coupling capacitance between the bit lines and enhancing the device performance. In addition, the second electrode 42 can be set in the first groove A1 and the second groove A2. Compared with the solution in which the second electrode 42 is only set in the first groove A1, the electrode area can be increased, thereby increasing the capacitance, and the second groove A2 is located in the insulating layer, without increasing the area occupied by the device. In addition, there is a second electrode 42 set in the second groove A2 between the first source / drain electrodes 51 of adjacent layers, which can shield the first source / drain electrodes 51 of adjacent layers, reduce the coupling between the first source / drain electrodes 51 of adjacent layers, and enhance the stability of the device.

[0270] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0271] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate; the transistors include a gate electrode and a semiconductor layer; A bit line extending in a direction perpendicular to the substrate and connected to the plurality of semiconductor layers of the plurality of transistors; A word line extending in a first direction parallel to the substrate, comprising the gate electrode and a connecting electrode distributed in the first direction, wherein the connecting electrode extends along the first direction and contacts the gate electrode; The semiconductor layer is an annular semiconductor layer, the sidewall of the annular semiconductor layer extends along a second direction parallel to the substrate, the gate electrode surrounds the outer sidewall of the semiconductor layer and is insulated from the semiconductor layer, and the first direction intersects with the second direction; The transistor also includes a first source / drain electrode, which is in contact with the inner side wall of the annular semiconductor layer, and the area on the annular semiconductor layer between the first source / drain electrode and the bit line is the channel area of ​​the transistor; the inner side wall of the annular semiconductor layer includes a first source / drain electrode contact area and a bit line contact area, and the space enclosed by the inner side wall of the annular semiconductor layer in the channel area is filled with a dielectric material; the dielectric material and the first source / drain electrode contact area of ​​the semiconductor layer form a hole, and the first source / drain electrode is located on the inner side wall of the hole.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer includes two ends opposite to each other in the second direction, and the bit line contacts at least one of one of the ends, an inner sidewall adjacent to the end, and an outer sidewall adjacent to the end of the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that A protrusion is disposed on the side wall of the bit line, and the protrusion extends into the inner side wall of the semiconductor layer and is connected to the inner side wall.

4. The semiconductor device according to claim 1, wherein: The semiconductor layers of the transistors are separated by a first insulating layer.

5. The semiconductor device according to claim 3, characterized in that The dielectric material and the bit line contact region of the semiconductor layer form an opening, and the protrusion of the bit line is filled in the opening.

6. The semiconductor device according to claim 1, wherein: The orthographic projection of the first source / drain electrode on the substrate is located outside the orthographic projection of the gate electrode on the substrate.

7. The semiconductor device according to claim 1, wherein: An orthographic projection of the gate electrode on the substrate does not overlap with an orthographic projection of the bit line on the substrate.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a capacitor, the capacitor comprising a first electrode and a second electrode, the first electrode and the first source / drain electrode sharing a same electrode; The second electrode is insulated from the first source / drain electrode by a dielectric layer, and the second electrode includes a first portion filling the hole where the first source / drain electrode is located.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device also includes: a groove arranged between first source / drain electrodes adjacent to each other in a direction perpendicular to the substrate, and the opening of the groove is away from the bit line, and the second pole also includes a second part filling the groove; the first part and the second part of the second pole are an integrated structure.

10. The semiconductor device according to claim 9, characterized in that A first insulating layer is arranged between the stacked transistors, and the grooves are respectively arranged in two first insulating layers adjacent to the first source / drain electrodes. The two grooves extend in the first insulating layer toward the channel region and extend to the end of the gate electrode.

11. The semiconductor device according to claim 8, characterized in that The semiconductor device includes: a multi-layer memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array includes multiple rows and columns of memory cells distributed along the first direction and the second direction respectively, the memory cell includes the transistor and the capacitor, the multiple transistors are multiple transistors at the same position in different layers of memory cell arrays, the transistor and the capacitor of the same memory cell are arranged along the second direction, and the gate electrodes of any two adjacent transistors in the same row are connected through the connecting electrode.

12. The semiconductor device according to claim 1, wherein: The semiconductor device includes a stacked first insulating layer and a sacrificial layer, the sacrificial layer is a conductive layer, the sacrificial layer has a through hole extending along the second direction, the through hole separates the sacrificial layer into a first connecting electrode and a second connecting electrode both extending in the first direction; the side wall of the through hole includes an end of the first connecting electrode, an end of the second connecting electrode and two adjacent first insulating layers, the gate electrode is formed on the side wall of the through hole and connected to the first connecting electrode and the second connecting electrode, and the semiconductor layer is formed on the side wall of the through hole and is insulated from the gate electrode.

13. The semiconductor device according to claim 11, characterized in that In the same column of storage cells, every two adjacent transistors are arranged facing each other, a bit line is arranged between the two transistors, and the bit line is connected to the semiconductor layers of the two transistors at the same time.

14. The semiconductor device according to claim 11, characterized in that The plurality of semiconductor layers of the same row of memory cells are respectively connected to different bit lines.

15. The semiconductor device according to claim 14, characterized in that The different bit lines are located in the same trench and are spaced apart in the first direction and insulated from each other.

16. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to the substrate, the transistors comprising a gate electrode and a semiconductor layer; a bit line extending along a direction perpendicular to the substrate; a word line extending along a first direction parallel to the substrate, comprising the gate electrode and connecting electrodes located on both sides of the gate electrode, the semiconductor layer being an annular semiconductor layer, the sidewall of the annular semiconductor layer extending along a second direction parallel to the substrate, the gate electrode surrounding the outer sidewall of the semiconductor layer and being insulated from the semiconductor layer, the first direction intersecting with the second direction; the transistor further comprising a first source / drain electrode, the first source / drain electrode contacting the inner sidewall of the annular semiconductor layer, the region on the annular semiconductor layer between the first source / drain electrode and the bit line being the channel region of the transistor; the inner sidewall of the annular semiconductor layer comprising a first source / drain electrode contact region and a bit line contact region, the space enclosed by the inner sidewall of the annular semiconductor layer in the channel region being filled with a dielectric material; the dielectric material and the first source / drain electrode contact region of the semiconductor layer forming a hole, the first source / drain electrode being located on the inner sidewall of the hole; The manufacturing method comprises: Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate, wherein the sacrificial layers are conductive layers; A plurality of grooves extending along a first direction are formed on the stack structure, the stack between any two adjacent grooves comprises a transistor region, and a word line region connecting the transistors and extending along the first direction, the word line region comprises a gate electrode region of the transistor region and two connection regions located on both sides of the gate electrode region, the connection regions extending along the first direction; an isolation layer penetrating the first insulating layer and the sacrificial layer and extending to the groove is provided between the two connection regions and the groove; the isolation layer of the groove exposes the first insulating layer and the sacrificial layer of the transistor region and shields the two connection regions; Using the isolation layer as an etching barrier layer in the two trenches, etching the exposed sacrificial layers, so that the sacrificial layer between two adjacent trenches in the transistor region is etched to form a through hole, wherein the through hole disconnects the sacrificial layer and exposes the end of the sacrificial layer; A gate electrode, a gate insulating layer and a semiconductor layer surrounding the side wall of each through hole are formed in sequence in each through hole, and the gate electrode is connected to the end of the disconnected sacrificial layer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The gate electrodes surrounding the side walls of the through holes are sequentially formed in each through hole, including: depositing a gate electrode film covering the side walls of each through hole and the two grooves; and dry etching to remove the gate electrode film covering the two grooves, so that the gate electrode films of different transistors are disconnected.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: Sequentially forming a gate insulating layer and a semiconductor layer surrounding the sidewall of each through hole in each through hole comprises: After forming mutually disconnected gate electrode films, sequentially depositing a gate insulating film, a semiconductor film, and a dielectric film covering the sidewalls of each through hole and the two trenches, wherein the dielectric film fills the through hole; The dielectric film and the semiconductor film in the two grooves are removed by dry etching, so that the semiconductor films of different transistors are disconnected, and the remaining semiconductor film is the semiconductor layer of the transistor.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The manufacturing method further includes: filling a dielectric layer in one of the grooves, patterning the dielectric layer to form a plurality of bit line grooves spaced apart in a first direction and extending in a direction perpendicular to the substrate, the bit line grooves exposing ends of the through holes, laterally etching back the dielectric film in the through holes in the bit line grooves to expose the inner side walls of the semiconductor layer as bit line contact areas, and filling the bit line grooves with a conductive material to form a bit line connected to the inner side walls of the semiconductor layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: After forming the bit line, the method further includes: wet etching a gate electrode film in the through hole in another of the trenches to form the gate electrode; The method further includes: after forming the gate electrode, etching back the dielectric film in the through hole in the other groove until it is close to the end of the gate electrode to form a hole; forming a conductive layer on the inner side wall of the semiconductor layer exposed by the removed dielectric film, the conductive layer being the first electrode of the capacitor; and forming a second electrode insulated from the first electrode on the inner side wall of the hole in which the first electrode is formed.

21. The method for manufacturing a semiconductor device according to claim 16, wherein: When the through hole is formed, the sacrificial layer in the word line region is separated by the through hole to serve as a connection electrode for the word line.

22. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 16, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 16 to 21.

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