Detecting Power Delivery Network Marginality in Computing Devices

Abstract

A system-on-chip (SoC) in a computing device may be equipped with a power delivery network (PDN) self-test to detect marginal PDN performance. During this self-test, a current surge may be generated on the power connector of a logic circuit block. In response to the current surge, a voltage monitor may measure the voltage drop across the power connector. The voltage drop measurement may be compared to a threshold. If the voltage drop measurement exceeds the threshold, an action may be taken, such as generating an alert.

Description

[0001] Related technical description

[0002] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a portable computing device ("PCD") such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, or the like. Still other types of PCDs may be used in automotive and Internet of Things ("IoT") applications.

[0003] Multiple subsystems, cores, or other components of a computing device may be included within the same integrated circuit chip or in different chips. A “system on a chip” or “SoC” is an example of a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a digital signal processor (“DSP”), and a neural processing unit (“NPU”). An SoC may include other subsystems, such as a transceiver or “modem” subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0004] Computing devices and their components may experience failures during their operation, which may result in undesirable outcomes. In certain types of computing devices, such as safety-critical systems, unexpected failures may result in conditions that are dangerous to users or others. While failures may have many causes, one such cause is related to the degradation of components over time. For example, the effectiveness of power delivery network components involved in delivering power to other components may decrease over time, resulting in unpredictable performance of the computing device. A power delivery network that experiences marginal performance may fail in some use cases but not in others. Some computing devices may perform self-tests of digital logic during startup or at other times, but such digital self-tests may not predict failures caused by marginal performance of the power delivery network. Summary of the Invention

[0005] Systems, methods, computer-readable media, and other examples are disclosed for testing a power delivery network ("PDN") in a system on a chip ("SoC") of a computing device.

[0006] An exemplary system for testing a power distribution network (PDN) in a system-on-chip (SoC) of a computing device may include a current surge generator circuit, a processor system, and at least one voltage monitor. The current surge generator circuit may be configured to generate a current surge across multiple power connectors of multiple logic circuit blocks. The voltage monitor may be configured to measure a voltage drop across one or more of the power connectors in response to the current surge. The processor system may be configured to receive a voltage drop measurement from the voltage monitor concurrently with the generation of the current surge. The processor system may also be configured to compare the voltage drop measurement to a threshold. The processor system may further be configured to generate a warning when the voltage drop measurement exceeds the threshold.

[0007] An exemplary method for testing a PDN in a SoC of a computing device may include loading a test vector into a register. The method may also include generating a current surge on multiple power connections of multiple logic circuit blocks in response to the test vector loaded into the register. The method may also include measuring a voltage drop on one or more of the power connections in response to the current surge. The method may include receiving a voltage drop measurement after loading the test vector into the register. The method may also include comparing the voltage drop measurement to a threshold. The method may also include generating a warning when the voltage drop measurement exceeds the threshold.

[0008] Another exemplary system for testing a PDN in a SoC of a computing device may include means for loading a test vector into a register. The exemplary system may also include means for generating a current surge on a plurality of power connections of a plurality of logic circuit blocks in response to the test vector loaded into the register. The system may also include means for measuring a voltage drop on one or more of the power connections in response to the current surge. The system may include means for receiving a voltage drop measurement after loading the test vector into the register. The system may also include means for comparing the voltage drop measurement to a threshold. The system may also include means for generating a warning when the voltage drop measurement exceeds the threshold.

[0009] An exemplary computer-readable medium for testing a power distribution network (PDN) in a system-on-chip (SoC) of a computing device may include a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form. When executed by a processing system of the computing device, these instructions may configure the processing system to load a test vector into a register. These instructions may also configure the processing system to control the generation of a current surge across multiple power connectors of multiple logic circuit blocks in response to the test vector loaded into the register. These instructions may further configure the processing system to control the measurement of a voltage drop across one or more of the power connectors in response to the current surge. These instructions may configure the processing system to receive a voltage drop measurement after loading the test vector into the register. These instructions may further configure the processing system to compare the voltage drop measurement with a threshold. These instructions may further configure the processing system to generate a warning when the voltage drop measurement exceeds the threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter designations, such as "102A" or "102B," the letter designations may distinguish between two similar parts or elements in the same figure. Letter designations may be omitted when the intention is that a reference numeral encompass all parts having the same reference numeral in all figures.

[0011] Figure 1 is a block diagram illustrating a system for testing a power delivery network ("PDN") in a system on a chip ("SoC") of a computing device according to an exemplary embodiment.

[0012] Figure 2 is a flow chart illustrating a method for testing a PDN in a SoC of a computing device according to an exemplary embodiment.

[0013] Figure 3 is a graph illustrating a measured voltage drop according to an exemplary embodiment.

[0014] Figure 4 is a conceptual plan view of a SoC with a dynamic voltage monitor according to an exemplary embodiment.

[0015] Figure 5 is a block diagram of a SoC subsystem having a current surge generator circuit including a clock gating circuit according to an exemplary embodiment.

[0016] Figure 6 is a block diagram of a SoC subsystem having a current surge generator circuit including a power switching circuit according to an exemplary embodiment.

[0017] Figure 7 is a block diagram of a computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0018] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "exemplary" is used herein synonymously with "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0019] Safety-critical systems, such as automotive computing systems, may run a built-in self-test, or "BIST," before they begin operation. For example, when a driver starts a car, the car's computing system may run a BIST. If the results of the BIST indicate that the computing system may be subject to a certain type of failure, measures may be taken to reduce the likelihood that the computing system failure will endanger vehicle occupants or other people. For example, the driver may be warned of the condition. In addition, the car may be prohibited from driving, or the car may be constrained to operate below a relatively low maximum speed. The operation of a system under such mitigation measures is generally referred to as "safe mode." This type of BIST may involve self-testing various aspects of the computing system's digital logic. However, digital logic BIST is typically only capable of detecting "hard" or predictable failures, and cannot detect marginal performance that may cause less predictable failures while the system is being operated (e.g., while the vehicle is being driven).

[0020] The term power delivery network ("PDN") generally refers to the collection of components involved in delivering power to other components of a computing device, such as boards, chips, batteries, packages, connectors, circuit board traces, and more. Some PDN components may degrade or degrade over time due to aging, wear and tear, temperature variations, radiation, and other effects, resulting in marginal performance. Unlike failures in digital logic, which are generally predictable, failures due to degraded PDN components can be unpredictable and undetectable by digital logic BIST. That is, whether a failure occurs may depend on the demand for power delivered to various components under various use cases or combinations of use cases.

[0021] exist Figure 1 , an exemplary system 100 for self-testing a PDN 101 in a system-on-chip ("SoC") 103 is illustrated. Although not shown in FIG. Figure 1 Although not shown in FIG, SoC 103 may be included in a computing system or device. The computing device may control, for example, aspects of a complex, safety-critical system such as an autonomous or semi-autonomous vehicle. It may be desirable to detect conditions that could lead to failures in the computing device. According to the exemplary embodiments described herein, PDN 101 may be tested in a manner that detects marginal PDN performance.

[0022] SoC 103 may include at least one subsystem 102. Subsystem 102 may broadly include any SoC subsystem, such as, for example, a CPU, GPU, NPU, DSP, modem, etc., or cores thereof. Subsystem 102 may include a plurality of logic circuit blocks 104, such as a first logic circuit block 104A, a second logic circuit block 104B, and so on, through an Nth logic circuit block 104N. For example, there may be tens, hundreds, or even thousands of logic circuit blocks 104 in subsystem 102 or other subsystems (not shown) of SoC 103. The term "logic circuit block" is used herein to refer to a group of multiple interconnected logic elements (e.g., gates, flip-flops, registers, multiplexers, etc.) configured to perform one or more functions together.

[0023] PDN 101 may include a power supply component 114 located external to SoC 103. PDN 101 may also include a metal trace network located within SoC 103 that is configured to distribute power from power supply component 114 to logic circuit blocks 104. Although not shown in the figure for clarity, Figure 1 103, but PDN 101 may include additional elements such as, for example, switches. As described below, self-tests may be performed on the portion of PDN 101 within SoC 103. The portion of PDN 101 within SoC 103 that feeds or distributes power to logic circuit block 104 may be referred to as a power connection to logic circuit block 104.

[0024] While digital logic BIST can be performed on logic blocks 104 (e.g., when booting up SoC 103, or at other times), such logic testing cannot detect marginal or unpredictable performance caused by PDN degradation over time. Some logic blocks 104 may behave differently depending on whether they are properly receiving power from PDN 101. For example, under some use cases or combinations of use cases, PDN 101 may be stressed by the current demands of logic blocks 104, resulting in current spikes or surges.

[0025] A current surge is a high rate of change of current (e.g., within a few nanoseconds). The rate of change of current may be referred to as "di / dt," or the first derivative of current with respect to time. Current surges are typically associated with capacitance in logic circuit blocks 104 and the portion of PDN 101 that feeds logic circuit blocks 104. The current surge may cause a corresponding voltage sag on the portion of PDN 101 that feeds one or more of logic circuit blocks 104. A voltage sag exceeding a threshold, such as, for example, five percent of the supply voltage ("VDD"), may prevent those logic circuit blocks 104 from operating properly when the voltage sag occurs. Example embodiments described herein involve testing portions of PDN 101 to detect marginal PDN performance. For example, SoC 103 may perform such a self-test when it boots up in preparation for participating in controlling a safety-critical system, such as, for example, a vehicle.

[0026] SoC 103 may include a processor 106 configured to perform the self-tests of PDN 101 mentioned above. Processor 106 may be configured to issue warnings, apply mitigation measures (e.g., fail-safe operating mode), or take other actions based on the results of the self-tests. Although the processor 106 in the illustrated embodiment is separated from subsystem 102 for clarity of description, in other embodiments, such a processor may be included in subsystem 102 or other subsystems. Processor 106 may be any SoC processor. For example, processor 106 may be a CPU (also known as an application processor) on which various tasks may be performed. Alternatively, processor 106 may be a separate processor provided as a supplement to the CPU and other SoC subsystem processors and dedicated to the self-tests described herein.

[0027] Broadly speaking, performing a self-test can include processor 106 loading one or more test vectors into one or more registers 108. The outputs of registers 108 are coupled to current surge generator circuits 110, some or all of which may be in subsystem 102. Other SoC subsystems (not shown) may similarly include other portions of such current surge generator circuits. Thus, other SoC subsystems can be tested in the manner described herein with respect to exemplary subsystem 102. Current surge generator circuit 110 can be configured to respond to the test vectors in register 108 by generating a current surge on the power supply connections to logic circuit block 104.

[0028] The test vectors may be determined, for example, by the entity that designs or produces the SoC 103. For example, a chip design and verification software tool may be used to analyze an electronic design model of the SoC 103 during the SoC design phase (before the SoC 103 is manufactured), sometimes also referred to as the "pre-silicon" phase. The design and verification software tool may enable test data to be input to the SoC model, and such test data may include the test vectors described above. The design and verification software tool may include a power analysis software tool that, among other features, may capture current levels and voltage levels on various power rails under simulated SoC operating conditions. An example of such a power analysis tool is the PRIMETIME PX from Synopsys of Mountain View, California. Other examples of power analysis tools are known to those of ordinary skill in the art.

[0029] The term "use case" refers to the operation of a computing device toward a goal from the perspective of a user. Different use cases may correspond to the execution of different software applications or other tasks on a processing system. The term "use case" includes a combination of concurrent use cases. For example, a use case may involve a CPU subsystem executing a navigation application while a communication subsystem concurrently provides a wireless connection for navigation. It is generally known to those skilled in the art under which use cases the PDN 101 or a portion thereof experiences a current surge (and therefore a voltage sag). Those skilled in the art can determine use cases in which a portion of the PDN 101 experiences a current surge or voltage sag that reaches a threshold. The threshold may be a voltage below which a person skilled in the art may not predict the correct operation of one or more of the logic circuit blocks 104. In other words, the threshold represents the maximum voltage sag on the corresponding portion of the (non-degraded) PDN 101 that can be actually expected under the use case.

[0030] When a use case is determined in which a portion of PDN 101 experiences a current surge or voltage dip of magnitude exceeding the aforementioned threshold, a corresponding test vector that produces a similar effect (e.g., a target voltage dip) can be determined. That is, a test vector (or combination of sequential test vectors) that, when loaded into register 108, causes current surge generator circuit 110 to generate a current surge or voltage dip of substantially the same magnitude as in the use case can be determined. Multiple test vectors can be determined for corresponding portions of the PDN in this manner, as described below. The test vectors can be stored in a location accessible to processor 106 (e.g., in non-volatile memory (not shown) on or external to SoC 103).

[0031] A dynamic voltage monitor ("DVM") 112 in subsystem 102 may be configured to measure the voltage (and therefore the voltage droop) on portions of PDN 101, such as power connections feeding various logic circuit blocks 104. Processor 106 may be configured to read the voltage measurements produced by DVM 112, as conceptually indicated by the curved arrows.

[0032] exist Figure 2 In the example embodiment, a method 200 for testing a SoC PDN in a computing device to detect PDN degradation may include the following. Although the processor 106 may initiate a self-test at any time, in the exemplary method 200, the processor 106 may initiate a self-test during the process of booting up the SoC 103. The SoC 103 may be booted up to prepare to participate in a control system, such as, for example, a vehicle or other safety-critical system. Alternatively, the processor 106 may initiate a self-test at other times, such as periodically during operation (e.g., of a vehicle). This built-in self-test, or "BIST," may reduce the likelihood of unexpected failures occurring while the vehicle is being operated.

[0033] As indicated by block 202, the processor 106 may write to one or more registers 108 ( Figure 1 ) loads one or more test vectors. Loading one or more registers 108 may include sequentially loading multiple test vectors, shifting the test vectors bit by bit in register 108, or other actions that result in a change in the output of register 108. In a manner further described below, the change may cause current generator circuit 110 ( Figure 1 ) produces a current surge (and therefore a voltage dip).

[0034] As indicated at block 204, the processor 106 may then read the voltage measurements generated by the DVM 112. These voltage measurements may capture any voltage dips that occur in response to the loading of the test vector. The processor 106 may read the voltage measurements generated by the various DVMs 112 in the subsystem 102 and any other such subsystems (not shown) of the SoC 103.

[0035] Brief reference Figure 3, the supply voltage graph 300 illustrates an example in which the measured supply voltage 302 exhibits a first voltage dip ("ΔV1") within a first time interval ("Δt1") and then later exhibits a second voltage dip ("ΔV2") within a second time interval ("Δt2"). Each time interval may be, for example, 5 nanoseconds. A voltage dip is the amount that the supply voltage 302 is less than the nominal supply voltage level 304. The processor 106 may read voltage measurements from the DVM 112 within a time span after applying the test vector in order to capture any voltage dips that occur during the time span. In the illustrated example, the processor 106 may capture the first voltage dip and the second voltage dip. In the illustrated example, the first voltage dip may exceed a threshold value, while the second voltage dip may not exceed the threshold value.

[0036] Return to Figure 2 As indicated at block 206, the processor 106 may compare the voltage droop measurement to one or more thresholds. In some examples of method 200, multiple thresholds may exist. For example, there may be a threshold corresponding to each of the DVMs 112 and, therefore, corresponding to the voltage droop measurement for that DVM. In such an example, the processor 106 may compare the voltage droop measurement generated by each DVM 112 to the threshold corresponding to that DVM 112.

[0037] Brief reference Figure 4 , illustrates an exemplary physical or spatial layout of subsystems 102, such as first subsystem 102A and second subsystem 102B, on SoC 103. DVMs 112 are spatially distributed around each of the exemplary subsystems 102A and 102B. Each DVM 112 can thus be coupled to a different portion of the PDN ( Figure 4 ), such as PDN to logic circuit elements in different spatial areas of SoC 103 ( Figure 4 ) and various branches (e.g., circuit traces) that are powered by the power supply.

[0038] Return to Figure 2 If the processor 106 determines (block 206) that no measured voltage dip exceeds the corresponding threshold, the processor 106 may proceed to prepare the entire system (e.g., vehicle system) including the processor 106 to operate in a normal or full operational mode, as indicated by block 208. That is, because the test results indicate that the PDN has not degraded to an extent that would cause a logic circuit failure when stressed by one or more current surges, no action is required. For example, the processor 106 may cause the SoC 103 to boot in a manner that prepares it to participate in controlling the vehicle.

[0039] However, if the processor 106 determines (block 206) that at least one measured voltage drop exceeds a corresponding threshold, the processor 106 may stop the process of preparing the system (e.g., a vehicle system) including the processor 106 for normal or full operation. Alternatively or additionally, one or more actions may be taken. The startup sequence may be stopped or interrupted to take action, or alternatively, action may be taken after the startup sequence is complete. Such action may include generating a warning. The warning may be of any type and provided in any manner. For example, generating a warning may include warning the operator of the vehicle that there may be increased risk when operating the vehicle. A third party, such as a service provider, may be warned remotely via wireless communication. The warning may include transmitting the captured voltage measurement data to a remote party for analysis. Additionally or alternatively, the action may include measures to mitigate the risk, such as placing the vehicle in a fail-safe operating mode. The fail-safe operating mode may be distinguished from the normal or full operating mode mentioned above (block 208). For example, in fail-safe mode, power may be prioritized to safety-related subsystems by throttling the supply voltage (or frequency, display resolution, etc.) to non-safety-related vehicle features or subsystems, such as the infotainment system. In contrast, in normal or full operating mode, both safety-related and non-safety-related subsystems may be fully operational. Alternatively or in addition, fail-safe mode may prevent the vehicle from operating at speeds exceeding a threshold. In contrast, in normal or full operating mode, the vehicle is not prevented from operating at speeds exceeding the threshold. Another alternative may be to prevent vehicle operation entirely. Each DVM may have multiple thresholds for comparison, and there may be several such DVMs distributed throughout the SoC. The action taken in the event of high attenuation may depend on the number of thresholds crossed on a given DVM, the number of DVMs whose thresholds have been crossed, and the specific location of these DVMs on the SoC die.

[0040] exist Figure 5 , an example is illustrated in which a subsystem 502 is coupled to an output terminal of one or more registers 504. The subsystem 502 and the register 504 may be the subsystem 102 and the register 108 ( Figure 1 In the illustrated example, the clock gating circuit 506 acts as the Figure 1An example of a current surge generator circuit 110 is described. The clock gating circuit 506 may include clock gating cells ("CGCs") 508, 510, 512, etc. Although three CGCs 508 to 512 are shown in the clock gating circuit 506 as an example, the clock gating circuit 506 may include any number (e.g., on the order of tens, hundreds, thousands, etc.) of CGCs or other clock signal control circuits. The clock gating circuit 506 may also include a buffer in the form of, for example, a series-coupled inverter 514. The buffer couples the outputs of the CGCs 508, 510, and 512 to the clock signal inputs of logic circuit blocks 516, 518, and 520, respectively. Although three logic circuit blocks 516 to 520 are shown in the subsystem 502 as an example, the subsystem 502 may include any number (e.g., on the order of tens, hundreds, thousands, etc.) of logic circuit blocks. The logic circuit blocks 516 to 520 may be the logic circuit blocks 104 ( Figure 1 ) example.

[0041] Each of the CGCs 508 to 512 has three connections: a clock signal input, a gate or enable input, and a clock signal output. Providing a value of "1" at the CGC enable input enables the CGC to pass the clock signal from its clock signal input to its clock signal output. Providing a value of "0" at the CGC enable input disables the CGC from passing the clock signal from its clock signal input to its clock signal output.

[0042] In normal operation, i.e., when subsystem 502 is not undergoing the self-tests described herein, CGCs 508, 510, and 512 can be controlled or enabled by local clock enable signals Local_en_1, Local_en_2, and Local_en_3, respectively, provided to the CGC enable inputs. These local clock enable signals can be provided by other circuits (not shown) in subsystem 502. In normal operation, the local clock enable signals are not asserted (e.g., transitioned from "0" to "1") simultaneously. Instead, for example, Local_en_1 can be asserted first, which enables CGC 508 to pass the clock signal to logic circuit block 516. Then, after logic circuit block 516 has operated for a certain number of clock cycles, Local_en_2 can be asserted, which enables CGC 510 to pass the clock signal to logic circuit block 518. Then, after logic circuit block 518 has been operating for a certain number of clock cycles, Local_en_3 may be asserted, which enables CGC 512 to pass the clock signal to logic circuit block 520. It should be understood that the foregoing signal sequence is intended merely as an example, illustrating the principle of not asserting all such local clock enable signals at the same time in normal operation, and therefore not beginning to clock all logic circuit blocks 516 through 520 at the same time in normal operation.

[0043] However, when subsystem 502 undergoes the self-test described herein, a global clock enable signal Global_en may enable many (or all) of CGCs 508 through 512 to simultaneously begin passing clock signals to logic circuit blocks 516 through 520, respectively. OR gates 522, 524, and 526 provide either a local clock enable signal (when asserted) or a global clock enable signal (when asserted) to CGCs 508 through 512. The global clock enable signal may be an output of register 504. Thus, when register 504 is loaded with a value including the asserted global clock enable signal (e.g., having a value of "1"), logic circuit blocks 516 through 520 begin being clocked substantially simultaneously. Because the portion of the PDN feeding logic circuit blocks 516 through 520 may include some parasitic capacitance or the like, logic circuit blocks 516 through 520 may draw an inrush current when they begin being clocked.

[0044] The portion of the PDN that connects the power rail (VDD) to one or more of the circuit blocks 516 to 520 may experience current surges and, therefore, voltage dips. Figure 1 and Figure 4 As described, DVM 112 ( Figure 5 The power connections on which DVM 112 can measure the voltage drop include any portion of the PDN that delivers power to circuit blocks 516 to 520.

[0045] The illustrated global clock enable signal Global_en provided to the subsystem 502 may be one of any number of such global clock enable signals. Other such global clock enable signals may be provided to other subsystems ( Figure 5 not shown).

[0046] In order to determine a test vector that produces a voltage drop of a target magnitude, an iterative search may be performed. A first candidate test vector that enables only a small number of CGCs in the exemplified subsystem 502 and other subsystems may be loaded into register 504. A voltage drop magnitude measurement in response to the first candidate test vector may be obtained and compared to the target voltage drop. If the measured voltage drop magnitude in response to the candidate test vector is approximately equal to the target voltage drop, the candidate test vector may be stored as described above for use during self-test. If the measured voltage drop magnitude is less than the target voltage drop, the next (e.g., second) candidate test vector that enables a larger number of CGCs may be loaded into register 504. A voltage drop magnitude measurement in response to the next candidate test vector may be obtained and compared to the target voltage drop. This method may be repeated until a voltage drop measurement that is approximately equal to the target voltage drop is found.

[0047] exist Figure 6 , an example is illustrated in which a subsystem 602 is coupled to an output terminal of one or more registers 604. The subsystem 602 and the register 604 may be the subsystem 102 and the register 108 ( Figure 1 ) example. In the illustrated example, the power switching circuit 606 acts as the above Figure 1 6. An example of a current surge generator circuit 110 is described. The power switching circuit 606 may include multiplexers ("MUX") 608, 610, etc. Although two MUXs 608 and 610 are shown in the power switching circuit 606 as an example, the power switching circuit 606 may include any number of MUXs or similar power switching circuits. The power switching circuit 606 may also include a power switch 612, such as power switches 612A, 612B, 612C, 612D, etc. In the illustrated example, the power switches 612A, 612B, 612C, and 612D selectively couple the power rail (VDD) to the supply voltage connections of logic circuit blocks 614, 616, 618, and 620, respectively. Although four logic circuit blocks 614 to 620 are shown in the subsystem 602 as an example, the subsystem 602 may include any number of such logic circuit blocks. The logic circuit blocks 614 to 620 may be the logic circuit block 104 ( Figure 1 ) example.

[0048] System 600 may include any number of power controllers or switch controllers, referred to herein as globally distributed switch controllers ("GDSCs") 622, such as GDSCs 622A through 622N. In the illustrated example, exemplary GDSC 622N may be coupled to power switch 612 (via MUXs 608 and 610). During normal operation, i.e., when subsystem 602 is not undergoing self-testing as described herein, GDSC 622N may control or select which of switches 612 are closed and, therefore, couple power rails to the supply voltage connections of logic circuit blocks 614 through 620. However, when subsystem 602 is undergoing self-testing as described herein, MUXs 608 and 610 may override this functionality of GDSC 622N. For example, during normal operation, MUX 608 may select one of its two inputs to be coupled to the output of GDSC 622N. Thus, GDSC 622N can control whether the power rail is coupled to the supply voltage connections of logic circuit blocks 614 and 616, respectively, by controlling power switches 612A and 612B. Similarly, in normal operation, MUX 610 can select one of its two inputs to be coupled to the other output of GDSC 622N. Thus, GDSC 622N can control whether the power rail is coupled to the supply voltage connections of logic circuit blocks 618 and 620, respectively, by controlling power switches 612C and 612D. Other GDSCs 622 can similarly couple to power switches of other subsystems (not shown).

[0049] In the illustrated example, various output bits of one or more registers 604 can be coupled to control or selector inputs of MUXs 608 and 610 and two other MUXs 622 and 624. For example, bits 626, 628, 630, and 632 can be coupled to selector inputs of MUXs 608, 610, 622, and 624, respectively. In normal operation, i.e., when subsystem 602 is not undergoing the self-tests described herein, bits 626 through 632 loaded into register 604 can have a value of "0," thereby causing MUXs 608 and 610 to respond as described above. However, when subsystem 602 is undergoing the self-tests described herein, other values ​​for bits 626 through 632 can be loaded into register 604. For example, bit 626 may initially be loaded with a value of "1," thereby causing MUX 608 to select the other of its two inputs coupled to a "1" voltage level (e.g., VDD), thereby overwriting the output of GDSC 622N. MUX 608 provides the "1" value of its selected input to its output, which may be referred to as "en_subset" in this example. In the illustrated example, the "en_subset" signal is coupled to the control inputs of power switches 612A and 612B. Thus, when bit 626 has a value of "1," power switches 612A and 612B may couple the power rail to the supply voltage connections of logic circuit blocks 614 and 616, respectively. During this time, the value of "0" in bit 628 may continue to cause power switches 612C and 612D to not couple the power rail to the supply voltage connections of logic circuit blocks 618 and 620, respectively. Thus, in this initial state of self-test, logic circuit blocks 614 and 616 are powered or coupled to the power rail, while logic circuit blocks 618 and 620 are not powered or coupled to the power rail.

[0050] Then, in the next state of the self-test, bit 628 may be loaded with a value of "1," thereby causing MUX 610 to select the other of its two inputs that is coupled to a "1" voltage level (e.g., VDD). MUX 610 provides the "1" value of its selected input to its output, which may be referred to as "en_rest" in this example. The "en_rest" signal is coupled to the control inputs of the other power switches 612C and 612D (i.e., the remaining power switches in power switches 612 in this example). Thus, when a first test vector in which bits 626 and 628 have values ​​of "1" and "0," respectively, is loaded into register 604, power switches 612A and 612B couple the power rail to only a subset of all logic circuit blocks 614 through 620, i.e., only logic circuit blocks 614 and 616. However, when a second test vector in which bit 628 has a value of “1” is subsequently loaded into register 604, power switches 612C and 612D couple the power rail to the remaining or remaining logic circuit blocks 618 and 620. That is, when a second test vector in which bits 626 and 628 both have a value of “1” is subsequently loaded into register 604, power switch 612 together couples the power rail to all of logic circuit blocks 614 through 620.

[0051] When only a subset of logic blocks 614-620 is powered in this example, the subset draws less current than when all of logic blocks 614-620 are powered. Transitioning from loading a first test vector that causes only a subset of logic blocks 614-620 to be powered to loading a second test vector that causes all of logic blocks 614-620 to be powered can generate a current surge and, therefore, a voltage dip. While there are four logic blocks 614-620 in the illustrated example, there could be a much larger number, resulting in a significant current surge. MUX 608 can initially enable a percentage of such logic blocks, such as, for example, 25% of the logic blocks, and then enable the remaining percentage of such logic blocks, such as, for example, 75%, to generate the current surge and, therefore, the voltage dip.

[0052] The power switching circuit 606 may also include one or more clock disable MUXs 622 and one or more reset signal MUXs 624. Although only two such MUXs 622 and 624 are shown for clarity, there may be a number of clock disable MUXs 622 and reset signal MUXs 624 corresponding to the number of logic circuit blocks 614 to 620 (e.g., four in the illustrated example). The output of each MUX 622 may be coupled to a clock signal control circuit (not shown) that selectively enables and disables one or more clock signals on which the corresponding logic circuit block among the logic circuit blocks 614 to 620 operates. Similarly, the output of each MUX 624 may be coupled to a reset signal control circuit (not shown) that resets the corresponding logic circuit block among the logic circuit blocks 614 to 620.

[0053] Before powering down logic circuit blocks 614 to 620 in the manner described above, the clock signals on which the logic circuit blocks operate may be disabled by MUX 624. When bit 630 coupled to the selector input of MUX 622 has a value of "0," MUX 622 may provide a clock disable ("Clk_disable") signal to the corresponding logic circuit blocks 614 to 620. The Clk_disable signal may be generated by other SoC circuitry (not shown). In normal operation, i.e., when subsystem 602 is not undergoing the self-test described herein, the Clk_disable signal may control MUX 622 (via clock signal control circuitry (not shown)) to selectively provide one or more clock signals required for normal operation to the corresponding logic circuit blocks 614 to 620. Before powering up one of logic circuit blocks 614 to 620 in the manner described above, bit 630 may be switched to a "1" value, thereby causing MUX 622 to provide a "1" value (e.g., VDD) to the clock signal control circuitry of the corresponding one of logic circuit blocks 614 to 620. Enabling the clock signal in this manner allows logic circuit blocks 614 to 620 to participate in the self-test described above.

[0054] Similarly, when bit 632 coupled to the selector input of MUX 624 has a "0" value, MUX 624 can provide a "reset" signal to the corresponding logic circuit block 614 to 620. The reset signal can be generated by other SoC circuits (not shown) that control the resetting of the logic circuit blocks 614 to 620 during normal operation. In order to place the logic circuit blocks 614 to 620 in a known or reset state before starting the self-test, the logic circuit blocks 614 to 620 can be reset by one or more MUXs 624. Before powering on one of the logic circuit blocks 614 to 620 in the manner described above, bit 632 can be switched to a "1" value, thereby causing MUX 624 to provide a "1" value (e.g., VDD) to the reset signal control circuit (not shown) that resets the corresponding logic circuit block 614 to 620.

[0055] The power supply (VDD) connection of one or more of the circuit blocks 612 may experience current surges and, therefore, voltage dips. Figure 1 and Figure 4 As described, DVM 112 ( Figure 6 The power connections on which DVM 112 can measure the voltage drop include any portion of the PDN that delivers power to circuit block 612.

[0056] Figure 7 An example of a PCD 700, such as a mobile phone, is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples of self-testing a PDN may be provided. For clarity, Figure 7 Some data registers, interconnects, clock signals, etc. are not shown. Although PCD 700 is shown as an example, other embodiments of systems, methods, computer-readable media, and other examples of self-testing a PDN may be provided in other types of computing devices or systems. An example of such a system may be a safety-critical system. An example of a safety-critical system may be a motor vehicle, such as an autonomous or semi-autonomous vehicle. However, other examples of self-testing a PDN may be provided in data centers, the Internet of Things ("IoT"), and other environments.

[0057] PCD 700 may include SoC 702. SoC 702 may include CPU 704, NPU 705, GPU 706, DSP 707, analog signal processor 708, modem / modem subsystem 754, or other processors. CPU 704 may include one or more CPU cores, such as a first CPU core 704A, a second CPU core 704B, and so on to an Nth CPU core 704N. SoC 702 may be the CPU core described above. Figure 1The aforementioned subsystems such as CPU 704, NPU 705, GPU 706, DSP 707, analog signal processor 708, and modem subsystem 754 may be examples of the aforementioned subsystem 102 ( Figure 1 and Figure 4 )、502( Figure 5 )、602( Figure 6 ) etc.

[0058] A display controller 710 and a touch screen controller 712 may be coupled to the CPU 704. A touch screen display 714 external to the SoC 702 may be coupled to the display controller 710 and the touch screen controller 712. The PCD 700 may also include a video decoder 716 coupled to the CPU 704. A video amplifier 718 may be coupled to the video decoder 716 and the touch screen display 714. A video port 720 may be coupled to the video amplifier 718. A universal serial bus ("USB") controller 722 may also be coupled to the CPU 704, and a USB port 724 may be coupled to the USB controller 722. A subscriber identity module ("SIM") card 726 may also be coupled to the CPU 704.

[0059] One or more memories may be coupled to CPU 704. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 728 and dynamic random access memory ("DRAM") 730 and 731. Such memories may be external to SoC 702, such as DRAM 730, or internal to SoC 702, such as DRAM 731. A DRAM controller 732 coupled to CPU 704 may control the writing of data to DRAM 730 and DRAM 731 and the reading of data from these DRAMs.

[0060] Multiple DVMs 735 (only one of which is shown for clarity) may be spatially distributed around the SoC 702 and coupled to the spatially distributed portion of the PDN, as described above with respect to FIG. Figure 4 described. Figure 7 As a block diagram, it is not intended to indicate physical locations, but it should be understood that the DVM 735 may be physically located within various subsystems. For example, the DVM 735 may be located within any or all of the CPU 704, NPU 705, GPU 706, DSP 707, analog signal processor 708, modem subsystem 754, etc.

[0061] A stereo audio codec 734 may be coupled to the analog signal processor 708. In addition, an audio amplifier 736 may be coupled to the stereo audio codec 734. A first stereo speaker 738 and a second stereo speaker 740 may be coupled to the audio amplifier 736, respectively. In addition, a microphone amplifier 742 may be coupled to the stereo audio codec 734, and a microphone 744 may be coupled to the microphone amplifier 742. A frequency modulation ("FM") radio tuner 746 may be coupled to the stereo audio codec 734. An FM antenna 748 may be coupled to the FM radio tuner 746. In addition, stereo headphones 750 may be coupled to the stereo audio codec 734. Other devices that may be coupled to the CPU 704 include one or more digital (e.g., CCD or CMOS) cameras 752.

[0062] A modem or RF transceiver 754 may be coupled to the analog signal processor 708 and the CPU 704. An RF switch 756 may be coupled to the RF transceiver 754 and the RF antenna 758. Additionally, a keypad 760, a mono headset with a microphone 762, and a vibrator device 764 may be coupled to the analog signal processor 708.

[0063] SoC 702 may have one or more internal or on-chip thermal sensors 770A and may be coupled to one or more external or off-chip thermal sensors 770B. Analog-to-digital converter controller 772 may convert the voltage drops generated by thermal sensors 770A and 770B into digital signals.

[0064] The power supply 774 and the PMIC 776 may provide power to the PDN (not shown) of the SoC 702. The power supply 774 and the PMIC 776 may be the same as those described above with respect to Figure 1 An example of a power supply assembly 114 is described.

[0065] The firmware or software may be stored in any of the aforementioned memories, such as DRAM 730 or 731, SRAM 728, or the like, or may be stored in local memory directly accessible by the processor hardware on which the software or firmware is executed. Execution of such firmware or software may control aspects of any of the aforementioned methods or configure aspects of any of the aforementioned systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in patent dictionaries.

[0066] Specific implementation examples are described in the following numbered clauses:

[0067] 1. A system for testing a power delivery network in a system on chip (SoC) of a computing device, comprising:

[0068] a current surge generator circuit configured to generate a current surge on a plurality of power connections of a plurality of logic circuit blocks;

[0069] at least one voltage monitor configured to measure a voltage drop across one or more of the power connections in response to the current surge; and

[0070] A processor system, the processor system being configured to:

[0071] receiving a voltage sag measurement from the at least one voltage monitor concurrently with the generation of the current surge;

[0072] comparing the voltage drop measurement to a threshold; and

[0073] A warning is generated when the voltage dip measurement exceeds the threshold.

[0074] 2. The system of clause 1, wherein the threshold is associated with a predetermined use case dropout.

[0075] 3. A system according to claim 1 or 2, wherein a plurality of voltage monitors are spatially distributed on the SoC, each voltage monitor is configured to measure a corresponding voltage drop, and the processor system is configured to compare a plurality of voltage drop measurements measured by the plurality of voltage monitors with a corresponding plurality of threshold values.

[0076] 4. The system of any one of clauses 1 to 3 further comprising: a register, wherein the current surge generator circuit is coupled to the register and is configured to generate a current surge on a plurality of power supply connections of a plurality of logic circuit blocks in response to a test vector loaded in the register.

[0077] 5. The system of any one of clauses 1 to 4, wherein the processor system is configured to load the test vector into the register, receive the voltage droop measurement, compare the voltage droop measurement, and generate a warning during startup of the SoC.

[0078] 6. The system of any one of clauses 1 to 5, wherein the current surge generator circuit comprises a clock gating circuit configured to simultaneously switch on a clock signal to the plurality of logic circuit blocks.

[0079] 7. The system of any of clauses 1 to 6, wherein the current surge generator circuit comprises a power switching circuit configured to switch a plurality of power signals on the plurality of power connections.

[0080] 8. A system according to claim 7, wherein the power switching circuit is configured to first connect a subset of the multiple power signals to a subset of the multiple power connectors, and then connect the power signals to all of the multiple power connectors.

[0081] 9. The system of any of clauses 1 to 8, wherein the SoC is included in a safety-critical system.

[0082] 10. The system of clause 9, wherein the safety-critical system is a vehicle, and the

[0083] The SoC is activated to prepare for operation of the vehicle.

[0084] 11. The system of clause 10, wherein the processor system is further configured to switch vehicle operation to a fail-safe mode.

[0085] 12. A method for testing a power delivery network in a system on chip (SoC) of a computing device, comprising:

[0086] Load test vectors into registers;

[0087] generating a current surge on a plurality of power connections of a plurality of logic circuit blocks in response to a test vector loaded in the register;

[0088] measuring a voltage drop across one or more of a plurality of power connections in response to the current surge; and

[0089] receiving a voltage droop measurement after loading the register with the test vector;

[0090] comparing the voltage drop measurement to a threshold; and

[0091] A warning is generated when the voltage dip measurement exceeds the threshold.

[0092] 13. The method of clause 12, wherein the threshold is associated with a predetermined use case degradation.

[0093] 14. A system according to clause 12 or 13, wherein a plurality of voltage monitors are spatially distributed on the SoC, each voltage monitor is configured to measure a corresponding voltage droop, and the processor system is configured to compare a plurality of voltage droop measurements measured by the plurality of voltage monitors with a corresponding plurality of threshold values.

[0094] 15. The method of any of clauses 12 to 14, wherein generating the current surge comprises simultaneously switching on a clock signal to the plurality of logic circuit blocks.

[0095] 16. The method of any of clauses 12 to 15, wherein generating the current surge comprises switching a plurality of power signals on the plurality of power connections.

[0096] 17. The method of clause 16, wherein connecting a plurality of power signals comprises first connecting a subset of the plurality of power signals to a subset of the plurality of power connections, and

[0097] The power signal is then connected to all power connectors in the plurality of power connectors.

[0098] 18. The method of any of clauses 12 to 17, wherein the SoC is comprised in a safety-critical system.

[0099] 19. The method of clause 18, wherein loading the register, receiving the voltage droop measurement, comparing the voltage droop measurement, and generating the warning are performed during startup of the SoC.

[0100] 20. The method of clause 19, wherein the safety-critical system is a vehicle, and the booting of the SoC is performed to prepare for operation of the vehicle.

[0101] 21. The method of clause 20, wherein the warning is directed to an operator of the vehicle.

[0102] 22. The method of clause 21 further comprising switching vehicle operation to a fail-safe mode.

[0103] 23. A system for testing a power delivery network in a system on a chip (SoC) of a computing device, comprising:

[0104] A component for loading test vectors into registers;

[0105] means for generating a current surge on a plurality of power supply connections of a plurality of logic circuit blocks in response to a test vector loaded in the register;

[0106] means for measuring a voltage drop across one or more of the plurality of power connections in response to the current surge; and

[0107] means for receiving a voltage drop measurement after loading the register with the test vector;

[0108] means for comparing the voltage dip measurement to a threshold value; and

[0109] Means for generating a warning when the voltage dip measurement exceeds the threshold.

[0110] 24. The system of clause 23, wherein the threshold is associated with a predetermined use case dropout.

[0111] 25. The system of clause 23 or 24, wherein the means for generating a current surge comprises means for simultaneously switching on a clock signal to the plurality of logic circuit blocks.

[0112] 26. The system of clause 23 or 24, wherein the means for generating a current surge comprises means for switching on a plurality of power signals on the plurality of power connections.

[0113] 27. A system according to any of clauses 23 to 26, wherein the SoC is included in a safety-critical system, and wherein the means for loading, the means for generating, the means for measuring, the means for receiving, the means for comparing and the means for generating are active during startup of the SoC.

[0114] 28. The system of clause 27, wherein the SoC is included in a vehicle, and the

[0115] The SoC is activated to prepare for operation of the vehicle.

[0116] 29. A computer-readable medium for testing a power delivery network in a system-on-chip (SoC) of a computing device, the computer-readable medium comprising a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form, the instructions, when executed by a processing system of the computing device, configuring the processing system to control:

[0117] Load test vectors into registers;

[0118] generating a current surge on a plurality of power connections of a plurality of logic circuit blocks in response to a test vector loaded in the register;

[0119] measuring a voltage drop across one or more of a plurality of power connections in response to the current surge; and

[0120] receiving a voltage droop measurement after loading the register with the test vector;

[0121] comparing the voltage drop measurement to a threshold; and

[0122] A warning is generated when the voltage dip measurement exceeds the threshold.

[0123] 30. The computer-readable medium of clause 29, wherein the threshold is associated with a predetermined use case rolloff.

[0124] 31. The computer-readable medium of clause 29 or 30, wherein the instructions to configure the processing system to control generating a current surge include instructions to configure the processing system to control simultaneously turning on a clock signal to the plurality of logic circuit blocks.

[0125] 32. The computer-readable medium of clause 29 or 30, the instructions configuring the processing system to control generating a current surge comprising instructions configuring the processing system to control switching on a plurality of power signals on the plurality of power connections.

[0126] Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains.Thus, while selected aspects have been shown and described in detail, it should be understood that various substitutions and changes can be made therein.

Claims

1. A system for testing a power delivery network in a system-on-chip (SoC) of a computing device, comprising: a current surge generator circuit configured to generate a current surge on a plurality of power supply connections of a plurality of logic circuit blocks, the current surge generator circuit comprising a clock gating circuit configured to simultaneously turn on a clock signal to the plurality of logic circuit blocks to generate the current surge, the clock gating circuit being coupled to the plurality of logic circuit blocks, the clock gating circuit turning on the clock signal simultaneously in response to receiving a global clock enable signal controlled by a register; at least one voltage monitor configured to measure a voltage drop across one or more of the power connections in response to the current surge; as well as A processor system, the processor system being configured to: receiving a voltage sag measurement from the at least one voltage monitor concurrently with the generation of the current surge; comparing the voltage drop measurement to a threshold; as well as A warning is generated when the voltage dip measurement exceeds the threshold.

2. The system of claim 1, wherein the threshold is associated with a predetermined use case degradation.

3. The system of claim 2 , wherein a plurality of voltage monitors are spatially distributed on the SoC, each voltage monitor being configured to measure a corresponding voltage droop, and the processor system being configured to compare a plurality of voltage droop measurements measured by the plurality of voltage monitors with a corresponding plurality of threshold values. The system of claim 1 , wherein the register is loaded with a test vector. 5 . The system of claim 4 , wherein the processor system is configured to load the test vector into the register, receive the voltage droop measurement, compare the voltage droop measurement, and generate the warning during startup of the SoC. The system of claim 1 , wherein the SoC is included in a safety-critical system. 7 . The system of claim 6 , wherein the safety-critical system is a vehicle, and the booting of the SoC is performed to prepare for operation of the vehicle. 8 . The system of claim 7 , wherein the processor system is further configured to switch vehicle operation to a fail-safe mode.

9. A method for testing a power delivery network in a system-on-chip (SoC) of a computing device, comprising: coupling the clock gating circuit to the plurality of logic circuit blocks; Load test vectors into registers; generating a current surge by the clock gating circuit simultaneously switching on a clock signal to the plurality of logic circuit blocks in response to a global clock enable signal controlled by the register; generating the global clock enable signal in response to receiving the test vector loaded in the register; measuring a voltage drop across one or more power connections of a plurality of power connections of the plurality of logic circuit blocks in response to the current surge; receiving a voltage drop measurement after the current surge; comparing the voltage drop measurement to a threshold; as well as A warning is generated when the voltage dip measurement exceeds the threshold.

10. The method of claim 9, wherein the threshold is associated with a predetermined use case degradation.

11. The method of claim 10, wherein a plurality of voltage monitors are spatially distributed on the SoC, each voltage monitor being configured to measure a corresponding voltage droop, and the method further comprising comparing a plurality of voltage droop measurements measured by the plurality of voltage monitors to a corresponding plurality of threshold values.

12. The method of claim 9, wherein the SoC is included in a safety-critical system.

13. The method of claim 12, wherein loading the register, receiving the voltage droop measurement, comparing the voltage droop measurement, and generating the warning are performed during startup of the SoC. 14 . The method of claim 13 , wherein the safety-critical system is a vehicle, and the booting of the SoC is performed to prepare for operation of the vehicle.

15. The method of claim 14, wherein the warning is directed to an operator of the vehicle.

16. The method of claim 15 further comprising switching vehicle operation to a fail-safe mode.

17. A non-transitory computer-readable medium for testing a power delivery network in a system-on-chip (SoC) of a computing device, the SoC having clock gating circuitry coupled to a plurality of logic circuit blocks, the non-transitory computer-readable medium having instructions stored thereon in computer-executable form, the instructions, when executed by a processing system of the computing device, configuring the processing system to control: Load test vectors into registers; generating a current surge by the clock gating circuit simultaneously switching on a clock signal to the plurality of logic circuit blocks in response to a global clock enable signal controlled by the register; generating the global clock enable signal in response to receiving the test vector loaded in the register; measuring a voltage drop across one or more power connections of a plurality of power connections of the plurality of logic circuit blocks in response to the current surge; receiving a voltage drop measurement after the current surge; comparing the voltage drop measurement to a threshold; as well as A warning is generated when the voltage dip measurement exceeds the threshold.

18. The non-transitory computer-readable medium of claim 17, wherein the threshold is associated with a predetermined use case rolloff.

19. The non-transitory computer readable medium of claim 17, wherein loading the register, receiving the voltage droop measurement, comparing the voltage droop measurement, and generating the warning are performed during boot-up of the SoC.

20. The non-transitory computer-readable medium of claim 17, wherein the SoC is included in a safety-critical system.

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