Artificial intelligence processors, integrated circuit chips, boards, electronic devices

Abstract

The present disclosure discloses a computing device, an integrated circuit chip, a board, an electronic device, and a method for using the aforementioned computing device to perform computing operations. The computing device may be included in a combined processing device, which may also include a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operations specified by the user. The combined processing device may also include a storage device, which is respectively connected to the device and other processing devices for storing data of the device and other processing devices. The solution disclosed herein can improve the operating efficiency of operations in various data processing fields, including, for example, the field of artificial intelligence, thereby reducing the overall overhead and cost of operations.

Description

[0001] This application is a divisional application of the patent application with application number 202010619460.8, application date June 30, 2020, and invention name “Computing device, integrated circuit chip, board, electronic device and computing method”. Technical Field

[0002] The present disclosure generally relates to the field of computing and, more particularly, to a computing device, an integrated circuit chip, a board, an electronic device, and a computing method. Background Art

[0003] In a computing system, an instruction set is a set of instructions used to perform calculations and control the computing system, and plays a key role in improving the performance of computing chips (such as processors) in computing systems. Current computing chips (particularly those in the field of artificial intelligence) utilize associated instruction sets to perform various general or specific control and data processing operations. However, current instruction sets still have many shortcomings. For example, existing instruction sets are limited by hardware architecture and lack flexibility. Furthermore, many instructions can only perform a single operation, while executing multiple operations typically requires multiple instructions, which potentially increases on-chip I / O data throughput. Furthermore, current instructions still need improvement in terms of execution speed, execution efficiency, and chip power consumption.

[0004] In addition, the computing instructions of traditional processor CPUs are designed to perform basic single-data scalar operations. Here, single-data operation means that each operand of the instruction is a scalar data. However, in tasks such as image processing and pattern recognition, the operands are often multi-dimensional vectors (i.e., tensor data). Using only scalar operations cannot enable the hardware to efficiently complete the computing tasks. Therefore, how to efficiently perform multi-dimensional tensor operations is also a problem that needs to be solved urgently in the current computing field. Summary of the Invention

[0005] In order to at least solve the problems existing in the above-mentioned prior art, the present disclosure provides a solution for a hardware architecture platform and related instructions. Utilizing the solution disclosed in the present disclosure, the flexibility of instructions can be increased, the efficiency of instruction execution can be improved, and computing costs and overhead can be reduced. Furthermore, the solution disclosed in the present disclosure supports efficient memory access and processing of tensor data based on the aforementioned hardware architecture, thereby accelerating tensor operations and reducing the computational overhead brought about by tensor operations when multi-dimensional vector operands are included in the computing instructions.

[0006] In a first aspect, the present disclosure discloses a computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

[0007] The main processing circuit is configured to perform main computing operations in response to main instructions,

[0008] The slave processing circuit is configured to perform slave arithmetic operations in response to slave instructions,

[0009] The master operation includes a pre-processing operation and / or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, wherein the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand.

[0010] The master processing circuit and / or the slave processing circuit are configured to execute respective corresponding master computing operations and / or slave processing operations according to the storage address.

[0011] In a second aspect, the present disclosure discloses an integrated circuit chip comprising the computing device mentioned in the previous aspect and described in the following embodiments.

[0012] In a third aspect, the present disclosure discloses a board comprising the integrated circuit chip mentioned in the previous aspect and described in the subsequent embodiments.

[0013] In a fourth aspect, the present disclosure discloses an electronic device comprising the integrated circuit chip mentioned in the previous aspect and described in the subsequent embodiments.

[0014] In a fifth aspect, the present disclosure discloses a method for performing a computing operation using the aforementioned computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising:

[0015] configuring the primary processing circuit to perform primary computing operations in response to primary instructions,

[0016] configuring the slave processing circuit to perform slave arithmetic operations in response to slave instructions,

[0017] The master operation includes a pre-processing operation and / or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computation instruction received by the computing device, the operand of the computation instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine a storage address of data corresponding to the operand.

[0018] The method further includes configuring the master processing circuit and / or the slave processing circuit to execute respective corresponding master computing operations and / or slave processing operations according to the storage address.

[0019] The computing device, integrated circuit chip, board, electronic device, and method disclosed herein can efficiently execute master instructions and slave instructions related to master and slave operations, thereby accelerating the execution of the operations. Furthermore, due to the combination of master and slave operations, the computing device disclosed herein can support more types of operations and operations. In addition, based on the pipeline operation arrangement of the computing device disclosed herein, computing instructions can be flexibly configured to meet computing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts.

[0021] Figure 1a is a schematic diagram illustrating a computing device according to an embodiment of the present disclosure;

[0022] Figure 1b is a schematic diagram illustrating a data storage space according to an embodiment of the present disclosure;

[0023] Figure 2 is a block diagram illustrating a computing device according to an embodiment of the present disclosure;

[0024] Figure 3 is a block diagram illustrating a main processing circuit of a computing device according to an embodiment of the present disclosure;

[0025] Figure 4a 4b and 4c are schematic diagrams showing matrix conversion performed by the data conversion circuit according to an embodiment of the present disclosure;

[0026] Figure 5 is a block diagram illustrating a slave processing circuit of a computing device according to an embodiment of the present disclosure;

[0027] Figure 6 is a structural diagram illustrating a combined processing device according to an embodiment of the present disclosure; and

[0028] Figure 7 2 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The solution disclosed herein utilizes the hardware architecture of a main processing circuit and at least one slave processing circuit to perform associated data operations, so that relatively complex operations can be completed using relatively flexible and simplified calculation instructions. Specifically, the solution disclosed herein utilizes the main instructions and slave instructions obtained by parsing the slave calculation instructions, and makes the main processing circuit execute the main instructions to implement the main operation, and makes the slave processing circuit execute the slave instructions to implement the slave operation, so as to implement various complex operations including, for example, vector operations. Here, the main operation may include pre-processing operations and / or post-processing operations for the slave operation. In one embodiment, the pre-processing operation may be, for example, a data conversion operation and / or a data splicing operation. In another embodiment, the post-processing operation may be, for example, an arithmetic operation on the result output from the processing circuit. In some scenarios, when the operand of the calculation instruction includes a descriptor for indicating the shape of a tensor, the solution disclosed herein utilizes the descriptor to determine the storage address of the data corresponding to the operand. Based on this, the master processing circuit and / or the slave processing circuit can be configured to perform their respective corresponding master operations and / or slave operations according to the storage address, wherein the master operations and / or slave operations can involve various types of operations on tensor data. In addition, depending on the different operation circuits or operators in the master processing circuit, the computing instructions disclosed herein support flexible and personalized configuration to meet different application scenarios.

[0030] The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1a FIG is a schematic diagram showing a computing device 100 according to an embodiment of the present disclosure. Figure 1a As shown in the figure, the computing device 100 may include a master processing circuit 102 and slave processing circuits, such as the slave processing circuits 104, 106 and 108 shown in the figure. Although three slave processing circuits are shown here, those skilled in the art will understand that the computing device 100 disclosed herein may include any suitable number of slave processing circuits, and multiple slave processing circuits and multiple slave processing circuits and the master processing circuit may be connected in different ways, and the present disclosure does not impose any limitations. In one or more embodiments, the multiple slave processing circuits disclosed herein may execute various slave instructions (e.g., obtained by parsing computing instructions) in parallel to improve the processing efficiency of the computing device.

[0032] In the context of the present disclosure, a computing instruction may be an instruction in an instruction system of an interactive interface between software and hardware, which may be a machine language in binary or other forms for hardware such as a processor (or processing circuit) to receive and process. The computing instruction may include an opcode and an operand for indicating the operation of the processor. Depending on different application scenarios, the computing instruction may include one or more opcodes, and when the aforementioned computing instruction includes an opcode, the opcode may be used to indicate multiple operations of the processor. In addition, the computing instruction may also include one or more operands. According to the scheme of the present disclosure, the operand may include a descriptor for indicating the shape of a tensor, which may be used to determine the storage address of the data corresponding to the operand.

[0033] In one embodiment, the master instruction and the slave instruction can be obtained by parsing the calculation instruction received by the computing device. In operation, the master processing circuit can be configured to perform the master operation in response to the master instruction, and the slave processing circuit can be configured to perform the slave operation in response to the slave instruction. According to the scheme disclosed herein, the aforementioned master instruction or slave instruction can be a microinstruction or control signal running inside the processor, and can include (or indicate) one or more operations. When the operand of the calculation instruction includes a descriptor as described above, the master processing circuit and / or the slave processing circuit can be configured to access the tensor according to the storage address obtained based on the descriptor. Through the descriptor-based memory access mechanism, the scheme disclosed herein can significantly improve the reading and storage speed of tensor data in the execution of tensor operations, thereby accelerating the calculation and reducing the calculation overhead.

[0034] In one embodiment, the aforementioned main operation may include pre-processing operations and / or post-processing operations for the slave operation. Specifically, for the main instruction executed by the main processing circuit, it may include, for example, pre-processing operations for data conversion and / or data splicing of the data to be involved in the operation. In some application scenarios, the main instruction may also include pre-processing operations that only selectively read the data, such as reading out the data stored in a dedicated or private buffer and sending it to the slave processing circuit, or generating corresponding random numbers for the operation of the slave processing circuit. In other application scenarios, depending on the type and number of operators included in the main processing circuit, the main instruction may include one or more post-processing operations associated with the functions of the operators. For example, the main instruction may include adding, multiplying, looking up, comparing, averaging, filtering, and other types of operations on the intermediate operation results or final operation results obtained after the slave processing circuit executes the slave instruction. In some application scenarios, the aforementioned intermediate operation results or final operation results may be the aforementioned tensors, and their storage addresses can be obtained according to the descriptors disclosed herein.

[0035] In order to facilitate the identification of pre-processing operations and / or post-processing operations, in some application scenarios, the main instruction may include an identification bit for identifying the pre-processing operations and / or post-processing operations. Thus, when the main instruction is obtained, the main processing circuit can determine whether to perform a pre-processing operation or a post-processing operation on the operation data based on the identification bit. Additionally or alternatively, the pre-processing operation and the post-processing operation in the main instruction can be matched by the preset position (or instruction domain segment) of the calculation instruction. For example, when a preset position including (main instruction + slave instruction) is provided in the calculation instruction, it can be determined that the main instruction in this calculation instruction involves a pre-processing operation for the slave operation. For another example, when a preset position including (slave instruction + main instruction) is provided in the calculation instruction, it can be determined that the main instruction in this calculation instruction involves a post-processing operation for the slave operation. For ease of understanding, assuming that the computing instruction has a length of three predetermined bit widths (i.e., the preset positions mentioned above), the instruction located in the first segment of the predetermined bit width can be designated as the main instruction for the pre-processing operation, the instruction located in the middle position of the second segment of the predetermined bit width can be designated as the slave instruction for the slave operation, and the instruction located in the last position of the third segment of the predetermined bit width can be designated as the main instruction for the post-processing operation.

[0036] For the slave instructions executed by the slave processing circuit, they may include one or more operations associated with the functions of one or more arithmetic circuits in the slave processing circuit. The slave instructions may include operations for performing operations on data after the master processing circuit performs pre-processing operations. In some application scenarios, the slave instructions may include various operations such as arithmetic operations, logical operations, data type conversions, etc. For example, the slave instructions may include performing various vector-related multiplication and addition operations on the data after the pre-processing operations, including, for example, convolution operations. In other application scenarios, when the aforementioned calculation instructions do not include master instructions for pre-processing operations, the slave processing circuit may also directly perform slave arithmetic operations on the input data according to the slave instructions.

[0037] In one or more embodiments, the main processing circuit 102 can be configured to obtain a computing instruction and parse it, thereby obtaining the aforementioned master instruction and slave instruction, and sending the slave instruction to the slave processing circuit. Specifically, the main processing circuit may include one or more decoding circuits (or decoders) for parsing the computing instruction. Through the internal decoding circuit, the main processing circuit can parse the received computing instruction into one or more master instructions and / or slave instructions, and send the corresponding slave instruction to the slave processing circuit so that the slave processing circuit performs the slave operation. Here, depending on the application scenario, the slave instruction can be sent to the slave processing circuit in a variety of ways. For example, when the computing device includes a storage circuit, the main processing circuit can send the slave instruction to the storage circuit, and send it to the slave processing circuit via the storage circuit. For another example, when multiple slave processing circuits perform parallel operations, the main processing circuit can broadcast the same slave instruction to multiple slave processing circuits. Additionally or optionally, in some hardware architecture scenarios, the computing device may also include a separate circuit, unit or module dedicated to parsing the computing instruction received by the computing device, such as later combined with Figure 2 The described architecture.

[0038] In one or more embodiments, the slave processing circuit of the present disclosure may include a plurality of operation circuits for performing slave operation, wherein the plurality of operation circuits may be connected and configured to perform multi-stage pipeline operation. Depending on the operation scenario, the operation circuit may include one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit for performing at least vector operations. In one embodiment, when the computing device of the present disclosure is applied to calculations in the field of artificial intelligence, the slave processing circuit may perform multidimensional convolution operations in a neural network according to slave instructions.

[0039] As mentioned above, the main operation and / or slave operation disclosed in the present invention may also include various types of operations on tensor data. For this purpose, the scheme disclosed in the present invention proposes to use descriptors to obtain information related to the shape of the tensor in order to determine the storage address of the tensor data, thereby obtaining and saving the tensor data through the aforementioned storage address.

[0040] In one possible implementation, a descriptor can be used to indicate the shape of N-dimensional tensor data, where N is a positive integer, such as N = 1, 2, or 3, or zero. Among them, a tensor can contain various forms of data composition, and a tensor can be of different dimensions. For example, a scalar can be regarded as a 0-dimensional tensor, a vector can be regarded as a 1-dimensional tensor, and a matrix can be a tensor of 2 dimensions or more. The shape of a tensor includes information such as the dimension of the tensor and the size of each dimension of the tensor. For example, for a tensor:

[0041]

[0042] The shape of the tensor can be described by the descriptor as (2, 4), that is, the two parameters indicate that the tensor is a two-dimensional tensor, and the size of the first dimension (columns) of the tensor is 2, and the size of the second dimension (rows) of the tensor is 4. It should be noted that this application does not limit the way in which the descriptor indicates the shape of the tensor.

[0043] In one possible implementation, the value of N can be determined according to the dimension (order) of the tensor data, or it can be set according to the usage requirements of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor can be used to indicate the shape of the three-dimensional tensor data in three dimensions (such as offset, size, etc.). It should be understood that those skilled in the art can set the value of N according to actual needs, and this disclosure does not limit this.

[0044] In one possible implementation, the descriptor may include a descriptor identifier and / or descriptor content. The descriptor identifier is used to distinguish the descriptor, for example, the descriptor identifier may be a number; the descriptor content may include at least one shape parameter representing the shape of the tensor data. For example, if the tensor data is three-dimensional data, and the shape parameters of two of the three dimensions of the tensor data are fixed, the descriptor content may include the shape parameter representing the other dimension of the tensor data.

[0045] In one possible implementation, the identifier and / or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, on-chip SRAM, or other media cache. The tensor data indicated by the descriptor may be stored in a data storage space (internal memory or external memory), such as an on-chip cache or off-chip memory. This disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

[0046] In one possible implementation, the identifier, content of the descriptor, and the tensor data indicated by the descriptor can be stored in the same area of the internal memory. For example, a continuous area of the on-chip cache can be used to store the relevant content of the descriptor, and its address is ADDR0-ADDR1023. Among them, the address ADDR0-ADDR63 can be used as a descriptor storage space to store the identifier and content of the descriptor, and the address ADDR64-ADDR1023 can be used as a data storage space to store the tensor data indicated by the descriptor. In the descriptor storage space, the address ADDR0-ADDR31 can be used to store the identifier of the descriptor, and the address ADDR32-ADDR63 can be used to store the content of the descriptor. It should be understood that the address ADDR is not limited to 1 bit or 1 byte. It is used here to represent an address and is an address unit. Those skilled in the art can determine the descriptor storage space, data storage space and their specific addresses according to actual conditions, and this disclosure is not limited to this.

[0047] In one possible implementation, the descriptor identifier, content, and tensor data indicated by the descriptor can be stored in different areas of the internal memory. For example, registers can be used as descriptor storage space to store the descriptor identifier and content, and on-chip cache can be used as data storage space to store the tensor data indicated by the descriptor.

[0048] In one possible implementation, when registers are used to store the identifier and content of descriptors, the register number can be used to represent the identifier of the descriptor. For example, when the register number is 0, the identifier of the descriptor stored in it is set to 0. When the descriptor in the register is valid, an area in the cache space can be allocated to store the tensor data based on the size of the tensor data indicated by the descriptor.

[0049] In one possible implementation, the identifier and content of the descriptor may be stored in internal memory, and the tensor data indicated by the descriptor may be stored in external memory. For example, the identifier and content of the descriptor may be stored on-chip, while the tensor data indicated by the descriptor may be stored off-chip.

[0050] In one possible implementation, the data address of the data storage space corresponding to each descriptor can be a fixed address. For example, a separate data storage space can be allocated for tensor data, and the starting address of each tensor data in the data storage space corresponds one-to-one with the descriptor. In this case, the control circuit can determine the data address of the data corresponding to the operand in the data storage space based on the descriptor.

[0051] In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor can also include at least one address parameter representing the address of the tensor data. For example, the tensor data is 3-dimensional data. When the descriptor points to the address of the tensor data, the content of the descriptor may include an address parameter representing the address of the tensor data, such as the starting physical address of the tensor data, or may include multiple address parameters of the address of the tensor data, such as the starting address + address offset of the tensor data, or the address parameters of the tensor data based on each dimension. Those skilled in the art can set the address parameters according to actual needs, and this disclosure does not limit this.

[0052] In one possible implementation, the address parameter of the tensor data may include a reference address of the data reference point of the descriptor in the data storage space of the tensor data. The reference address may vary depending on the data reference point. This disclosure does not limit the selection of the data reference point.

[0053] In one possible implementation, the reference address may include the starting address of the data storage space. When the data reference point of the descriptor is the first data block in the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

[0054] In one possible implementation, the shape parameters of the tensor data include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address. The data description position is the mapping position of the point or area in the tensor data indicated by the descriptor. For example, when the tensor data is 3D data, the descriptor can use three-dimensional space coordinates (x, y, z) to represent the shape of the tensor data. The data description position of the tensor data can be the position of the point or area mapped in the three-dimensional space represented by the three-dimensional space coordinates (x, y, z).

[0055] It should be understood that those skilled in the art can select shape parameters representing tensor data according to actual circumstances, and this disclosure does not limit this. By using descriptors in the data access process, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

[0056] In one possible implementation, the content of the descriptor of the tensor data can be determined based on the reference address of the data reference point of the descriptor in the data storage space of the tensor data, the size of the data storage space in at least one of the N dimensional directions, the size of the storage area in at least one of the N dimensional directions, and / or the offset of the storage area in at least one of the N dimensional directions.

[0057] Figure 1b Schematic diagram showing the data storage space according to the embodiment of the present disclosure. Figure 1b As shown, data storage space 21 stores two-dimensional data in a row-major manner, which can be represented by (x, y) (where the X axis is horizontally to the right and the Y axis is vertically downward). The size in the X-axis direction (the size of each row) is ori_x (not shown in the figure), and the size in the Y-axis direction (the total number of rows) is ori_y (not shown in the figure). The starting address PA_start (base address) of data storage space 21 is the physical address of the first data block 22. Data block 23 is part of the data in data storage space 21. Its offset 25 in the X-axis direction is represented by offset_x, its offset 24 in the Y-axis direction is represented by offset_y, its size in the X-axis direction is represented by size_x, and its size in the Y-axis direction is represented by size_y.

[0058] In one possible implementation, when a descriptor is used to define data block 23, the first data block in data storage space 21 can be used as the data reference point for the descriptor. The descriptor's reference address can be agreed upon to be the starting address PA start of data storage space 21. The content of the descriptor for data block 23 can then be determined by combining the X-axis size ori_x and Y-axis size ori_y of data storage space 21, as well as the Y-axis offset offset_y and X-axis offset offset_x of data block 23, the X-axis size size_x, and the Y-axis size size_y.

[0059] In a possible implementation, the following formula (1) can be used to express the content of the descriptor:

[0060]

[0061] It should be understood that although in the above examples, the content of the descriptor represents a two-dimensional space, those skilled in the art can set the specific dimension represented by the content of the descriptor according to actual conditions, and this disclosure does not limit this.

[0062] In one possible implementation, the reference address of the data reference point of the descriptor in the data storage space can be agreed upon, and based on the reference address, the content of the descriptor of the tensor data is determined according to the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point.

[0063] For example, the data reference point of the descriptor can be agreed to be the reference address PA_base in the data storage space. For example, a data (e.g., data at position (2, 2)) can be selected in the data storage space 21 as the data reference point, and the physical address of the data in the data storage space can be used as the reference address PA_base. The position of the two vertices at the diagonal position relative to the data reference point can be used to determine the reference address PA_base. Figure 1b The content of the descriptor of data block 23 in the data block 23 is determined. First, the positions of at least two vertices at the diagonal positions of the data block 23 relative to the data reference point are determined. For example, the positions of the diagonal vertices from the upper left to the lower right relative to the data reference point are used, where the relative position of the upper left vertex is (x_min, y_min) and the relative position of the lower right vertex is (x_max, y_max). Then, the content of the descriptor of data block 23 can be determined based on the reference address PA_base, the relative position of the upper left vertex (x_min, y_min), and the relative position of the lower right vertex (x_max, y_max).

[0064] In a possible implementation, the following formula (2) can be used to express the content of the descriptor (the base address is PA_base):

[0065]

[0066] It should be understood that although the vertices at the upper left corner and the lower right corner are used in the above example to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two diagonal positions according to actual needs, and this disclosure does not limit this.

[0067] In one possible implementation, the content of the tensor data descriptor can be determined based on the reference address of the descriptor's data reference point in the data storage space and the mapping relationship between the data description position and the data address of the tensor data indicated by the descriptor. The mapping relationship between the data description position and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional spatial data, the function f(x, y, z) can be used to define the mapping relationship between the data description position and the data address.

[0068] In one possible implementation, the following formula (3) can be used to express the content of the descriptor:

[0069]

[0070] In a possible implementation, the descriptor is further used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor further includes at least one address parameter representing the address of the tensor data. For example, the content of the descriptor may be:

[0071]

[0072] Where PA is the address parameter. The address parameter can be a logical address or a physical address. The descriptor parsing circuit can use PA as any vertex, midpoint, or preset point of the vector shape and combine it with the shape parameters in the X and Y directions to obtain the corresponding data address.

[0073] In a possible implementation, the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address includes a starting address of the data storage space.

[0074] In one possible implementation, the descriptor may further include at least one address parameter representing the address of the tensor data. For example, the content of the descriptor may be:

[0075]

[0076] PA_start is the base address parameter and will not be described in detail.

[0077] It should be understood that those skilled in the art can set the mapping relationship between the data description location and the data address according to actual conditions, and this disclosure does not limit this.

[0078] In one possible implementation, a predetermined reference address can be set within a task. All descriptors in instructions within this task use this reference address, and the descriptor content can include shape parameters based on this reference address. This reference address can be determined by setting the task's environment parameters. A description of the reference address and its use can be found in the above embodiments. With this implementation, the descriptor content can be mapped to data addresses more quickly.

[0079] In one possible implementation, the base address can be included in the content of each descriptor, so that the base address of each descriptor can be different. Compared with the method of using environmental parameters to set a common base address, each descriptor in this method can describe data more flexibly and use a larger data address space.

[0080] In one possible implementation, the data address of the data corresponding to the operand of the processing instruction in the data storage space can be determined based on the content of the descriptor. The data address is calculated automatically by hardware, and the calculation method of the data address varies depending on the representation of the descriptor content. This disclosure does not limit the specific method for calculating the data address.

[0081] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, and the size is size_x*size_y. Then, the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is (x,y) It can be determined using the following formula (4):

[0082] PA1 (x,y) =PA_start+(offset_y-1)*ori_x+offset_x (4)

[0083] The data starting address PA1 is determined according to the above formula (4) (x,y) , combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of the tensor data indicated by the descriptor in the data storage space can be determined.

[0084] In one possible implementation, when the operand also includes a data description location for a descriptor, the data address of the data corresponding to the operand in the data storage space can be determined based on the content of the descriptor and the data description location. In this way, partial data (e.g., one or more data) in the tensor data indicated by the descriptor can be processed.

[0085] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y respectively, and the size is size_x*size_y. The data description position for the descriptor included in the operand is (x q ,y q ), then the data address PA2 of the tensor data indicated by the descriptor in the data storage space (x,y) It can be determined using the following formula (5):

[0086] PA2 (x,y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q ) (5)

[0087] Combination of the above Figure 1a and Figure 1b The computing device disclosed in the present invention is described. By utilizing the computing device disclosed in the present invention and the master and slave instructions, multiple operations can be completed using a single computing instruction, thereby reducing the data transfer required for each instruction due to the need for multiple instructions to complete multiple operations. This solves the IO bottleneck problem of the computing device and effectively improves computing efficiency and reduces computing overhead. In addition, the solution disclosed in the present invention can also flexibly set the type and number of operations included in the computing instruction based on the type of arithmetic unit configured in the master processing circuit, the function of the arithmetic circuit configured in the slave processing circuit, and through the collaboration of the master processing circuit and the slave processing circuit, so that the computing device can perform multiple types of computing operations, thereby expanding and enriching the application scenarios of the computing device and meeting different computing needs.

[0088] In addition, since the master processing circuit and the slave processing circuit can be configured to support multi-stage pipeline operations, the execution efficiency of the arithmetic units in the master processing circuit and the slave processing circuit is improved, further shortening the calculation time. Figure 1a The hardware architecture shown is only exemplary and not restrictive. Based on the disclosure and teachings of this disclosure, those skilled in the art can also add new circuits or devices based on this architecture to achieve more functions or operations. For example, Figure 1a The architecture shown in the figure adds a storage circuit to store various instructions and data (such as tensor data). Furthermore, the master processing circuit and the slave processing circuit can also be arranged in different physical or logical locations, and the two can be connected through various data interfaces or interconnection units, so that the master operation and the slave operation mentioned above can be completed through the interaction between the two, including the combination of Figure 1b Various operations on tensors are described.

[0089] Figure 2 2 is a block diagram illustrating a computing device 200 according to an embodiment of the present disclosure. It is understood that Figure 2 The computing device 200 shown in FIG. Figure 1a A specific implementation of the computing device 100 shown, therefore combined with Figure 1a The details of the master processing circuit and the slave processing circuit of the computing device 100 described above also apply to Figure 2 Computing device 200 is shown.

[0090] like Figure 2 As shown in FIG, the computing device 200 according to the present disclosure includes a master processing circuit 202 and a plurality of slave processing circuits 204, 206 and 208. Figure 1a The operation of the master processing circuit and the slave processing circuit has been described in detail and will not be repeated here. Figure 1a The computing device 100 shown has the same master processing circuitry and slave processing circuitry, Figure 2 The computing device 200 further includes a control circuit 210 and a storage circuit 212. In one embodiment, the control circuit may be configured to obtain the computing instruction and parse the computing instruction to obtain the master instruction and the slave instruction, and send the master instruction to the master processing circuit 202 and send the slave instruction to one or more of the plurality of slave processing circuits 204, 206 and 208. In one scenario, the control circuit may send the slave instruction obtained after parsing to the slave processing circuit through the master processing circuit, i.e. Figure 2 As shown in . Alternatively, when there is a connection between the control circuit and the slave processing circuit, the control circuit may also send the parsed slave instruction directly to the slave processing circuit. Similarly, when there is a connection between the storage circuit and the slave processing circuit, the control circuit may also send the slave instruction to the slave processing circuit via the storage circuit. In some computing scenarios, when the computing instruction includes operands involving tensor operations, the control circuit may use the descriptors discussed above to determine the storage address of the data corresponding to the operand, such as the starting address of the tensor, and may instruct the master processing circuit or the slave processing circuit to obtain the tensor data involved in the tensor operation from the corresponding storage address in the storage circuit 212 in order to perform the tensor operation.

[0091] In one or more embodiments, the storage circuit 212 can store various types of data or instructions related to the calculation, such as the tensors described above. In one scenario, the storage circuit can store neuron or weight data related to the neural network operation, or store the final operation result obtained after the main processing circuit performs the post-processing operation. Additionally, the storage circuit can store the intermediate results obtained after the main processing circuit performs the pre-processing operation, or the intermediate results obtained after the slave processing circuit performs the operation operation. In the operation for the tensor, the aforementioned intermediate results can also be tensor type data, and are read and stored through the storage address determined by the descriptor. In some application scenarios, the storage circuit can be used as an on-chip memory of the computing device 200 to perform data read and write operations with the off-chip memory, such as through a direct memory access ("DMA") interface. In some scenarios, when the calculation instruction is parsed by the control circuit, the storage circuit can store the operation instruction obtained after the control circuit parses, such as the master instruction and / or the slave instruction. In addition, although Figure 2 The storage circuit is shown in a block diagram, but depending on the application scenario, the storage circuit can be implemented as a memory including a main memory and a main cache, wherein the main memory can be used to store relevant operation data such as neurons, weights and various constant terms, and the main cache module can be used to temporarily store intermediate data, such as data after the pre-processing operation and data before the post-processing operation, and these intermediate data can be invisible to the operator according to the settings.

[0092] In the interactive application of the main memory and the main processing circuit, the pipeline operation circuit in the main processing circuit can also perform corresponding operations with the help of the mask stored in the main storage circuit. For example, in the process of performing pipeline operations, the operation circuit can read a mask from the main storage circuit, and can use the mask to indicate whether the data performing the operation in the operation circuit is valid. The main storage circuit can not only perform internal storage applications, but also has the function of interacting with the storage device outside the computing device of the present disclosure, for example, it can exchange data with the external storage device through direct memory access ("DMA").

[0093] Figure 3 FIG. 3 is a block diagram illustrating a main processing circuit 300 of a computing device according to an embodiment of the present disclosure. Figure 3 The main processing circuit 300 shown is also combined with Figure 1a and Figure 2 The main processing circuit shown and described is therefore Figure 1a and Figure 2 The description of the main processing circuit in the following also applies to the Figure 3 Description.

[0094] like Figure 3As shown in , the master processing circuit 300 may include a data processing unit 302, a first group of pipeline operation circuits 304, a last group of pipeline operation circuits 306, and one or more groups of pipeline operation circuits located between the two groups (replaced by black circles). In one embodiment, the data processing unit 302 includes a data conversion circuit 3021 and a data splicing circuit 3022. As previously described, when the master operation includes a pre-processing operation for the slave operation, such as a data conversion operation or a data splicing operation, the data conversion circuit 3021 or the data splicing circuit 3022 will perform the corresponding conversion operation or splicing operation according to the corresponding master instruction. The conversion operation and splicing operation will be explained below with examples.

[0095] As far as data conversion operations are concerned, when the data bit width input to the data conversion circuit is high (for example, the data bit width is 1024 bits wide), the data conversion circuit can convert the input data into data with a lower bit width (for example, the output data bit width is 512 bits wide) according to the operation requirements. Depending on different application scenarios, the data conversion circuit can support conversions between multiple data types, for example, FP16 (16-bit floating point number), FP32 (32-bit floating point number), FIX8 (8-bit fixed point number), FIX4 (4-bit fixed point number), FIX16 (16-bit fixed point number) and other data types with different bit widths can be converted. When the data input to the data conversion circuit is a matrix, the data conversion operation can be a transformation performed on the arrangement position of the matrix elements. The transformation can, for example, include matrix transposition and mirroring (later combined Figure 4a-4c Description), matrix rotation according to a predetermined angle (for example, 90 degrees, 180 degrees or 270 degrees) and matrix dimension conversion.

[0096] With respect to data concatenation operations, the data concatenation circuit can perform operations such as parity concatenation on data blocks extracted from the data according to, for example, the bit length set in the instruction. For example, when the data bit length is 32 bits, the data concatenation circuit can divide the data into eight data blocks, 1 to 8, with a bit width of 4 bits, and then concatenate four data blocks, 1, 3, 5, and 7, and four data blocks, 2, 4, 6, and 8, for operation.

[0097] In other application scenarios, the above data splicing operation can also be performed on the data M (for example, a vector) obtained after the operation is performed. Assume that the data splicing circuit can first split the lower 256 bits of the even-numbered rows of data M into 8-bit bit width as 1 unit data to obtain 32 even-numbered row unit data (represented as M_2i0 to M_2i 31Similarly, the lower 256 bits of the odd-numbered rows of data M can also be split into 8-bit units as 1 unit data to obtain 32 odd-numbered row unit data (represented as M_(2i+1)0 to M_(2i+1) 31 ). Further, the 32 odd-row unit data and the 32 even-row unit data after splitting are alternately arranged in the order of data bits from low to high, first even rows and then odd rows. Specifically, the even-row unit data 0 (M_2i0) is arranged at the low position, and then the odd-row unit data 0 (M_(2i+1)0) is arranged in sequence. Then, the even-row unit data 1 (M_2i1) is arranged... and so on. When the odd-row unit data 31 (M_(2i+1) 31 ), 64 unit data are spliced together to form a new data with a bit width of 512 bits.

[0098] Depending on the application scenario, the data conversion circuit and data splicing circuit in the data processing unit can be used in conjunction to perform data pre-processing more flexibly. For example, depending on the different operations included in the main instruction, the data processing unit can only perform data conversion without performing data splicing operations, only perform data splicing operations without performing data conversion, or perform both data conversion and data splicing operations. In some scenarios, when the main instruction does not include pre-processing operations for the slave operation, the data processing unit can be configured to disable the data conversion circuit and data splicing circuit.

[0099] As mentioned above, the main processing circuit according to the present disclosure may include one or more groups of multi-stage pipeline operation circuits, such as Figure 3 The two groups of multi-stage pipeline operation circuits 304 and 306 shown in the figure, wherein each group of multi-stage pipeline operation circuits performs multi-stage pipeline operations including the first stage to the Nth stage, wherein each stage may include one or more operators to perform multi-stage pipeline operations according to the main instruction. In one embodiment, the main processing circuit of the present disclosure can be implemented as a single instruction multiple data (SIMD) module, and each group of multi-stage pipeline operation circuits can form an operation pipeline. The operation pipeline can be set up with different or identical functional modules (i.e., operators of the present disclosure) in different stages according to the operation requirements, such as various types of functional modules such as addition modules (or adders), multiplication modules (or multipliers), and table lookup modules (or table lookups).

[0100] In some application scenarios, when the pipeline's sequential requirements are met, different functional modules within a pipeline can be combined, with one stage of pipeline completing the operation represented by an opcode ("op") within a microinstruction. Thus, the SIMD disclosed herein can support different levels of pipeline operations. That is, based on the configuration of the arithmetic units within the arithmetic pipeline, the SIMD disclosed herein can flexibly support combinations of different numbers of ops.

[0101] Assume that there is a pipeline (named "stage 1") similar to the first set of multi-stage pipeline operation circuits 304 and the second set of multi-stage pipeline operation circuits 306. It is arranged in a six-stage pipeline with six functional modules arranged in order from top to bottom. Specifically, they can be: stage 1-1 - adder 1 (first-stage adder), stage 1-2 - adder 2 (second-stage adder), stage 1-3 - multiplier 1 (first-stage multiplier), stage 1-4 - multiplier 2 (second-stage multiplier), stage 1-5 - adder 1 (first-stage adder), stage 1-6 - adder 2 (second-stage adder). It can be seen that the first-stage adder (which serves as the first stage of the pipeline) and the second-stage adder (which serves as the second stage of the pipeline) are used in conjunction to complete the two-stage addition operation. Similarly, the first-stage multiplier and the second-stage multiplier also perform a similar two-stage operation. Of course, the two-stage adder or multiplier here is merely exemplary and not restrictive. In some application scenarios, only one-stage adder or multiplier may be provided in a multi-stage pipeline.

[0102] In some embodiments, two or more pipelines as described above may also be provided, wherein each pipeline may include a number of identical or different operators to implement the same or different functions. Further, different pipelines may include different operators so that each pipeline implements operations of different functions. The operators or circuits that implement the aforementioned different functions may include, but are not limited to, random number processing circuits, addition and subtraction circuits, subtraction circuits, table lookup circuits, parameter configuration circuits, multipliers, dividers, poolers, comparators, absolute value circuits, logical operators, position index circuits, or filters. Here, a pooler is taken as an example, which may be exemplarily composed of operators such as adders, dividers, and comparators to perform pooling operations in a neural network.

[0103] In some application scenarios, the multi-stage pipeline operation in the main processing circuit can support unary operations (i.e., a situation where there is only one input data). Taking the operation at the scale layer + relu layer in the neural network as an example, it is assumed that the calculation instruction to be executed is expressed as result = relu (a * ina + b), where ina is the input data (for example, it can be a vector, a matrix or a tensor), and a and b are both operation constants. For this calculation instruction, a set of three-stage pipeline operation circuits including a multiplier, an adder, and a nonlinear operator disclosed in the present invention can be applied to perform the operation. Specifically, the multiplier of the first stage pipeline can be used to calculate the product of the input data ina and a to obtain the first stage pipeline operation result. Then, the adder of the second stage pipeline can be used to perform an addition operation on the first stage pipeline operation result (a * ina) and b to obtain the second stage pipeline operation result. Finally, the relu activation function of the third stage pipeline can be used to activate the second stage pipeline operation result (a * ina + b) to obtain the final operation result result.

[0104] In some application scenarios, the multi-stage pipeline operation circuit in the main processing circuit can support binary operations (such as the convolution calculation instruction result = conv(ina, inb)) or ternary operations (such as the convolution calculation instruction result = conv(ina, inb, bias)), where the input data ina, inb and bias can be one-dimensional tensors (i.e., vectors, which can be, for example, integer, fixed-point or floating-point data), two-dimensional tensors (i.e., matrices), or 3-dimensional or higher tensors. Taking the convolution calculation instruction result = conv(ina, inb) as an example, the convolution operation expressed by the calculation instruction can be performed using multiple multipliers, at least one addition tree and at least one nonlinear operator included in the three-stage pipeline operation circuit structure, where the two input data ina and inb can be, for example, neuron data. Specifically, the first-stage pipeline multiplier in the three-stage pipeline operation circuit can be used for calculation first, so that the first-stage pipeline operation result product = ina*inb (regarded as a microinstruction in the operation instruction, which corresponds to the multiplication operation) can be obtained. The addition tree in the second-stage pipeline circuit then performs a sum operation on the first-stage pipeline result "product" to obtain the second-stage pipeline result "sum". Finally, the nonlinear operator in the third-stage pipeline circuit performs an activation operation on "sum" to obtain the final convolution result.

[0105] In some application scenarios, one or more stages of pipeline operation circuits that will not be used in the operation can be bypassed. That is, one or more stages of the multi-stage pipeline operation circuit can be selectively used according to the needs of the operation, without requiring the operation to pass through all the multi-stage pipeline operation stages. Taking the operation of calculating Euclidean distance as an example, assuming that its calculation instruction is expressed as dis = sum((ina - inb)^2), only several stages of pipeline operation circuits consisting of adders, multipliers, adder trees, and accumulators can be used to perform the operation to obtain the final operation result. For unused pipeline operation circuits, they can be bypassed before or during the pipeline operation.

[0106] In the aforementioned pipeline operation, each group of pipeline operation circuits can independently perform the pipeline operation. However, each group of pipeline operation circuits in multiple groups can also perform the pipeline operation in a collaborative manner. For example, the output of the first and second stages of the first group of pipeline operation circuits after performing serial pipeline operation can be used as the input of the third stage of the pipeline of another group of pipeline operation circuits. For another example, the first and second stages of the first group of pipeline operation circuits perform parallel pipeline operation and respectively output the results of their respective pipeline operations as the input of the first and / or second stage pipeline operation of another group of pipeline operation circuits.

[0107] Figure 4a 4b and 4c are schematic diagrams illustrating matrix conversions performed by the data conversion circuit according to an embodiment of the present disclosure. To better understand the conversion operations performed by the data conversion circuit 3021 in the main processing circuit, the following description will further illustrate the transposition and horizontal mirroring operations performed on an original matrix (which can be considered a 2-dimensional tensor in the present disclosure).

[0108] like Figure 4a As shown, the original matrix is a matrix of (M+1) rows × (N+1) columns. According to the requirements of the application scenario, the data conversion circuit can Figure 4a The original matrix shown in is transformed by transposing operation to obtain Figure 4b Specifically, the data conversion circuit can exchange the row numbers and column numbers of the elements in the original matrix to form a transposed matrix. Specifically, in Figure 4a The coordinate of the original matrix shown is the element "10" at row 1 and column 0. Figure 4b The coordinates in the transposed matrix shown are row 0 and column 1. Similarly, Figure 4a The coordinates of the original matrix shown are the element "M0" at row M+1 and column 0, which is Figure 4b The coordinates in the transposed matrix shown are then row 0 and column M+1.

[0109] like Figure 4c As shown, the data conversion circuit can Figure 4aThe original matrix shown is horizontally mirrored to form a horizontal mirror matrix. Specifically, the data conversion circuit can convert the arrangement order of the elements from the first row to the last row in the original matrix into the arrangement order from the last row to the first row by the horizontal mirror operation, while the column numbers of the elements in the original matrix remain unchanged. Specifically, Figure 4a The coordinates of the original matrix shown are the element "00" at row 0 and column 0 and the element "10" at row 1 and column 0. Figure 4c The coordinates in the horizontal mirror matrix shown in are the M+1th row, 0th column and the Mth row, 0th column. Figure 4a The coordinates of the original matrix shown are the element "M0" at row M+1 and column 0. Figure 4c The coordinates in the horizontal mirror matrix shown are then row 0 and column 0.

[0110] Figure 5 is a block diagram illustrating a slave processing circuit 500 of a computing device according to an embodiment of the present disclosure. It should be understood that the structure shown in the figure is merely exemplary and non-limiting, and those skilled in the art, based on the teachings of the present disclosure, may also conceive of adding more operators to form a pipeline operation circuit with more stages.

[0111] like Figure 5 As shown in FIG, the slave processing circuit 500 includes a four-stage pipeline operation circuit consisting of a multiplier 502, a comparator 504, a selector 506, an accumulator 508, and a converter 510. In one application scenario, the slave processing circuit as a whole can perform vector (including, for example, matrix) operations.

[0112] When performing vector operations, the vector data (which can be regarded as a 1-dimensional tensor under the present disclosure) including weight data and neuron data is controlled by the processing circuit 500 according to the received microinstructions (the control signals shown in the figure) to be input into the multiplier. After performing the multiplication operation, the multiplier inputs the result to the selector 506. Here, the selector 506 chooses to pass the result of the multiplier rather than the result from the comparator to the accumulator 508 to perform the accumulation operation in the vector operation. Then, the accumulator passes the accumulated result to the converter 510 to perform the data conversion operation described above. Finally, the converter outputs the accumulated sum (i.e., "ACC_SUM" shown in the figure) as the final result.

[0113] In addition to performing the matrix multiply-add ("MAC") operation between the neuron data and the weight data described above, Figure 5The four-stage pipeline operation circuit shown can also be used to perform histogram operations, depthwise layer multiplication and addition operations, integration, and Winograd multiplication and addition operations in neural network operations. When performing a histogram operation, in the first stage of the operation, the slave processing circuit inputs the input data to the comparator according to the microinstruction. Accordingly, here, the selector 506 selects to pass the comparator result rather than the multiplier result to the accumulator to perform subsequent operations.

[0114] From the above description, those skilled in the art will understand that, in terms of hardware arrangement, the slave processing circuit of the present disclosure may include multiple arithmetic circuits for performing slave arithmetic operations, and the multiple arithmetic circuits are connected and configured to perform multi-stage pipeline arithmetic operations. In one or more embodiments, the aforementioned arithmetic circuits may include, but are not limited to, one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit to perform at least vector operations, such as multidimensional convolution operations in neural networks.

[0115] In one operation scenario, the slave processing circuit disclosed herein can operate on the data that has been pre-processed by the main processing circuit according to a slave instruction (implemented as, for example, one or more microinstructions or control signals) to obtain the expected operation result. In another operation scenario, the slave processing circuit can send the intermediate result obtained after its operation (for example, via an interconnection interface) to the data processing unit in the main processing circuit, so that the data conversion circuit in the data processing unit can perform data type conversion on the intermediate result or the data splicing circuit in the data processing unit can perform data splitting and splicing operations on the intermediate result, thereby obtaining the final operation result. The operation of the main processing circuit and the slave processing circuit disclosed herein will be described below in conjunction with several exemplary instructions.

[0116] Taking the calculation instruction "COSHLC" including pre-processing operations as an example, the operations performed by it (including the pre-processing operations performed by the master processing circuit and the slave operation performed by the slave processing circuit) can be expressed as:

[0117] COSHLC=FPTOFIX+SHUFFLE+LT3DCONV,

[0118] FPTOFIX represents a data type conversion operation performed by a data conversion circuit in the main processing circuit, i.e., converting input data from floating-point numbers to fixed-point numbers; SHUFFLE represents a data splicing operation performed by a data splicing circuit; and LT3DCONV represents a 3DCONV operation performed by a slave processing circuit (represented by "LT"), i.e., a convolution operation on 3D data. It will be appreciated that when only a convolution operation on 3D data is performed, both FPTOFIX and SHUFFLE, which are part of the main operation, can be set as optional operations.

[0119] Taking the calculation instruction LCSU including the post-processing operation as an example, the operation performed by it (including the slave operation performed by the slave processing circuit and the post-processing operation performed by the master processing circuit) can be expressed as:

[0120] LCSU=LT3DCONV+SUB,

[0121] After the slave processing circuit performs the LT3DCONV operation to obtain the 3D convolution result, the subtractor in the master processing circuit can perform a subtraction operation SUB on the 3D convolution result. Thus, in each instruction execution cycle, a binary operand (i.e., the convolution result and the subtrahend) can be input and a single univariate operand (i.e., the final result obtained after executing the LCSU instruction) can be output.

[0122] Taking the calculation instruction SHLCAD including pre-processing operation, slave operation and post-processing operation as an example, the operations performed by it (including the pre-processing operation performed by the main processing circuit, the slave operation performed by the slave processing circuit and the post-processing operation performed by the main processing circuit) can be expressed as follows:

[0123] SHLCAD=SHUFFLE+LT3DCONV+ADD

[0124] In the pre-processing operation, the data splicing circuit performs a data splicing operation represented by SHUFFLE. Next, the slave processing circuit performs an LT3DCONV operation on the spliced data to obtain a 3D convolution result. Finally, the adder in the master processing circuit performs an addition operation ADD on the 3D convolution result to obtain the final calculation result.

[0125] From the above examples, it can be understood by those skilled in the art that after parsing the calculation instructions, the operation instructions obtained by the present disclosure include one of the following combinations according to the specific operation operations: pre-processing instructions and sub-processing instructions; sub-processing instructions and post-processing instructions; and pre-processing instructions, sub-processing instructions and post-processing instructions. Based on this, in some embodiments, the pre-processing instructions may include data conversion instructions and / or data splicing instructions. In other embodiments, the post-processing instructions include one or more of the following: random number processing instructions, addition instructions, subtraction instructions, table lookup instructions, parameter configuration instructions, multiplication instructions, pooling instructions, activation instructions, comparison instructions, absolute value instructions, logical operation instructions, position index instructions or filtering instructions. In other embodiments, the sub-processing instructions may include various types of operation instructions, including but not limited to instructions similar to those in the post-processing instructions and instructions for complex data processing, such as vector operation instructions or tensor operation instructions.

[0126] Based on the above combined with Figure 1 (including Figure 1a and Figure 1b)- Figure 5 The present disclosure also discloses a method for performing a computing operation using a computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit (i.e., the method described above in conjunction with FIG. 1 to FIG. 2 ). Figure 5 The method includes configuring the master processing circuit to perform a master operation in response to a master instruction, and configuring the slave processing circuit to perform a slave operation in response to a slave instruction. In one embodiment, the master operation includes a pre-processing operation and / or a post-processing operation for the slave operation, and the master instruction and the slave instruction are parsed according to the computing instruction received by the computing device. In another embodiment, the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand.

[0127] Based on the above-mentioned descriptor settings, the method may further include configuring the master processing circuit and / or the slave processing circuit to execute the respective corresponding master operation and / or slave processing operation according to the storage address. As previously mentioned, through the descriptor settings disclosed in the present invention, the efficiency of tensor operations and the rate of data access can be improved, and the overhead of tensor operations can be further reduced. In addition, although the other steps of the method are not described here for the purpose of simplicity, those skilled in the art can understand that the method disclosed in the present invention can be executed in conjunction with Figures 1- Figure 5 Various operations described.

[0128] Figure 6 FIG. 6 is a structural diagram showing a combined processing device 600 according to an embodiment of the present disclosure. Figure 6 As shown in FIG1 , the combined processing device 600 includes a computing processing device 602, an interface device 604, other processing devices 606, and a storage device 608. According to different application scenarios, the computing processing device may include one or more computing devices 610, which may be configured to perform the processing described in conjunction with FIG1 Figure 5 The described operation.

[0129] In various embodiments, the computing and processing device of the present disclosure may be configured to perform user-specified operations. In exemplary applications, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, the computing and processing device of the present disclosure may be considered to have a single-core structure or a homogeneous multi-core structure.

[0130] In exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through interface means, to jointly complete the operation specified by the user. Depending on the difference in implementation, the other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as central processing unit (Central Processing Unit, CPU), graphics processing unit (Graphics Processing Unit, GPU), artificial intelligence processor. These processors may include but are not limited to digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0131] In one or more embodiments, the other processing device may serve as an interface between the computing device disclosed herein (which may be embodied as an artificial intelligence computing device such as a neural network computing device) and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, and so on. In other embodiments, the other processing device may also collaborate with the computing device to jointly complete computing tasks.

[0132] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0133] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0134] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 7 In one implementation, the chip is a system on chip (SoC) and integrates one or more components such as Figure 6 The chip can be connected to the external interface device (such as Figure 7 The external interface device 706 shown in the figure is connected to other related components. The related components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) can be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 7 The board is described in detail.

[0135] Figure 7 FIG. 7 is a schematic diagram showing the structure of a board 700 according to an embodiment of the present disclosure. Figure 7 As shown in , the board includes a storage device 704 for storing data, which includes one or more storage units 710. The storage device can be connected to the control device 708 and the chip 702 described above and transmit data by means of, for example, a bus. Further, the board also includes an external interface device 706, which is configured for data relay or transfer function between the chip (or the chip in the chip packaging structure) and the external device 712 (such as a server or computer, etc.). For example, the data to be processed can be passed to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0136] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the working state of the chip.

[0137] According to the above combination Figure 6 and Figure 7 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0138] According to different application scenarios, the electronic devices or devices disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic devices or devices disclosed herein may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic devices or devices disclosed herein may also be used in cloud, edge, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0139] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teachings of the present disclosure, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present disclosure. In addition, depending on the different schemes, the description of some embodiments of the present disclosure also has different emphases. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0140] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this document divides them based on the consideration of logical functions, and there may be other ways of division in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0141] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solution described in the embodiments of this disclosure. In addition, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically separately.

[0142] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program code, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0143] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0144] The foregoing content can be better understood in accordance with the following terms:

[0145] Clause 1. A computing device comprising a master processing circuit and at least one slave processing circuit, wherein:

[0146] The main processing circuit is configured to perform main computing operations in response to main instructions,

[0147] The slave processing circuit is configured to perform slave arithmetic operations in response to slave instructions,

[0148] The master operation includes a pre-processing operation and / or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computing instruction received by the computing device, wherein the operand of the computing instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine the storage address of the data corresponding to the operand.

[0149] The master processing circuit and / or the slave processing circuit are configured to execute respective corresponding master computing operations and / or slave processing operations according to the storage address.

[0150] Clause 2. A computing device according to clause 1, wherein the computing instruction includes an identification of a descriptor and / or content of the descriptor, the content of the descriptor including at least one shape parameter representing a shape of tensor data.

[0151] Clause 3. A computing device according to clause 2, wherein the contents of the descriptor further include at least one address parameter representing an address of tensor data.

[0152] Clause 4. A computing device according to clause 3, wherein the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data.

[0153] Clause 5. The computing device of clause 4, wherein the shape parameter of the tensor data comprises at least one of the following:

[0154] The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of the tensor data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

[0155] Clause 6. The computing device of clause 1, wherein the main processing circuit is configured to:

[0156] Obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

[0157] The slave instruction is sent to the slave processing circuit.

[0158] Clause 7. The computing device of clause 1, further comprising a control circuit configured to:

[0159] Obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

[0160] The master instruction is sent to the master processing circuit and the slave instruction is sent to the slave processing circuit.

[0161] Clause 8. The computing device according to clause 1, wherein the main instruction includes an identification bit for identifying the pre-processing operation and / or the post-processing operation.

[0162] Clause 9. The computing device according to clause 1, wherein the computing instruction includes a preset bit for distinguishing the pre-processing operation and the post-processing operation in the main instruction.

[0163] Item 10. A computing device according to Item 1, wherein the main processing circuit includes a data processing unit for performing the main computing operation, and the data processing unit includes a data conversion circuit for performing a data conversion operation and / or a data splicing circuit for performing a data splicing operation.

[0164] Item 11. The computing device according to Item 10, wherein the data conversion circuit comprises one or more converters for implementing conversion of computing data between a plurality of different data types.

[0165] Clause 12. The computing device according to clause 10, wherein the data splicing circuit is configured to split the computing data into predetermined bit lengths and splice the multiple data blocks obtained after the splitting in a predetermined order.

[0166] Item 13. A computing device according to Item 1, wherein the main processing circuit includes one or more groups of pipeline operation circuits, each group of pipeline operation circuits forms an operation pipeline and includes one or more operators, wherein when each group of pipeline operation circuits includes multiple operators, the multiple operators are connected and configured to selectively participate in performing the main operation according to the main instruction.

[0167] Clause 14. The computing device according to clause 13, wherein the main processing circuit comprises at least two operation pipelines, and each operation pipeline comprises one or more of the following operators or circuits:

[0168] Random number processing circuit, addition and subtraction circuit, subtraction circuit, table lookup circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.

[0169] Item 15. A computing device according to Item 1, wherein the slave processing circuit includes a plurality of arithmetic circuits for performing the slave arithmetic operations, and the plurality of arithmetic circuits are connected and configured to perform a multi-stage pipeline arithmetic operation, wherein the arithmetic circuit includes one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit to perform at least vector operations.

[0170] Clause 16. The computing device according to clause 15, wherein the slave instruction comprises a convolution instruction for performing a convolution operation on the calculation data subjected to the pre-processing operation, and the slave processing circuit is configured to:

[0171] A convolution operation is performed on the calculated data after the pre-processing operation according to the convolution instruction.

[0172] Clause 17. An integrated circuit chip comprising the computing device according to any one of clauses 1-16.

[0173] Clause 18. A board comprising the integrated circuit chip according to clause 17.

[0174] Clause 19. An electronic device comprising the integrated circuit chip according to clause 17.

[0175] Clause 20. A method of performing a computing operation using a computing device, wherein the computing device includes a master processing circuit and at least one slave processing circuit, the method comprising:

[0176] configuring the primary processing circuit to perform primary computing operations in response to primary instructions,

[0177] configuring the slave processing circuit to perform slave arithmetic operations in response to slave instructions,

[0178] The master operation includes a pre-processing operation and / or a post-processing operation for the slave operation, the master instruction and the slave instruction are obtained by parsing the computation instruction received by the computing device, the operand of the computation instruction includes a descriptor for indicating the shape of a tensor, and the descriptor is used to determine a storage address of data corresponding to the operand.

[0179] The method further includes configuring the master processing circuit and / or the slave processing circuit to execute respective corresponding master computing operations and / or slave processing operations according to the storage address.

[0180] Clause 21. A method according to clause 20, wherein the computation instruction includes an identification of a descriptor and / or content of the descriptor, the content of the descriptor including at least one shape parameter representing a shape of the tensor data.

[0181] Clause 22. The method of clause 21, wherein the contents of the descriptor further comprise at least one address parameter representing an address of tensor data.

[0182] Clause 23. The method according to clause 22, wherein the address parameter of the tensor data comprises a base address of a data base point of the descriptor in a data storage space of the tensor data.

[0183] Clause 24. The method of clause 23, wherein the shape parameter of the tensor data comprises at least one of the following:

[0184] The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of the tensor data in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address, where N is an integer greater than or equal to zero.

[0185] Clause 25. The method of clause 20, wherein the main processing circuit is configured to:

[0186] Obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

[0187] The slave instruction is sent to the slave processing circuit.

[0188] Clause 26. The method of clause 20, wherein the computing device includes a control circuit, the method further comprising configuring the control circuit to:

[0189] Obtaining the computing instruction and parsing the computing instruction to obtain the master instruction and the slave instruction; and

[0190] The master instruction is sent to the master processing circuit and the slave instruction is sent to the slave processing circuit.

[0191] Clause 27. The method according to clause 20, wherein the main instruction includes an identification bit for identifying the pre-processing operation and / or the post-processing operation.

[0192] Clause 28. The method of clause 20, wherein the computation instruction includes a preset bit for distinguishing the pre-processing operation from the post-processing operation in the host instruction.

[0193] Item 29. A method according to Item 20, wherein the main processing circuit includes a data processing unit, and the data processing unit includes a data conversion circuit and / or a data splicing circuit, and the method includes configuring the data processing unit to perform the main operation, and configuring the data conversion circuit to perform a data conversion operation, and configuring the data splicing circuit to perform a data splicing operation.

[0194] Clause 30. The method of clause 29, wherein the data conversion circuitry comprises one or more converters, the method comprising configuring the one or more converters to implement conversion of computational data between a plurality of different data types.

[0195] Item 31. The method according to Item 29, wherein the data splicing circuit is configured to split the calculation data into predetermined bit lengths and splice the multiple data blocks obtained after the splitting in a predetermined order.

[0196] Item 32. A method according to Item 20, wherein the main processing circuit includes one or more groups of pipeline operation circuits, each group of pipeline operation circuits forms an operation pipeline and includes one or more operators, wherein when each group of pipeline operation circuits includes multiple operators, the method includes connecting the multiple operators and configuring them to selectively participate in performing the main operation according to the main instruction.

[0197] Clause 33. The method of clause 32, wherein the main processing circuit comprises at least two operation pipelines, and each operation pipeline comprises one or more of the following operators or circuits:

[0198] Random number processing circuit, addition and subtraction circuit, subtraction circuit, table lookup circuit, parameter configuration circuit, multiplier, divider, pooler, comparator, absolute value circuit, logic operator, position index circuit or filter.

[0199] Item 34. A method according to Item 20, wherein the slave processing circuit includes a plurality of arithmetic circuits, the method includes configuring the plurality of arithmetic circuits to perform the slave arithmetic operations, and the method also includes connecting and configuring the plurality of arithmetic circuits to perform multi-stage pipeline arithmetic operations, wherein the arithmetic circuits include one or more of a multiplication circuit, a comparison circuit, an accumulation circuit, and a rotation circuit to perform at least vector operations.

[0200] Clause 35. The method of clause 34, wherein the slave instruction comprises a convolution instruction for performing a convolution operation on the computation data subjected to the pre-processing operation, the method comprising configuring the slave processing circuit to:

[0201] A convolution operation is performed on the calculated data after the pre-processing operation according to the convolution instruction.

[0202] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many modifications, changes, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. An artificial intelligence processor for executing a computational instruction, the computational instruction including a descriptor, the artificial intelligence processor comprising: storage circuits; a main processing circuit, configured to access the tensor and perform pre-processing operations based on a storage address in the storage circuit obtained from the descriptor and a shape of the N-dimensional tensor, wherein the storage address includes a reference address of a data reference point of the descriptor in the data storage space; a plurality of slave processing circuits configured to perform N-dimensional matrix operations in parallel based on the tensor after the pre-processing operation; The shape of the N-dimensional tensor is indicated by: a size of the data storage space in at least one of the N dimensions, a size of the storage area of the tensor in at least one of the N dimensions, and an offset of the storage area in at least one of the N dimensions, and / or at least one of the following: The mapping relationship between the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point, the data description position of the tensor indicated by the descriptor and the data address, wherein the data description position is the mapping position of the point or area in the tensor data indicated by the descriptor expressed using spatial coordinates, and N is an integer greater than or equal to zero.

2. The artificial intelligence processor according to claim 1, wherein the main processing circuit is used to perform the data splicing operation in the pre-processing operation.

3. The artificial intelligence processor according to claim 1, wherein the main processing circuit is used to perform data conversion operations in the pre-processing operations.

4. The artificial intelligence processor according to claim 1, wherein the tensors are stored in the same area of the internal memory.

5. The artificial intelligence processor of claim 1 , wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operations.

6. The artificial intelligence processor according to claim 5, wherein the main processing circuit matches the pre-processing operation and the post-processing operation by using an identification bit of the computing instruction.

7. The artificial intelligence processor of claim 5, wherein the computational instructions comprise one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction.

8. The artificial intelligence processor of claim 1 , wherein the slave processing circuit performs data type conversion.

9. The artificial intelligence processor according to claim 1, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations.

10. An artificial intelligence processor for executing a computational instruction, the computational instruction including a descriptor, the artificial intelligence processor comprising: A main processing circuit configured to perform a main operation, the main operation including accessing the tensor using a storage address obtained from the descriptor and a shape of the N-dimensional tensor, and a pre-processing operation; Wherein, the main processing circuit is used to perform the splicing operation in the pre-processing operation; Wherein, the storage address includes the agreed reference address of the data reference point of the descriptor in the data storage space; The shape of an N-dimensional tensor may include: a size of the data storage space in at least one of the N dimensions, a size of the storage area of the tensor in at least one of the N dimensions, and an offset of the storage area in at least one of the N dimensions, and / or at least one of the following: The mapping relationship between the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point, the data description position of the tensor indicated by the descriptor and the data address, wherein the data description position is the mapping position of the point or area in the tensor data indicated by the descriptor expressed using spatial coordinates, and N is an integer greater than or equal to zero.

11. The artificial intelligence processor according to claim 10, wherein the main processing circuit is used to perform a data conversion operation in the pre-processing operation.

12. The artificial intelligence processor according to claim 10, further comprising: A plurality of slave processing circuits are configured to perform N-dimensional matrix operations in parallel based on the tensor after the pre-processing operation.

13. The artificial intelligence processor according to claim 12, wherein the tensors are stored in the same area of the internal memory.

14. The artificial intelligence processor of claim 12, wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operation.

15. The artificial intelligence processor according to claim 14, wherein the main processing circuit distinguishes the pre-processing operation from the post-processing operation by using an identification bit of the computing instruction.

16. The artificial intelligence processor of claim 14, wherein the computational instructions comprise one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction.

17. The artificial intelligence processor of claim 12, wherein the slave processing circuit performs data type conversion.

18. The artificial intelligence processor according to claim 12, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations.

19. An artificial intelligence processor for executing a computational instruction, the computational instruction including a descriptor, the artificial intelligence processor comprising: A main processing circuit configured to perform a main operation, the main operation including accessing the tensor using a storage address obtained from the descriptor and a shape of the N-dimensional tensor, and a pre-processing operation; wherein the main processing circuit is used to perform the data conversion operation in the pre-processing operation; wherein the storage address comprises a predetermined reference address of a data reference point of the descriptor in the data storage space; The shape of an N-dimensional tensor may include: a size of the data storage space in at least one of the N dimensions, a size of the storage area of the tensor in at least one of the N dimensions, and an offset of the storage area in at least one of the N dimensions, and / or at least one of the following: The mapping relationship between the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point, the data description position of the tensor indicated by the descriptor and the data address, wherein the data description position is the mapping position of the point or area in the tensor data indicated by the descriptor expressed using spatial coordinates, and N is an integer greater than or equal to zero.

20. The artificial intelligence processor according to claim 19, further comprising: A plurality of slave processing circuits are configured to perform N-dimensional matrix operations in parallel based on the tensor after the pre-processing operation.

21. The artificial intelligence processor according to claim 20, wherein the tensors are stored in the same area of the internal memory.

22. The artificial intelligence processor of claim 20, wherein the main processing circuit performs post-processing operations based on the N-dimensional matrix operation.

23. The artificial intelligence processor according to claim 22, wherein the main processing circuit matches the pre-processing operation and the post-processing operation by using an identification bit of the computing instruction.

24. The artificial intelligence processor of claim 22, wherein the computational instructions comprise one of the following combinations: a pre-processing instruction and a sub-processing instruction; a sub-processing instruction and a post-processing instruction; and a pre-processing instruction, a sub-processing instruction, and a post-processing instruction.

25. The artificial intelligence processor of claim 20, wherein the slave processing circuit performs data type conversion.

26. The artificial intelligence processor of claim 20, wherein the master processing circuit and the slave processing circuit are configured to support multi-stage pipeline operations.

27. An integrated circuit chip comprising the artificial intelligence processor according to any one of claims 1-26.

28. A board comprising the integrated circuit chip according to claim 27.

29. An electronic device comprising the integrated circuit chip according to claim 27.

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