A wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof

Abstract

The present invention provides a wide bandgap semiconductor trench MOSFET device structure and a method for fabricating the same. The structure comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P+ shielding layer, a gate electrode, and a source P+ region. The first epitaxial layer and the second epitaxial layer are sequentially stacked and grown on the substrate. Multiple gate electrodes are sequentially spaced apart in the second epitaxial layer along the length of the device structure. A P+ shielding layer is provided at the bottom of each gate electrode, and the P+ shielding layer is located in the second epitaxial layer. The source P+ region extends through the P+ shielding layer at intervals along the length of the gate electrode, and the P+ shielding layer and the P+ buried layer are electrically connected to the source P+ region. This structure not only improves the device's conduction characteristics but also provides excellent shielding, thereby enhancing the device's dynamic reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Currently, silicon carbide (SiC) devices can achieve P-type doping through ion implantation or epitaxial growth. However, it is more difficult to achieve P-type doping through ion implantation for materials with wider bandgap widths than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). P-type can be achieved through special processes such as epitaxial growth or oxide growth. However, in actual operation, wide bandgap semiconductor trench MOSFET devices still have several problems in process manufacturing and application: (1) The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, causing the gate dielectric layer to quickly break down under high drain voltage; the device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; (2) In order to reduce the electric field at the gate trench corner, traditional devices need to sacrifice part of the chip area, so the device conduction characteristics deteriorate.

[0003] Therefore, it is necessary to design a new structure for the MOSFET device structure. The present invention provides a new wide bandgap semiconductor trench MOSFET device structure. Summary of the Invention

[0004] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof, which can not only improve the conduction characteristics of the device, but also enhance the dynamic reliability of the device.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] In a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, comprising: a substrate, a first epitaxial layer, a second epitaxial layer, a P+ masking layer, a gate electrode, and a source P+ region;

[0007] The first epitaxial layer and the second epitaxial layer are sequentially stacked and grown on the substrate;

[0008] A plurality of gate electrodes are sequentially and spaced apart in the second epitaxial layer along the length direction of the device structure, and the bottom of any gate electrode is provided with the P+ shielding layer, and the P+ shielding layer is located in the second epitaxial layer;

[0009] The source P+ regions are spaced apart and penetrate the P+ shielding layer along the length direction of the gate electrode, and the P+ shielding layer and the P+ buried layer are electrically connected to the source P+ regions.

[0010] On the basis of the above technical solution, the present invention can also be improved as follows.

[0011] Furthermore, the wide bandgap semiconductor trench MOSFET device structure further includes a P+ buried layer;

[0012] The P+ buried layer is formed between the first epitaxial layer and the second epitaxial layer;

[0013] An N+ current channel is provided in the P+ buried layer and is located directly below the P+ shielding layer.

[0014] Furthermore, the source P+ region is arranged in the middle area of the gate electrode along the length direction of the device structure, the bottom of the source P+ region contacts the P+ buried layer, and the sidewall of the source P+ region contacts the P+ masking layer.

[0015] Furthermore, the wide bandgap semiconductor trench MOSFET device structure further includes a gate connection trench;

[0016] The plurality of gate electrodes are connected through the gate connection groove, the source P+ region is wrapped in the gate connection groove, and the gate connection groove is used to assist source P+ ion implantation.

[0017] Furthermore, a plurality of source P+ regions are spaced apart and penetrate the gate electrode along the length direction of the gate electrode.

[0018] Furthermore, the P+ shielding layer and the P+ Halo region / P+ Teeth region are provided at the bottom of the gate electrode, and the P+ Halo region / P+ Teeth region are provided on both sides of the P+ shielding layer.

[0019] Furthermore, a P-well region, a source N+ region, an ohmic contact region and a source electrode are sequentially formed on the second epitaxial layer from bottom to top.

[0020] Furthermore, the gate electrode includes a gate trench, a gate dielectric layer and gate polysilicon;

[0021] The gate trench is provided through the source N+ region, the P-well region and a portion of the second epitaxial layer;

[0022] The gate dielectric layer is provided on the inner wall side of the gate trench, and the gate trench is filled with the gate polysilicon.

[0023] Furthermore, the wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode;

[0024] The drain electrode is arranged at the bottom of the substrate.

[0025] In a second aspect, the present invention further provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure as described in the first aspect, comprising:

[0026] Epitaxially grow an epitaxial layer on the substrate, then form a P-well region through ion implantation, secondary epitaxy, and growth of a P-type oxide, and then form a source N+ region on the P-well region through ion implantation;

[0027] epitaxially growing a first epitaxial layer, a P+ buried layer and a second epitaxial layer in sequence on a substrate;

[0028] A P-well region is formed by ion implantation, secondary epitaxy, and growth of a P-type oxide, and then a source N+ region is formed on the P-well region by ion implantation;

[0029] forming a source trench and a gate trench by dry etching;

[0030] Forming a source P+ region by ion implantation;

[0031] Forming a P+ masking layer by P-type ion implantation;

[0032] Forming an N+ current channel by N-type ion implantation;

[0033] The gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, and drain metal deposition are sequentially performed to obtain the product.

[0034] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0035] Compared with the prior art, the wide bandgap semiconductor trench MOSFET device structure and the manufacturing method thereof provided by the present invention have the following advantages:

[0036] (1) A wide bandgap semiconductor trench gate MOSFET device structure is formed by constructing a P-well region, a P+ masking layer, a gate connection groove, a source P+ region and a source N+ region, a source electrode and a drain electrode, wherein the gate connection groove and the gate trench are connected together above the semiconductor through gate polysilicon, and the surfaces of the source P+ regions on both sides simultaneously form ohmic contacts with the source N+ regions. The gate connection groove is in the shape of a long strip and is directly connected to the polysilicon around the chip. Therefore, the constructed gate connection groove can provide a gate layout design for a block-shaped gate structure;

[0037] (2) In the traditional solution, both sides of each gate trench need source P+ regions to shield the electric field at the gate trench corner. The source P+ region will occupy a large chip area. If the electric field needs to be further reduced, a P+ shielding layer in a grounded state needs to be maintained, which will also occupy a certain chip area. This solution can ensure a low gate trench corner electric field by utilizing the design of the P+ shielding layer to improve the dynamic reliability of the device. At the same time, the chip area where the P+ shielding layer is grounded and the chip area of the source P+ region can use the same area in space, saving one ion implantation and process cost. At the same time, it greatly saves chip area and improves the conduction characteristics of the device.

[0038] (3) By adopting NPN sandwich epitaxy, the P+ buried layer can naturally form a protective effect on the gate groove corner, the N+ current channel can form the device conduction area, and the source P+ region is electrically connected to the P+ shielding layer and the P+ buried layer. The surface of the source P+ region on both sides of the gate connection groove will form an ohmic contact with the source N+ region at the same time, short-circuiting the source N+ region, source P+ region, P+ buried layer, and P+ shielding layer together. This structure has a good shielding effect and can improve the dynamic reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0040] Figure 2 A schematic top-down cross-sectional view of a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0041] Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure at section A;

[0042] Figure 4 for Figure 1 Schematic diagram of the cross-sectional structure at section B;

[0043] Figure 5 A schematic diagram of a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0044] Figures 6 to 9 Schematic diagram of several configurations of the source P+ region of the wide bandgap semiconductor trench MOSFET device structure provided by the present invention;

[0045] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0046] 1. Substrate; 2. First epitaxial layer; 3. Second epitaxial layer; 4. P+ shielding layer; 5. P-well region; 6. Source N+ region; 7. Gate electrode; 701. Gate dielectric layer; 702. Gate polysilicon; 8. P+ buried layer; 9. Gate connection groove; 10. N+ current channel; 11. Ohmic contact region; 12. Source P+ region; 13. Drain electrode. DETAILED DESCRIPTION

[0047] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0048] It will be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other element will be oriented as "on" the other element or feature. Therefore, the exemplary terms "on the front side of" and "on the back side of" are only used to define two opposite sides. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] The present invention provides a novel wide bandgap semiconductor trench MOSFET device structure and a method for manufacturing the same. The embodiments of the present invention are further described in detail below with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present invention but are not intended to limit the scope of the present invention.

[0050] First, as Figure 1 As shown, an embodiment of the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including: a substrate 1, a first epitaxial layer 2, a second epitaxial layer 3, a P+ masking layer 4, a gate electrode 7 and a source P+ region 12.

[0051] The first epitaxial layer 2 and the second epitaxial layer 3 are sequentially stacked and grown on the substrate 1 .

[0052] A plurality of gate electrodes 7 are sequentially and spaced apart in the second epitaxial layer 3 along the length direction of the device structure. A P+ shielding layer 4 is provided at the bottom of any gate electrode 7 and the P+ shielding layer 4 is located in the second epitaxial layer 3 .

[0053] The source P+ regions 12 are spaced apart and penetrate the gate electrode 7 along the length direction of the gate electrode 7 , and the P+ shielding layer 4 and the P+ buried layer 8 are electrically connected to the source P+ regions 12 .

[0054] Specifically, the epitaxial layer includes a first epitaxial layer 2 and a second epitaxial layer 3 which are sequentially stacked on a substrate 1; Figure 1 As shown, the P+ buried layer 8 is formed between the first epitaxial layer 2 and the second epitaxial layer 3 ; an N+ current channel 10 is provided in the P+ buried layer 8 and the N+ current channel 10 is located directly below the P+ shielding layer 4 .

[0055] A P-well region 5 , a source N+ region 6 , an ohmic contact region 11 and a source electrode are sequentially formed on the second epitaxial layer 3 from bottom to top.

[0056] The gate electrode 7 includes a gate trench, a gate dielectric layer 701 and a gate polysilicon 702 ; the gate trench penetrates the source N+ region 6 , the P-well region 5 and a portion of the second epitaxial layer 3 .

[0057] A gate dielectric layer 701 is provided on the inner wall side of the gate trench, and the gate trench is filled with gate polysilicon 702.

[0058] like Figure 1 As shown, the wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode 13 ; the drain electrode 13 is provided at the bottom of the substrate 1 .

[0059] In an optional embodiment, if Figure 1 As shown, the source P+ region 12 is arranged in the middle area of the gate electrode 7 along the length direction of the device structure, the bottom of the source P+ region 12 contacts the P+ buried layer 8, and the sidewall of the source P+ region 12 contacts the P+ masking layer 4.

[0060] The wide bandgap semiconductor trench MOSFET device structure further includes a gate connection groove 9; multiple gate electrodes 7 are connected through the gate connection groove 9, and the source P+ region 12 is wrapped in the gate connection groove 9. The gate connection groove 9 is used to assist the source P+ ion implantation. Figure 1 and Figure 4 As shown, the gate trench constructed above the P+ buried layer 8 can be square-shaped. If it is square-shaped, a gate connection groove structure is required for connection. The gate connection groove 9 is in the shape of a long strip and is directly connected to the polysilicon around the chip. The constructed gate connection groove can provide a gate layout design for the square-shaped gate structure.

[0061] The opening of the N+ current channel 10 may be greater than, less than, or equal to the gate trench width, and the N+ current channel 10 may be located directly below, to the lower left, or to the lower right of the gate trench.

[0062] Figure 2The figure shows a top view of the P+ buried layer 8, the source P+ region 12, the P+ shielding layer 4 and the N+ current channel 10, wherein the width of the P+ shielding layer 4 can be greater than, less than or equal to the width of the N+ current channel 10. Figure 3 As shown, it can be seen that both the P+ shielding layer 4 and the P+ buried layer 8 can maintain electrical connection with the source P+ region 12 in space.

[0063] It should be noted that the source P+ region 12 also includes multiple implementations, which are listed as follows: Figure 6 As for Figure 9 As shown, Figure 6 Take sections A and B in the figure as an example to demonstrate.

[0064] In an optional embodiment, if Figure 6 As shown, the gate trench constructed above the P+ buried layer can also be in the shape of a long strip. When the gate trench is in the shape of a long strip, a source P+ region can also be formed in space. Multiple source P+ regions are spaced through the gate electrode along the length direction of the gate electrode, so that the chip area where the P+ shielding layer is grounded and the chip area of the source P+ region can use the same area in space, saving one ion implantation, while greatly saving the chip area and improving the conduction characteristics of the device.

[0065] like Figure 7 As shown, when manufacturing the device structure, a secondary epitaxial process is used to form a suspended junction, which can modulate the electric field distribution of the device and improve the breakdown characteristics of the device; at the same time, a separate layout is used in the secondary epitaxial-ion implantation process in section B so that the two layers of suspended junctions remain connected here, where the number of layers of the suspended junction is N, N ≥ 1; at the same time, a source P+ region can also be formed on section B, so that the P+ masking layer and the suspended junction are both kept grounded through the source P+ region, thereby improving the dynamic characteristics of the suspended junction device; the design of the gate connection groove and the source P+ region greatly saves chip area and improves the conduction characteristics of the device.

[0066] like Figure 8 As shown, when there is no P+ buried layer and N+ current channel, and the gate structure is a single-stage trench, multi-stage trench, or a single-stage and multi-stage spaced arrangement combination, the P+ masking layer and P+ Halo region (P+ halo region) formed by vertical injection at the bottom and injection at a certain angle can provide better protection for the gate. The P+ halo region is arranged on both sides of the P+ masking layer to reduce the electric field of the gate oxide layer. The entire surface of P+ in section B is injected to form the source P+ region. At the same time, the P+ masking layer can be kept grounded in space, thereby improving the dynamic reliability of the device.

[0067] like Figure 9As shown, when there is no P+ buried layer and N+ current channel, and the gate structure is a single-stage trench, a multi-stage trench, or a single-stage and multi-stage spaced arrangement combination, the P+ masking layer and the P+ Teeth region (P+ toothed region) formed by the vertical injection at the bottom of the multi-stage trench and the injection at a larger sidewall angle can provide better protection for the multi-stage trench gate. The P+ toothed region is arranged on both sides of the P+ masking layer. There is no need to inject the P+ masking layer at the bottom of the single-stage trench. The P+ Teeth region of the multi-stage trench can provide better protection for the single-stage gate trench, reduce the electric field of the gate oxide layer, and the entire surface of P+ in section B is injected to form the source P+ region. At the same time, the P+ masking layer can be kept grounded in space, thereby improving the dynamic reliability of the device.

[0068] The above examples are only some embodiments of the present invention, all of which fall within the scope of protection of this application. For other embodiments that conform to the above examples, those skilled in the art can design correspondingly based on the above examples.

[0069] The embodiment of the present invention forms a wide bandgap semiconductor trench gate MOSFET device structure by constructing a P-well region, a P+ shielding layer, a gate connection groove, a source P+ region and a source N+ region, a source electrode and a drain electrode, wherein the gate connection groove and the gate trench are connected together above the semiconductor through the gate polysilicon, and the surfaces of the source P+ regions on both sides form ohmic contacts with the source N+ regions at the same time. The gate connection groove is in the shape of a long strip and is directly connected to the polysilicon around the chip. Therefore, the constructed gate connection groove provides a gate layout design for a block-shaped gate structure; in the traditional solution, each gate trench The source P+ region is required on both sides of the groove to shield the electric field at the gate groove corner. The source P+ region will occupy a larger chip area. If the electric field needs to be further reduced, the P+ shielding layer needs to be kept in a grounded state, which will also occupy a certain chip area. This solution uses the design of the P+ shielding layer to ensure a low gate groove corner electric field to improve the dynamic reliability of the device. At the same time, the chip area where the P+ shielding layer is grounded and the chip area of the source P+ region can use the same area in space, saving one ion implantation and saving process costs. At the same time, it greatly saves chip area and improves the conduction characteristics of the device.

[0070] In addition, this structure uses NPN sandwich epitaxy, and the P+ buried layer can naturally protect the gate groove corners. The N+ current channel can form a device conduction area, and the source P+ region is electrically connected to the P+ shielding layer and the P+ buried layer. The source P+ region surfaces on both sides of the gate connection groove will form ohmic contacts with the source N+ region at the same time, short-circuiting the source N+ region, source P+ region, P+ buried layer, and P+ shielding layer together. This structure has a good masking effect and can improve the dynamic reliability of the device.

[0071] In a second aspect, the present invention also provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure (using cross sections A and B as examples for illustration), see Figure 5 As shown, the operation is as follows:

[0072] Step S1: (Cross-section A&B) A first N-epitaxial layer is grown on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate.

[0073] Step S2: (Cross Sections A & B) Growing a P+ buried layer on the first N- epitaxial layer.

[0074] Step S3: (Cross Sections A & B) A second N- epitaxial layer is grown on the P+ buried layer.

[0075] Step S4: (cross sections A & B) forming a P-well region by ion implantation, secondary epitaxy, growing a P-type oxide, etc.; forming a source N+ region by ion implantation.

[0076] Step S5: (Cross-Section A (left) & Cross-Section B (right)) Dry etching to form a gate trench and a gate connection trench.

[0077] Step S6: (cross section B) forming a source P+ region by ion implantation.

[0078] Step S7: (Cross-Section A (left) & Cross-Section B (right)) Form a P+ masking layer by P-type ion implantation.

[0079] Step S8: (Cross-Section A (left) & Cross-Section B (right)) Forming an N+ current channel by N-type ion implantation.

[0080] Step S9: (Section A (left) & Section B (right)) Gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric growth and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, drain metal deposition.

[0081] Since this manufacturing method is used to manufacture a wide bandgap semiconductor trench MOSFET device structure, the beneficial effects of the wide bandgap semiconductor trench MOSFET device structure are also applicable to this manufacturing method. For its beneficial effects, please refer to the above description of the effects and will not be repeated here.

[0082] Throughout this specification, reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples, and features of different embodiments or examples, described in this specification, unless otherwise mutually incompatible.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide bandgap semiconductor trench MOSFET device structure, characterized in that: include: Substrate, first epitaxial layer, second epitaxial layer, P+ shielding layer, gate electrode and source P+ region; The first epitaxial layer and the second epitaxial layer are sequentially stacked and grown on the substrate; A plurality of gate electrodes are sequentially and spaced apart in the second epitaxial layer along the length direction of the device structure, and the bottom of any gate electrode is provided with the P+ shielding layer, and the P+ shielding layer is located in the second epitaxial layer; The source P+ region is spaced apart and penetrates the P+ shielding layer along the length direction of the gate electrode, and the P+ shielding layer and the P+ buried layer are electrically connected to the source P+ region; It also includes a P+ buried layer and a gate connection trench; The P+ buried layer is formed between the first epitaxial layer and the second epitaxial layer; An N+ current channel is provided in the P+ buried layer and the N+ current channel is located directly below the P+ shielding layer; The source P+ region is arranged in the middle area of the gate electrode along the length direction of the device structure, the bottom of the source P+ region is in contact with the P+ buried layer, and the sidewall of the source P+ region is in contact with the P+ shielding layer; The plurality of gate electrodes are connected through the gate connection groove, the source P+ region is wrapped in the gate connection groove, and the gate connection groove is used to assist source P+ ion implantation.

2. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: A plurality of source P+ regions are spaced apart and penetrate the gate electrode along a length direction of the gate electrode.

3. The wide bandgap semiconductor trench MOSFET device structure according to claim 2, characterized in that: The P+ shielding layer and the P+ Halo region / P+ Teeth region are provided at the bottom of the gate electrode, and the P+ Halo region / P+ Teeth region are provided on both sides of the P+ shielding layer.

4. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: A P-well region, a source N+ region, an ohmic contact region and a source electrode are sequentially formed on the second epitaxial layer from bottom to top.

5. The wide bandgap semiconductor trench MOSFET device structure according to claim 4, characterized in that: The gate electrode includes a gate trench, a gate dielectric layer and gate polysilicon; The gate trench is provided through the source N+ region, the P-well region and a portion of the second epitaxial layer; The gate dielectric layer is provided on the inner wall side of the gate trench, and the gate trench is filled with the gate polysilicon.

6. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode; The drain electrode is arranged at the bottom of the substrate.

7. A method for manufacturing a wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 6, characterized in that: include: epitaxially growing a first epitaxial layer, a P+ buried layer and a second epitaxial layer in sequence on a substrate; A P-well region is formed by ion implantation, secondary epitaxy, and growth of a P-type oxide, and then a source N+ region is formed on the P-well region by ion implantation; forming a source trench and a gate trench by dry etching; Forming a source P+ region by ion implantation; Forming a P+ masking layer by P-type ion implantation; Forming an N+ current channel by N-type ion implantation; The gate dielectric growth, gate polysilicon deposition and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, and drain metal deposition are sequentially performed to obtain the product.

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