Micro display chip, micro display module and manufacturing method thereof

Abstract

The present application relates to the field of display, and discloses a microdisplay chip, a microdisplay module, and a method for manufacturing the same. The microdisplay chip includes: a substrate, including a first surface and a second surface relative to each other; a driving circuit, including a plurality of driving units and a plurality of signal lines, wherein the plurality of signal lines extend into the substrate, the plurality of signal lines are electrically connected to the plurality of driving units, and at least one signal line includes at least one interface; a plurality of wiring structures, located on the first surface and / or the second surface; and a plurality of first pads, located on the side where the second surface of the substrate is located, and the first pads are electrically connected to the interfaces of the corresponding signal lines through the corresponding wiring structures. The above-mentioned microdisplay chip no longer needs to reserve a binding area, which facilitates the realization of a narrow frame design.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a micro display chip, a micro display module and a manufacturing method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) display modules are considered to be the most suitable display modules for application in the field of Augmented Reality (AR) due to their high stability and high brightness.

[0003] The micro-display chip of the existing micro-display module needs to reserve a binding area at the edge, and the binding area is arranged with pads for binding. The binding area will occupy the planar space of the micro-display chip and cannot meet the AR glasses' demand for a narrow frame of the micro-display module. Summary of the invention

[0004] The present application provides a micro display chip, a micro display module and a manufacturing method thereof, which can obtain a micro display module with a narrower frame.

[0005] In a first aspect, an embodiment of the present application provides a micro display chip, the micro display chip comprising: a substrate, comprising a first surface and a second surface opposite to each other; a driving circuit, comprising a plurality of driving units and a plurality of signal lines, the plurality of driving units being arranged in an array within the substrate, each of the driving units being used to drive a corresponding micro light-emitting diode to emit light, the plurality of signal lines extending within the substrate, the plurality of signal lines being electrically connected to the plurality of driving units, at least one of the signal lines comprising at least one interface; a plurality of wiring structures, located on the first surface and / or the second surface; and a plurality of first pads, located on the side of the second surface of the substrate, the first pads being electrically connected to the interfaces of the corresponding signal lines through the corresponding wiring structures.

[0006] According to the aforementioned implementation of the first aspect of the present application, the positions of the orthographic projections of the first pad and the interface electrically connected by the same wiring structure on the substrate do not overlap.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the at least one interface of the signal line includes a first interface, and the wiring structure includes a first wiring structure located on the first surface; the micro display chip also includes: a first interconnect structure extending from the first surface to the first interface and electrically connecting the first wiring structure to the first interface; a second interconnect structure extending through the substrate and electrically connecting the first wiring structure to the first pad.

[0008] According to any of the aforementioned implementations of the first aspect of the present application, the average value of the cross-sectional area of ​​the second interconnect structure is greater than the average value of the cross-sectional area of ​​the first interconnect structure.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the micro display chip also includes: a first passivation layer, located between the first wiring structure and the substrate, between the first interconnection structure and the substrate, and between the second interconnection structure and the substrate; a first protective layer, covering the first surface, the first protective layer covering the first wiring structure.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the at least one interface of the signal line includes a second interface, and the wiring structure includes a second wiring structure located on the second surface; the micro display chip also includes: a third interconnect structure extending from the second surface to the second interface and electrically connecting the second wiring structure to the second interface; a second passivation layer located between the second wiring structure and the substrate, and between the third interconnect structure and the substrate.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the micro display chip also includes: a second protective layer covering the second surface, the second protective layer covering the second wiring structure, and the first pad is located on a side of the second protective layer away from the substrate and electrically connected to the second wiring structure.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the at least one interface of the signal line includes a first interface and a second interface, the distance from the first interface to the first surface is smaller than the distance from the second interface to the first surface, and the wiring structure includes a first wiring structure located on the first surface and a second wiring structure located on the second surface, wherein the first interface of at least one of the signal lines is electrically connected to the first pad through the first wiring structure, and the second interface of at least one of the signal lines is electrically connected to the first pad through the second wiring structure.

[0013] According to any of the aforementioned implementations of the first aspect of the present application, the plurality of first pad arrays are arranged on the side where the second surface of the substrate is located.

[0014] In a second aspect, an embodiment of the present application provides a micro display module, comprising: a micro display chip according to any of the aforementioned embodiments of the first aspect of the present application; and a driving board, located on the side where the second surface of the substrate is located, and a plurality of second pads are provided on the driving board, wherein each of the first pads is bonded to a corresponding one of the second pads.

[0015] In a third aspect, an embodiment of the present application provides a method for manufacturing a micro display module, comprising: forming a driving circuit in a substrate to obtain a micro display chip, the substrate comprising a first surface and a second surface relative to each other, the driving circuit comprising a plurality of driving units and a plurality of signal lines, each of the driving units being used to drive a corresponding micro light-emitting diode to emit light, the plurality of signal lines being electrically connected to the plurality of driving units, and at least one of the signal lines comprising at least one interface; forming a plurality of wiring structures on the first surface and / or the second surface of the substrate, wherein the wiring structures are electrically connected to the interfaces of the corresponding signal lines; forming a plurality of first solder pads on the side where the second surface of the substrate is located, wherein the first solder pads are electrically connected to the corresponding wiring structures; bonding the first solder pads to the corresponding second solder pads on the driving board to obtain a micro display module.

[0016] According to the micro-display chip of the embodiment of the present application, the micro-display chip includes a substrate, a driving circuit, a plurality of wiring structures and a plurality of first pads, the wiring structure is located on the first surface and / or the second surface, the driving circuit includes a plurality of signal lines, and the first pad is electrically connected to the interface of the corresponding signal line through the corresponding wiring structure. Therefore, the interface of at least one signal line is rewired through the wiring structure and then led out to the first pad on the side where the second surface of the substrate is located, which improves the flexibility of the position of the first pad to a certain extent. The above-mentioned micro-display module no longer needs to reserve a binding area on the micro-display chip, thereby avoiding the position occupation of the binding area on the plane space of the micro-display chip, and facilitating the narrow frame design of the micro-display module. In the micro-display module of the above-mentioned embodiment of the present application, the first pad is used to bond and connect with the second pad at the corresponding position on the driving board, so as to realize the circuit structure connection between the micro-display chip and the driving board, and abandon the packaging method of the traditional micro-display module using a flexible circuit board to realize the electrical connection between the micro-display chip and the driving board. After the micro-display chip and the driving board are packaged, the spacing between the micro-display chip and the driving board is smaller, thereby reducing the delay of signal transmission and improving the display response speed of the micro-display module. The micro-display chip and the driver board can be packaged by surface mounting fixed connection, which improves the working stability of the micro-display module and the heat dissipation efficiency of the micro-display module. In addition, compared with the packaging method of realizing the electrical connection between the micro-display chip and the driver board through metal wire bonding, BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0018] Figure 1 A cross-sectional schematic diagram of an embodiment of a micro display module of the present application;

[0019] Figure 2 This is a bottom view of an embodiment of a micro display chip of the present application;

[0020] Figures 3 to 15 Schematic cross-sectional views of various stages of an embodiment of a method for manufacturing a micro display module of the present application.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0023] It should be noted that all directional indications in the embodiments of the present application, such as up, down, left, right, front, back, etc., are only used to explain the relative position relationship, movement, etc. between the components in a certain specific posture as shown in the accompanying drawings. If the specific posture changes, the directional indication will also change accordingly. When describing the structure of a component, when a layer or an area is referred to as being "above" or "above" another layer or another area, it may refer to being directly above another layer or another area, or containing other layers or areas between it and another layer or another area. Furthermore, if the component is turned over, the layer or the area will be "below" or "below" another layer or another area.

[0024] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that the combination of such technical solutions does not exist and is not within the scope of protection required by this application.

[0025] The embodiments of the present application provide a micro display chip and a micro display module. Figure 1 FIG. 1 is a cross-sectional view of an embodiment of a micro display module of the present application. The micro display module includes a micro display chip 100 and a driving board 200 .

[0026] The micro display wafer 100 includes a substrate 110 , a driving circuit 120 , a plurality of wiring structures 130 , and a plurality of first pads 140 .

[0027] The substrate 110 includes a first surface S1 and a second surface S2 opposite to each other. In some embodiments, the first surface S1 is the front surface of the substrate 110, ie, the surface for display, and the second surface S2 is the back surface of the substrate 110, ie, the surface opposite to the display surface.

[0028] The driving circuit 120 includes a plurality of driving units and a plurality of signal lines LN. The plurality of driving units are arrayed in the substrate 110, and each driving unit is used to drive a corresponding micro-light emitting diode (Micro-LED) to emit light. The plurality of signal lines LN extend in the substrate 110, and the plurality of signal lines LN are electrically connected to the plurality of driving units, and at least one signal line LN includes at least one interface 121.

[0029] Herein, the driving unit refers to a part of the circuit structure unit formed in the substrate 110, each of which corresponds to a light-emitting pixel, that is, corresponds to a micro-light-emitting diode, and is used to drive the light-emitting pixel to emit light. In some embodiments, the driving unit is a complementary metal oxide semiconductor (CMOS) driving unit, that is, the driving unit includes a CMOS transistor.

[0030] Herein, the plurality of signal lines LN are directly or indirectly electrically connected to the plurality of driving units, and are used to provide a plurality of signals to the driving circuit 120. In some embodiments, the plurality of signal lines LN include a plurality of signal lines LN that transmit different plurality of signals. For example, the plurality of signal lines LN include a clock signal line CLK, a first power supply voltage line VDD, a second power supply voltage line VSS, a plurality of data lines, etc. In some embodiments, the plurality of signal lines LN also include a reset line RESET, a test line TEST, etc.

[0031] A plurality of wiring structures 130 are located on the first surface S1 and / or the second surface S2 .

[0032] A plurality of first pads 140 are located on the side of the second surface S2 of the substrate 110. The first pads 140 are electrically connected to the interfaces 121 of the corresponding signal lines LN through the corresponding wiring structures 130.

[0033] The driving board 200 is located at the side where the second surface S2 of the substrate 110 is located, and a plurality of second pads 210 are disposed on the driving board 200 .

[0034] In this embodiment, each first pad 140 is bonded to a corresponding second pad 210 .

[0035] Herein, a "micro display chip" refers to a display component that uses micro light emitting diodes as light-emitting pixels, which may include a drive array substrate having a drive circuit. In some embodiments, the drive array substrate is formed on a silicon-based chip.

[0036] Herein, "micro" light emitting diodes and other "micro" devices refer to the size of light emitting diodes and devices. In some embodiments, the term "micro" refers to the size of the device at a scale of 1 micron to 100 microns. However, it is understood that the embodiments of the present application may not be limited thereto, and certain aspects of the embodiments may be applicable to larger or smaller sizes.

[0037] The first pad 140 may be formed of a conductive metal such as Ta, Ti, Cu, Au, Al, Ag, Cr, Ni, Pt, TaN, or TiN, or an alloy thereof, and may be a single layer or a stacked layer structure. In some embodiments, the diameter of the first pad 140 is 20 um to 80 um.

[0038] According to the micro display chip 100 and the micro display module of the embodiment of the present application, the micro display chip 100 includes a substrate 110, a driving circuit 120, a plurality of wiring structures 130 and a plurality of first pads 140, the wiring structure 130 is located on the first surface S1 and / or the second surface S2, the driving circuit 120 includes a plurality of signal lines LN, and the first pads 140 are electrically connected to the interfaces 121 of the corresponding signal lines LN through the corresponding wiring structures 130. Therefore, the interface 121 of at least one signal line LN is rewired through the wiring structure 130 and then led out to the first pad 140 on the side where the second surface S2 of the substrate 110 is located, which improves the flexibility of the position of the first pad 140 to a certain extent. The above-mentioned micro display module no longer needs to reserve a binding area on the micro display chip 100, thereby avoiding the position occupation of the binding area on the plane space of the micro display chip 100, facilitating the realization of the narrow frame design of the micro display module, facilitating the improvement of the screen ratio of the micro display module, and in addition, reducing the volume and weight of the micro display module. In the micro-display chip 100 and the micro-display module of the above-mentioned embodiment of the present application, the first pad 140 is used to bond and connect with the second pad 210 at the corresponding position on the driving board 200, which can realize the circuit structure connection between the micro-display chip 100 and the driving board 200, abandoning the packaging method of the traditional micro-display module using a flexible circuit board to realize the electrical connection between the micro-display chip 100 and the driving board 200. After the micro-display chip 100 and the driving board 200 are packaged, the distance between the micro-display chip 100 and the driving board 200 is smaller, thereby reducing the delay of signal transmission and improving the display response speed of the micro-display module. The micro-display chip 100 and the driving board 200 can be packaged by a surface mount fixed connection method, which improves the working stability of the micro-display module and also improves the heat dissipation efficiency of the micro-display module.

[0039] According to the micro display module of the embodiment of the present application, compared with the packaging method of realizing the electrical connection between the micro display chip 100 and the driving board 200 by metal wire bonding, the packaging method of the embodiment of the present application by bonding the first pad 140 and the second pad 210 can reduce the circuit loss of the electrical connection structure between the micro display chip 100 and the driving board 200, improve the conductive performance of the electrical connection structure, provide the possibility for the use scenario of high brightness by large current driving, and reduce the requirements for related process equipment that need to adopt die bonding and wire bonding processes.

[0040] In some embodiments, the interface 121 of the signal line LN is close to the first surface S1 of the substrate 110. In some embodiments, the interface 121 of the signal line LN is close to the second surface S2 of the substrate 110. In some embodiments, the signal line LN includes a single interface 121. In some embodiments, the signal line LN includes two, three, four, or other numbers of interfaces 121. In some embodiments, the signal line LN includes at least two interfaces 121, wherein at least one interface 121 is close to the first surface S1 of the substrate 110, and at least one interface 121 is close to the second surface S2 of the substrate 110. In some embodiments, the multiple interfaces 121 of the signal line LN are all close to the first surface S1 of the substrate 110 or are all close to the second surface S2 of the substrate 110.

[0041] In some embodiments, the orthographic projections of the first pad 140 and the interface 121 electrically connected by the same wiring structure 130 on the substrate 110 do not overlap, so that the wiring structure 130 is used to adjust the position of the actual electrical connection end of the signal line LN on the plane of the substrate 110.

[0042] In some embodiments, at least one interface 121 of the signal line LN includes a first interface 121a. The wiring structure 130 includes a first wiring structure 130a located on the first surface S1. In some embodiments, the first interface 121a is close to the first surface S1 of the substrate 110, that is, the distance between the first interface 121a and the first surface S1 is less than the distance between the first interface 121a and the second surface S2.

[0043] In some embodiments, the micro display wafer 100 further includes a first interconnect structure 151 and a second interconnect structure 152. The first interconnect structure 151 extends from the first surface S1 to the first interface 121a and electrically connects the first wiring structure 130a to the first interface 121a. The second interconnect structure 152 extends through the substrate 110 and electrically connects the first wiring structure 130a to the first pad 140.

[0044] The first interconnect structure 151 and the second interconnect structure 152 are conductive structures. In some embodiments, the first interconnect structure 151 and the second interconnect structure 152 are made of metal materials.

[0045] In some embodiments, the average cross-sectional area of ​​the second interconnect structure 152 is greater than the average cross-sectional area of ​​the first interconnect structure 151 , ensuring that the second interconnect structure 152 has good conductivity.

[0046] In some embodiments, the micro display wafer 100 further includes a first passivation layer 161 , which is located between the first wiring structure 130 a and the substrate 110 , between the first interconnect structure 151 and the substrate 110 , and between the second interconnect structure 152 and the substrate 110 .

[0047] In some embodiments, the first passivation layer 161 has a thickness of 20 nm to 350 nm. In this embodiment, the first passivation layer 161 is preferably a silicon oxide (SiOx) layer with a thickness of 150 nm. At this time, while achieving good insulation performance and relatively low film stress, the process is easier to implement. In some other embodiments, the material of the first passivation layer 161 can also be an insulating material such as silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0048] In some embodiments, the micro display wafer 100 further includes a first protection layer 171 . The first protection layer 171 covers the first surface S1 . The first protection layer 171 covers the first wiring structure 130 a .

[0049] The first protective layer 171 is formed of an insulating material, which can be an organic material. In some embodiments, the first protective layer 171 is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride. In this embodiment, the first protective layer 171 is formed of a silicon oxide material with a thickness of 40um to 400um. By providing the first protective layer 171, the first wiring structure 130a can be effectively protected.

[0050] In some embodiments, at least one interface 121 of the signal line LN includes a second interface 121b. The wiring structure 130 includes a second wiring structure 130b located on the second surface S2. In some embodiments, the second interface 121b is close to the second surface S2 of the substrate 110, that is, the distance between the second interface 121b and the second surface S2 is less than the distance between the second interface 121b and the first surface S1.

[0051] In some embodiments, the micro display wafer 100 further includes a third interconnect structure 153. The third interconnect structure 153 extends from the second surface S2 to the second interface 121b, and electrically connects the second wiring structure 130b with the second interface 121b.

[0052] The third interconnect structure 153 is a conductive structure. In some embodiments, the third interconnect structure 153 is a metal material.

[0053] In some embodiments, the micro display wafer 100 further includes a second passivation layer 162 located between the second wiring structure 130 b and the substrate 110 and between the third interconnect structure 153 and the substrate 110 .

[0054] The second passivation layer 162 has a thickness of 20 nm to 350 nm. In this embodiment, the second passivation layer 162 is preferably a silicon oxide layer with a thickness of 150 nm. At this time, while obtaining good insulation performance and relatively low film stress, the process is easier to implement. In some other embodiments, the material of the second passivation layer 162 can also be an insulating material such as silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0055] In some embodiments, the micro display chip 100 further includes a second protective layer 172 covering the second surface S2 and the second wiring structure 130b. The first pad 140 is located on a side of the second protective layer 172 away from the substrate 110 and is electrically connected to the second wiring structure 130b.

[0056] The first protection layer 171 is formed of an insulating material. In some embodiments, the second protection layer 172 is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride. By providing the second protection layer 172, the second wiring structure 130b can be effectively protected.

[0057] In some embodiments, at least one interface 121 of the signal line LN includes a first interface 121a and a second interface 121b, and the distance from the first interface 121a to the first surface S1 is less than the distance from the second interface 121b to the first surface S1. The wiring structure 130 includes a first wiring structure 130a located on the first surface S1 and a second wiring structure 130b located on the second surface S2. The first interface 121a of at least one signal line LN is electrically connected to the first pad 140 through the first wiring structure 130a, and the second interface 121b of at least one signal line LN is electrically connected to the first pad 140 through the second wiring structure 130b.

[0058] Figure 2 1 is a bottom view of an embodiment of the micro display chip of the present application. In some embodiments, a plurality of first pads 140 are arranged in an array on the side where the second surface S2 of the substrate 110 is located. The interfaces 121 of the plurality of signal lines LN are rewired through the wiring structure 130 and then led out to the first pads 140 on the side where the second surface S2 of the substrate 110 is located. The plurality of first pads 140 are arranged in an array, which facilitates the surface mounting process between the micro display chip 100 and the driving board 200.

[0059] The present application also provides a method for manufacturing a micro display module, which is, for example, the method for manufacturing a micro display module of some of the above embodiments. In this embodiment, the method for manufacturing a micro display module includes steps S110 to S140.

[0060] like Figure 3In step S110, a driving circuit 120 is formed in the substrate 110 to obtain a micro display chip 100. The substrate 110 includes a first surface S1 and a second surface S2 relative to each other. The driving circuit 120 includes a plurality of driving units and a plurality of signal lines LN. Each driving unit is used to drive a corresponding micro light-emitting diode to emit light. The plurality of signal lines LN are electrically connected to the plurality of driving units, and at least one signal line LN includes at least one interface 121.

[0061] In step S120 , a plurality of wiring structures 130 are formed on the first surface S1 and / or the second surface S2 of the substrate 110 , wherein each wiring structure 130 is electrically connected to the interface 121 of the corresponding signal line LN.

[0062] In some embodiments, the at least one interface 121 of the signal line LN includes a first interface 121 a. The step S120 of forming a plurality of wiring structures 130 on the first surface S1 and / or the second surface S2 of the substrate 110 may include the following steps.

[0063] like Figure 4 In step S121 , the substrate 110 is patterned on the first surface S1 to form a first via hole 111 connected from the first surface S1 to the first interface 121 a , and a second via hole 112 extending from the first surface S1 to the second surface S2 .

[0064] The patterned substrate 110 is formed, for example, by an etching process to form a first via 111 and a second via 112. The width of the first via 111 is 0.2um to 3um, and the aspect ratio of the first via 111 is 5 to 20, so as to ensure good conductivity and process reliability. The width of the second via 112 is 0.5um to 20um, the aspect ratio of the second via 112 is 10 to 50, and the depth of the second via 112 ranges from 20 um to 200um. The second via 112 is used to form a second interconnect structure 152 that penetrates the substrate 110, and therefore has a deeper depth than the first via 111. In some embodiments, the average width of the second via 112 is greater than the average width of the first via 111, so that the average value of the cross-sectional area of ​​the second interconnect structure 152 formed subsequently is greater than the average value of the cross-sectional area of ​​the first interconnect structure 151, ensuring that the second interconnect structure 152 has good conductivity.

[0065] In one example, the diameter of the first via 111 is 0.8um, and the etching depth of the first via 111 is 10um. In one example, the first interface 121a is overetched by about 0.3um at the first via 111 to facilitate better contact. In one example, the diameter of the second via 112 is 2um, and the etching depth of the second via 112 is 150um. In some embodiments, the second via 112 is located between adjacent signal lines LN.

[0066] The step S120 of forming a plurality of wiring structures 130 on the first surface S1 and / or the second surface S2 of the substrate 110 further includes steps S122 and S123 .

[0067] like Figure 5 In step S122 , a first passivation layer 161 is formed on the first surface S1 .

[0068] like Figure 6 In step S123 , the first passivation layer 161 is patterned so that the first interface 121 a is exposed in the first via hole 111 .

[0069] like Figure 7 Step S120 may include step S124, in which a first interconnect structure 151 electrically connected to the first interface 121a is formed in the first via 111, a second interconnect structure 152 is formed in the second via 112, and a patterned first wiring structure 130a is formed on the first surface S1, wherein the first wiring structure 130a is electrically connected to the first interconnect structure 151 and the second interconnect structure 152.

[0070] There are many ways to form the first interconnection structure 151, the second interconnection structure 152, and the first wiring structure 130a. For example, a first metal layer is formed on the first surface S1 by physical vapor deposition (PVD) or sputtering process or evaporation coating process. The first metal layer is Ta, Ti, Cu, Au, Al, Ag, Cr, Ni, Pt, TaN, or TiN, and its thickness is 0.5um to 50um. Preferably, the first metal layer is TaN3nm / Cr10nm / Cu1000nm / Al8000nm material. After the first metal layer is formed, the first metal layer is thinned by a thinning and polishing process to retain the first metal layer with a thickness of 2um to 5um, and then the first metal layer is patterned by an etching process to obtain the first interconnection structure 151, the second interconnection structure 152, and the first wiring structure 130a. In some embodiments, a lift-off process can also be used to form the patterned first interconnection structure 151, the second interconnection structure 152, and the first wiring structure 130a.

[0071] In some embodiments, after step S124, step S120 may further include step S125.

[0072] like Figure 8 In step S125 , a first protection layer 171 is formed on the first surface S1 to cover the first surface S1 and the first wiring structure 130 a .

[0073] The first protection layer 171 is formed by, for example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and the first protection layer 171 is, for example, a silicon oxide layer.

[0074] like Fig. 9 Step S120 may include step S126. In step S126, the substrate 110 is thinned from the second surface S2 so that the second interconnect structure 152 is exposed at the second surface S2.

[0075] In some embodiments, after the thinning process, the thickness of the substrate 110 is 80um to 150um. Preferably, after the thinning process, the thickness of the substrate 110 is 110um to 125um, which can ensure that the substrate 110 has sufficient strength to meet the subsequent process requirements.

[0076] In some embodiments, at least one interface 121 of the signal line LN further includes a second interface 121 b , and a distance from the first interface 121 a to the first surface S1 is smaller than a distance from the second interface 121 b to the first surface S1 .

[0077] In some embodiments, step S120 of forming a plurality of wiring structures 130 on the first surface S1 and / or the second surface S2 of the substrate 110 further includes steps S127 , S128 , and S129 .

[0078] like Fig.10 In step S127 , the substrate 110 is patterned on the second surface S2 to form a third via hole 113 connected from the second surface S2 to the second interface 121 b .

[0079] like Fig.11 In step S128 , a second passivation layer 162 is formed on the second surface S2 , and the second passivation layer 162 is patterned so that the second interface 121 b is exposed in the second via hole 112 .

[0080] like Fig.12 In step S129 , a third interconnect structure 153 electrically connected to the second interface 121 b is formed in the third via 113 , and a patterned second wiring structure 130 b is formed on the second surface S2 , wherein the second wiring structure 130 b is electrically connected to the third interconnect structure 153 .

[0081] There are many ways to form the third interconnect structure 153 and the second wiring structure 130b. For example, a second metal layer is formed on the second surface S2 by physical vapor deposition or sputtering process or evaporation coating process. The second metal layer is Ta, Ti, Cu, Au, Al, Ag, Cr, Ni, Pt, TaN, or TiN, and its thickness is 0.5um to 50um. Preferably, the second metal layer is TaN3nm / Cr10nm / Cu1000nm / Al8000nm material. After the second metal layer is formed, the second metal layer is thinned by a thinning and polishing process to retain a second metal layer with a thickness of 2um to 5um, and then the second metal layer is patterned by an etching process to obtain the third interconnect structure 153 and the second wiring structure 130b. In some embodiments, a lift-off process can also be used to form a patterned third interconnect structure 153 and a second wiring structure 130b.

[0082] In step S130 , a plurality of first pads 140 are formed on the side where the second surface S2 of the substrate 110 is located, wherein each first pad 140 is electrically connected to a corresponding wiring structure 130 .

[0083] In some embodiments, step S130 of forming a plurality of first pads 140 on the side where the second surface S2 of the substrate 110 is located includes steps S131 to S133 .

[0084] like Fig.13 In step S131 , a second protection layer 172 is formed on the second surface S2 to cover the second surface S2 and the second wiring structure 130 b .

[0085] In step S132 , the second protection layer 172 is patterned to form openings that expose a portion of the second wiring structure 130 b and the second interconnect structure 152 .

[0086] like Fig.14 In step S133 , a plurality of first pads 140 are formed on a side of the second protection layer 172 away from the substrate 110 , and each first pad 140 is electrically connected to the second wiring structure 130 b or to the second interconnect structure 152 .

[0087] There are many ways to form the first pad 140, for example, a third metal layer is formed on the side of the second protective layer 172 away from the substrate 110 by physical vapor deposition or sputtering process or evaporation coating process, and the third metal layer is Ta, Ti, Cu, Au, Al, Ag, Cr, Ni, Pt, TaN, or TiN, and its thickness is 5 um to 100 um. Exemplarily, the third metal layer is a 50 um thick Al material. After the third metal layer is formed, the third metal layer is thinned by a thinning and polishing process. Exemplarily, a 30 um thick third metal layer is retained, and then the third metal layer is patterned by an etching process to obtain the first pad 140. In some embodiments, a lift-off process can also be used to form a patterned first pad 140. The width of the first pad 140 is 30 um to 120 um. In one example, the width of the first pad 140 is 60 um.

[0088] like Fig.15 In step S140, the first pad 140 is bonded to the corresponding second pad 210 on the driving board 200 to obtain a micro display module.

[0089] In some embodiments, in order to improve the bonding efficiency, solder paste may be applied on the surface of the first pad 140 and / or the second pad 210 before bonding, thereby completing the bonding connection by using a reflow soldering process.

[0090] According to the manufacturing method of the micro display module of the embodiment of the present application, a plurality of wiring structures 130 are formed on the first surface S1 and / or the second surface S2 of the substrate 110, wherein the wiring structure 130 is electrically connected to the interface 121 of the corresponding signal line LN, and a plurality of first pads 140 are formed on the side where the second surface S2 of the substrate 110 is located, wherein each first pad 140 is electrically connected to the corresponding wiring structure 130, and the interface 121 of the signal line LN is rewired through the wiring structure 130 and then led out to the first pad 140 on the side where the second surface S2 of the substrate 110 is located, thereby improving the flexibility of the position of the first pad 140 to a certain extent. The micro display module obtained by the above manufacturing method no longer needs to reserve a binding area on the micro display chip 100, thereby avoiding the position occupation of the binding area on the plane space of the micro display chip 100, facilitating the realization of a narrow frame design of the micro display module, facilitating the improvement of the screen-to-body ratio of the micro display module, and further reducing the volume and weight of the micro display module. In the micro-display module manufacturing method of the above-mentioned embodiment of the present application, the first pad 140 is bonded to the second pad 210 at the corresponding position on the driving board 200, which can realize the circuit structure connection between the micro-display chip 100 and the driving board 200, abandoning the packaging method of the traditional micro-display module using a flexible circuit board to realize the electrical connection between the micro-display chip 100 and the driving board 200, and the spacing between the micro-display chip 100 and the driving board 200 is smaller, thereby reducing the delay of signal transmission and improving the display response speed of the micro-display module. The micro-display chip 100 and the driving board 200 can be packaged by a surface mount fixed connection method, which improves the working stability of the micro-display module and also improves the heat dissipation efficiency of the micro-display module. In addition, compared with the packaging method of electrically connecting the micro display chip 100 and the driving board 200 through metal wire bonding, the packaging method of the embodiment of the present application through bonding the first pad 140 and the second pad 210 can reduce the circuit loss of the electrical connection structure between the micro display chip 100 and the driving board 200, improve the conductive performance of the electrical connection structure, provide the possibility for high-brightness usage scenarios with large current driving, and reduce the requirements for related process equipment that need to adopt die bonding and wire bonding processes.

[0091] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made under the concept of the present application using the contents of the present application specification and drawings, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A micro display chip, characterized in that: include: a substrate comprising opposing first and second surfaces; A driving circuit, comprising a plurality of driving units and a plurality of signal lines, wherein the plurality of driving units are arranged in an array in the substrate, each of the driving units is used to drive a corresponding micro-LED to emit light, the plurality of signal lines extend in the substrate, the plurality of signal lines are electrically connected to the plurality of driving units, and at least one of the signal lines comprises at least one interface; A plurality of wiring structures, located on the first surface and / or the second surface; as well as A plurality of first pads are located on the side where the second surface of the substrate is located, and the first pads are electrically connected to the interfaces of the corresponding signal lines through the corresponding wiring structures; The at least one interface of the signal line includes a first interface, and the wiring structure includes a first wiring structure located on the first surface; The micro display chip also includes: a first interconnect structure extending from the first surface to the first interface and electrically connecting the first wiring structure to the first interface; The second interconnect structure extends through the substrate and electrically connects the first wiring structure with the first pad.

2. The micro display chip according to claim 1, characterized in that: The positions of the orthographic projections of the first pad and the interface electrically connected by the same wiring structure on the substrate do not overlap.

3. The micro display chip according to claim 1, characterized in that: An average value of the cross-sectional areas of the second interconnect structures is greater than an average value of the cross-sectional areas of the first interconnect structures.

4. The micro display chip according to claim 1, characterized in that: The micro display chip also includes: a first passivation layer, located between the first wiring structure and the substrate, between the first interconnect structure and the substrate, and between the second interconnect structure and the substrate; A first protective layer covers the first surface, and the first protective layer covers the first wiring structure.

5. The micro display chip according to claim 1, characterized in that: The at least one interface of the signal line includes a second interface, and the wiring structure includes a second wiring structure located on the second surface; The micro display chip also includes: a third interconnect structure extending from the second surface to the second interface and electrically connecting the second wiring structure to the second interface; The second passivation layer is located between the second wiring structure and the substrate and between the third interconnect structure and the substrate.

6. The micro display chip according to claim 5, characterized in that: The micro display chip also includes: A second protective layer covers the second surface, the second protective layer covers the second wiring structure, and the first pad is located on a side of the second protective layer away from the substrate and is electrically connected to the second wiring structure.

7. The micro display chip according to claim 1, characterized in that: The at least one interface of the signal line includes a first interface and a second interface, the distance from the first interface to the first surface is smaller than the distance from the second interface to the first surface, The wiring structure includes a first wiring structure located on the first surface and a second wiring structure located on the second surface. The first interface of at least one of the signal lines is electrically connected to the first pad through the first wiring structure, and the second interface of at least one of the signal lines is electrically connected to the first pad through the second wiring structure.

8. A micro display module, characterized in that: include: The micro display chip according to any one of claims 1 to 7; as well as a driving board, located on the side where the second surface of the substrate is located, and a plurality of second pads are provided on the driving board, Each of the first pads is bonded to a corresponding second pad.

9. A method for manufacturing a micro display module, characterized in that: include: A drive circuit is formed in a substrate to obtain a micro display chip, wherein the substrate comprises a first surface and a second surface opposite to each other, the drive circuit comprises a plurality of drive units and a plurality of signal lines, each of the drive units is used to drive a corresponding micro light emitting diode to emit light, the plurality of signal lines are electrically connected to the plurality of drive units, and at least one of the signal lines comprises at least one interface; forming a plurality of wiring structures on the first surface and / or the second surface of the substrate, wherein the wiring structures are electrically connected to interfaces of corresponding signal lines; forming a plurality of first pads on the side where the second surface of the substrate is located, wherein the first pads are electrically connected to the corresponding wiring structures; Bonding the first pad to a corresponding second pad on the driving board to obtain a micro display module; Wherein, the at least one interface of the signal line includes a first interface, the wiring structure includes a first wiring structure located on the first surface; and the micro display chip further includes: a first interconnect structure extending from the first surface to the first interface and electrically connecting the first wiring structure to the first interface; The second interconnect structure extends through the substrate and electrically connects the first wiring structure with the first pad.

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