Gate driving circuit and display panel

Abstract

Embodiments of the present disclosure relate to a gate driving circuit and a display panel, which can prevent a malfunction from occurring during a non-driving period when a scan signal line is not driven without causing any circuit problem, by including a scan output buffer including a scan pull-up transistor and a scan pull-down transistor and outputting a first scan signal, and a control circuit configured to control the scan output buffer and including a first transistor for charging a QB node and two or more transistors connected between a gate node of the first transistor and a low potential node to which a low potential voltage is applied.

Description

Gate driving circuit and display panel

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0158063, filed on November 23, 2022, which is incorporated herein by reference for all purposes as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to gate drive circuits and display panels. Background Technology

[0004] With the development of the information society, the demand for various forms of display devices for displaying images is increasing. In recent years, various display devices, such as liquid crystal displays and organic light-emitting diode displays, are being utilized.

[0005] The display device may include: a display panel with multiple data lines and multiple gate lines, a data driving circuit that outputs data signals to the multiple data lines, and a gate driving circuit that outputs scan signals to multiple scan signal lines.

[0006] For an image to be displayed correctly on a display device, proper operation of the gate drive circuit is absolutely necessary. However, if a problem occurs during the scanning operation (gate drive operation) through the gate drive circuit, image anomalies may occur and image quality may be significantly degraded. Summary of the Invention

[0007] Embodiments of this disclosure may provide a gate driving circuit and a display panel including an embedded gate driving circuit, the gate driving circuit including: an inverter circuit having a circuit structure capable of preventing faults without causing circuit problems during non-driving periods when the scan signal line is not driven.

[0008] Embodiments of this disclosure may provide a gate drive circuit and a display panel including an embedded gate drive circuit that prevents unwanted leakage current in transistors involved in the on-off control of QB node charging transistors.

[0009] The gate drive circuit according to an embodiment of the present disclosure may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel, and includes a scan pull-up transistor and a scan pull-down transistor; and a control circuit configured to control the scan output buffer.

[0010] The control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0011] The inverter circuit may include a first transistor that controls the connection between the high-potential node and the QB node, a second transistor that controls the connection between the QB node and the low-potential node, a third transistor that controls the connection between the high-potential node and the first control node, a fourth transistor that controls the connection between the second control node and the low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0012] In the inverter circuit, the gate node of the first transistor can be electrically connected to the first control node, the gate node of the second transistor can be electrically connected to the Q node, and the gate node of the fourth transistor is electrically connected to the Q node.

[0013] In the inverter circuit, the gate node of the third transistor can be electrically connected to a high-potential node, and the gate node of the fifth transistor can be electrically connected to the Q node or a node different from the Q node.

[0014] In this case, the inverter circuit may also include a control capacitor between the QB node and the second control node.

[0015] In the inverter circuit, the gate node of the fifth transistor can be electrically connected to a high-potential node, and the gate node of the third transistor can be electrically connected to a node different from the QB node or the high-potential node.

[0016] During the non-drive period when the first scan signal line is not driven, the first control node in the inverter circuit may have a voltage higher than the high potential voltage applied to the high potential node.

[0017] During non-driving periods, the second control node in the inverter circuit can have a voltage lower than the high potential.

[0018] During non-driving periods, the voltage difference between the drain and source nodes of the fourth transistor in the inverter circuit can be less than the voltage difference between the high potential voltage and the low potential voltage applied to the low potential node.

[0019] During the non-driving period when the first scan signal line is not driven, the QB node may have a voltage between the voltage of the first control node and the voltage of the second control node.

[0020] The display panel according to the embodiment may include a plurality of scan signal lines and a gate driving circuit that outputs a scan signal to each of the plurality of scan signal lines.

[0021] The gate drive circuit may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines, and includes a scan pull-up transistor and a scan pull-down transistor; and a control circuit configured to control the scan output buffer.

[0022] The control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0023] The inverter circuit may include a first transistor that controls the connection between the high-potential node and the QB node, a second transistor that controls the connection between the QB node and the low-potential node, a third transistor that controls the connection between the high-potential node and the first control node, a fourth transistor that controls the connection between the second control node and the low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0024] In the inverter circuit, the gate node of the first transistor can be electrically connected to the first control node. The gate node of the second transistor can be electrically connected to the Q node. The gate node of the fourth transistor can be electrically connected to the Q node.

[0025] In the inverter circuit, the gate node of the third transistor can be electrically connected to a high-potential node. The gate node of the fifth transistor can be electrically connected to the Q node or a node different from the Q node.

[0026] The inverter circuit may also include a control capacitor between the QB node and the second control node.

[0027] In the inverter circuit, the gate node of the fifth transistor can be electrically connected to a high-potential node, and the gate node of the third transistor can be electrically connected to a node different from the QB node or the high-potential node.

[0028] During the non-driving period when the first scan signal line is not driven, the first control node may have a voltage higher than the high potential voltage applied to the high potential node.

[0029] During the non-driving period when the first scan signal line is not driven, the second control node may have a voltage lower than the high potential voltage.

[0030] During the non-driving period when the first scan signal line is not driven, the voltage difference between the drain node and the source node of the fourth transistor can be less than the voltage difference between the high potential voltage and the low potential voltage.

[0031] During the non-driving period when the first scan signal line is not driven, the QB node may have a voltage between the voltage of the first control node and the voltage of the second control node.

[0032] The gate drive circuit according to an embodiment of the present disclosure may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel, and includes a scan pull-up transistor and a scan pull-down transistor; and a control circuit configured to control the scan output buffer.

[0033] In the gate drive circuit according to an embodiment of the present disclosure, the control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0034] In the gate drive circuit according to an embodiment of the present disclosure, the inverter circuit may include a first transistor for charging the QB node and two or more transistors connected between the gate node of the first transistor and a low-potential node to which a low-potential voltage is applied.

[0035] In the gate drive circuit according to an embodiment of the present disclosure, the inverter circuit may include a first transistor that controls the connection between a high-potential node and a QB node, a second transistor that controls the connection between a QB node and a low-potential node, a third transistor that controls the connection between a high-potential node and a first control node, a fourth transistor that controls the connection between a second control node and a low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0036] The two or more transistors connected between the gate node and the low-potential node of the first transistor may include a fourth transistor and a fifth transistor.

[0037] According to embodiments of the present disclosure, a gate driving circuit and a display panel including an embedded gate driving circuit can be provided. The gate driving circuit includes an inverter circuit having a circuit structure capable of preventing faults without causing circuit problems during non-driving periods when the scan signal line is not driven.

[0038] According to embodiments of this disclosure, a gate drive circuit and a display panel including an embedded gate drive circuit can be provided, the gate drive circuit being able to prevent unwanted leakage current in transistors involved in the on-off control of QB node charging transistors. Attached Figure Description

[0039] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0040] Figure 1 is a view schematically illustrating the system configuration of a display device according to an embodiment of the present disclosure;

[0041] Figures 2 and 3 are equivalent circuit diagrams illustrating sub-pixels of a display device according to embodiments of the present disclosure;

[0042] Figure 4 is a view illustrating an example system configuration of a display device according to an embodiment of the present disclosure;

[0043] Figure 5 is a view schematically illustrating a scan drive circuit included in a gate drive circuit according to an embodiment of the present disclosure;

[0044] Figure 6 is a block diagram illustrating a scan drive circuit included in a gate drive circuit according to an embodiment of the present disclosure;

[0045] Figure 7 is a detailed view illustrating the scan drive circuit included in a gate drive circuit according to an embodiment of the present disclosure;

[0046] Figure 8 is an operation timing diagram illustrating the scan drive circuit included in the gate drive circuit according to an embodiment of the present disclosure;

[0047] Figure 9 is another detailed view illustrating a scan drive circuit included in a gate drive circuit according to an embodiment of the present disclosure;

[0048] Figure 10 is another detailed view illustrating a scan drive circuit included in a gate drive circuit according to an embodiment of the present disclosure;

[0049] Figure 11 is an operation timing diagram showing the scan drive circuit of Figures 9 and 10;

[0050] Figure 12 shows the operating state of the inverter circuit included in the scan drive circuit of Figure 9 during the non-drive period;

[0051] Figure 13 shows the voltage states of the main nodes in the scan drive circuit of Figure 9;

[0052] Figure 14 illustrates the operating state of the inverter circuit included in the scan drive circuit of Figure 10 during the non-drive period; and

[0053] Figure 15 shows the voltage states of the main nodes in the scan drive circuit of Figure 10. Detailed Implementation

[0054] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by illustration, and wherein the same reference numerals or symbols may be used to designate the same or similar components, even if shown in drawings different from each other. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that the description would make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “forming,” and “form” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0055] This document may use terms such as “first,” “second,” “A,” “B,” “A,” or “B” to describe the elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0056] When referring to the first element as "connected or coupled to," "in contact with," or "overlapping" the second element, it should be interpreted as meaning that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlapping" the second element, but the third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0057] When using time-related terms such as “after,” “later,” “next,” or “before” to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless the terms “direct” or “immediate” are used together with them.

[0058] Furthermore, when referring to any size, relative size, etc., the numerical value or corresponding information of the element or feature (e.g., grade, range, etc.) should be considered, including the tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "may".

[0059] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a view schematically illustrating the system configuration of a display device 100 according to an embodiment of the present disclosure.

[0061] Referring to FIG1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110.

[0062] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130. The display device 100 may also include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

[0063] The display panel 110 may include a substrate SUB and signal lines, such as multiple data lines DL and multiple gate lines GL arranged on the substrate SUB. The display panel 110 may include multiple sub-pixels SP connected to the multiple data lines DL and the multiple gate lines GL.

[0064] The display panel 110 may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed. In the display panel 110, a plurality of sub-pixels SP for displaying the image may be arranged in the display area DA, and driving circuits 120, 130, and 140 may be electrically connected to or arranged in the non-display area NDA. Furthermore, pad units for connecting integrated circuits or printed circuits may be arranged in the non-display area NDA.

[0065] Data driver circuit 120 is used to drive multiple data lines DL and can provide data signals to the multiple data lines DL. Gate driver circuit 130 is used to drive multiple gate lines GL and can provide gate signals to the multiple gate lines GL. Controller 140 can provide data control signal DCS to data driver circuit 120 to control the operating timing of data driver circuit 120. Controller 140 can provide gate control signal GCS to gate driver circuit 130 to control the operating timing of gate driver circuit 130.

[0066] The controller 140 can initiate scanning according to the timing implemented in each frame, convert input image data from external input into image data Data suitable for the data signal format used in the data drive circuit 120, provide the image data Data to the data drive circuit 120, and control the data drive at an appropriate time suitable for scanning.

[0067] The controller 140 receives various timing signals (including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal DE, and clock signal) and input image data from external sources (e.g., host system 150).

[0068] In order to control the data drive circuit 120 and the gate drive circuit 130, the controller 140 receives timing signals such as the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, and the clock signal CLK, generates various control signals DCS and GCS, and outputs the control signals to the data drive circuit 120 and the gate drive circuit 130.

[0069] For example, in order to control the gate drive circuit 130, the controller 140 outputs various gate control signals GCS, including the gate start pulse GSP, the gate shift clock GSC, and the gate output enable signal (Gate Output Enable, GOE).

[0070] In order to control the data drive circuit 120, the controller 140 outputs various data control signals DCS, including, for example, the source start pulse SSP, the source sampling clock SSC, and the source output enable signal (source output enable, SOE).

[0071] The controller 140 can be implemented as a component separate from the data drive circuit 120, or the controller 140 and the data drive circuit 120 can be implemented as an integrated circuit.

[0072] The data drive circuit 120 receives image data Data from the controller 140 and provides data voltage to multiple data lines DL, thereby driving the multiple data lines DL. The data drive circuit 120 is also called the 'source drive circuit'.

[0073] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0074] Each source driver integrated circuit (SDIC) may include a shift register, latch circuitry, a digital-to-analog converter (DAC), and an output buffer. In some cases, each source driver integrated circuit (SDIC) may also include an analog-to-digital converter (ADC).

[0075] For example, each source driver integrated circuit (SDIC) can be connected to the display panel 110 via a tape auto-bonding (TAB) method, or to the bonding pad of the display panel 110 via a chip-on-glass (COG) or chip-on-panel (COP) method, or it can be implemented and connected to the display panel 110 via a chip-on-film (COF) method.

[0076] The gate drive circuit 130 can output a gate signal with an on-level voltage or a gate signal with an off-level voltage according to the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by sequentially providing gate signals with on-level voltages to multiple gate lines GL.

[0077] The gate driving circuit 130 can be connected to the display panel 110 via the TAB method, or to the bonding pads of the display panel 110 via the COG or COP method, or to the display panel 110 via the COF method. Alternatively, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110 as a gate in-panel (GIP) type. The gate driving circuit 130 can be disposed on the substrate SUB or can be connected to the substrate SUB. In other words, the GIP type gate driving circuit 130 can be disposed in the non-display area NDA of the substrate SUB. The chip-on-glass (COG) type or chip-on-film (COF) type gate driving circuit 130 can be connected to the substrate SUB.

[0078] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 can be arranged in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be arranged to not overlap with the sub-pixel SP or to overlap with all or some of the sub-pixels SP.

[0079] When a specific gate line GL is turned on by the gate drive circuit 130, the data drive circuit 120 can convert the image data Data received from the controller 140 into an analog data voltage and provide it to multiple data lines DL.

[0080] The data driving circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving scheme or panel design, the data driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or to two or more of the four sides of the display panel 110.

[0081] The gate drive circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving scheme or panel design, the gate drive circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or to two or more of the four sides of the display panel 110.

[0082] The controller 140 may be a timing controller used in typical display technologies, a control device capable of performing other control functions as well as the functions of a timing controller, or a control device other than a timing controller, or it may be a circuit in a control device. The controller 140 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0083] The controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via the printed circuit board or flexible printed circuit.

[0084] The controller 140 can send signals to / receive signals from the data drive circuit 120 according to one or more predetermined interfaces. These interfaces may include, for example, a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-to-Point (EPI) interface, and a Serial Peripheral Interface (SPI).

[0085] The controller 140 may include a storage medium, such as one or more registers.

[0086] The display device 100 according to embodiments of the present disclosure may be a display including a backlight unit (such as a liquid crystal display), or it may be a self-emitting display (such as an organic light-emitting diode (OLED) display, a quantum dot display, or a micro light-emitting diode (LED) display).

[0087] If the display device 100 according to an embodiment of the present disclosure is an OLED display, then each sub-pixel SP may include an organic light-emitting diode (OLED), which itself emits light as a light-emitting element. If the display device 100 according to an embodiment of the present disclosure is a quantum dot display, then each sub-pixel SP may include a light-emitting element formed of quantum dots, which are self-emissive semiconductor crystals. If the display device 100 according to an embodiment of the present disclosure is a micro-LED display, then each sub-pixel SP may include a micro-LED as a light-emitting element, which is self-emissive and formed of inorganic materials.

[0088] Figures 2 and 3 are equivalent circuit diagrams illustrating the sub-pixels SP of a display device 100 according to an embodiment of the present disclosure.

[0089] Referring to FIG2, each of a plurality of sub-pixels SP arranged on a display panel 110 of a display device 100 according to an embodiment of the present disclosure may include a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0090] Referring to Figure 2, the light-emitting element ED may include a pixel electrode PE and a common electrode CE, and may include a light-emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0091] The pixel electrode PE of the light-emitting element ED can be an electrode arranged in each sub-pixel SP, and the common electrode CE of the light-emitting element ED can be an electrode commonly arranged in all sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Conversely, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode. A base voltage EVSS, which is a type of common voltage used for display driving, can be applied to the common electrode CE of the light-emitting element ED.

[0092] For example, the light-emitting element ED can be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting element.

[0093] The driving transistor DRT is a transistor used to drive the light-emitting element ED, and may include a first node N1, a second node N2, and a third node N3.

[0094] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source node or drain node of the scanning transistor SCT.

[0095] The second node N2 of the driving transistor DRT can be the source node or the drain node of the driving transistor DRT, and can be electrically connected to the source node or the drain node of the sensing transistor SENT, and can also be electrically connected to the pixel electrode PE of the light-emitting element ED.

[0096] The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that provides the driving voltage EVDD, which is another type of common voltage used for display driving.

[0097] The scan transistor SCT can be controlled by a scan signal SC, which is a gate signal type, and can be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scan transistor SCT can be turned on or off according to the scan signal SC provided from the scan signal line SCL, controlling the connection between the data line DL and the first node N1 of the driving transistor DRT. Here, the scan signal line SCL can be a type of gate line GL, and the scan signal SC can be a type of gate signal.

[0098] The scanning transistor SCT can be turned on by the scanning signal SC with a turn-on voltage, and the data voltage Vdata provided from the data line DL is transmitted to the first node N1 of the driving transistor DRT.

[0099] If the scanning transistor SCT is an n-type transistor, the on-state voltage of the scanning signal SC can be a high-level voltage. If the scanning transistor SCT is a p-type transistor, the on-state voltage of the scanning signal SC can be a low-level voltage.

[0100] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0101] The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference between its two ends, and is used to maintain the voltage difference between its two ends for a predetermined frame time. Therefore, during the predetermined frame time, the corresponding sub-pixel SP can emit light.

[0102] Referring to FIG3, each of the plurality of sub-pixels SP arranged on the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include a sensing transistor SENT.

[0103] The sensing transistor SENT can be controlled by the sensing signal SE, which is of the gate signal type, and can be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL.

[0104] In other words, the connection between the reference voltage line RVL and the second node N2 of the drive transistor DRT can be controlled by turning the sensing transistor SENT on or off based on the sensing signal SE provided from the sensing signal line SENL, which is another type of gate line GL.

[0105] The sensing transistor SENT can be turned on by a sensing signal SE with a turn-on level voltage, and the reference voltage Vref provided from the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0106] The sensing transistor SENT can be turned on by a sensing signal SE with a conduction level voltage, transmitting the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0107] If the sensing transistor SENT is an n-type transistor, the on-state voltage of the sensing signal SE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-state voltage of the sensing signal SE can be a low-level voltage.

[0108] The function of the sensing transistor SENT in transmitting the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used to sense the feature value of the sub-pixel SP during driving. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage used to calculate the feature value of the sub-pixel SP or a voltage reflecting the feature value of the sub-pixel SP.

[0109] In this disclosure, the feature values ​​of the sub-pixel SP can be feature values ​​of the driving transistor DRT or the light-emitting element ED. The feature values ​​of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The feature values ​​of the light-emitting element ED can include the threshold voltage of the light-emitting element ED.

[0110] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In this disclosure, for ease of description, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is an n-type transistor.

[0111] The storage capacitor Cst is not a parasitic capacitor (such as Cgs or Cgd) that exists between the gate node and source node (or drain node) of the driving transistor DRT, but can be an external capacitor that is intentionally designed to be outside the driving transistor DRT.

[0112] The scan signal line SCL and the sensing signal line SENL can be different gate lines GL. In this case, the scan signal SC and the sensing signal SE can be separate gate signals, and the turn-on / off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be independent. In other words, the turn-on / off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be the same or different.

[0113] Alternatively, the scan signal line SCL and the sensing signal line SENL can be the same gate line GL. In other words, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in a sub-pixel SP can be connected to a single gate line GL. In this case, the scan signal SC and the sensing signal SE can be the same gate signal, and the turn-on / turn-off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be the same.

[0114] The structure of the subpixel SP shown in Figures 2 and 3 is merely an example and can be modified in various ways, such as by including one or more transistors or one or more capacitors.

[0115] Although the subpixel structure is described in conjunction with Figures 2 and 3 under the assumption that the display device 100 is a self-emitting display device, if the display device 100 is a liquid crystal display, each subpixel SP may include a transistor and a pixel electrode.

[0116] Figure 4 is a view showing an example system configuration of a display device 100 according to an embodiment of the present disclosure.

[0117] Referring to Figure 4, the display panel 110 may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed.

[0118] Referring to Figure 4, when the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented as a chip-on-film (COF) type, each source driver integrated circuit SDIC can be mounted on the circuit film SF connected to the non-display area NDA of the display panel 110.

[0119] Referring to Figure 4, the gate drive circuit 130 can be implemented as a gate in-panel (GIP) type. In this case, the gate drive circuit 130 can be formed in the gate drive circuit region GIPA included in the non-display area NDA of the display panel 110. Unlike Figure 4, the gate drive circuit 130 can be implemented as a chip on film (COF) type.

[0120] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between one or more source driver integrated circuits (SDICs) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0121] The source driver integrated circuit (SDIC) encapsulation film SF can be connected to at least one source printed circuit board (SPCB). In other words, one side of the source driver integrated circuit (SDIC) encapsulation film SF can be electrically connected to the display panel 110, and its opposite side can be electrically connected to the source printed circuit board (SPCB).

[0122] The controller 140 and the power management integrated circuit (PMIC) 410 can be mounted on a control printed circuit board (CPCB). The controller 140 can perform overall control functions related to driving the display panel 110, and can control the operation of the data drive circuit 120 and the gate drive circuit 130. The power management integrated circuit 410 can provide various voltages or currents to the data drive circuit 120 and the gate drive circuit 130, or can control the various voltages or currents provided to them.

[0123] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be connected via at least one connecting cable (CBL). Here, the connecting cable (CBL) can be, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC).

[0124] At least one source printed circuit board (SPCB) and control printed circuit board (CPCB) can be integrated into a single printed circuit board.

[0125] The display device 100 according to embodiments of the present disclosure may further include a level shifter 400 for adjusting voltage levels. For example, the level shifter 400 may be disposed on a control printed circuit board (CPCB) or a source printed circuit board (SPCB).

[0126] Specifically, in the display device 100 according to an embodiment of the present disclosure, the level shifter 400 can provide signals required for gate driving to the gate driving circuit 130. For example, the level shifter 400 can provide multiple clock signals to the gate driving circuit 130. Therefore, the gate driving circuit 130 can generate multiple gate signals (e.g., scan signal SC and sensing signal SE) based on the multiple clock signals input from the level shifter 400, and output them to multiple gate lines GL (e.g., scan signal line SCL and sensing signal line SENL). The multiple gate lines GL can transmit the multiple gate signals (e.g., scan signal SC and sensing signal SE) to the sub-pixels SP arranged in the display area DA of the substrate SUB.

[0127] Figure 5 is a schematic view of a scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure.

[0128] Referring to FIG5, the gate drive circuit 130 according to an embodiment of the present disclosure may include a plurality of scan drive circuits 500, the scan drive circuits 500 being configured to output a scan signal SC to each of a plurality of scan signal lines SCL arranged on the display panel 110.

[0129] Each of the multiple scan drive circuits 500 can be connected to one or more scan signal lines SCL. In other words, each of the multiple scan drive circuits 500 can output a scan signal SC to one or more scan signal lines SCL.

[0130] The scan drive circuit 500 shown in Figure 5 is the nth stage circuit used to provide the first scan signal SC(n) to the first scan signal line SCL(n) among multiple scan signal lines SCL.

[0131] Referring to FIG5, each of the plurality of scan drive circuits 500 included in the gate drive circuit 130 may include one or more scan output buffers 510 configured to output one or more scan signals SC and control circuitry 530 configured to control one or more scan output buffers 510.

[0132] Referring to Figure 5, the scan output buffer 510 can output the first scan signal SC(n) to the scan output node NOSCn, which is electrically connected to the first scan signal line SCL(n) among the multiple scan signal lines SCL arranged on the display panel 110.

[0133] For this purpose, the scan output buffer 510 may include a scan pull-up transistor Tu connected between the scan clock input node NCn and the scan output node NOSCn, and a scan pull-down transistor Td connected between the off-level voltage node NLV0 and the scan output node NOSCn.

[0134] The scan clock input node NCn can be electrically connected to the drain or source node of the scan pull-up transistor Tu. The first scan clock signal SCCLK(n) required to generate the first scan signal SC(n) can be input to the scan clock input node NCn.

[0135] The scan output node NOSCn can be electrically connected to the first scan signal line SCL(n). The scan output node NOSCn can be electrically connected to the source or drain node of the scan pull-up transistor Tu, and can also be electrically connected to the source or drain node of the scan pull-down transistor Td.

[0136] The off-level voltage node NLV0 can be electrically connected to the drain or source node of the scan pull-up transistor Tu or the scan pull-down transistor Td.

[0137] The shutdown level voltage NLV0 can be input to the shutdown level voltage node NLV0. The shutdown level voltage NLV0 can be a voltage that can turn off the scan transistor SCT.

[0138] Referring to Figure 5, the scan output buffer 510 may also include a scan capacitor Csc connected between the gate node and the source node (or drain node) of the scan pull-up transistor Tu.

[0139] Referring to Figure 5, the control circuit 530 can be configured to control the Q node electrically connected to the gate node of the scan pull-up transistor Tu and the QB node electrically connected to the gate node of the scan pull-down transistor Td.

[0140] The voltage states of the Q node and the QB node can be opposite. When the Q node is in a high voltage state (which can include two or more high voltage states), the QB node can be in a low voltage state. Conversely, when the Q node is in a low voltage state, the QB node can be in a high voltage state.

[0141] Referring to Figure 5, the scan output buffer 510 may further include a carry output buffer 520, which is configured to output the first carry signal C(n) to the carry output node NOCRn.

[0142] Therefore, the carry output buffer 520 may include a carry pull-up transistor Tuc and a carry pull-down transistor Tdc.

[0143] The carry pull-up transistor Tuc can be connected between the carry clock input node NCRn and the carry output node NOCRn.

[0144] The carry pull-down transistor Tdc can be connected between the low-potential node NLV1 and the carry output node NOCRn.

[0145] The carry clock input node NCRn can be electrically connected to the drain or source node of the carry pull-up transistor Tuc. The first carry clock signal CRCLK(n) required to generate the first carry signal C(n) can be input to the carry clock input node NCRn.

[0146] The carry output node NOCRn is the node to which the first carry signal C(n) is output, and it can be electrically connected to the source or drain node of the carry pull-up transistor Tuc, and it can also be electrically connected to the source or drain node of the carry pull-down transistor Tdc.

[0147] The low-potential node NLV1 can be electrically connected to either the drain or source node of the carry pull-down transistor Tdc. A low-potential voltage GVSS1 can be applied to the low-potential node NLV1.

[0148] Referring to Figure 5, the gate node of the carry pull-up transistor Tu can be electrically connected to the gate node of the scan pull-up transistor Tu. Therefore, the gate nodes of both the carry pull-up transistor Tu and the scan pull-up transistor Tu can be electrically connected to the Q node.

[0149] Therefore, the control circuit 530 can simultaneously control the on-off state of the carry pull-up transistor Tu and the on-off state of the scan pull-up transistor Tu.

[0150] The gate node of the carry pull-down transistor Tdc can be electrically connected to the gate node of the scan pull-down transistor Td. Therefore, the gate nodes of both the carry pull-down transistor Tdc and the scan pull-down transistor Td can be electrically connected to the QB node.

[0151] Therefore, the control circuit 530 can simultaneously control the on-off state of the carry pull-down transistor Tdc and the on-off state of the scan pull-down transistor Td.

[0152] When the gate drive circuit 130 is a gate in panel (GIP) type, the scan output buffer 510, carry output buffer 520 and control circuit 530 included in the scan drive circuit 500 in the gate drive circuit 130 can be circuits embedded in the display panel 110.

[0153] Figure 6 is a block diagram of a scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure.

[0154] Referring to FIG6, the scan drive circuit 500 included in the gate drive circuit 130 according to an embodiment of the present disclosure may include a scan output buffer 510 for outputting a first scan signal SC(n), a carry output buffer 520 for outputting a first carry signal C(n), and a control circuit 530.

[0155] Referring to Figure 6, the control circuit 530 can control the voltage state of the Q node and the voltage state of the QB node to control the scan output buffer 510 and the carry output buffer 520.

[0156] Referring to Figure 6, the control circuit 530 may include a Q-node charging circuit 610 configured to charge the Q-node, a Q-node discharging circuit 620 configured to discharge the Q-node, a QH-node control circuit 630 configured to control the QH-node (holding node), and a Q-node stabilizing circuit 640 configured to stabilize the voltage of the Q-node.

[0157] Referring to Figure 6, the control circuit 530 may also include an inverter circuit 600 for charging or discharging the QB node.

[0158] Referring to Figure 6, the Q-node charging circuit 610 can receive the second carry signal C(n-2) output from the scan drive circuit 500, which corresponds to the previous stage of the current stage.

[0159] Referring to Figure 6, the Q-node discharge circuit 620 can receive the third carry signal C(n+-2) output from the scan drive circuit 500 corresponding to the next level of the current level.

[0160] Referring to Figure 6, the QH node control circuit 630 and the inverter circuit 600 can be electrically connected to the high-potential node NHV to receive the high-potential voltage GVDD.

[0161] Referring to Figure 6, the Q-node discharge circuit 620, the Q-node stabilization circuit 640, and the inverter circuit 600 can be electrically connected to the low-potential node NLV1 to receive the low-potential voltage GVSS1.

[0162] Referring to Figure 6, the Q node can be electrically connected to the Q node charging circuit 610, the Q node discharging circuit 620, the QH node control circuit 630, the Q node stabilization circuit 640, and the inverter circuit 600.

[0163] Referring to Figure 6, the QB node can be electrically connected to the Q node stabilization circuit 640 and the inverter circuit 600.

[0164] Referring to Figure 6, the QH node can be electrically connected to the Q node charging circuit 610, the Q node discharging circuit 620, the QH node control circuit 630, and the Q node stabilization circuit 640.

[0165] In the following text, the Q-node charging circuit 610, Q-node discharging circuit 620, QH-node control circuit 630, Q-node stabilization circuit 640 and inverter circuit 600 included in the control circuit 530 will be described in more detail with reference to FIG7.

[0166] FIG7 is a detailed view of a scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure, and FIG8 is an operation timing diagram of the scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure.

[0167] Referring to Figure 7, the Q-node charging circuit 610 may include: a sixth transistor T6 for controlling the connection between the QH node and the previous carry signal input node NPCR to which the second carry signal C(n-2) preceding the first carry signal C(n) is input; and a seventh transistor T7 for controlling the connection between the QH node and the Q node.

[0168] The second carry signal C(n-2) before the first carry signal C(n) can be input together to the gate node of the sixth transistor T6 and the gate node of the seventh transistor T7.

[0169] Referring to Figure 7, the Q-node discharge circuit 620 may include an eighth transistor T8 for controlling the connection between the Q-node and the QH-node and a ninth transistor T9 for controlling the connection between the QH-node and the low-potential node NLV1.

[0170] The third carry signal C(n+2) following the first carry signal C(n) can be input together to the gate node of the eighth transistor T8 and the gate node of the ninth transistor T9.

[0171] Referring to Figure 7, the QH node control circuit 630 may include a tenth transistor T10 for controlling the connection between the high-potential node NHV and the QH node.

[0172] The gate node of the tenth transistor T10 can be electrically connected to the Q node.

[0173] Referring to Figure 7, the Q-node stabilization circuit 640 may include an eleventh transistor T11 for controlling the connection between the Q-node and the QH-node and a twelfth transistor T12 for controlling the connection between the QH-node and the low-potential node NLV1.

[0174] The gate node of the eleventh transistor T11 and the gate node of the twelfth transistor T12 can be electrically connected together to the QB node.

[0175] Referring to Figure 7, the inverter circuit 600 is a circuit for charging or discharging the QB node, and may include a main control node including a first control node NET1 and a second control node NET2.

[0176] Referring to Figure 7, the inverter circuit 600 may include a first transistor T1 for controlling the connection between the high-potential node NHV and the QB node, a second transistor T2 for controlling the connection between the QB node and the low-potential node NLV1, a third transistor T3 for controlling the connection between the high-potential node NHV and the first control node NET1, and a fourth transistor T4 for controlling the connection between the first control node NET1 and the low-potential node NLV1.

[0177] Referring to Figure 7, the inverter circuit 600 may include a first inverter circuit unit and a second inverter circuit unit. The first inverter circuit unit may include a third transistor T3 and a fourth transistor T4, and the second inverter circuit unit may include a first transistor T1 and a second transistor T2.

[0178] Referring to Figure 7, the gate node of the first transistor T1 can be electrically connected to the first control node NET1. The gate node of the second transistor T2 can be electrically connected to the Q node. The gate node of the fourth transistor T4 can be electrically connected to the Q node.

[0179] Referring to Figure 7, the inverter circuit 600 may also include an auxiliary transistor T2a, which is controlled to be turned on and off according to the second carry signal C(n-2) and controls the connection between the QB node and the low-potential node NLV1.

[0180] Referring to Figure 7, in the inverter circuit 600, the first transistor T1 can be a transistor used to charge the QB node, the second transistor T2 and the auxiliary transistor T2a can be transistors used to discharge the QB node, and the third and fourth transistors T3 and T4 can be transistors used to control the on / off state of the first transistor T1.

[0181] Referring to Figure 7, the second transistor T2 and the fourth transistor T4 can be turned on or off according to the voltage of the Q node, and the first transistor T1 can be turned on or off according to the on-off state of the fourth transistor T4.

[0182] Referring to Figures 7 and 8, in the inverter circuit 600, when the first control node NET1 becomes a voltage (high level voltage) that enables the first transistor T1 to conduct, the first transistor T1 can be turned on.

[0183] Therefore, the QB node can be charged by applying a high potential voltage GVDD to the QB node through the first transistor T1.

[0184] Referring to Figures 7 and 8, in the inverter circuit 600, when the voltage at the Q node becomes a high-level voltage that enables the second transistor T2 to conduct, the second transistor T2 can be turned on.

[0185] Therefore, the QB node can be discharged because a low potential voltage GVSS1 is applied to the QB node through the second transistor T2.

[0186] Referring to Figures 7 and 8, in the inverter circuit 600, when the auxiliary transistor T2a is turned on by the second carry signal C(n-2), the low potential voltage GVSS1 can be applied to the QB node through the auxiliary transistor T2a. Therefore, the QB node can be discharged.

[0187] Referring to Figures 7 and 8, the operation period of the scan drive circuit 500 may include a drive period Td in which the first scan signal line SCL(n) is driven and a non-drive period Tnd in which the first scan signal line SCL(n) is not driven.

[0188] Referring to Figures 7 and 8, during the driving period Td, the first scan signal SC(n) can have a conduction level voltage (high level voltage). Therefore, the Q node can have two high-level voltage states, the QB node can have a low-level voltage state, and the QH node can have a high-level voltage state. In other words, during the driving period Td, the Q node can be charged, the QB node can be discharged, and the QH node can be charged.

[0189] Referring to Figures 7 and 8, during the non-driving period Tnd, the first scan signal SC(n) can have a turn-off level voltage (low level voltage). Therefore, the Q node can have a low level voltage state, the QB node can have a high level voltage state, and the QH node can have a low level voltage state. In other words, during the non-driving period, the Q node can be discharged, the QB node can be charged, and the QH node can be discharged.

[0190] Referring to Figures 7 and 8, during the driving period Td, the second transistor T2 and the fourth transistor T4 can be turned on by the high-level voltage of the Q node.

[0191] Since the fourth transistor T4 is turned on during the drive period Td, the low-potential voltage GVSS1 can be applied to the first control node NET1 through the fourth transistor T4. Because the low-potential voltage GVSS1 is applied to the first control node NET1, the first transistor T1 can be turned off. Therefore, the connection between the high-potential node NHV and the QB node is broken, and the high-potential voltage GVDD is not applied to the QB node.

[0192] When the second transistor T2 is turned on during the drive period Td, the low potential voltage GVSS1 can be applied to the QB node through the second transistor T2.

[0193] By using the scan drive circuit 500 included in the gate drive circuit 130 according to the above embodiments of the present disclosure, the Q node and QB node can be precisely controlled, and thus precise scan drive operations can be performed to help enhance image quality.

[0194] Referring to Figures 7 and 8, during the non-driving period Tnd, the Q node can have a voltage (low level voltage) that enables the second transistor T2 and the fourth transistor T4 to be turned off, and the QB node can have a high level voltage.

[0195] Since the fourth transistor T4 is turned off during the non-driving period Tnd, the low potential voltage GVSS1 can be applied to the first control node NET1 without passing through the fourth transistor T4, and the first control node NET1 can be in a state where the high potential voltage GVDD is applied.

[0196] The first transistor T1 can be turned off by applying a high-potential voltage GVDD to the first control node NET1. Therefore, the high-potential node NHV and the QB node can be connected, and the high-potential voltage GVDD can be applied to the QB node.

[0197] During the non-driving period Tnd, the second transistor T2 can be turned off by the low-level voltage of the Q node, and the auxiliary transistor T2a can be turned off by the second carry signal C(n-2). Therefore, the QB node can remain in a high-level voltage state.

[0198] Referring to Figure 7, the parasitic capacitor Cgs can exist between the QB node and the first control node NET1. Here, the parasitic capacitor Cgs can be an internal capacitor existing between the gate node and the source node of the first transistor T1.

[0199] Because there is a parasitic capacitor Cgs between the QB node and the first control node NET1, voltage coupling may occur between the QB node and the first control node NET1.

[0200] During the non-drive period Tnd, the inverter circuit 600 can first apply a high-potential voltage GVDD to the first control node NET1, and then apply the high-potential voltage GVDD to the QB node.

[0201] Therefore, when a high-potential voltage GVDD is applied to the first control node NET1 during the non-driving period Tnd, and then applied to the QB node, the voltage of the first control node NET1 can increase from the high-potential voltage GVDD to a first voltage a (see Figure 8) due to the voltage coupling between the QB node and the first control node NET1. Here, the first voltage a can be a positive voltage value higher than 0 (zero).

[0202] Therefore, during the non-driving period Tnd, the first control node NET1 can have a voltage GVDD+a that is the high potential voltage GVDD plus the first voltage a, and thus the fourth transistor T4 can maintain a state in which the voltage difference Vds between the drain node and the source node is high (see Figure 8).

[0203] During the non-driving period Tnd, the voltage difference Vds between the drain node and source node of the fourth transistor T4 can be the difference between the voltage of the first control node NET1 and the low potential voltage GVSS1.

[0204] During the non-driving period Tnd, since the first control node NET1 has a voltage GVDD+a generated by increasing the high potential voltage GVDD by the first voltage a, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be the value GVDD-GVSS1+a obtained by adding the voltage difference GVDD-GVSS1 between the high potential voltage GVDD and the low potential voltage GVSS1 to the first voltage a.

[0205] For example, when the high potential voltage GVDD is 24V and the low potential voltage GVSS1 is -12V, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be (36+a)[V].

[0206] During the non-driving period Tnd, a low-level voltage is applied to the gate node of the fourth transistor T4, causing the fourth transistor T4 to be turned off.

[0207] However, during the non-driving period Tnd, since the fourth transistor T4, which should be turned off, keeps the voltage difference Vds between the drain node and the source node high, unwanted carrier current may be generated through the channel of the fourth transistor T4, and leakage current may be generated through the fourth transistor T4.

[0208] When leakage current occurs in the fourth transistor T4, a low-potential voltage GVSS1 can be applied to the first control node NET1. Therefore, the first transistor T1 is turned off, allowing the QB node to not maintain a high-level voltage state. Consequently, the scan drive circuit 500 may malfunction, leading to image abnormalities.

[0209] Meanwhile, all or some of the transistors in the scan drive circuit 500 included in the gate drive circuit 130 may be oxide semiconductor transistors.

[0210] When the fourth transistor T4 is an oxide semiconductor transistor, it is easier to generate a high Vds in the fourth transistor T4 during the non-drive period Tnd, and therefore, it is easier to generate leakage current in the fourth transistor T4.

[0211] However, even when the fourth transistor T4 is a transistor other than an oxide semiconductor transistor, a high Vds can be generated in the fourth transistor T4 during the non-drive period Tnd, and leakage current can be generated in the fourth transistor T4.

[0212] The following describes a scan drive circuit 500 for preventing leakage current in the fourth transistor T4 due to the high Vds of the fourth transistor T4 during the non-drive period Tnd.

[0213] Figure 9 is another detailed view of a scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure.

[0214] Apart from inverter circuits 600A and 600, the scan drive circuit 500 in Figure 9 and the scan drive circuit 500 in Figure 7 have the same configuration. Therefore, the description of the scan drive circuit 500 in Figure 9 focuses mainly on inverter circuit 600A.

[0215] Referring to Figure 9, the control circuit 530 may include a first control node NET1 and a second control node NET2, and may include an inverter circuit 600A for charging or discharging the QB node.

[0216] Referring to Figure 9, the inverter circuit 600A may include a first transistor T1 for controlling the connection between the high-potential node NHV and the QB node, a second transistor T2 for controlling the connection between the QB node and the low-potential node NLV1, a third transistor T3 for controlling the connection between the high-potential node NHV and the first control node NET1, a fourth transistor T4 for controlling the connection between the second control node NET2 and the low-potential node NLV1, and a fifth transistor T5 for controlling the connection between the first control node NET1 and the second control node NET2.

[0217] Referring to Figure 9, in the inverter circuit 600A, the gate node of the first transistor T1 can be electrically connected to the first control node NET1, the gate node of the second transistor T2 can be electrically connected to the Q node, and the gate node of the fourth transistor T4 can be electrically connected to the Q node.

[0218] Referring to Figure 9, in inverter circuit 600A, the gate node of the third transistor T3 can be electrically connected to the high-potential node NHV.

[0219] Referring to Figure 9, in inverter circuit 600A, the gate node of the fifth transistor T5 can be electrically connected to the Q node or a node different from the Q node. Here, the node different from the Q node can be the QH node, which has a voltage state similar to that of the Q node.

[0220] Referring to Figure 9, the inverter circuit 600A may also include a control capacitor Ca between the QB node and the second control node NET2.

[0221] FIG10 is another detailed view of a scan drive circuit 500 included in a gate drive circuit 130 according to an embodiment of the present disclosure.

[0222] Apart from inverter circuits 600B and 600, the scan drive circuit 500 in Figure 10 and the scan drive circuit 500 in Figure 7 have the same configuration. Therefore, the description of the scan drive circuit 500 in Figure 10 focuses mainly on inverter circuit 600B.

[0223] Referring to Figure 10, the control circuit 530 may include a first control node NET1 and a second control node NET2, and may include an inverter circuit 600B for charging or discharging the QB node.

[0224] Referring to Figure 10, the inverter circuit 600B may include a first transistor T1 for controlling the connection between the high-potential node NHV and the QB node, a second transistor T2 for controlling the connection between the QB node and the low-potential node NLV1, a third transistor T3 for controlling the connection between the high-potential node NHV and the first control node NET1, a fourth transistor T4 for controlling the connection between the second control node NET2 and the low-potential node NLV1, and a fifth transistor T5 for controlling the connection between the first control node NET1 and the second control node NET2.

[0225] Referring to Figure 10, in the inverter circuit 600B, the gate node of the first transistor T1 can be electrically connected to the first control node NET1, the gate node of the second transistor T2 can be electrically connected to the Q node, and the gate node of the fourth transistor T4 can be electrically connected to the Q node.

[0226] Referring to Figure 10, in inverter circuit 600B, the gate node of the fifth transistor T5 can be electrically connected to the high-potential node NHV.

[0227] Referring to Figure 10, in inverter circuit 600B, the gate node of the third transistor T3 can be electrically connected to a high-potential node NHV or a QB node different from the QB node. Here, if the scan drive circuit 500 in Figure 10 is the nth stage, the QB node different from the QB node can be the QB node in the (n-1)th stage scan drive circuit 500.

[0228] Figure 11 is the operation timing diagram of the scan drive circuit 500 in Figures 9 and 10.

[0229] Referring to Figure 11, during the non-driving period Tnd when the scan drive circuit 500 of the nth stage does not drive the first scan signal line SCL(n), the Q node and QH node can have a low-level voltage, and the QB node can have a high-level voltage. Here, the high-level voltage can be a high potential voltage GVDD, and the low-level voltage can be a low potential voltage GVSS1.

[0230] The non-driving period Tnd of the nth-stage scan drive circuit 500 not driving the first scan signal line SCL(n) can be the period when the first scan signal SC(n) output from the nth-stage scan drive circuit 500 has a turn-off level voltage (low level voltage).

[0231] Referring to Figure 11, during the non-driving period Tnd during which the first scan signal line SCL(n) is not driven, the QB node in the nth stage scan drive circuit 500 can have a high-level voltage period at a timing shifted from the high-level voltage period of the QB node QB[n-1] in the (n-1)th stage scan drive circuit 500 preceding the nth stage.

[0232] Referring to Figure 11, during the non-driving period Tnd during which the first scan signal line SCL(n) is not driven, the first control node NET1 may have a voltage GVDD+a that is higher than the high potential voltage GVDD applied to the high potential node NHV by a first voltage a.

[0233] Referring to Figure 11, during the non-driving period Tnd when the first scan signal line SCL(n) is not driven, the second control node NET2 can have a positive voltage GVDD-b that is lower than the high potential voltage GVDD by a second voltage b. Here, the second voltage b can be a positive voltage value higher than 0 (zero).

[0234] Referring to Figure 11, during the non-driving period Tnd when the first scan signal line SCL(n) is not driven, the voltage difference Vds between the drain and source nodes of the fourth transistor T4 can be a second voltage b smaller than the voltage difference GVDD-GVSS1 between the high potential voltage GVDD and the low potential voltage GVSS1 applied to the low potential node NLV1. Here, the second voltage b can be the voltage difference between the first control node NET1 and the second control node NET2.

[0235] Figure 12 shows the operating state of the inverter circuit 600A included in the scan drive circuit 500 of Figure 9 during the non-drive period Tnd, and Figure 13 is a simulation diagram showing the voltage states of the master nodes NET1, NET2 and QB in the scan drive circuit 500 of Figure 9.

[0236] Referring to Figure 12, the parasitic capacitor Cgs can exist between the QB node and the first control node NET1. Here, the parasitic capacitor Cgs can be an internal capacitor existing between the gate node and the source node of the first transistor T1.

[0237] Referring to Figure 12, since there is a parasitic capacitor Cgs between the QB node and the first control node NET1, voltage coupling can occur between the QB node and the first control node NET1.

[0238] Referring to Figures 12 and 13, during the non-drive period Tnd, in inverter circuit 600A, a high-potential voltage GVDD can first be applied to the first control node NET1, and then the high-potential voltage GVDD can be applied to the QB node.

[0239] Referring to Figures 12 and 13, when a high-potential voltage GVDD is applied to the first control node NET1 during the non-driving period Tnd, and then applied to the QB node, the voltage of the first control node NET1 can be GVDD+a, which is a voltage increased by a first voltage a from the high-potential voltage GVDD due to voltage coupling between the QB node and the first control node NET1. Here, the first voltage a can be a positive voltage value higher than 0 (zero).

[0240] Referring to Figures 12 and 13, the control capacitor Ca is connected between the second control node NET2 and the QB node. In other words, the second control node NET2 and the QB node are capacitively coupled.

[0241] Referring to Figures 12 and 13, during the non-driving period Tnd, the second control node NET2 can have a voltage GVDD-b that reduces the second voltage b from the high potential voltage GVDD.

[0242] Referring to Figures 12 and 13, during the non-driving period Tnd, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be the difference between the voltage of the second control node NET2 and the low potential voltage GVSS1.

[0243] During the non-driving period Tnd, the voltage of the second control node NET2 can be reduced from the voltage of the first control node NET1 by the voltage of the second voltage b, NET1-b, through the fifth transistor T5.

[0244] Therefore, referring to Figures 12 and 13, during the non-driving period Tnd, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be obtained by subtracting the second voltage b from the voltage difference (GVDD-GVSS1) between the high potential voltage GVDD and the low potential voltage GVSS1 (Vds = (voltage of NET2) – GVSS1 = (GVDD – b) – GVSS1 = (GVDD – GVSS1) – b).

[0245] Referring to Figures 12 and 13, during the non-driving period Tnd, the voltage difference Vds = GVDD - GVSS1 - b between the drain and source nodes of the fourth transistor T4 in the scan drive circuit 500 of Figure 9 is lower than the voltage difference Vds = GVDD - GVSS1 + a between the drain and source nodes of the fourth transistor T4 in the scan drive circuit 500 of Figure 7.

[0246] For example, when the high potential voltage GVDD is 24V and the low potential voltage GVSS1 is -12V, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be (36-b)[V].

[0247] Referring to Figure 13, during the non-driving period Tnd, the voltage GVDD+a of the first control node NET1 can be a first voltage a higher than the voltage GVDD of the QB node, and the voltage GVDD-b of the second control node NET2 can be a second voltage b lower than the voltage GVDD of the QB node. In other words, during the non-driving period Tnd, the QB node can have a voltage between the voltage of the first control node NET1 and the voltage of the second control node NET2.

[0248] Figure 14 shows the operating state of the inverter circuit 600B included in the scan drive circuit 500 of Figure 10 during the non-drive period Tnd, and Figure 15 is a simulation diagram showing the voltage states of the master nodes NET1, NET2 and QB in the scan drive circuit 500 of Figure 10.

[0249] Referring to Figure 14, the parasitic capacitor Cgs can exist between the QB node and the first control node NET1. Here, the parasitic capacitor Cgs can be an internal capacitor existing between the gate node and the source node of the first transistor T1.

[0250] Referring to Figure 14, since there is a parasitic capacitor Cgs between the QB node and the first control node NET1, voltage coupling can occur between the QB node and the first control node NET1.

[0251] Referring to Figures 14 and 15, during the non-drive period Tnd, in the inverter circuit 600B, the high potential voltage GVDD can first be applied to the first control node NET1, and then the high potential voltage GVDD can be applied to the QB node.

[0252] Referring to Figures 14 and 15, when a high-potential voltage GVDD is applied to the first control node NET1 during the non-driving period Tnd, and then applied to the QB node, the voltage of the first control node NET1 can be GVDD+a, which is a voltage that increases from the high-potential voltage GVDD to a first voltage a through voltage coupling between the QB node and the first control node NET1. Here, the first voltage a can be a positive voltage value higher than 0 (zero).

[0253] Referring to Figures 14 and 15, during the non-driving period Tnd, the second control node NET2 can have a voltage GVDD-b that decreases from the high potential voltage GVDD to the second voltage b.

[0254] Referring to Figures 14 and 15, during the non-driving period Tnd, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be the voltage difference between the second control node NET2 and the low potential voltage GVSS1.

[0255] During the non-driving period Tnd, the voltage of the second control node NET2 can be reduced from the voltage of the first control node NET1 by the voltage of the second voltage b, NET1-b, through the fifth transistor T5.

[0256] Therefore, referring to Figures 14 and 15, during the non-driving period Tnd, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be obtained by subtracting the second voltage b from the voltage difference (GVDD-GVSS1) between the high potential voltage GVDD and the low potential voltage GVSS1 (GVDD-GVSS1) - b (Vds = (voltage of NET2) – GVSS1 = (GVDD – b) – GVSS1 = (GVDD – GVSS1) - b).

[0257] Referring to Figures 14 and 15, during the non-driving period Tnd, the voltage difference Vds = GVDD - GVSS1 - b between the drain and source nodes of the fourth transistor T4 in the scan drive circuit 500 of Figure 9 is lower than the voltage difference Vds = GVDD - GVSS1 + a between the drain and source nodes of the fourth transistor T4 in the scan drive circuit 500 of Figure 7.

[0258] For example, when the high potential voltage GVDD is 24V and the low potential voltage GVSS1 is -12V, the voltage difference Vds between the drain node and the source node of the fourth transistor T4 can be (36-b)[V].

[0259] Referring to Figure 15, during the non-driving period Tnd, the voltage GVDD+a of the first control node NET1 can be a first voltage a higher than the voltage GVDD of the QB node, and the voltage GVDD-b of the second control node NET2 can be a second voltage b lower than the voltage GVDD of the QB node. In other words, during the non-driving period Tnd, the QB node can have a voltage between the voltage of the first control node NET1 and the voltage of the second control node NET2.

[0260] In the inverter circuit 600B of Figure 14, the first voltage a may be the same as or different from the first voltage a in the inverter circuit 600A of Figure 12.

[0261] In the inverter circuit 600B of Figure 14, the second voltage b may be the same as or different from the second voltage b in the inverter circuit 600A of Figure 12.

[0262] The inverter circuit 600B in Figure 14 does not include the control capacitor Ca included in the inverter circuit 600A in Figure 12.

[0263] In the inverter circuit 600B of Figure 14, the second voltage b can be lower than the second voltage b in the inverter circuit 600A of Figure 12. Therefore, during the non-drive period Tnd, the voltage of the second control node NET2 in the inverter circuit 600B of Figure 14 can be higher than the voltage of the second control node NET2 in the inverter circuit 600A of Figure 12.

[0264] The above embodiments are briefly described below.

[0265] A gate drive circuit may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel and includes a scan pull-up transistor connected between a scan clock input node and a scan output node and a scan pull-down transistor connected between a turn-off level voltage node and a scan output node; and a control circuit configured to control a Q node electrically connected to the gate node of the scan pull-up transistor and a QB node electrically connected to the gate node of the scan pull-down transistor.

[0266] The control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0267] The inverter circuit may include a first transistor that controls the connection between the high-potential node and the QB node, a second transistor that controls the connection between the QB node and the low-potential node, a third transistor that controls the connection between the high-potential node and the first control node, a fourth transistor that controls the connection between the second control node and the low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0268] In the inverter circuit, the gate node of the first transistor can be electrically connected to the first control node, the gate node of the second transistor can be electrically connected to the Q node, and the gate node of the fourth transistor is electrically connected to the Q node.

[0269] In the inverter circuit, the gate node of the third transistor can be electrically connected to a high-potential node, and the gate node of the fifth transistor can be electrically connected to the Q node or a node different from the Q node.

[0270] In this case, the inverter circuit may also include a control capacitor between the QB node and the second control node.

[0271] In the inverter circuit, the gate node of the fifth transistor can be electrically connected to a high-potential node, and the gate node of the third transistor can be electrically connected to a node different from the QB node or the high-potential node.

[0272] During the non-drive period when the first scan signal line is not driven, the first control node in the inverter circuit may have a voltage higher than the high potential voltage applied to the high potential node.

[0273] During non-driving periods, the second control node in the inverter circuit can have a voltage lower than the high potential.

[0274] During non-driving periods, the voltage difference between the drain and source nodes of the fourth transistor in the inverter circuit can be less than the voltage difference between the high potential voltage and the low potential voltage applied to the low potential node.

[0275] During the non-driving period when the first scan signal line is not driven, the QB node may have a voltage between the voltage of the first control node and the voltage of the second control node.

[0276] The gate drive circuit according to an embodiment of the present disclosure may further include: a carry output buffer, including a carry pull-up transistor that outputs a first carry signal to the carry output node and is connected between the carry clock input node and the carry output node, and a carry pull-down transistor connected between the low-potential node and the carry output node; a Q-node charging circuit, including a sixth transistor that controls the connection between the QH node and the previous carry signal input node that receives the second carry signal before the first carry signal, and a seventh transistor that controls the connection between the QH node and the Q node; and a Q-node discharging circuit, including an eighth transistor that controls the connection between the Q node and the QH node, and a ninth transistor that controls the connection between the QH node and the low-potential node.

[0277] The second carry signal preceding the first carry signal can be input together to the gate node of the sixth transistor and the gate node of the seventh transistor.

[0278] The third carry signal following the first carry signal can be input together to the gate node of the eighth transistor and the gate node of the ninth transistor.

[0279] The gate drive circuit according to an embodiment of the present disclosure may further include: a QH node control circuit, including a tenth transistor that controls the connection between the high-potential node and the QH node; and a Q node stabilization circuit, including an eleventh transistor that controls the connection between the Q node and the QH node and a twelfth transistor that controls the connection between the QH node and the low-potential node.

[0280] The gate node of the tenth transistor can be electrically connected to the Q node, and the gate nodes of the eleventh and twelfth transistors are jointly electrically connected to the QB node.

[0281] The inverter circuit may also include an auxiliary transistor, which is controlled to be turned on or off according to a second carry signal and controls the connection between the QB node and the low-potential node.

[0282] The fourth transistor can be an oxide semiconductor transistor.

[0283] The display panel according to the embodiment may include a plurality of scan signal lines and a gate driving circuit that outputs a scan signal to each of the plurality of scan signal lines.

[0284] The gate drive circuit may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines, and includes a scan pull-up transistor connected between a scan clock input node and a scan pull-down transistor connected between a turn-off level voltage node and a scan output node; and a control circuit configured to control a Q node electrically connected to the gate node of the scan pull-up transistor and a QB node electrically connected to the gate node of the scan pull-down transistor.

[0285] The control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0286] The inverter circuit may include a first transistor that controls the connection between the high-potential node and the QB node, a second transistor that controls the connection between the QB node and the low-potential node, a third transistor that controls the connection between the high-potential node and the first control node, a fourth transistor that controls the connection between the second control node and the low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0287] In the inverter circuit, the gate node of the first transistor can be electrically connected to the first control node. The gate node of the second transistor can be electrically connected to the Q node. The gate node of the fourth transistor can be electrically connected to the Q node.

[0288] In the inverter circuit, the gate node of the third transistor can be electrically connected to a high-potential node. The gate node of the fifth transistor can be electrically connected to the Q node or a node different from the Q node.

[0289] The inverter circuit may also include a control capacitor between the QB node and the second control node.

[0290] In the inverter circuit, the gate node of the fifth transistor can be electrically connected to a high-potential node, and the gate node of the third transistor can be electrically connected to a node different from the QB node or the high-potential node.

[0291] During the non-driving period when the first scan signal line is not driven, the first control node may have a voltage higher than the high potential voltage applied to the high potential node.

[0292] During the non-drive period when the first scan signal line is not driven, the second control node may have a voltage lower than the high potential voltage.

[0293] During the non-driving period when the first scan signal line is not driven, the voltage difference between the drain node and the source node of the fourth transistor can be less than the voltage difference between the high potential voltage and the low potential voltage.

[0294] During the non-driving period when the first scan signal line is not driven, the QB node may have a voltage between the voltage of the first control node and the voltage of the second control node.

[0295] The gate drive circuit according to an embodiment of the present disclosure may include: a scan output buffer that outputs a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel, and includes a scan pull-up transistor and a scan pull-down transistor; and a control circuit configured to control the scan output buffer.

[0296] In the gate drive circuit according to an embodiment of the present disclosure, the control circuit may include a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node.

[0297] In the gate drive circuit according to an embodiment of the present disclosure, the inverter circuit may include a first transistor for charging the QB node and two or more transistors connected between the gate node of the first transistor and a low-potential node to which a low-potential voltage is applied.

[0298] In the gate drive circuit according to an embodiment of the present disclosure, the inverter circuit may include a first transistor that controls the connection between a high-potential node and a QB node, a second transistor that controls the connection between a QB node and a low-potential node, a third transistor that controls the connection between a high-potential node and a first control node, a fourth transistor that controls the connection between a second control node and a low-potential node, and a fifth transistor that controls the connection between the first control node and the second control node.

[0299] The two or more transistors connected between the gate node and the low-potential node of the first transistor may include a fourth transistor and a fifth transistor.

[0300] According to the embodiments of the present disclosure described above, a gate driving circuit and a display panel including an embedded gate driving circuit can be provided. The gate driving circuit includes an inverter circuit having a circuit structure that can prevent faults without causing circuit problems during non-driving periods when the scan signal line is not driven.

[0301] According to embodiments of this disclosure, a gate drive circuit and a display panel including an embedded gate drive circuit can be provided, the gate drive circuit being able to prevent unwanted leakage current in transistors involved in the on-off control of QB node charging transistors.

[0302] The above description is provided to enable those skilled in the art to implement and use the technical ideas of this disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The examples of the technical ideas of this disclosure provided in the above description and accompanying drawings are for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure.

Claims

1. A gate driving circuit, comprising: A scan output buffer is configured to output a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel, and includes a scan pull-up transistor and a scan pull-down transistor. The system also includes a control circuit configured to control the scan output buffer, wherein the control circuit includes a first control node and a second control node, and includes an inverter circuit configured to charge or discharge the QB node, wherein the inverter circuit includes: a first transistor configured to control the connection between the high-potential node and the QB node; a second transistor configured to control the connection between the QB node and a low-potential node; a third transistor configured to control the connection between the high-potential node and the first control node; a fourth transistor configured to control the connection between the second control node and the low-potential node; and a fifth transistor configured to control the connection between the first control node and the second control node, wherein the gate node of the first transistor is electrically connected to the first control node, the gate node of the second transistor is electrically connected to the Q node, and the gate node of the fourth transistor is electrically connected to the Q node; and wherein the low-potential node connected to the second transistor and the low-potential node connected to the fourth transistor are disposed on the same line to which a low-potential voltage is applied.

2. The gate driving circuit according to claim 1, wherein, The gate node of the third transistor is electrically connected to the high-potential node, and the gate node of the fifth transistor is electrically connected to the Q node or a node different from the Q node.

3. The gate driving circuit according to claim 1, wherein, The inverter circuit also includes a control capacitor between the QB node and the second control node.

4. The gate driving circuit according to claim 1, wherein, The gate node of the fifth transistor is electrically connected to the high-potential node, and the gate node of the third transistor is electrically connected to a node different from the QB node or the high-potential node.

5. The gate driving circuit according to claim 1, wherein, During the non-driving period when the first scan signal line is not driven, the first control node has a voltage higher than the high potential voltage applied to the high potential node.

6. The gate driving circuit according to claim 5, wherein, During the non-driving period, the second control node has a voltage lower than the high potential voltage.

7. The gate driving circuit according to claim 6, wherein, During the non-driving period, the voltage difference between the drain node and the source node of the fourth transistor is less than the voltage difference between the high potential voltage and the low potential voltage applied to the low potential node.

8. The gate driving circuit according to claim 1, wherein, During the non-driving period when the first scan signal line is not driven, the QB node has a voltage between the voltage of the first control node and the voltage of the second control node.

9. The gate driving circuit according to claim 1, further comprising: A carry-out buffer includes: a carry-up transistor configured to output a first carry signal to a carry-out node and connected between a carry clock input node and the carry-out node; and a carry-down transistor connected between a low-level node and the carry-out node; a Q-node charging circuit including: a sixth transistor configured to control the connection between a QH node and a previous carry signal input node that receives a second carry signal preceding the first carry signal; and a seventh transistor configured to control the connection between the QH node and the Q node; and a Q-node discharging circuit including: an eighth transistor configured to control the connection between the Q node and the QH node; and a ninth transistor configured to control the connection between the QH node and the low-level node, wherein the second carry signal preceding the first carry signal is commonly input to the gate node of the sixth transistor and the gate node of the seventh transistor, and the third carry signal following the first carry signal is commonly input to the gate node of the eighth transistor and the gate node of the ninth transistor.

10. The gate driving circuit according to claim 9, further comprising: QH node control circuitry includes a tenth transistor configured to control the connection between the high-potential node and the QH node; The circuit includes a Q-node stabilization circuit comprising: an eleventh transistor configured to control the connection between the Q-node and the QH-node; and a twelfth transistor configured to control the connection between the QH-node and the low-potential node, wherein the gate node of the tenth transistor is electrically connected to the Q-node, and the gate nodes of the eleventh transistor and the twelfth transistor are jointly electrically connected to the QB-node.

11. The gate driving circuit according to claim 9, wherein, The inverter circuit also includes an auxiliary transistor, which is controlled to be turned on or off according to the second carry signal, and controls the connection between the QB node and the low-potential node.

12. The gate driving circuit according to claim 1, wherein, The fourth transistor is an oxide semiconductor transistor.

13. A display panel, comprising: Multiple scan signal lines; The system includes a gate drive circuit configured to output a scan signal to each of the plurality of scan signal lines. The gate drive circuit includes a scan output buffer configured to output a first scan signal to a scan output node electrically connected to a first scan signal line among the plurality of scan signal lines, and includes a scan pull-up transistor and a scan pull-down transistor. A control circuit configured to control the scan output buffer includes a first control node and a second control node, and includes an inverter circuit configured to charge or discharge a QB node. The inverter circuit includes a first transistor configured to control the connection between a high-potential node and the QB node; and a second transistor configured to... The system comprises: a third transistor configured to control the connection between the QB node and the low-potential node; a fourth transistor configured to control the connection between the high-potential node and the first control node; a fifth transistor configured to control the connection between the first control node and the second control node; wherein the gate node of the first transistor is electrically connected to the first control node, the gate node of the second transistor is electrically connected to the Q node, and the gate node of the fourth transistor is electrically connected to the Q node; and wherein the low-potential node connected to the second transistor and the low-potential node connected to the fourth transistor are disposed on the same line to which a low-potential voltage is applied.

14. The display panel according to claim 13, wherein, The gate node of the third transistor is electrically connected to the high-potential node, and the gate node of the fifth transistor is electrically connected to the Q node or a node different from the Q node.

15. The display panel according to claim 13, wherein, The inverter circuit also includes a control capacitor between the QB node and the second control node.

16. The display panel according to claim 13, wherein, The gate node of the fifth transistor is electrically connected to the high-potential node, and the gate node of the third transistor is electrically connected to a QB node different from the QB node or the high-potential node.

17. The display panel according to claim 13, wherein, During the non-driving period when the first scan signal line is not driven, the first control node has a voltage higher than the high potential voltage applied to the high potential node.

18. The display panel according to claim 17, wherein, During the non-driving period when the first scan signal line is not driven, the second control node has a voltage lower than the high potential voltage.

19. The display panel according to claim 18, wherein, During the non-driving period when the first scan signal line is not driven, the voltage difference between the drain node and the source node of the fourth transistor is less than the voltage difference between the high potential voltage and the low potential voltage.

20. A gate driving circuit, comprising: A scan output buffer is configured to output a first scan signal to a scan output node electrically connected to a first scan signal line among a plurality of scan signal lines arranged on a display panel, and includes a scan pull-up transistor and a scan pull-down transistor. The system also includes a control circuit configured to control the scan output buffer, wherein the control circuit includes a first control node and a second control node, and includes an inverter circuit for charging or discharging the QB node, wherein the inverter circuit includes a first transistor configured to charge the QB node and two or more transistors connected between the gate node of the first transistor and a low-potential node to which a low-potential voltage is applied; wherein the two or more transistors include: a second transistor configured to control the connection between the QB node and the low-potential node; a third transistor configured to control the connection between a high-potential node and the first control node; a fourth transistor configured to control the connection between the second control node and the low-potential node; and a fifth transistor configured to control the connection between the first control node and the second control node, wherein the low-potential node connected to the second transistor and the low-potential node connected to the fourth transistor are disposed on the same line to which a low-potential voltage is applied.

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