Optoelectronic semiconductor device structure, optoelectronic logic gate device and method of operation

Abstract

The present disclosure provides a photoelectric semiconductor device structure, a photoelectric logic gate device and an operating method, the photoelectric logic gate device is prepared based on a semiconductor epitaxial wafer structure, and the photoelectric logic gate device comprises an electrical signal input unit, an optical signal input unit and a logic gate control unit; wherein: the electrical signal input unit is used for applying an input electrical signal; the optical signal input unit is used for applying an input optical signal to make the photoelectric logic gate device generate a photoresponsive current; and the logic gate control unit is used for applying a bias voltage, so that the photoelectric logic gate device realizes different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponsive current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of optoelectronic technology, and in particular to an optoelectronic semiconductor device structure, an optoelectronic logic gate device and an operating method thereof. BACKGROUND

[0002] A logic gate is a basic electronic device in digital circuits, used to perform logical operations. It produces an output signal according to the different signal states (usually logic "0" or "1") of the input end through internal logic operation rules. Through the combination and connection of logic gates, complex logic operations and data processing can be realized, which is the basic component unit in digital circuits. The basic logic gates currently include AND gate, OR gate, NOT gate, XOR gate, NOR gate, NAND gate, etc. There are two main research directions for logic gate devices, namely traditional silicon-based electrical logic gate devices and all-optical logic gate devices based on optical input and output. Figure 4 As shown in the figure, the first kind of traditional electrical logic gate is manufactured based on silicon-based integrated circuit technology, usually composed of transistors and other basic electronic elements. The traditional silicon-based double-input NOR and NAND logic gates require at least four transistors to participate in the construction, and this structure has a large volume and a relatively complex circuit system, which not only limits the integration of the system, but also increases the power consumption and preparation cost of the system itself. Moreover, the traditional logic gate can only change its specific logic function by changing the internal structure of the circuit, but cannot be changed by changing the external applied conditions, which leads to insufficient flexibility in actual application. In addition, based on the current rapid development of optoelectronic devices, traditional logic gates are difficult to achieve good compatibility with optoelectronic devices, and are limited in the application of future optoelectronic chips. The second kind of all-optical logic gate using optical input and output is designed and constructed based on complex optical components, such as terahertz asymmetric multi-decomposition, nonlinear interferometer and semiconductor amplifier. Although optical logic gate has advantages such as good optical gain, saturated output power and gain bandwidth, due to its high preparation cost and large component volume, it is still far from practical application at this stage. In addition, the straight-line propagation of light is a considerable obstacle to the construction of highly integrated systems, because integrating optical components together can cause considerable optical loss.

[0003] Therefore, there is an urgent need for an optoelectronic semiconductor structure and an optoelectronic logic gate device that can solve the problems of high cost, difficulty in achieving high integration, low flexibility, and poor compatibility with optoelectronic devices. SUMMARY

[0004] Based on the above problems, the present disclosure provides an optoelectronic semiconductor device structure, an optoelectronic logic gate device and an operating method thereof to alleviate the technical problems in the prior art.

[0005] (I) Technical solutions

[0006] In one aspect of the present disclosure, an optoelectronic logic gate device is provided, which is prepared based on a semiconductor epitaxial wafer structure, and comprises an electrical signal input unit, an optical signal input unit, and a logic gate control unit. The electrical signal input unit is configured to apply an input electrical signal. The optical signal input unit is configured to apply an input optical signal to make the optoelectronic logic gate device generate a photoresponsive current. The logic gate control unit is configured to apply a bias voltage, so that the optoelectronic logic gate device implements different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponsive current.

[0007] According to an embodiment of the present disclosure, the optoelectronic logic gate device can implement an AND gate function or an OR gate function.

[0008] According to an embodiment of the present disclosure, the logic gate control unit comprises a P-type electrode and an N-type electrode.

[0009] According to an embodiment of the present disclosure, the electrical signal input unit is a capacitor structure composed of a semiconductor material layer, a dielectric layer, and an electrode layer.

[0010] According to an embodiment of the present disclosure, the semiconductor material layer is prepared from Al x Ga y In 1-x-y N, or Al x Ga y In 1-x- y As, or Al x Ga y In 1-x-y P, 0≤x≤1, 0≤y≤1.

[0011] According to an embodiment of the present disclosure, the dielectric layer is prepared from at least one of aluminum oxide, silicon oxide, hafnium oxide, carbon nanotubes, and barium titanate.

[0012] According to an embodiment of the present disclosure, the capacitor structure can be prepared on the N-type semiconductor material layer or on the etched mesa sidewall of the N-type semiconductor material layer, or can be prepared on the P-type semiconductor material layer.

[0013] According to an embodiment of the present disclosure, the etched mesa or the electrode of the optoelectronic logic gate device has any one of a triangular shape, a quadrilateral shape, a pentagonal shape, a hexagonal shape, an octagonal shape, and a circular shape, and the size of the optoelectronic logic gate device is 10 nm 2 ~ 1 mm 2 The optical signal input unit is arranged at a substrate of the optoelectronic logic gate device, and the substrate is prepared from sapphire, Si, SiC, A1N, GaN, or quartz glass.

[0014] In another aspect of the present disclosure, an operating method of the optoelectronic logic gate device is provided, the operating method comprising: operation S1, applying an input electrical signal to a capacitor structure in the optoelectronic logic gate device prepared based on a semiconductor epitaxial wafer structure; operation S2, applying an input optical signal to a substrate in the optoelectronic logic gate device to make the optoelectronic logic gate device generate a photoresponsive current; operation S3, applying a bias voltage between a P-type electrode and an N-type electrode in the optoelectronic logic gate device, so that the optoelectronic logic gate device realizes different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponsive current.

[0015] In another aspect of the present disclosure, an optoelectronic semiconductor device structure is provided, prepared from a semiconductor epitaxial wafer comprising, from bottom to top, a substrate, a buffer layer, an N-type semiconductor material layer, a multi-quantum well layer, and a P-type semiconductor material layer; a portion of the epitaxial wafer structure is etched to expose the surface of the N-type semiconductor material layer, and an N-type electrode is arranged on the exposed surface of the N-type semiconductor material layer; a P-type electrode is arranged on the surface of the P-type semiconductor material layer; a capacitor structure is further arranged based on the P-type semiconductor material layer or the N-type semiconductor material layer, the capacitor structure comprising, from bottom to top, the P-type semiconductor material layer or the N-type semiconductor material layer, a dielectric layer, and an electrode layer; an insulating layer is arranged on the surface of the epitaxial wafer structure outside the N-type electrode, the P-type electrode, and the capacitor structure; the shape of the etched mesa or the electrode of the optoelectronic semiconductor device structure is any one of a triangle, a quadrilateral, a pentagon, a hexagon, an octagon, or a circle, and the size of the optoelectronic semiconductor device structure is 10 nm 2 ~ 1 mm 2 .

[0016] (II) Beneficial Effects

[0017] From the above technical solutions, the optoelectronic semiconductor device structure, the optoelectronic logic gate device, and the operating method thereof of the present disclosure at least have one or part of the following beneficial effects:

[0018] (1) The preparation method is simple, and the integration degree is good. In actual systems, operations can be performed on a single device, thus avoiding problems such as complex circuits and large device size, and the integration degree and efficiency of the system can be improved;

[0019] (2) The problem that traditional logic gates can only change the specific logic functions realized by changing the internal structure of the circuit, but cannot be changed by changing external conditions, is overcome. The optoelectronic logic gate can be flexibly configured by changing external conditions;

[0020] (3) The logic gate function of the chip can be flexibly switched by controlling the voltage applied to the electrodes of the optoelectronic logic gate device.

[0021] (4) No special epitaxial wafer structure needs to be designed, thus overcoming the defects of complex process, poor repeatability and high cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The cross-sectional structure schematic diagram of the optoelectronic semiconductor device structure and the optoelectronic logic gate device of the embodiment of the present disclosure.

[0023] Figure 2 The top view structure schematic diagram of the optoelectronic semiconductor device structure and the optoelectronic logic gate device of the embodiment of the present disclosure.

[0024] Figure 3 The flow chart of the operation method of the optoelectronic logic gate device of the embodiment of the present disclosure.

[0025] Figure 4 The schematic diagram of the NOR and NAND logic gates respectively composed of MOSFET as the basic element in the prior art.

[0026] Figure 5 The working principle schematic diagram of the optoelectronic logic gate device of the embodiment of the present disclosure to realize different logic functions.

[0027] Figure 6 The test result diagram of the optoelectronic logic gate device of the embodiment of the present disclosure to realize different logic functions.

[0028] Figure 7 The test result schematic diagram of the optoelectronic semiconductor device structure of different sizes of the embodiment of the present disclosure.

[0029] MAIN ELEMENT SYMBOLS OF THE EMBODIMENT OF THE PRESENT DISCLOSURE IN THE DRAWINGS

[0030] 1: substrate; 2: buffer layer; 3: N-type semiconductor layer; 4: multi-quantum well layer; 5: P-type semiconductor layer; 6: N-type electrode; 7: P-type electrode; 8: dielectric layer; 9: capacitor electrode; 10: insulating layer; 11: electrode pad. DETAILED DESCRIPTION

[0031] The present disclosure provides a photoelectric semiconductor device structure, a photoelectric logic gate device and an operating method thereof. The capacitor structure in the photoelectric logic gate device is composed of a semiconductor material of the device itself, a dielectric layer and a metal contact layer on the surface. The additional integrated capacitor provides additional freedom to control the dynamic optical response of the photoelectric logic gate device. Specifically, the electrical signal applied on the capacitor and the optical signal applied on the photoelectric logic gate device are regarded as two inputs respectively, and the corresponding output signal is the photoelectric response that can be detected between the P-type electrode and the N-type electrode. Based on the above principle, by controlling the bias voltage applied on the P-type electrode and the N-type electrode of the photoelectric logic gate device, various photoelectric logic gates including NAND and NOR can be flexibly configured. Compared with traditional silicon-based logic gates, the photoelectric logic gate device of the present disclosure can more easily realize logic gates with the same function, and can be operated on a single device. The simplified architecture can improve the integration and efficiency of the system. Since the implementation of the photoelectric logic gate does not require complex semiconductor epitaxy and preparation process, it also avoids a large number of complex circuits. Different logic functions can be flexibly realized on the same device, and the use of optical signals as input signals can also improve the compatibility of the logic device with other optoelectronic devices. Therefore, the three-port photoelectric logic gate device proposed in the present disclosure greatly improves the integration, flexibility and cost advantage of the basic logic gate.

[0032] For the purpose, technical solutions and advantages of the present disclosure to be clearer, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the drawings.

[0033] In the embodiments of the present disclosure, as shown in Figure 1 、 Figure 2 、 Figure 5 , a photoelectric logic gate device is provided, which is prepared based on a semiconductor epitaxial wafer structure. The photoelectric logic gate device includes an electrical signal input unit, an optical signal input unit and a logic gate control unit. The electrical signal input unit is used to apply an input electrical signal. The optical signal input unit is used to apply an input optical signal to make the photoelectric logic gate device generate a photoresponse current. The logic gate control unit is used to apply a bias voltage, so that the photoelectric logic gate device realizes different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponse current.

[0034] In the embodiments of the present disclosure, as shown in Figure 1 、 Figure 2 、 Figure 5As shown, the bump-shaped optoelectronic logic gate device is prepared based on a semiconductor epitaxial wafer structure, which includes a substrate 1, a buffer layer 2, an N-type semiconductor material layer 3, a multi-quantum well layer 4, and a P-type semiconductor material layer 5. After a part of the epitaxial wafer structure is etched to expose the surface of the N-type semiconductor material layer 3, a bump structure is formed. An N-type electrode 6 is prepared on the exposed surface of the N-type semiconductor material layer 3. A P-type electrode 7 is prepared on a part of the surface of the P-type semiconductor material layer 5. A dielectric layer 8 is prepared on another part of the surface of the P-type semiconductor material layer 5. A capacitor electrode 9 is prepared on the dielectric layer 8. An insulating layer 10 is prepared on the surface of the epitaxial wafer structure except the N-type electrode 6, the P-type electrode 7, and the capacitor electrode 9. Metal electrode pads 11 are prepared on the N-type electrode 6 and the P-type electrode 7.

[0035] According to the embodiment of the present disclosure, the logic gate control unit includes a P-type electrode and an N-type electrode.

[0036] According to the embodiment of the present disclosure, the electrical signal input unit is a capacitor structure composed of a semiconductor material layer, a dielectric layer, and an electrode layer.

[0037] According to the embodiment of the present disclosure, the optoelectronic logic gate device can realize an OR NOT gate function or an AND NOT gate function. For example, the bias voltage applied by the logic gate control unit is V p-n When V p-n < 0, the optoelectronic logic gate device is in an OR NOT gate state; when V p-n > 0, the optoelectronic logic gate device is in an AND NOT gate state.

[0038] According to the embodiment of the present disclosure, the preparation material of the dielectric layer is selected from at least one of aluminum oxide, silicon oxide, hafnium oxide, carbon nanotubes, and barium titanate.

[0039] According to the embodiment of the present disclosure, the optoelectronic logic gate device is a bump-shaped optoelectronic logic gate device prepared based on a semiconductor epitaxial wafer structure.

[0040] According to the embodiment of the present disclosure, the optical signal input unit is arranged at the substrate of the optoelectronic logic gate device, and the preparation material of the substrate is selected from sapphire, Si, SiC, AlN, GaN, or quartz glass.

[0041] According to the embodiment of the present disclosure, as Figures 1-2As shown, a photoelectric semiconductor device structure is also provided, which is fabricated from a semiconductor epitaxial wafer. The semiconductor epitaxial wafer structure, from bottom to top, includes a substrate 1, a buffer layer 2, an N-type semiconductor material layer 3, a multiple quantum well layer 4, and a P-type semiconductor material layer 5. A portion of the epitaxial wafer structure is etched to expose the surface of the N-type semiconductor material layer, and an N-type electrode 6 is disposed on the exposed surface of the N-type semiconductor material layer. A P-type electrode 7 is disposed on the surface of the P-type semiconductor material layer. Further, based on the P-type semiconductor material layer or the N-type semiconductor material layer, [further details are needed]. The device includes a capacitor structure, which, from bottom to top, consists of a P-type or N-type semiconductor material layer, a dielectric layer, and an electrode layer. An insulating layer 10 is disposed on the surface of the epitaxial wafer structure other than the N-type electrode, P-type electrode, and capacitor structure. Metal electrode pads 11 are correspondingly fabricated on the N-type electrode 6 and the P-type electrode 7. The device etching mesa or electrode shape of the optoelectronic semiconductor device structure is any one of triangular, quadrilateral, pentagonal, hexagonal, octagonal, or circular, and the etching mesa or planar dimension of the optoelectronic semiconductor device structure is 10 nm. 2 ~1mm 2 .like Figure 7 As shown, by analyzing 800μm 2 400μm 2 200μm 2 100μm 2 Testing of four different sizes of optoelectronic semiconductor device structures revealed that the response speed of the device increases as the device size decreases. This means that reducing the device size not only improves the integration density of the optical logic gate system but also enhances its operational speed.

[0042] According to embodiments of this disclosure, the insulating layer 10 is made of at least one of silicon oxide, silicon nitride, aluminum nitride, scandium nitride, gallium oxide, or aluminum oxide, and the insulating layer 10 and the dielectric layer 8 are made of different materials.

[0043] According to the embodiments of this disclosure, the dielectric layer 8 is made of at least one of alumina, silicon oxide, hafnium oxide, carbon nanotubes, and barium titanate, and the dielectric layer 8 and the insulating layer 10 are made of different materials.

[0044] According to an embodiment of this disclosure, preferably, the thickness of the buffer layer 2 is 10-100 nm;

[0045] Preferably, the thickness of the N-type semiconductor material layer 3 is 100-3000 nm;

[0046] Preferably, the thickness of the multiple quantum well layer 4 is 50-100 nm;

[0047] Preferably, the thickness of the P-type semiconductor material layer 5 is 20-500 nm;

[0048] Preferably, the thickness of the insulating layer 10 is 50-1000nm;

[0049] Preferably, the thickness of the medium layer 8 is 5-50nm.

[0050] The preparation material of the N-type semiconductor material layer 3 and the P-type semiconductor material layer 5 is selected from Al x Ga y In 1-x-y N, or Al x Ga y In 1-x-y As, or Al x Ga y In 1-x-y P, 0≤x≤1, 0≤y≤1. For example, the material of the semiconductor material layer includes GaN, AlN, InN, or corresponding ternary alloy material or quaternary alloy material, or GaAs, AlAs, InAs, or corresponding ternary alloy material or quaternary alloy material, or GaP, AlP, InP, or corresponding ternary alloy material or quaternary alloy material.

[0051] According to the embodiment of the present disclosure, the N-type electrode 6 and the P-type electrode 7 constitute a logic gate control unit, and the capacitor structure composed of the P-type semiconductor material layer 5, the medium layer 8, and the capacitor electrode 9; the preparation material of the N-type electrode 6 is selected from at least one of Ni, Cr, Ti, Al, or Au; for example, the N-type electrode 6 is a Ti / Al / Ti / Au multi-metal, a Ti / Au multi-metal, a Ti / Al / Ni / Au multi-metal, a Cr / Au multi-metal, or a Cr / Al / Ti / Au multi-metal. The preparation material of the P-type electrode 7 is selected from at least one of Ni, Cr, Ti, Au, or an ITO conductive layer; for example, the P-type electrode 7 is a Ni / Au multi-metal, a Ti / Au multi-metal, an ITO conductive layer, or a Cr / Au multi-metal. The preparation material of the capacitor electrode 9 is selected from at least one of Ni, Cr, Ti, Au, or an ITO conductive layer; for example, the capacitor electrode can be a Ni / Au multi-metal, a Ti / Au multi-metal, an ITO conductive layer, a Cr / Au multi-metal, or any other conductive contact layer.

[0052] According to the embodiment of the present disclosure, the etching mesa or electrode shape of the optoelectronic logic gate device is any one of a triangle, a quadrilateral, a pentagon, a hexagon, an octagon, or a circle, and the size of the etching mesa of the optoelectronic logic gate device is 10nm 2 ~1mm 2 .

[0053] It should be noted that the design of the three electrode patterns of the N-type electrode 6, the P-type electrode 7, and the capacitor electrode 9 does not affect the functional use, and changes in electrode shape (for example, block electrodes, interdigitated electrodes, etc.), changes in the area ratio of the three electrodes, and the like do not affect the functional implementation of the device. Moreover, the three electrodes can be flexibly selected and configured according to the specific needs of the capacitor structure and the logic gate control unit. For example, in the embodiment of the present disclosure, the capacitor structure is prepared on the P-type semiconductor material layer, and can also be arranged on the N-type semiconductor material layer according to needs, which all belong to the scope of protection.

[0054] Through the above operation, an optoelectronic logic gate device (chip) that can be used in an optoelectronic logic gate and can directly achieve different logic functions by controlling an applied bias voltage is prepared. A top view structural diagram of the chip is shown in Figure 2 .

[0055] According to the embodiment of the present disclosure, as shown in Figure 3 , an operation method of an optoelectronic logic gate device is also provided. The operation method includes:

[0056] Operation S1: An input electrical signal is applied to the capacitor structure of the optoelectronic logic gate device prepared based on a semiconductor epitaxial wafer structure.

[0057] Operation S2: An input optical signal is applied to the substrate of the optoelectronic logic gate device to make the optoelectronic logic gate device generate a photoresponsive current.

[0058] Operation S3: A bias voltage is applied between the P-type electrode and the N-type electrode of the optoelectronic logic gate device, so that the optoelectronic logic gate device implements different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponsive current.

[0059] It can be seen that the integrated capacitor in the above photoelectric logic gate device can provide additional degrees of freedom to control the dynamic light response. By controlling the bias voltage applied to the P-type electrode and the N-type electrode of the photoelectric logic gate device, various photoelectric logic gates including NAND and NOR can be flexibly configured. In terms of the internal principle, when a positive voltage is applied to the P-type electrode and the N-type electrode of the photoelectric logic gate device, the potential barrier between the PN junctions becomes small, the PN junction is in a conductive state, and a positive conduction current is generated; therefore, when the voltage between the PN junctions is positive, the negative current generated by the PN junction under light will offset part of the positive current; when the capacitor electrode is applied with a negative bias, the potential barrier difference of the PN junction increases, thereby further offsetting part of the positive current. Under the joint action of light and the capacitor electrode bias, the current between the PN junctions finally presents an overall negative current. In the logic circuit, without light and capacitor electrode bias, the device is a positive current (the output state is 1); only with light and without capacitor electrode bias, the device is a positive current (the output state is 1); only with the capacitor electrode bias and without light, the device is a positive current (the output state is 1); both with light and with the capacitor electrode bias, the device is a negative current (the output state is 0). Therefore, an NAND logic circuit is formed. When the voltage between the PN junctions is zero bias or negative bias, the potential barrier between the PN junctions becomes large, the PN junction is in a cut-off state, and there is no current in the device; therefore, when the voltage between the PN junctions is zero bias or negative bias, the negative current generated by the PN junction under light is generated. When the capacitor electrode is applied with a negative bias, the potential barrier of the PN junction further increases, and the negative current increases. In the logic circuit, without light and capacitor electrode bias, the device is a zero current (the output state is 1); only with light and without capacitor electrode bias, the device is a negative current (the output state is 0); only with the capacitor electrode bias and without light, the device is a negative current (the output state is 0); both with light and with the capacitor electrode bias, the device is a negative current (the output state is 0), and therefore an NOR logic circuit is formed.

[0060] According to the embodiments of the present disclosure, the implementation of the proposed photoelectric logic gate device is tested to prove the logic function of the NOR gate and the NAND gate. In combination with the above description of the photoelectric logic gate device, the implementation of the photoelectric logic gate device is tested to prove the logic function of the NOR gate and the NAND gate. Figures 5-6As shown, when the voltage difference between the P-type electrode and the N-type electrode is -6V to 0V, the device behaves as a NOR gate, and when the voltage difference is 0V to 1.5V, the device behaves as a NAND gate. An electrical signal is input on the capacitor electrode, and when the applied voltage is equal to 5V, it is regarded as a signal "1", and when the applied voltage is 0V, it is regarded as a signal "0"; a light source with a corresponding wavelength is arranged below the substrate 1, and is used to input a light signal, wherein when the input light power of the light source is greater than the threshold power (threshold power: the minimum light power that can make the device generate a light response current), it is regarded as a signal "1", and when the input light power is 0, it is regarded as a signal "0"; the output signal is the light response current between the N-type electrode and the P-type electrode, and the definition of the positive current is that the current flows from the P-type electrode to the N-type electrode, and when the light response current is less than 0, it is regarded as a signal "0", and when the light response current is greater than 0, it is regarded as a signal "1". Further, the working principle of the new optical communication system based on the photoelectric logic gate device of the present disclosure is as shown in Figure 5 As shown, the input electrical signal is applied to the capacitor electrode of the photoelectric logic gate device, and the light source is placed below the chip substrate to provide an input light signal. A bias voltage V p-n is provided between the P-type electrode and the N-type electrode by using a semiconductor analyzer, and the logic gate function realized by controlling the bias voltage is controlled. The real-time current between the P-type electrode and the N-type electrode can be displayed on the semiconductor analyzer, and this electrical signal is the output signal. The final test result is as shown in Figure 6 As shown, the photoelectric logic gate device of the present disclosure can flexibly switch the logic gate function that can be realized by the chip by controlling the voltage applied to the electrode of the logic gate control unit. The problem that the traditional logic gate can only change the specific logic function realized by changing the internal structure of the circuit, and cannot be changed by changing the external applied conditions, can be overcome, and the photoelectric logic gate can be flexibly configured by changing the external conditions. The preparation method is simple, the integration degree is good, and the operation can be performed on a single device in an actual system, so as to avoid the problems of complex circuit and large device size, and the integration degree and efficiency of the system can be improved. Since it is not necessary to design a special epitaxial wafer structure, the defects of complex process, poor repeatability and high cost are overcome.

[0061] So far, the embodiments of the present disclosure have been described in detail with reference to the drawings. It should be noted that the implementation modes not shown or described in the drawings or the text of the specification are known to those skilled in the art, and are not described in detail. In addition, the definitions of the elements and methods described above are not limited to the various specific structures, shapes or modes mentioned in the embodiments, and can be simply changed or replaced by those skilled in the art.

[0062] It is also necessary to note that the above is provided by different embodiments of the present disclosure. These embodiments are used to illustrate the technical content of the present disclosure, and are not used to limit the protection scope of the present disclosure. A feature of an embodiment can be applied to other embodiments by suitable modification, substitution, combination, separation.

[0063] In addition, in this article, except for the specifically indicated, the ordinal numbers of "first", "second", etc. are only used to distinguish multiple elements with the same name, and do not represent the existence of a hierarchy, level, execution order, or process order between them. A "first" element and a "second" element can appear together in the same component, or separately in different components. The existence of an element with a larger ordinal number does not necessarily mean the existence of another element with a smaller ordinal number.

[0064] In this article, except for the specifically indicated, the so-called feature A "or" (or) o r) or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" (and) or "with" (and) or "and" (and) feature B means that A and B exist at the same time; the so-called "includes", "contains", "has", "contains" means including but not limited to.

[0065] In addition, in this article, the so-called "up", "down", "left", "right", "front", "back", or "between" and other terms are only used to describe the relative position between the elements, and in the interpretation can be extended to include translation, rotation, or mirror image. In addition, in this article, except for the specifically indicated, "an element on another element" or similar statements do not necessarily mean that the element contacts the other element.

[0066] In addition, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the desired design. And the above embodiments can be mixed and used with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0067] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of the present disclosure. It should be understood that the above is only a specific embodiment of the present disclosure and is not used to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A photoelectric logic gate device, fabricated based on a semiconductor epitaxial wafer structure, the photoelectric logic gate device comprising an electrical signal input unit, an optical signal input unit, and a logic gate control unit; wherein: The electrical signal input unit is a capacitor structure composed of a semiconductor material layer, a dielectric layer, and an electrode layer, used to apply input electrical signals; The optical signal input unit is used to apply an input optical signal to cause the optoelectronic logic gate device to generate a photoresponse current; The logic gate control unit includes P-type electrodes and N-type electrodes for applying bias voltage, enabling the optoelectronic logic gate device to perform different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponse current.

2. The optoelectronic logic gate device according to claim 1 can realize the OR gate function or the NAND gate function.

3. The optoelectronic logic gate device according to claim 1, wherein the semiconductor material layer is prepared from Al. x Ga y In 1-x-y N, or Al x Ga y In 1-x-y As, or Al x Ga y In 1-x-y P, 0≤x≤1, 0≤y≤1.

4. The optoelectronic logic gate device according to claim 1, wherein the material for preparing the dielectric layer is selected from at least one of alumina, silicon oxide, hafnium oxide, carbon nanotubes, and barium titanate.

5. The optoelectronic logic gate device according to claim 1, wherein the capacitor structure can be fabricated on an N-type semiconductor material layer or on the etched mesa sidewall of the N-type semiconductor material layer, or it can be fabricated on a P-type semiconductor material layer.

6. The optoelectronic logic gate device according to claim 1, wherein the etched mesa or electrode shape is any one of triangle, quadrilateral, pentagon, hexagon, octagon, or circle, and the size of the optoelectronic logic gate device is 10 nm. 2 ~1mm 2 The optical signal input unit is disposed on the substrate of the optoelectronic logic gate device, and the substrate is made of sapphire, Si, SiC, AlN, GaN or quartz glass.

7. A method for operating an optoelectronic logic gate device, comprising operating the optoelectronic logic gate device according to any one of claims 1-6, the method comprising: Operation S1: Apply an input electrical signal to the capacitor structure in the optoelectronic logic gate device fabricated based on the semiconductor epitaxial wafer structure; Operation S2: Apply an input optical signal to the substrate in the optoelectronic logic gate device to cause the optoelectronic logic gate device to generate a photoresponse current; Operation S3: Apply a bias voltage between the P-type electrode and the N-type electrode in the optoelectronic logic gate device to enable the optoelectronic logic gate device to perform different logic gate functions, thereby outputting different logic operation results based on the input electrical signal and the photoresponse current.

8. A photoelectric semiconductor device structure, fabricated from a semiconductor epitaxial wafer, wherein the semiconductor epitaxial wafer comprises, from bottom to top, a substrate, a buffer layer, an N-type semiconductor material layer, a multiple quantum well layer, and a P-type semiconductor material layer; A portion of the epitaxial wafer structure is etched to expose the surface of an N-type semiconductor material layer, and an N-type electrode is disposed on the exposed surface of the N-type semiconductor material layer. A P-type electrode is disposed on the surface of a P-type semiconductor material layer; A capacitor structure is also provided based on the P-type semiconductor material layer or N-type semiconductor material layer. The capacitor structure consists of a P-type semiconductor material layer or N-type semiconductor material layer, a dielectric layer, and an electrode layer from bottom to top. An insulating layer is provided on the surface of the epitaxial wafer structure other than the N-type electrode, P-type electrode, and capacitor structure. The etched mesa or electrode of the optoelectronic semiconductor device structure can be any one of the following shapes: triangular, quadrilateral, pentagonal, hexagonal, octagonal, or circular. The size of the optoelectronic semiconductor device structure is 10 nm. 2 ~1mm 2 .

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