Pressure sensor, pressure sensing device, and electronic device

Abstract

Some embodiments of the present disclosure disclose a pressure sensor, a pressure sensing device and an electronic device, which relate to the technical field of micro-electro-mechanical systems, and can reduce the influence of metal wiring thermal adhesive plastic stress and / or thermal adhesive elastic stress on the pressure sensitive resistor, so as to improve the performance of the pressure sensor. The pressure sensor comprises a first substrate structure. The first substrate structure comprises a pressure sensitive layer, a plurality of pressure sensitive resistors and a plurality of interconnection wirings. A part of the pressure sensitive layer is used for sensing pressure change; the plurality of pressure sensitive resistors are located on a first side of the pressure sensitive layer; the plurality of pressure sensitive resistors are configured to generate an electrical signal based on the pressure change sensed by the pressure sensitive layer. The plurality of interconnection wirings are at least partially located on a second side of the pressure sensitive layer, the second side of the pressure sensitive layer being opposite to the first side of the pressure sensitive layer; the plurality of interconnection wirings are configured to couple the plurality of pressure sensitive resistors with each other. The pressure sensor provided by some embodiments of the present disclosure is used for measuring pressure.

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronic machinery technology, and in particular to a pressure sensor, a pressure sensing device, and an electronic device. Background Art

[0002] Micro-Electro-Mechanical System (MEMS) pressure sensors are miniature devices with pressure detection capabilities, manufactured using MEMS technology. They are primarily classified into three types: piezoresistive, capacitive, and resonant. They are used in consumer electronics, industrial production, and other fields. Piezoresistive MEMS pressure sensors are widely used due to their advantages, such as small size, light weight, simple structure, low cost, and high measurement accuracy.

[0003] In related technologies, piezoresistive MEMS pressure sensors consist of a pressure-sensitive membrane and a piezoresistor. The membrane deforms under external pressure, generating stress. The stress causes the piezoresistor to change its resistance, which is converted into a voltage output. Therefore, the voltage output reflects the magnitude of the external pressure.

[0004] However, during use, the metal traces connected to the varistor will introduce thermo-viscoplastic stress and / or thermo-viscoelastic stress, and this thermo-viscoplastic stress and / or thermo-viscoelastic stress is easily transmitted to the varistor, causing hysteresis and drift during temperature cycling, affecting the performance of the pressure sensor. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a pressure sensor, a pressure sensing device, and an electronic device, which can reduce the influence of thermo-viscoplastic stress and / or thermo-viscoelastic stress of metal traces on piezoresistors, thereby improving the performance of the pressure sensor.

[0006] In a first aspect, a pressure sensor is provided. The pressure sensor includes a first substrate structure. The first substrate structure includes a pressure-sensitive layer, a plurality of piezoresistors, and a plurality of interconnecting traces. A portion of the pressure-sensitive layer is used to sense pressure changes. The plurality of piezoresistors are located on a first side of the pressure-sensitive layer; the plurality of piezoresistors are configured to generate electrical signals based on pressure changes sensed by the pressure-sensitive layer. A plurality of interconnecting traces are at least partially located on a second side of the pressure-sensitive layer, the second side of the pressure-sensitive layer being opposite to the first side of the pressure-sensitive layer; the plurality of interconnecting traces are configured to couple the plurality of piezoresistors to each other.

[0007] In the pressure sensor provided by some embodiments of the present disclosure, at least some of the multiple interconnection lines are located on the second side of the pressure-sensitive layer, so that the interconnection lines located on the second side of the pressure-sensitive layer can be distributed on both sides of the pressure-sensitive layer with multiple piezoresistors. In this way, the interconnection lines located on the second side of the pressure-sensitive layer can be interconnected on the second side of the pressure-sensitive layer (for example: connected on the surface of the second side of the pressure-sensitive layer to form part of the bridge structure) and are not directly connected to the multiple piezoresistors. In this way, the influence of the thermo-viscoplastic stress and / or thermo-viscoelastic stress generated by the multiple interconnection lines on the multiple piezoresistors can be reduced, the hysteresis and drift during temperature cycling can be reduced, the thermal hysteresis can be reduced, and the performance of the pressure sensor can be improved.

[0008] Optionally, the plurality of interconnecting traces include lead traces located on a first side of the pressure-sensitive layer and main traces located on a second side of the pressure-sensitive layer. The first pressure-sensitive layer includes a first liner and a buried oxide layer. The buried oxide layer is disposed on one side of the first liner; the first liner is closer to the second side of the pressure-sensitive layer relative to the buried oxide layer. A plurality of varistors are located on a surface of the buried oxide layer away from the first liner and are arranged at intervals around the center of the buried oxide layer. The main trace is disposed on a side of the first liner away from the buried oxide layer. The orthographic projection of the main trace on the surface of the buried oxide layer away from the first liner is located outside the area enclosed by the plurality of varistors.

[0009] Optionally, a surface of the first liner away from the buried oxide layer has a groove recessed toward the buried oxide layer; or, the first liner includes an opening in the middle.

[0010] Optionally, the portion of the pressure-sensitive layer for sensing pressure changes includes a middle portion of the first lining. In the first lining, the portion for sensing pressure changes has a first thickness, and the remaining portion has a second thickness; the first thickness is consistent with the second thickness.

[0011] Optionally, the first substrate structure further includes a first insulating layer. The first insulating layer is disposed on the second surface of the first liner; wherein the main trace is disposed on a surface of the first insulating layer away from the first liner.

[0012] Optionally, the first substrate structure further includes a plurality of first through holes, a plurality of first conductive bumps, and a plurality of first conductive layers. The plurality of first through holes penetrate the first liner, the buried oxide layer, and the first insulating layer, and the plurality of first through holes are located outside the area enclosed by the plurality of varistors. The plurality of first conductive bumps are located on the surface of the buried oxide layer away from the first liner; the plurality of first conductive bumps cover the openings of the plurality of first through holes; each first conductive bump is coupled to a varistor. The plurality of first conductive layers are correspondingly arranged in the inner cavities of the plurality of first through holes and are coupled to the plurality of first conductive bumps; the first conductive layers are insulated from the first liner. The main wiring is coupled to the plurality of varistors through the plurality of first conductive bumps and the plurality of first conductive layers.

[0013] Optionally, the first substrate structure further includes a plurality of first pads. The plurality of first pads are located on a surface of the first insulating layer away from the first liner; and the first pads are connected between the two main traces.

[0014] Optionally, the pressure sensor further includes a second substrate structure. The second substrate structure is located on one side of the first substrate structure and is connected to the first substrate structure. The second substrate structure includes a second substrate and a readout integrated circuit. The readout integrated circuit is integrated within the second substrate and coupled to the plurality of piezoresistors. The readout integrated circuit is configured to process electrical signals generated by the plurality of piezoresistors.

[0015] Optionally, the second substrate structure further includes a plurality of second conductive bumps. The plurality of second conductive bumps are located on a surface of the second substrate adjacent to the first substrate structure and coupled to the readout integrated circuit; at least a portion of the plurality of second conductive bumps are in corresponding contact with a portion of the plurality of first conductive bumps.

[0016] Optionally, the first substrate structure further includes at least one second through-hole, at least one third conductive bump, and at least one second conductive layer. The at least one second through-hole penetrates the first liner, the buried oxide layer, and the first insulating layer. The at least one third conductive bump is located on a surface of the buried oxide layer away from the first liner; the at least one third conductive bump covers the opening of the at least one second through-hole; the at least one third conductive bump contacts a portion of the plurality of second conductive bumps. The at least one second conductive layer is correspondingly disposed in the inner cavity of the at least one second through-hole and is correspondingly coupled to the at least one third conductive bump; the second conductive layer is insulated from the first liner.

[0017] Optionally, the first substrate structure further includes at least one second pad. The at least one second pad is located on a surface of the first insulating layer away from the first liner; and the at least one second pad is coupled to the at least one second conductive layer.

[0018] Optionally, the plurality of first pads include ground pads, the plurality of first conductive bumps include first ground conductive bumps, the plurality of second conductive bumps include second ground conductive bumps, and the ground pads, the first ground conductive bumps, and the second ground conductive bumps are coupled.

[0019] Optionally, the second substrate structure further includes a second insulating layer located on a surface of the second liner proximate to the first substrate structure; the plurality of second conductive bumps extend through the second insulating layer; a solder ring is disposed between opposing surfaces of the buried oxide layer and the second insulating layer; the varistor, the plurality of first conductive bumps, and the at least one third conductive bump are located within the solder ring and are spaced apart from the solder ring.

[0020] Optionally, the second substrate structure further includes a plurality of support bumps. The plurality of support bumps are located on a surface of the second insulating layer adjacent to the first substrate structure. Among the plurality of first conductive bumps, other first conductive bumps, except the first conductive bump coupled to the second conductive bump, are in corresponding contact with the plurality of support bumps.

[0021] Optionally, the first substrate structure and the second substrate structure are combined to form a vacuum cavity; multiple varistors are located inside the vacuum cavity; or, a third through hole is commonly opened in the middle of the second lining and the middle of the second insulating layer; the first substrate structure and the second substrate structure are combined to form a gauge pressure cavity; multiple varistors are located inside the gauge pressure cavity.

[0022] Optionally, when the first substrate structure and the second substrate structure are enclosed to form a vacuum cavity, the pressure sensor further includes a getter sheet located in the vacuum cavity.

[0023] In a second aspect, a pressure sensing device is provided. The pressure sensing device includes a pressure sensor provided by the above technical solution and a control integrated circuit. The control integrated circuit is coupled to a plurality of piezoresistors. If the pressure sensor also includes a readout integrated circuit, the control integrated circuit is further coupled to the readout integrated circuit.

[0024] The beneficial effects that can be achieved by the pressure sensing device provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by a pressure sensor provided by the above technical solution, and will not be repeated here.

[0025] In a third aspect, an electronic device is provided, which includes a housing and a pressure sensing device provided by the above technical solution and arranged on the housing.

[0026] The beneficial effects that can be achieved by the electronic devices provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the pressure sensing device provided by the above technical solution, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the embodiments of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0028] Figure 1 A structural diagram of a pressure sensor provided in some embodiments of the present disclosure;

[0029] Figure 2 A structural diagram of a first substrate structure provided for some embodiments of the present disclosure;

[0030] Figure 3AA structural diagram of a first substrate structure provided for further embodiments of the present disclosure;

[0031] Figure 3B A structural diagram of a first substrate structure provided for further embodiments of the present disclosure;

[0032] Figure 4A For the Figure 3A A cross-sectional view of the pressure sensor along line AA;

[0033] Figure 4B For the Figure 3A A cross-sectional view of the pressure sensor along line BB;

[0034] Figure 5 A structural diagram of a second substrate structure provided for some embodiments of the present disclosure;

[0035] Figure 6 A structural diagram of a second substrate structure provided for still further embodiments of the present disclosure;

[0036] Figure 7 For the Figure 3B A cross-sectional view of the pressure sensor along line CC in FIG.

[0037] Figure 8 A flow chart for preparing a pressure sensor provided in some embodiments of the present disclosure;

[0038] Figure 9 A structural diagram of a pressure sensing device provided for some embodiments of the present disclosure;

[0039] Figure 10 A structural diagram of an electronic device provided for some embodiments of the present disclosure;

[0040] Figure 11 A diagram illustrating the connection structure between a pressure sensor and a tube shell provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] Unless otherwise required by context, the term "including" as used herein is to be interpreted as open-ended, i.e. the term "including" is to be interpreted as "including, but not limited to". In describing the disclosure, the terms "one embodiment", "some embodiments", "an exemplary embodiment", "an example", or "some examples" are used to indicate that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the disclosure. Such terms are not necessarily used consistently in all instances throughout the description. The terms "about" and "substantially" are used herein to indicate that the value, parameter, measurement, or other quantity so qualified is understood to be within the physical limits and / or the manufacturing tolerances of an item, and therefore such a quantity can not be perfectly exact. The terms "about" and "substantially" are used herein to indicate that the value, parameter, measurement, or other quantity so qualified is understood to be within the physical limits and / or the manufacturing tolerances of an item, and therefore such a quantity can not be perfectly exact.

[0043] In the description of the embodiments of the disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0044] As used herein, "parallel", "perpendicular", "equal" include the stated condition and a condition approximately the same as the stated condition, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel may, for example, be within 5° of deviation; "perpendicular" includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular may, for example, also be within 5° of deviation. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may, for example, be that the difference between the two is less than or equal to 5% of either.

[0045] The terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" are used only to describe the relative importance of the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0046] In the description of the embodiments of the disclosure, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be directly connected, or indirectly connected through an intermediate medium; can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0047] It should be noted that, for example, 1 / 2 in the drawings of the present disclosure indicates that both structure / line 1 and structure / line 2 can refer to this structure / line, for example, the structure / line 1 / 2 in the drawingFigure 4A N1 / N in the figure indicates that both the vacuum chamber N1 and the main chamber N can be represented by this structure. Other similar reference numerals appearing in the drawings also follow the above description.

[0048] In some examples, in a piezoresistive MEMS pressure sensor, when a piezoresistor undergoes stress and its resistance changes, this resistance change is converted into a voltage output through an interconnect structure (e.g., a Wheatstone bridge structure). The interconnect structure typically includes metal traces. As described in the background, metal traces can introduce thermoviscoplastic and / or thermoviscoelastic stresses, which are easily transmitted to the piezoresistor, causing hysteresis and drift during temperature cycling, generating thermal hysteresis and affecting the performance of the pressure sensor.

[0049] In some examples, the metal traces of the pressure sensor Q are electrically connected to the circuit structure (eg, located inside the tube shell P) through a wire bonding (WB) structure K. The connection method is, for example, Figure 11 When the wire bonding (WB) structure and the varistor are located on the same side, the thermal mismatch stress generated by the package P will crosstalk into the varistor through the WB leads, similarly causing hysteresis and drift during temperature cycling, generating thermal hysteresis and affecting the performance of the pressure sensor.

[0050] In some implementations, the pressure sensor is a MEMS piezoresistive pressure gauge structure, comprising a piezoresistive resistor, a heavily doped contact region, metal leads, a silicon strained membrane, a glass base, and a cavity between the silicon strained membrane and the glass base. The silicon strained membrane is a silicon wafer that is anodically bonded to the glass base and thinned on the non-bonding surface. One surface of the silicon strained membrane includes a piezoresistive resistor, a heavily doped contact region, lead holes, metal leads, and a metal pad. The piezoresistive resistor is sealed within the cavity, and the metal leads and metal pad are electrically connected to the piezoresistive resistor via the lead holes and the heavily doped contact region. Based on this structure, compared to typical pressure sensor structures, this MEMS piezoresistive pressure gauge structure has the advantages of simpler processing and smaller size. Furthermore, due to the use of anodic bonding and silicon wafer thinning, the fabrication process of this MEMS piezoresistive pressure gauge structure is compatible with the processing of standard bulk silicon piezoresistive pressure sensors, reducing processing costs and achieving a higher yield rate. However, it's worth noting that in the aforementioned MEMS piezoresistive pressure gauge structure, the piezoresistor, heavily doped contact area, lead holes, metal leads, and metal pads are all located on the bonding surface of the silicon strain film. Signal extraction is achieved via lateral metal leads located within the trenches. These metal traces are highly deformable and have relatively poor structural rigidity. This results in the thermo-viscoplastic and / or thermo-viscoelastic stresses introduced by the metal traces being easily transferred to the piezoresistor, causing hysteresis and drift during temperature cycling. Furthermore, the lateral metal traces used for signal extraction in the aforementioned structure suffer from poor airtightness and low reliability.

[0051] In other implementations, a MEMS piezoresistive pressure sensor includes a silicon strained membrane with a linear gradient beam-membrane structure, a piezoresistor, a heavily doped contact region, and metal leads. The silicon strained membrane is formed by etching the front surface of a silicon substrate and bonding it to a silicon wafer layer. The piezoresistor is located at the end of the beam-membrane structure. The metal leads and the heavily doped contact region form an ohmic contact on the front surface of the silicon strained beam-membrane. Based on the above structure, by adopting a beam-membrane structure with a linear gradient on the front surface of the silicon substrate, the linearity and sensitivity of the pressure sensor are simultaneously improved. However, it is worth noting that in the above MEMS piezoresistive pressure sensor, the piezoresistor is located on the device surface rather than in the vacuum cavity, and the interconnection traces and the piezoresistor are both located on the same active surface, so that the interconnection traces are directly connected to the piezoresistor, resulting in the thermo-viscoplastic stress and / or thermo-viscoelastic stress introduced by the metal traces being transmitted to the piezoresistor, causing hysteresis and drift during temperature cycling.

[0052] Based on this, in order to reduce the influence of the thermo-viscoplastic stress and / or thermo-viscoelastic stress of the metal traces on the varistor, such as Figure 1 、 Figure 2 、 Figure 4A and Figure 5As shown, some embodiments of the present disclosure provide a pressure sensor 100. Figure 4A For the Figure 3A Cross-sectional view along line AA; Figure 4B For the Figure 3A Cross-sectional view along line BB. The pressure sensor 100 includes a first substrate structure 10. The first substrate structure 10 includes a pressure-sensitive layer 11, a plurality of pressure-sensitive resistors 12, and a plurality of interconnection traces 15. A portion of the pressure-sensitive layer is used to sense pressure changes. The plurality of pressure-sensitive resistors 12 are located on a first side 11A of the pressure-sensitive layer 11; the plurality of pressure-sensitive resistors 12 are configured to generate electrical signals based on pressure changes sensed by the pressure-sensitive layer 11. The plurality of interconnection traces 15 are at least partially located on a second side 11B of the pressure-sensitive layer 11, the second side 11B of the pressure-sensitive layer 11 being opposite to the first side 11A of the pressure-sensitive layer 11; the plurality of interconnection traces 15 are configured to couple the plurality of pressure-sensitive resistors 12 to each other.

[0053] In some examples, the varistor 12 may be a doped silicon varistor, such as a P-type doped silicon varistor or an N-type doped silicon varistor; in other examples, the varistor 12 may be a metal film varistor, and the material of the metal film may be a material with a high piezoresistive strain coefficient, a low material noise factor, and a low resistance temperature coefficient, such as any one or more combinations of NiCr, Pt, FeNi, TiB, TaN, and TiN.

[0054] Exemplarily, the electrical signals generated by the plurality of varistors 12 are voltage signals.

[0055] Here, the plurality of interconnecting traces 15 are configured to couple the plurality of varistors 12 to each other, so that the plurality of interconnecting traces 15 and the plurality of varistors 12 can form an interconnection structure. As a possible implementation, the plurality of interconnecting traces 15 and the plurality of varistors 12 form a ring-shaped Wheatstone bridge structure. For example, Figure 2 and Figure 3A As shown, the Wheatstone bridge structure is in the shape of a square ring, and the four varistors 12 are located in the centers of the four sides of the square ring.

[0056] In some examples, such as Figure 2 and Figure 3A As shown, a portion of the plurality of interconnection traces 15 is located on the second side 11B of the pressure-sensitive layer 11 ; in other examples, all of the plurality of interconnection traces 15 are located on the second side 11B of the pressure-sensitive layer 11 .

[0057] Here, as Figure 2 and Figure 3A As shown, the interconnection traces 15 can connect the plurality of varistors 12 in a transverse direction (eg, in a direction parallel to the first substrate 13 ) to form an interconnection structure (eg, a Wheatstone bridge structure).

[0058] Exemplarily, the material of the interconnection trace 15 may be a low resistivity material, such as any one or more combinations of Al, Ti / Al, Au, and Cr / Au, so that a good circuit path can be formed.

[0059] For example, Figure 2 and Figure 3A As shown, the length of interconnect trace 15 is less than or equal to 50 μm, such as 10 μm, 20 μm, 34 μm, 40 μm, or 50 μm. Among the multiple dimensions of a cross section of interconnect trace 15 perpendicular to its extension direction, the dimension parallel to first liner 13 is the width L2 of interconnect trace 15, and the width L2 of interconnect trace 15 is less than or equal to 15 μm, such as 1 μm, 3 μm, 6 μm, 9 μm, or 15 μm. This can reduce the total volume of the multiple interconnect traces 15, thereby reducing the thermo-viscoplastic stress and / or thermo-viscoelastic stress of the metal traces.

[0060] It can be understood that when at least part of the plurality of interconnection traces 15 are located on the second side 11B of the pressure-sensitive layer 11, the interconnection traces 15 located on the second side 11B of the pressure-sensitive layer 11 can be distributed on both sides of the pressure-sensitive layer 11 with the plurality of varistors 12. In this way, the interconnection traces 15 located on the second side 11B of the pressure-sensitive layer 11 can be interconnected on the second side of the pressure-sensitive layer 11 (for example, connected on the surface of the second side of the pressure-sensitive layer 11 to form a part of the bridge structure) and are not directly connected to the plurality of varistors 12. In this way, the interconnection traces 15 located on the second side 11B of the pressure-sensitive layer 11 are not directly connected to the plurality of varistors 12. The generated thermoviscoplastic stress and / or thermoviscoelastic stress, as well as the thermal mismatch stress of the tube and shell introduced by the wire bonding structure connected to the interconnection trace 15 that may exist on the second side 11B of the pressure-sensitive layer 11, will not be transmitted to the multiple varistors 12. In this way, the influence of the thermoviscoplastic stress and / or thermoviscoelastic stress generated by the multiple interconnection traces 15 and the thermal mismatch stress of the tube and shell introduced by the wire bonding structure that may exist on the second side 11B of the pressure-sensitive layer 11 on the multiple varistors 12 can be reduced, the hysteresis and drift during temperature cycling can be reduced, the thermal hysteresis can be reduced, and the performance of the pressure sensor 100 can be improved.

[0061] In some embodiments, as Figures 1-4AAs shown, the plurality of interconnection traces 15 include a lead trace 151 located on the first side 11A of the pressure-sensitive layer 11 and a main trace 152 located on the second side 11B of the pressure-sensitive layer 11. The pressure-sensitive layer 11 includes a first liner 13 and a buried oxide layer 14. The buried oxide layer 14 is arranged on one side of the first liner 13; the first liner, relative to the buried oxide layer, is closer to the second side 11B of the pressure-sensitive layer. Among them, a plurality of varistors 12 are located on the surface of the buried oxide layer 14 away from the first liner 13 and are arranged at intervals around the center of the buried oxide layer. The main trace 152 is arranged on the side of the first liner 13 away from the buried oxide layer 14. The orthographic projection of the main trace on the surface of the buried oxide layer away from the first liner is located outside the area enclosed by the plurality of varistors.

[0062] As can be understood, by arranging the multiple varistors 12 on the surface of the buried oxide layer 14 away from the first substrate 13, the multiple varistors 12 can be located on the first side 11A of the varistor layer 11. Thus, the main traces 152 and the multiple varistors 12 can be distributed on both sides of the varistor layer 11. This reduces the effects of the thermo-viscoplastic stress and / or thermo-viscoelastic stress generated by the multiple interconnect traces 15, as well as the thermal mismatch stress of the package introduced by the wire bonding structure on the second side 11B of the varistor layer 11. This reduces hysteresis and drift during temperature cycling, thereby improving the performance of the pressure sensor 100. Furthermore, the buried oxide layer 14 can provide insulation between the multiple varistors 12 and the first substrate 13.

[0063] For example, the material of the first liner 13 can be silicon. The material of the buried oxide layer 14 can be an insulating material, such as any one or more combinations of SiO2, SiN, and glass. In this case, the first liner 13 and the buried oxide layer 14 can form a silicon-on-insulator (SOI) structure.

[0064] In some examples, the middle portion of the first liner 13 and the portion of the buried oxide layer 14 that faces the middle portion of the first liner 13 constitute part of the portion of the piezoresistive layer 11 that senses pressure changes. In other words, the middle portion of the first liner 13 and the portion of the buried oxide layer 14 that faces the middle portion of the first liner 13 can sense pressure changes and deform under the action of external pressure, generating stress. The stress causes the resistance of the piezoresistor 12 to change, and the resistance change is then converted into an electrical signal through an interconnect structure (e.g., a Wheatstone bridge structure).

[0065] In some embodiments, as Figure 4B As shown, the portion of the pressure-sensitive layer 11 for sensing pressure changes includes the middle portion of the first lining 13 ; in the first lining 13 , the portion for sensing pressure changes has a first thickness D1 , and the remaining portion has a second thickness D2 .

[0066] In some examples, the second surface of the first liner has a groove (e.g., a square column groove) that is recessed toward the buried oxide layer. In this case, the first thickness is less than the second thickness, so that the middle portion of the first liner has a higher sensitivity for sensing pressure.

[0067] In other examples, the first lining includes an opening in the middle. In this case, the first thickness is less than the second thickness, so that the middle portion of the first lining has a higher sensitivity for sensing pressure.

[0068] In some embodiments, as Figure 4B As shown, the first thickness D1 is consistent with the second thickness D2.

[0069] Exemplarily, the first thickness D1 and the second thickness D2 are equal, and both range from 10 μm to 150 μm, such as 10 μm, 25 μm, 50 μm, 85 μm, 100 μm or 150 μm.

[0070] It can be understood that when the first thickness D1 is consistent with the second thickness D2, compared with the case where the first thickness D1 is smaller than the second thickness D2, the overall thickness of the first substrate structure 10 is smaller, so that the overall height of the pressure sensor 100 is smaller. In this way, the volume of the pressure sensor 100 can be reduced, facilitating device integration.

[0071] In some examples, such as Figures 1-3A and Figure 4B As shown, the region where the piezoresistors 12 are located directly faces the region where the portion of the pressure-sensitive layer 11 that senses pressure changes (e.g., the middle portion of the pressure-sensitive layer 11, hereinafter referred to as the pressure-sensing portion S) is located. In this case, the multiple piezoresistors 12 are located directly below the pressure-sensing portion S, thereby increasing the sensitivity and accuracy of the pressure sensor 100 and enhancing its performance.

[0072] For example, Figures 1-3A and Figure 4B As shown, the pressure sensing portion S is a square; the first substrate structure 10 includes four piezoresistors 12, and the orthographic projections of the four piezoresistors 12 on the pressure sensing portion S are respectively located at the centers of the four ends of the pressure sensing portion S. It should be noted that Figure 4B The area shown by S in FIG. 1 is only an exemplary description of the pressure sensing portion and is not a limitation of the pressure sensing portion of the pressure-sensitive layer 11 .

[0073] Here, of the four boundaries of the pressure-sensing portion S, the boundary on the same side as the piezoresistor 12 is defined as the selected boundary; the distance between the boundary of the piezoresistor 12 closest to the selected boundary and the selected boundary is defined as the resistor film margin. For example, the right boundary of the pressure-sensing portion S is the selected boundary of the piezoresistor located on the right side. In this case, the distance between the right boundary of the piezoresistor and the right boundary of the pressure-sensing portion S is the resistor film margin of the piezoresistor. For understanding the resistor film margins of the other piezoresistors 12, please refer to the above description and will not be repeated here.

[0074] For example, the four piezoresistors 12 have equal resistor film margins, and the resistor film margins range from 0 to 20 μm, such as 0 μm, 5 μm, 10 μm, 15 μm, or 20 μm. Because the center of the pressure sensing portion S is the minimum stress region and the center of the end of the pressure sensing portion S is the maximum stress region, setting the resistor film margins within the range of 0 to 20 μm allows the piezoresistors 12 to be closer to the boundaries of the pressure sensing portion S and further away from the center of the pressure sensing portion S, thereby increasing the sensitivity of the pressure sensor 100.

[0075] In some examples, the varistor 12 is composed of multiple segments of sub-resistors, where the number of segments of the sub-resistors is defined as the folding number of the varistor 12. For example, the folding number of the varistor 12 can be an even number, such as 2, 4, 6, 8, or 10.

[0076] For example, Figure 3A As shown, the width of the four varistors 12 is the same, the length of the four varistors 12 along the extension direction is equal, and they are all distributed in two sections (i.e., two folds), and the two sections of varistors 12 are coupled through the lead traces 152. Figure 3A As shown, the piezoresistors 12 on the left and right sides have the same structure and dimensions, each including two parallel sub-resistors, both parallel to the top edge of the pressure sensing portion S. The piezoresistors 12 on the upper and lower sides have the same structure and dimensions, each including two parallel sub-resistors, both parallel to the top edge of the pressure sensing portion S. This maintains consistency among the four piezoresistors 12, forming a differential structure that improves the sensitivity and accuracy of the pressure sensor 100.

[0077] In some embodiments, the first substrate structure 10 further includes a first insulating layer 17 disposed on the second surface of the first liner 13 , wherein the main trace 152 is disposed on a surface of the first insulating layer 17 away from the first liner 13 .

[0078] Exemplarily, the material of the first insulating layer 17 is an insulating material, such as any one or more combinations of SiO 2 , SiN and glass.

[0079] It can be understood that the first insulating layer 17 can be used to achieve insulation between the main trace 152 and the first substrate 13 , thereby improving the reliability of the pressure sensor 100 .

[0080] In some embodiments, as Figures 1-4A As shown, the first substrate structure 10 also includes a plurality of first through holes 18, a plurality of first conductive bumps 16, and a plurality of first conductive layers 19. The plurality of first through holes 18 penetrate the first liner 13, the buried oxide layer 14, and the first insulating layer 17. The plurality of first through holes 18 are located outside the region 12R enclosed by the plurality of varistors 12. The plurality of first conductive bumps 16 are located on the surface of the buried oxide layer 14 away from the first liner 13; the plurality of first conductive bumps 16 correspondingly cover the openings of the plurality of first through holes 18. Each first conductive bump 16 is coupled to a varistor 12. The plurality of first conductive layers 19 are correspondingly arranged in the inner cavities of the plurality of first through holes 18 and are correspondingly coupled to the plurality of first conductive bumps 16; the first conductive layer 19 is insulated from the first liner 13. The main trace 152 is coupled to the plurality of varistors 12 through the plurality of first conductive bumps 16 and the plurality of first conductive layers 19.

[0081] It should be understood that Figure 4A As shown, when the plurality of first conductive bumps 16 are located on the surface of the buried oxide layer 14 away from the first liner 13 , the plurality of first conductive bumps 16 may correspondingly cover the openings of the plurality of first through holes 18 close to the buried oxide layer 14 .

[0082] Here, each first conductive bump 16 is coupled to a varistor 12. As a possible implementation, the first conductive bump 16 and a varistor 12 can be coupled by direct contact. As another possible implementation, Figure 1 、 Figure 2 and Figure 3A As shown, the first conductive bump 16 can be coupled to one varistor 12 via a lead trace 151 ; in this case, the number of first conductive bumps 16 coupled to the varistor 12 can be multiple, for example, two.

[0083] For example, Figures 1-3A As shown, the number of piezoresistors 12 is four; the number of first through holes 18, first conductive layers 19, and first conductive bumps 16 are all eight; every two first conductive bumps 16 are coupled to a piezoresistor 12, and the four pairs of first conductive bumps 16 correspond to the centers of the four ends of the distributed pressure sensing part S.

[0084] For example, Figure 3AAs shown, the shape of the first conductive bump 16 can be square, rectangular, circular, or elliptical. Moreover, when the shape of the first conductive bump 16 is square or rectangular, the side length L1' of the square or rectangle is in the range of 50 μm to 100 μm, for example, 50 μm, 58 μm, 70 μm, 80 μm, 90 μm, or 100 μm. When the shape of the first conductive bump 16 is circular or elliptical, the diameter of the circle or the major axis length of the ellipse is in the range of 50 μm to 100 μm, for example, 50 μm, 60 μm, 75 μm, 81 μm, 90 μm, or 100 μm.

[0085] For example, the material of the first conductive bump 16 may be any one or more combinations of Au, AuSn, AgSn, CuSn, and SnAgCu.

[0086] Here, the plurality of first conductive layers 19 are correspondingly disposed in the inner cavities of the plurality of first through holes 18 and are correspondingly coupled to the plurality of first conductive bumps 16; as a possible implementation, as Figure 4A As shown, the plurality of first conductive layers 19 are disposed in the inner cavities of the plurality of first through holes 18 in a one-to-one correspondence, and the plurality of first conductive layers 19 are coupled to the plurality of first conductive bumps 16 in a one-to-one correspondence.

[0087] It can be understood that when the plurality of first through holes 18 are located outside the region 12R enclosed by the plurality of piezoresistors 12 , the first through holes 18 have less impact on pressure sensing, thereby improving the accuracy of the pressure sensor 100 .

[0088] Exemplarily, the material of the first conductive layer 19 may be a low resistivity material, such as any one or more combinations of Al, Ti / Al, Au, and Cr / Au, so that a good circuit path can be formed.

[0089] Here, the first conductive layer 19 is insulated from the first substrate 13; as a possible implementation, Figure 4A As shown, a third insulating layer 61 (e.g., an oxide insulating layer) can be provided on the sidewall of the first through-hole 18, so that the first conductive layer 19 is formed on a side of the third insulating layer 61 away from the sidewall of the first through-hole 18. In some examples, the first conductive layer 19 is also formed on the surface of the first conductive bump 16 exposed in the first through-hole 18.

[0090] It can be understood that, through the above arrangement, the plurality of main body wires 152 can be coupled with the plurality of piezoresistors 12, so that the plurality of main body wires 152, the plurality of first conductive bumps 16 and the plurality of piezoresistors 12 can form an interconnection structure (for example, a Wheatstone bridge structure), and the resistance change of the plurality of piezoresistors 12 can be converted into an electrical signal through the interconnection structure. Moreover, since the first conductive bumps 16 and the first conductive layer 19 are through connection structures, the volume of the pressure sensor 100 can be reduced, which is convenient for device integration. In addition, compared with the planar wire type interconnection structure in some implementation manners, the bonding strength is high, and the reliability is stronger, so that the reliability of the pressure sensor 100 can be improved.

[0091] In some embodiments, as shown in Figures 1-4A , the first substrate structure 10 further includes a plurality of first pads 71. The plurality of first pads 71 is located on the surface of the first insulating layer 17 away from the first pad 13; the first pad 71 is connected between two main body wires 152.

[0092] Exemplarily, the material of the first pad 71 can be a low resistivity material, for example, any one or a combination of Al, Ti / Al, Au and Cr / Au, so that a good circuit path can be formed.

[0093] It can be understood that, when the first pad 71 is connected between two main body wires 152, the first pad 71 can be coupled with the interconnection structure (for example, a Wheatstone bridge structure) formed by the plurality of main body wires 152, the plurality of first conductive bumps 16 and the plurality of piezoresistors 12, so that when the interconnection structure needs to be coupled to a circuit structure (for example, a readout integrated circuit and / or a control integrated circuit described in detail below), the first pad 71 can be used to couple the interconnection structure with the circuit structure, thereby realizing signal transmission.

[0094] Exemplarily, the first pad 71 can be electrically connected with the circuit structure (for example, a control integrated circuit described in detail below) through a wire bonding (WB) structure.

[0095] In some embodiments, as shown in Figure 1 , Figure 2 and Figure 3A , the plurality of first pads 71 includes an input pad 71A, and an input end of the interconnection structure is coupled with the input pad 71A, so that an external integrated circuit (for example, a control integrated circuit described in detail below) can input a driving signal (for example, a voltage signal) to the interconnection structure to turn on the interconnection structure to realize the function of measuring pressure. In this case, the plurality of first conductive bumps 16 can include at least one first input conductive bump 16A adjacent to the input pad 71A, for example, the number of the first input conductive bump 16A can be two.

[0096] In some examples, the electrical signals generated by the plurality of piezoresistors are processed by a readout integrated circuit. Furthermore, the plurality of first pads further include an output pad, and the output end of the interconnect structure is coupled to the output pad. Thus, the interconnect structure (e.g., a Wheatstone bridge structure) can output an electrical signal (e.g., a voltage signal) to the readout integrated circuit, enabling the readout integrated circuit to process the electrical signals generated by the plurality of piezoresistors. In this case, the readout integrated circuit is located outside the pressure sensor.

[0097] In other examples, the readout integrated circuit is located inside the pressure sensor. The following will exemplarily describe a case where the pressure sensor includes the readout integrated circuit.

[0098] In some embodiments, as Figure 1 、 Figure 4A 、 Figure 5 and Figure 6 As shown, the pressure sensor 100 further includes a second substrate structure 20. The second substrate structure 20 is located on one side of the first substrate structure 10 and is connected to the first substrate structure 10. The second substrate structure 20 includes a second substrate 22 and a readout integrated circuit 21. The readout integrated circuit 21 is integrated within the second substrate 22 and coupled to the plurality of piezoresistors 12. The readout integrated circuit 21 is configured to process electrical signals generated by the plurality of piezoresistors 12.

[0099] Based on the above structure, the operating process of the pressure sensor 100 can be as follows: the pressure-sensitive layer 11 deforms and generates stress under the action of external pressure. The stress causes the resistance of the piezoresistors 12 to change. This resistance change is then converted into an electrical signal through an interconnection structure (for example, a Wheatstone bridge structure) and output to the readout integrated circuit 21. The readout integrated circuit 21 receives the electrical signals generated by the multiple piezoresistors 12 and processes them. The electrical signals processed by the readout integrated circuit 21 can reflect the magnitude of the external pressure, thus realizing the pressure measurement function of the pressure sensor 100.

[0100] For example, the readout integrated circuit 21 (ROIC) can be configured to amplify the electrical signals generated by the plurality of piezoresistors 12 and / or perform differential and other primary signal processing. Figure 6 As shown, the readout integrated circuit 21 includes a signal amplification module, a signal differentiation module, and metal traces connected between the signal amplification module and the signal differentiation module.

[0101] For example, the material of the second liner 22 may be silicon.

[0102] Here, the readout integrated circuit 21 is integrated into the interior of the second substrate 22. As a possible implementation, Figure 5 and Figure 6 As shown, the readout integrated circuit 21 can be manufactured inside the second substrate 22 using an integrated circuit process; in this case, the second substrate 22 can also be called a ROIC backing substrate.

[0103] It can be understood that through the above-mentioned setting, the first substrate structure 10 includes a pressure-sensitive layer 11 and multiple pressure-sensitive resistors 12, and the second substrate structure 20 includes a read-out integrated circuit 21, so that the pressure-sensitive layer 11, multiple pressure-sensitive resistors 12 and the read-out integrated circuit 21 can be distributed on both sides of the pressure sensor 100. In this way, compared with the situation where the pressure-sensitive layer 11, multiple pressure-sensitive resistors 12 and the read-out integrated circuit 21 are all arranged on one side of the pressure sensor 100, the volume of the pressure sensor 100 can be made smaller, which is conducive to the 3D packaging of the pressure sensor 100 and an external integrated circuit (for example, the control integrated circuit described in detail below).

[0104] In some embodiments, as Figure 1 、 Figure 4A and Figure 5 As shown, the second substrate structure 20 further includes a plurality of second conductive bumps 24. The plurality of second conductive bumps 24 are located on a surface of the second substrate 22 adjacent to the first substrate structure 10 and are coupled to the readout integrated circuit 21; at least a portion of the plurality of second conductive bumps 24 correspondingly contact a portion of the plurality of first conductive bumps 16.

[0105] Here, the second conductive bump 24 is coupled to the readout integrated circuit 21. As a possible implementation method, the material of the second liner 22 is silicon. By heavily doping the portion of the second liner 22 that contacts the second conductive bump 24, the second conductive bump 24 and the readout integrated circuit 21 integrated inside the second liner 22 can be coupled. As another possible implementation method, a metal trace that contacts the second conductive bump 24 can be integrated inside the second liner 22, and the second conductive bump 24 and the readout integrated circuit 21 integrated inside the second liner 22 can also be coupled.

[0106] For example, Figure 5As shown, the shape of the second conductive bump 24 can match the shape of the first conductive bump 16 and can be square, rectangular, circular, or elliptical. Moreover, when the shape of the second conductive bump 24 is square or rectangular, the side length L1 of the square or rectangle is in the range of 50 μm to 100 μm, for example, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm. When the shape of the second conductive bump 24 is circular or elliptical, the diameter of the circle or the major axis length of the ellipse is in the range of 50 μm to 100 μm, for example, 50 μm, 62 μm, 70 μm, 81 μm, 90 μm, or 100 μm.

[0107] For example, the material of the second conductive bump 24 may be any one or more combinations of Au, AuSn, AgSn, CuSn, and SnAgCu.

[0108] It should be noted that the phrase "at least a portion of the plurality of second conductive bumps 24 are in corresponding contact with a portion of the plurality of first conductive bumps 16" means that a portion of the plurality of first conductive bumps 16 are in one-to-one contact with at least a portion of the plurality of second conductive bumps 24, while another portion of the plurality of first conductive bumps 16 are not in contact with the second conductive bumps 24. There is no limitation on the number of second conductive bumps 24 in contact with the first conductive bumps 16. In other words, all second conductive bumps 24 may be in contact with the first conductive bumps 16, or a portion of the plurality of second conductive bumps 24 may be in contact with the first conductive bumps 16.

[0109] For example, Figure 1 and Figure 5 As shown, there are eight first conductive bumps 16 and five second conductive bumps 24 , and three of the five second conductive bumps 24 are in one-to-one contact with three of the eight first conductive bumps 16 .

[0110] In some examples, such as Figure 2 、 Figure 5 and Figure 6 As shown, the plurality of first conductive bumps 16 include at least one first output conductive bump 16B, and the second conductive bumps 24 contacting the first conductive bumps 16 include at least one second input conductive bump 24A. The output end of the interconnect structure (e.g., a Wheatstone bridge structure) is coupled to the input end 21A of the readout integrated circuit 21 via the at least one first output conductive bump 16B and the at least one second input conductive bump 24A.

[0111] For example, Figure 2 、 Figure 5 and Figure 6As shown, the number of the first output conductive bumps 16B is two, and the number of the second input conductive bumps 24A is two. Thus, the signal transmitted to the input terminal 21A of the readout integrated circuit 21 is two input signals. The readout integrated circuit 21 can perform differential processing on the electrical signals generated by the multiple varistors 12 based on the two input signals.

[0112] It can be understood that the first output conductive bump 16B and the second input conductive bump 24A can form a connection structure coupled between the input terminal 21A of the readout integrated circuit 21 and the output terminal of the interconnection structure (for example, a Wheatstone bridge structure). In this way, through the connection structure, the interconnection structure can output an electrical signal (for example, a voltage signal) to the readout integrated circuit 21, so that the readout integrated circuit 21 can process the electrical signals generated by multiple varistors 12.

[0113] Moreover, since the first output conductive bump 16B and the second input conductive bump 24A are both through-type connection structures, firstly, the volume of the pressure sensor 100 can be reduced, which is convenient for device integration; secondly, since the first conductive bump 16 is provided on the transmission path between the main wiring 152 and the varistor 12, the first conductive bump 16 and the second conductive bump 24 have a high bonding strength (the bonding method is, for example, eutectic bonding), the connection tightness is high, and the free deformation space is small, so that the thermo-viscoplastic stress and / or thermo-viscoelastic stress of the main wiring 152 can be isolated; thirdly, compared with the planar wiring type interconnection structure in some implementation methods, the bonding strength is high and the reliability is stronger, so that the reliability of the pressure sensor 100 can be improved.

[0114] In some examples, such as Figure 5 and Figure 6 As shown, in addition to the second input conductive bump 24A, the second conductive bump 24 also includes a second output conductive bump 24B, and the output terminal 21B of the readout integrated circuit 21 is coupled to the second output conductive bump 24B. The following will exemplarily describe the case where the second conductive bump 24 also includes the second output conductive bump 24B.

[0115] In some embodiments, as Figures 1-3A and Figure 6As shown, the first substrate structure 10 further includes at least one second through-hole 62, at least one third conductive bump 63, and at least one second conductive layer 64. The at least one second through-hole 62 penetrates the first liner 13, the buried oxide layer 14, and the first insulating layer 17. The at least one third conductive bump 63 is located on the surface of the buried oxide layer 14 away from the first liner 13; the at least one third conductive bump 63 covers the opening of the at least one second through-hole 62; and the at least one third conductive bump 63 contacts a portion of the plurality of second conductive bumps 24. The at least one second conductive layer 64 is disposed in the inner cavity of the at least one second through-hole 62 and is coupled to the at least one third conductive bump 63; the second conductive layer 64 is insulated from the first liner 13.

[0116] Here, at least one third conductive bump 63 contacts correspondingly with a portion of the multiple second conductive bumps 24; as a possible implementation method, at least one third conductive bump 63 contacts correspondingly with a portion of the multiple second conductive bumps 24; in this case, the second conductive bump 24 contacting the third conductive bump 63 can be the second output conductive bump 24B.

[0117] For example, Figures 4A-5 As shown, the number of the second output conductive bump 24B, the third conductive bump 63 , the second through hole 62 , and the second conductive layer 64 are all two.

[0118] It should be understood that Figure 4A As shown, when the third conductive bumps 63 are located on the surface of the buried oxide layer 14 away from the first liner 13 , the third conductive bumps 63 may correspondingly cover the openings of the second through holes 62 close to the buried oxide layer 14 .

[0119] For example, Figure 3A As shown, the shape of the third conductive bump 63 can match the shape of the second conductive bump 24, and can be square, rectangular, circular, or elliptical. Moreover, when the shape of the third conductive bump 63 is square or rectangular, the side length L2' of the square or rectangle is in the range of 50 μm to 100 μm, such as 50 μm, 55 μm, 70 μm, 83 μm, 90 μm, or 100 μm. When the shape of the third conductive bump 63 is circular or elliptical, the diameter of the circle or the major axis length of the ellipse is in the range of 50 μm to 100 μm, such as 50 μm, 60 μm, 70 μm, 81 μm, 95 μm, or 100 μm.

[0120] For example, the material of the third conductive bump 63 may be any one or more combinations of Au, AuSn, AgSn, CuSn, and SnAgCu.

[0121] Here, at least one second conductive layer 64 is correspondingly disposed in the inner cavity of at least one second through hole 62 and is correspondingly coupled to at least one third conductive bump 63; as a possible implementation, Figure 4A 、 Figure 2 and Figure 3A As shown, at least one second conductive layer 64 is disposed in the inner cavity of at least one second through hole 62 in a one-to-one correspondence, and at least one second conductive layer 64 is coupled to at least one third conductive bump 63 in a one-to-one correspondence.

[0122] Exemplarily, the material of the second conductive layer 64 may be a low resistivity material, such as any one or more combinations of Al, Ti / Al, Au, and Cr / Au, so that a good circuit path can be formed.

[0123] Here, the second conductive layer 64 is insulated from the first substrate 13; as a possible implementation, Figure 4A As shown, a fourth insulating layer 65 (e.g., an oxidized insulating layer) can be provided on the sidewalls of the second through-hole 62, so that the second conductive layer 64 is formed on a side of the fourth insulating layer 65 away from the sidewalls of the second through-hole 62. In some examples, the second conductive layer 64 is also formed on the surface of the third conductive bump 63 exposed in the second through-hole 62.

[0124] It can be understood that, through the above arrangement, the second output conductive bump 24B, the third conductive bump 63 and the second conductive layer 64 can form an output terminal 21B coupled to the readout integrated circuit 21 (see FIG. 21B ). Figure 6 ) connection structure, and through this connection structure, the processed electrical signal can be output to an external integrated circuit (for example, a control integrated circuit described in detail below), so that the transmission of pressure measurement data can be achieved.

[0125] Moreover, since the second output conductive bump 24B, the third conductive bump 63 and the second conductive layer 64 are a through-type interconnection structure, firstly, the volume of the pressure sensor 100 can be reduced, which facilitates device integration and is beneficial to the 3D packaging of the pressure sensor 100 and an external integrated circuit (for example, a control integrated circuit described in detail below); secondly, compared with the planar routing interconnection structure in some implementation methods, the bonding strength is high and the reliability is stronger, thus, the reliability of the pressure sensor 100 can be improved.

[0126] In some embodiments, as Figures 1-3A As shown, the first substrate structure 10 further includes at least one second pad 72 . The at least one second pad 72 is located on a surface of the first insulating layer 17 away from the first liner 13 ; and the at least one second pad 72 is coupled to the at least one second conductive layer 64 .

[0127] Here, asFigures 1-3A As shown, at least one second pad 72 is coupled to at least one second conductive layer 64 in correspondence. As a possible implementation, at least one second pad 72 is coupled to at least one second conductive layer 64 in a one-to-one correspondence through a metal trace.

[0128] For example, Figure 2 and Figure 3A As shown, when there are two second conductive layers 64 , there are two second pads 72 , and the two second pads 72 are arranged opposite to each other.

[0129] Exemplarily, the material of the second pad 72 may be a low-resistivity material, such as any one or more combinations of Al, Ti / Al, Au, and Cr / Au, so that a good circuit path can be formed.

[0130] For example, the second pad 72 may be electrically connected to a circuit structure (eg, a control integrated circuit described in detail below) through a wire bonding (WB) structure.

[0131] It can be understood that when at least one second pad 72 is coupled to at least one second conductive layer 64, the processed electrical signal can be output to an external integrated circuit (for example, a control integrated circuit described in detail below) using the second pad 72, thereby realizing the transmission of pressure measurement data.

[0132] In some examples, such as Figure 1 and Figure 6 As shown, to improve the safety of pressure sensor 100, pressure sensor 100 also requires access to a ground signal. Specifically, the ground terminal of the interconnect structure and the ground terminal 21C of the readout integrated circuit 21 must be grounded to achieve a ground connection for pressure sensor 100. The ground connection structure of pressure sensor 100 is described below as an example.

[0133] In some embodiments, as Figure 1 、 Figure 2 、 Figure 3A and Figure 5 As shown, the plurality of first pads 71 ​​include a ground pad 71C. The plurality of first conductive bumps 16 include a first ground conductive bump 16C. The plurality of second conductive bumps 24 include a second ground conductive bump 24C. The ground pad 71C, the first ground conductive bump 16C, and the second ground conductive bump 24C are coupled.

[0134] For example, Figure 3AAs shown, the ground pad 71C and the input pad 71A are located at two opposite corners of the first substrate structure 10. In this case, the pressure sensor 100 may further include two dummy pads 73, and the two dummy pads 73 are disposed at the other two corners of the first substrate structure 10. In this way, when the pressure sensor 100 is integrated, the force is more balanced, which can improve the structural stability of the pressure sensor 100.

[0135] It can be understood that the first ground conductive bump 16C, the second ground conductive bump 24C, and the ground pad 71C can form a ground structure coupled to the pressure sensor 100 to achieve a ground connection for the pressure sensor 100. Specifically, the ground terminal 21C of the readout integrated circuit 21 is grounded via the ground pad 71C, the first ground conductive bump 16C, and the second ground conductive bump 24C; and the ground terminal of the interconnect structure (e.g., a Wheatstone bridge structure) is grounded via the ground pad 71C.

[0136] In some examples, the pressure sensor further includes an annular encapsulation layer located between the first substrate structure and the second substrate structure. Thus, the encapsulation layer can be used to encapsulate the first and second substrate structures. The encapsulation layer is made of, for example, encapsulant.

[0137] In some embodiments, as Figure 1 、 Figure 4A and Figure 5 As shown, the second substrate structure 20 further includes a second insulating layer 23 located on a surface of the second liner 22 proximate to the first substrate structure 10; a plurality of second conductive bumps 24 extend through the second insulating layer 23. A solder ring 30 is disposed between opposing surfaces of the buried oxide layer 14 and the second insulating layer 23; the varistor 12, the plurality of first conductive bumps 16, and the at least one third conductive bump 63 are located inside the solder ring 30 and are spaced apart from the solder ring 30.

[0138] Exemplarily, the material of the second insulating layer 23 is an insulating material, such as any one or more combinations of SiO 2 , SiN and glass.

[0139] It should be understood that when a welding ring 30 is provided between the relative surfaces of the buried oxide layer 14 and the second insulating layer 23, the first liner 13 located inside the welding ring 30 can be part of the portion of the pressure-sensitive layer 11 used to sense pressure changes. This is because the first liner 13 located inside the welding ring 30 can be deformed and generate stress.

[0140] For example, Figure 4AAs shown, the thickness D3 of the solder ring 30 may range from 20 μm to 120 μm, such as 20 μm, 40 μm, 60 μm, 85 μm, 100 μm or 120 μm, etc. In this way, the packaging effect of the first substrate structure 10 and the second substrate structure 20 can be improved.

[0141] In some examples, the solder ring is formed on a surface of the buried oxide layer away from the first liner, and is fixedly contacted with a surface of the second insulating layer away from the second liner through packaging processes of the first and second substrate structures.

[0142] In other examples, the solder ring is formed on the surface of the second insulating layer away from the second liner, and the solder ring is fixedly contacted with the surface of the buried oxide layer away from the first liner through the packaging process of the first substrate structure and the second substrate structure.

[0143] In some other examples, such as Figure 4A As shown, the solder ring 30 is composed of a first solder ring 31 and a second solder ring 32. The first solder ring 31 is disposed on the surface of the buried oxide layer 14 away from the first substrate 13, with a distance between the first solder ring 31 and the varistor 12, the plurality of lead traces 152, the plurality of first conductive bumps 16, and the at least one third conductive bump 63. The second solder ring 32 is disposed on the surface of the second insulating layer 23 away from the second substrate 22, and matches the shape and position of the first solder ring 31. The solder ring 30 is formed by contacting and fixing the first and second solder rings 31 and 32, for example, by a high-temperature melting process.

[0144] In this case, if Figure 4A 、 Figure 2 and Figure 5 As shown, while the first and second solder rings 31 and 32 are in contact and fixed, the second input conductive bump 24A is in contact and fixed with the first output conductive bump 16B, thereby achieving coupling between the second input conductive bump 24A and the first output conductive bump 16B. If the pressure sensor 100 also includes at least one third conductive bump 63, the at least one third conductive bump 63 is in contact and fixed with the second output conductive bump 24B. If the pressure sensor 100 also includes a grounding structure, the first grounding conductive bump 16C is in contact and fixed with the second grounding conductive bump 24C. In one possible implementation, the thickness of the first solder ring 31 is the same as the height of the first conductive bump 16, and the height of the first conductive bump 16 is the same as the height of the third conductive bump 63. The thickness of the second solder ring 32 is the same as the sum of the height of the second conductive bump 24 and the thickness of the second insulating layer 23. This ensures the bonding strength between the first and second solder rings 31 and 32, while also ensuring the reliability of the interconnection between the second conductive bump 24 and the first conductive bump 16.

[0145] For example, Figure 4A As shown, when the solder ring 30 is composed of a first solder ring 31 and a second solder ring 32, the thickness of the first solder ring 31 and the thickness of the second solder ring 32 can be the same or different. The thickness L4 of the first solder ring 31 can be in the range of 10 μm to 60 μm, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, or 60 μm. The thickness L5 of the second solder ring 32 can be in the range of 10 μm to 60 μm, for example, 10 μm, 21 μm, 30 μm, 40 μm, 50 μm, or 60 μm. In this way, the packaging effect of the first substrate structure 10 and the second substrate structure 20 can be improved.

[0146] For example, Figure 4A As shown, when the solder ring 30 is composed of a first solder ring 31 and a second solder ring 32, a distance L6 between the inner edge of the first solder ring 31 and the first conductive bump 16 and / or the third conductive bump 63 is greater than or equal to 50 μm, such as 50 μm, 60 μm, 74 μm, 80 μm, 90 μm, or 100 μm. This allows for no electrical connection between the first solder ring 31 and the first conductive bump 16, and between the first solder ring 31 and the third conductive bump 63. A distance L7 between the inner edge of the second solder ring 32 and the second conductive bump 24 is greater than or equal to 50 μm, such as 50 μm, 60 μm, 75 μm, 82 μm, 90 μm, or 110 μm. This allows for no electrical connection between the second solder ring 32 and the second conductive bump 24.

[0147] Exemplarily, the material of the solder ring 30 may be eutectic solder, such as a combination of one or more of AuSn, AgSn, CuSn, and SnAgCu.

[0148] For example, Figure 4A As shown, the width L8 of the solder ring 30 is greater than or equal to 600 μm, such as 600 μm, 650 μm, 700 μm, 750 μm, 810 μm or 900 μm, etc. In this way, the packaging effect of the first substrate structure 10 and the second substrate structure 20 can be improved.

[0149] For example, Figure 4A As shown, the size of the first liner 13 is consistent with the size of the buried oxide layer 14, and the distance L9 between the outer boundary of the welding ring 30 and the boundary of the buried oxide layer 14 is greater than or equal to 50μm, for example, 50μm, 60μm, 70μm, 75μm, 80μm or 90μm, etc. In this way, the material of the welding ring 30 can be prevented from flowing to the outside of the surface of the buried oxide layer 14 away from the first liner 13 during the packaging process.

[0150] As can be understood, by including the solder ring 30 in the pressure sensor 100, the first substrate structure 10, the second substrate structure 20, and the solder ring 30 can enclose a main cavity N. Thus, when the pressure-sensitive layer 11 senses a change in pressure, stress is generated in response to the pressure and transmitted to the piezoresistor 12, thereby achieving the pressure measurement function. Furthermore, this improves the feasibility of packaging the first substrate structure 10 and the second substrate structure 20.

[0151] In some embodiments, as Figure 1 、 Figure 4A and Figure 5 As shown, the second substrate structure 20 further includes a plurality of support bumps 25. The plurality of support bumps 25 are located on a surface of the second insulating layer 23 adjacent to the first substrate structure 10. Among the plurality of first conductive bumps 16, the first conductive bumps 16 other than the first conductive bump 16 coupled to the second conductive bump 24 are in contact with the plurality of support bumps 25.

[0152] It should be understood that when the plurality of support bumps 25 are located on the surface of the second insulating layer 23 close to the first substrate structure 10 , the plurality of support bumps 25 are insulated from the second liner 22 , that is, the support bumps 25 are not electrically connected to the readout integrated circuit.

[0153] For example, Figure 1 , Figure 4 and Figure 5 As shown, the number of the first conductive bumps 16 is eight, the number of the third conductive bumps 63 is two, the number of the second conductive bumps 24 is five, and the number of the supporting bumps 25 is five.

[0154] It should be understood that when the pressure sensor 100 further includes a welding ring 30, and the welding ring 30 is composed of a first welding ring 31 and a second welding ring 32, the thickness of the second welding ring 32 can be the same as the height of the supporting bump 25, so that the bonding strength of the first welding ring 31 and the second welding ring 32 can be guaranteed.

[0155] For example, Figure 1 、 Figure 4A and Figure 5 As shown, the shape of the support bump 25 can match the shape of the first conductive bump 16, and can be square, rectangular, circular, or elliptical. Moreover, when the support bump 25 is square or rectangular, the side length L3' of the square or rectangle is in the range of 50 μm to 100 μm, such as 50 μm, 60 μm, 70 μm, 83 μm, 90 μm, or 100 μm. When the support bump 25 is circular or elliptical, the diameter of the circle or the major axis length of the ellipse is in the range of 50 μm to 100 μm, such as 50 μm, 60 μm, 70 μm, 80 μm, 95 μm, or 100 μm.

[0156] As mentioned above, in some examples, the number of first conductive bumps 16 is greater than the number of second conductive bumps 24. In this case, by providing the second substrate structure 20 with a plurality of supporting bumps 25, the other first conductive bumps 16 except the first conductive bumps 16 coupled to the second conductive bumps 24 can be in corresponding contact with the plurality of supporting bumps 25. In this way, firstly, the bonding strength between the first conductive bumps 16 and the plurality of supporting bumps 25 can be higher (the bonding method is, for example, eutectic bonding), the connection tightness is higher, and the free deformation space is small. In this way, the thermo-viscoplastic stress and / or thermo-viscoelastic stress of the main trace 152 and the thermal mismatch stress of the shell and tube introduced by the wire bonding structure that may exist on the second side 11B of the pressure-sensitive layer 11 can be isolated, thereby reducing thermal hysteresis. Secondly, the force on the second substrate structure 20 can be made more balanced, thereby improving the structural stability of the pressure sensor 100.

[0157] In some embodiments, as Figure 4A As shown, the first substrate structure 10 and the second substrate structure 20 enclose a vacuum cavity N1 ; a plurality of varistors 12 are located inside the vacuum cavity N1 .

[0158] Exemplarily, when the pressure sensor 100 further includes a solder ring 30 , the first substrate structure 10 , the second substrate structure 20 , and the solder ring 30 enclose a vacuum cavity N1 .

[0159] It can be understood that the vacuum cavity N1 is the aforementioned main cavity N. Moreover, when the first substrate structure 10 and the second substrate structure 20 enclose the vacuum cavity N1, the pressure sensor 100 is an absolute pressure pressure sensor, which can measure the absolute value of the pressure change and has the advantages of high precision and a large measurement range.

[0160] In some embodiments, as Figure 1 、 Figure 4A and Figure 5 As shown, when the first substrate structure 10 and the second substrate structure 20 enclose a vacuum cavity N1 , the pressure sensor 100 further includes a getter sheet 40 located in the vacuum cavity N1 .

[0161] For example, Figure 1 and Figure 5 As shown, the getter sheet 40 is a square getter sheet disposed on a surface of the second insulating layer 23 away from the second liner 22 . Furthermore, the area of ​​the getter sheet 40 is smaller than the area of ​​the pressure sensing portion S. In some examples, the geometric center of the getter sheet 40 is collinear with the geometric center of the pressure sensing portion S.

[0162] For example, Figure 1 and Figure 5As shown, when the getter sheet 40 is disposed on a surface of the second insulating layer 23 away from the second liner 22, the distance L10 between the second conductive bump 24 closest to the getter sheet 40 and the getter sheet 40 is greater than or equal to 50 μm, such as 50 μm, 60 μm, 70 μm, 75 μm, 80 μm, or 100 μm. This prevents the getter sheet 40 and the second conductive bump 24 from connecting with each other during use of the pressure sensor 100, thereby preventing the pressure sensor 100 from being used.

[0163] It can be understood that since the pressure sensor 100 also includes an air-getter sheet 40 located in the vacuum cavity N1, the air-getter sheet 40 can be used to absorb gas that may enter the vacuum cavity N1 during the use of the pressure sensor 100, so that the vacuum cavity N1 maintains a high vacuum degree.

[0164] Here, there is no limitation on the material of the getter sheet 40 , as long as it can absorb the gas that may enter the vacuum cavity N1 during use of the pressure sensor 100 and maintain the vacuum degree of the vacuum cavity N1 .

[0165] In some embodiments, as Figure 3B and Figure 7 As shown, a third through hole 50 is opened in the middle of the second lining 22 and the middle of the second insulating layer 23; the first substrate structure 10 and the second substrate structure 20 enclose a gauge pressure cavity N2; and a plurality of varistors 12 are located inside the gauge pressure cavity N2.

[0166] Exemplarily, when the pressure sensor 100 further includes a welding ring 30 , the first substrate structure 10 , the second substrate structure 20 , and the welding ring 30 enclose a gauge pressure cavity N2 .

[0167] Here, there is no limitation on the size of the through hole 50. In some examples, such as Figure 7 As shown, the aperture L11 of the through hole 50 ranges from 0 to 100 μm, for example, 0 μm, 10 μm, 30 μm, 50 μm, 70 μm or 100 μm.

[0168] Illustratively, a fifth insulating layer (not shown in the figure) may be provided on the sidewall of the through hole, thereby improving the safety and reliability of the pressure sensor.

[0169] It can be understood that the gauge pressure cavity N2 is the aforementioned main cavity N. The through hole 50 can be used to connect the gauge pressure cavity N2 to the external atmospheric environment, so that the pressure of the gauge pressure cavity N2 is equal to the external pressure. Moreover, when the first substrate structure 10 and the second substrate structure 20 are enclosed to form the gauge pressure cavity N2, the pressure sensor 100 is a gauge pressure type pressure sensor, which can be measured with atmospheric pressure as a reference object. It has the advantage of being easy to prepare and can be used to measure the relative pressure change values ​​of media such as water pressure and air pressure.

[0170] The following describes an exemplary method for preparing the pressure sensor 100 by taking the case where the pressure sensor 100 is an absolute pressure type pressure sensor as an example.

[0171] In some embodiments, a method for preparing the pressure sensor 100 includes S1:

[0172] S1: Forming a first substrate structure 10. The first substrate structure 10 includes a pressure-sensitive layer 11, a plurality of piezoresistors 12, and a plurality of interconnecting traces 15. The plurality of piezoresistors 12 are located on a first side 11A of the pressure-sensitive layer 11; the plurality of piezoresistors 12 are configured to generate electrical signals based on changes in pressure sensed by the pressure-sensitive layer 11. The plurality of interconnecting traces 15 are at least partially located on a second side 11B of the pressure-sensitive layer 11, the second side 11B of the pressure-sensitive layer 11 being opposite the first side 11A of the pressure-sensitive layer 11; the plurality of interconnecting traces 15 are configured to couple the plurality of piezoresistors 12 to each other.

[0173] In some examples, such as Figure 8 As shown, forming a first substrate structure 10 includes S1.1 to S1.3:

[0174] S1.1: Provide a first liner 13 and a buried oxide layer 14.

[0175] S1.2: forming a plurality of varistors 12 on the surface of the buried oxide layer 14 away from the first substrate 13 .

[0176] In some examples, after forming the plurality of varistors 12 on the surface of the buried oxide layer 14 away from the first liner 13 , a plurality of lead traces 151 are further formed on the surface of the buried oxide layer 14 away from the first liner 13 .

[0177] In some examples, the varistor 12 is a doped silicon varistor, and the process of forming the varistor 12 can be an ion implantation process or a process combining a diffusion process and an etching process to form the varistor 12 of a set shape.

[0178] In other examples, the varistor 12 may be a metal film varistor, and the process for forming the varistor 12 is a combination of a metal sputtering process and an etching process.

[0179] S1.3: forming a plurality of first conductive bumps 16 and a first bonding ring 31 on a surface of the buried oxide layer 14 away from the first substrate 13 .

[0180] In some examples, the preparation of multiple varistors 12, multiple lead traces 151, multiple first conductive bumps 16, and first solder ring 31 is completed through multiple steps. At this time, a mask can be used to expose the target area and block other areas except the target area.

[0181] In some examples, the third conductive bump 63 is formed simultaneously with the formation of the first conductive bump 16 .

[0182] In some examples, when the pressure sensor 100 further includes a second substrate structure 20, the method for preparing the pressure sensor 100 further includes S2: forming the second substrate structure 20. For example, Figure 8 As shown, before step S1.1, steps S2.1 to S2.3 are also included:

[0183] S2.1: Provide a second substrate 22, with a readout integrated circuit (not shown) fabricated inside the second substrate 22.

[0184] S2.2: Form a second insulating layer 23 on the surface of the second substrate 22 .

[0185] S2.3: forming a plurality of second conductive bumps 24 penetrating the second insulating layer 23 , and forming a second solder ring 32 on a surface of the second insulating layer 23 away from the second liner 22 .

[0186] For example, the process for forming the plurality of second conductive bumps 24 may be: opening holes in a predetermined area of ​​the second insulating layer 23, and then forming the plurality of second conductive bumps 24 in the opening area. The process for forming the plurality of second conductive bumps 24 in the opening area may be any one of a sputtering process, an evaporation process, an etching process, a lift-off process, and a ball implantation process.

[0187] In some examples, the preparation of the plurality of second conductive bumps 24 and the second solder ring 32 is completed in two steps. At this time, a mask can be used to expose the target area and block other areas except the target area.

[0188] In some examples, when the second substrate structure 20 further includes a plurality of supporting bumps 25 , after step S2.3, the following step is further included:

[0189] S2.4: Form a plurality of supporting bumps 25 on a surface of the second insulating layer 23 away from the second substrate 22 .

[0190] For example, the process of forming the plurality of supporting bumps 25 in the designated area of ​​the second insulating layer 23 may be any one of a sputtering process, an evaporation process, an etching process, a lift-off process and a ball implantation process.

[0191] It should be understood that the above steps S2.1 to S2.3 may be completed after step S1.3; that is, the order of forming the first substrate structure 10 and forming the second substrate structure 20 is not limited here.

[0192] In some examples, such as Figure 8 As shown, after step S1.3, the method for preparing the pressure sensor 100 further includes step S3:

[0193] S3: Bonding the first substrate structure 10 and the second substrate structure 20 .

[0194] In some examples, when the first thickness D1 and the second thickness D2 are consistent, as shown in FIG. Figure 8 As shown, after step S3, the method for preparing the pressure sensor 100 further includes step S4:

[0195] S4: The entire surface of the first backing sheet 13 is thinned, so that a portion of the first backing sheet 13 constituting the portion of the pressure-sensitive layer 11 for sensing pressure changes is reduced.

[0196] In some examples, when the first substrate structure 10 further includes the first through hole 18 and the second through hole 62, as shown in FIG. Figure 8 As shown, after step S4, the method for preparing the pressure sensor 100 further includes steps S5 to S7:

[0197] S5: Form a plurality of first through holes 18 and at least one second through hole 62 penetrating the first liner 13 and the buried oxide layer 14 on the first substrate structure 10, so that the plurality of first through holes 18 correspond to the positions of the plurality of first conductive bumps 16; and the plurality of second through holes 62 correspond to the positions of the plurality of third conductive bumps 63.

[0198] Exemplarily, the process of forming the plurality of first through-holes 18 and the at least one second through-hole 62 is, for example, a through silicon via (TSV) process.

[0199] S6: An insulating structure is formed on the sidewalls of the plurality of first through-holes 18, on the sidewalls of the at least one second through-hole 62, and on the surface of the first liner 13 away from the buried oxide layer 14, to passivate the sidewalls of the plurality of first through-holes 18 and the at least one second through-hole 62. It should be understood that the insulating structure includes the plurality of third insulating layers 61, the at least one fourth insulating layer 65, and the first insulating layer 17.

[0200] S7: A conductive structure is formed on the surfaces of the plurality of third insulating layers 61 away from the first through-holes 18, the surface of the at least one fourth insulating layer 65 away from the second through-holes 62, and the surface of the first insulating layer 17 away from the first liner 13. It should be understood that the conductive structure includes the plurality of first conductive layers 19, the at least one second conductive layer 64, and the main trace 152.

[0201] In some examples, in step S7 , a first pad 71 and a second pad 72 are further formed.

[0202] It can be understood that the above preparation method is simple in process and can reduce the manufacturing cost of the pressure sensor 100 .

[0203] It should be noted that the preparation methods listed above are examples of preparation methods of the pressure sensor 100 , and are not limitations of the preparation methods of the pressure sensor 100 .

[0204] like Figure 9 As shown, some embodiments of the present disclosure further provide a pressure sensing device 200. The pressure sensing device 200 includes a pressure sensor 100 provided by the above technical solution and a control integrated circuit 210. The control integrated circuit 210 is coupled to multiple piezoresistors (not shown) and is also coupled to a readout integrated circuit.

[0205] The beneficial effects that can be achieved by the pressure sensing device 200 provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the pressure sensor 100 provided by the above technical solution, and will not be repeated here.

[0206] It can be understood that when the control integrated circuit 210 is coupled to multiple piezoresistors, the control integrated circuit 210 can input a driving signal (for example, a voltage signal) to the piezoresistors or the interconnection structure; when the control integrated circuit 210 is coupled to a readout integrated circuit, the readout integrated circuit can output the processed electrical signal to the control integrated circuit 210, thereby realizing the transmission of pressure measurement data.

[0207] In some examples, such as Figure 1 and Figure 9 As shown, the control integrated circuit 210 is disposed on a circuit board, and the first pad 71 and the second pad 72 are connected to the circuit board via a wire bonding (WB) structure, thereby achieving coupling between the pressure sensor 100 and the control integrated circuit 210 .

[0208] like Figure 10 As shown, some embodiments of the present disclosure further provide an electronic device 300. The electronic device 300 includes a housing 310 and a pressure sensing device 200 provided by the above technical solution and disposed on the housing 310.

[0209] The beneficial effects that can be achieved by the electronic device 300 provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the pressure sensing device 200 provided by the above technical solution, and will not be repeated here.

[0210] In some examples, the electronic device 300 may be a mobile phone, a computer, or a portable electronic device, so that the pressure sensor 100 can be applied to technical scenarios such as automobiles and process production that require pressure measurement.

[0211] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pressure sensor, characterized in that: The invention comprises a first substrate structure, wherein the first substrate structure comprises: A pressure-sensitive layer; a portion of the pressure-sensitive layer for sensing pressure changes; a plurality of piezoresistors located on a first side of the pressure-sensitive layer; the plurality of piezoresistors being configured to: generate an electrical signal based on a pressure change sensed by the pressure-sensitive layer; and a plurality of interconnecting traces, at least partially located on a second side of the pressure-sensitive layer, the second side of the pressure-sensitive layer being opposite to the first side of the pressure-sensitive layer; the plurality of interconnecting traces being configured to: couple the plurality of varistors to each other; a plurality of first conductive bumps, each of the first conductive bumps being coupled to one of the piezoresistors; The pressure sensor further includes a second substrate structure; the second substrate structure is located on one side of the first substrate structure and is connected to the first substrate structure; the second substrate structure includes: a second lining; a readout integrated circuit, integrated in the interior of the second substrate and coupled to the plurality of piezoresistors, the readout integrated circuit being configured to at least: process electrical signals generated by the plurality of piezoresistors; and A plurality of second conductive bumps are located on a surface of the second liner close to the first substrate structure and coupled to the readout integrated circuit; at least part of the plurality of second conductive bumps are in corresponding contact with a part of the plurality of first conductive bumps.

2. The pressure sensor according to claim 1, wherein The plurality of interconnection traces include lead traces located on a first side of the pressure-sensitive layer and main traces located on a second side of the pressure-sensitive layer; The pressure-sensitive layer comprises: a first lining sheet; and a buried oxide layer disposed on one side of the first liner; the first liner is closer to the second side of the pressure-sensitive layer than the buried oxide layer; Among them, the multiple varistors are located on the surface of the buried oxide layer away from the first liner, and are arranged at intervals around the center of the buried oxide layer; the main wiring is arranged on the side of the first liner away from the buried oxide layer; the orthographic projection of the main wiring on the surface of the buried oxide layer away from the first liner is located outside the area enclosed by the multiple varistors.

3. The pressure sensor according to claim 2, wherein: The surface of the first liner away from the buried oxide layer has a groove recessed toward the buried oxide layer; or, The first lining includes an opening in the middle.

4. The pressure sensor according to claim 2, wherein: The portion of the pressure-sensitive layer used to sense pressure changes includes the middle portion of the first lining; in the first lining, the portion used to sense pressure changes has a first thickness, and the remaining portion has a second thickness; the first thickness is consistent with the second thickness.

5. The pressure sensor according to claim 2, wherein: The first substrate structure further includes: a first insulating layer, disposed on the second surface of the first liner; The main wiring is arranged on a surface of the first insulating layer away from the first lining.

6. The pressure sensor according to claim 5, characterized in that The first substrate structure further includes: a plurality of first through holes penetrating the first liner, the buried oxide layer, and the first insulating layer; the plurality of first through holes being located outside the region enclosed by the plurality of varistors; a plurality of first conductive bumps being located on a surface of the buried oxide layer away from the first liner; the plurality of first conductive bumps correspondingly covering openings of the plurality of first through holes; and, a plurality of first conductive layers, correspondingly disposed in the inner cavities of the plurality of first through holes and correspondingly coupled to the plurality of first conductive bumps; the first conductive layers are insulated from the first liner; The main body wiring is coupled to the plurality of varistors through the plurality of first conductive bumps and the plurality of first conductive layers.

7. The pressure sensor according to claim 5, characterized in that The first substrate structure further includes: A plurality of first pads are located on a surface of the first insulating layer away from the first liner; the first pads are connected between two of the main traces.

8. The pressure sensor according to claim 6, wherein: The first substrate structure further includes: at least one second through hole, passing through the first liner, the buried oxide layer, and the first insulating layer; At least one third conductive bump is located on a surface of the buried oxide layer away from the first liner; the at least one third conductive bump covers an opening of the at least one second through hole; the at least one third conductive bump contacts a portion of the plurality of second conductive bumps; and At least one second conductive layer is correspondingly disposed in the inner cavity of the at least one second through hole and is correspondingly coupled to the at least one third conductive bump; the second conductive layer is insulated from the first liner.

9. The pressure sensor according to claim 8, characterized in that The first substrate structure further includes: At least one second pad is located on a surface of the first insulating layer away from the first liner; the at least one second pad is coupled to the at least one second conductive layer accordingly.

10. The pressure sensor according to claim 8, wherein The first substrate structure further includes: A plurality of first pads are located on a surface of the first insulating layer away from the first liner; the first pads are connected between two of the main traces; The plurality of first pads include a ground pad, the plurality of first conductive bumps include a first ground conductive bump, the plurality of second conductive bumps include a second ground conductive bump, and the ground pad, the first ground conductive bump and the second ground conductive bump are coupled.

11. The pressure sensor according to claim 8, characterized in that The second substrate structure further includes a second insulating layer located on a surface of the second liner close to the first substrate structure; the plurality of second conductive bumps penetrate the second insulating layer; A solder ring is provided between the opposite surfaces of the buried oxide layer and the second insulating layer; the varistor, the plurality of first conductive bumps, and the at least one third conductive bump are located inside the solder ring and are spaced apart from the solder ring.

12. The pressure sensor according to claim 11, wherein The second substrate structure further includes: A plurality of supporting bumps are located on the surface of the second insulating layer close to the first substrate structure; among the plurality of first conductive bumps, other first conductive bumps except the first conductive bump coupled to the second conductive bump are in corresponding contact with the plurality of supporting bumps.

13. The pressure sensor according to claim 11, wherein The first substrate structure and the second substrate structure enclose a vacuum cavity; the plurality of varistors are located inside the vacuum cavity; or, A third through hole is formed in the middle of the second lining and the middle of the second insulating layer; the first substrate structure and the second substrate structure are combined to form a gauge pressure cavity; and the multiple varistors are located inside the gauge pressure cavity.

14. The pressure sensor according to claim 13, wherein: In a case where the first substrate structure and the second substrate structure are enclosed to form a vacuum cavity, the pressure sensor further includes a getter sheet located in the vacuum cavity.

15. A pressure sensing device, characterized in that: The pressure sensor according to any one of claims 1 to 14; further comprising: A control integrated circuit is coupled to the plurality of pressure-sensitive resistors; and when the pressure sensor further includes a readout integrated circuit, the control integrated circuit is also coupled to the readout integrated circuit.

16. An electronic device, characterized in that: The device comprises a housing and the pressure sensing device according to claim 15 which is arranged on the housing.

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