A short-circuit failure model time domain evaluation method based on safe working area of IGBT device
By utilizing the overlap ratio of voltage and current curves during short circuits within the safe operating area of IGBT devices, the accuracy problem of IGBT short-circuit failure models is solved, improving the design efficiency of devices such as frequency converters and reducing R&D costs.
Patent Information
- Application Number
- CN202410212371.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2044-02-27
AI Technical Summary
The lack of existing technology for quantitative accuracy assessment of IGBT device short-circuit failure models makes it impossible to effectively assess the short-circuit failure characteristics of IGBT devices under all operating conditions of devices such as frequency converters.
By using the overlap of the area of the phase plane curve composed of the collector-emitter voltage Vce and the collector current Ic during the short-circuit process within the safe operating area of the IGBT device as a quantitative indicator of the short-circuit failure model, the consistency between the simulation model and the actual device test is evaluated.
It provides clear quantitative indicators, improves the evaluation capability of IGBT short-circuit failure models, supports full-condition design of devices such as frequency converters, and reduces R&D cycle and cost.
Smart Images
Figure CN118095177B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically a time-domain evaluation method based on a short-circuit failure model of the safe operating region of IGBT devices. Background Technology
[0002] IGBTs, semiconductor devices, possess advantages such as high reliability, simple driving, easy protection, no need for buffer circuits, high switching frequency, voltage-driven operation, low drive power, low saturation voltage drop, and high withstand voltage, making them the most widely used power electronic switching devices in medium and high power frequency converters. However, during use, IGBTs are easily damaged in the event of a short circuit. To address this, numerous studies have simulated and modeled the short-circuit failure process of IGBTs, and in the model verification process, a simple comparison of the overlap between the simulated and measured voltage and current waveforms during the short circuit process has been made. However, this approach, lacking quantitative indicators, cannot effectively evaluate the accuracy of the model.
[0003] In the short-circuit failure process of IGBT devices, to ensure that the device is not damaged, it is necessary to follow the safe operating area of the IGBT device, including: the forward bias safe operating area, the reverse bias safe operating area, and the short-circuit safe operating area. To this end, this patent combines the short-circuit safe operating area of the device with the voltage and current waveforms of the device's switching transient process during a short circuit to form an evaluation index within the device's safe operating area.
[0004] IGBT transient models can analyze voltage and current stress changes during normal IGBT turn-on and turn-off, and can also simulate short-circuit failure processes. Therefore, applying this model in simulation experiments of devices such as frequency converters allows for better analysis of electrical stress changes in IGBT devices under various operating conditions, providing guidance for IGBT device selection and circuit design during device design. Currently, there is a lack of quantifiable accuracy indicators for IGBT short-circuit failure simulation models. Most literature only visually compares the peak values and slopes of voltage and current curves during the short-circuit failure process to determine the quality of the established IGBT short-circuit failure simulation model. This comparison without quantitative indicators is sufficient when the frequency converter is under normal steady-state operation, but once the frequency converter is under full operating conditions, especially when studying the switching characteristics of IGBT devices during short-circuit processes, it cannot intuitively and comprehensively reflect the accuracy of the short-circuit failure model. Summary of the Invention
[0005] To address the aforementioned problems, this invention provides a time-domain evaluation method for short-circuit failure models based on the safe operating region of IGBT devices.
[0006] This invention adopts the following technical solution: a time-domain evaluation method for short-circuit failure models based on the safe operating region of IGBT devices, comprising:
[0007] S1: Obtain the voltage V obtained from simulation model testing and actual device testing during the short-circuit failure process of the IGBT device. ce and current I c ;
[0008] S2: Based on the voltage V in S1 ce and current I c The voltage V obtained from the simulation model test and the actual device test is obtained. ce With current I c The phase plane curves formed;
[0009] S3: The area enclosed by the phase plane curves tested according to the simulation model. 仿真 The area S enclosed by the phase plane curve of the actual device test 实 The degree of overlap is used to determine the accuracy of the short-circuit failure model.
[0010] In some embodiments, in step S3, the area S enclosed by the phase plane curve tested by the simulation model is... 仿真 The area S enclosed by the phase plane curve of the actual device test 实 The higher the degree of overlap, the higher the accuracy of the short-circuit failure model, and the better it matches the actual short-circuit failure characteristics of the device.
[0011] In some embodiments, step S3 specifically includes:
[0012] S31: Determine the safe operating area of the IGBT device short-circuit failure process in the phase plane curve coordinate system;
[0013] S32: If the voltage V in the simulation model test and the actual device test is different... ce With current I c If the phase plane curve is within the safe operating area, proceed to the next step;
[0014] S33: Calculate the area S enclosed by the phase plane curves of the simulation model test. 仿真 And the area S enclosed by the phase plane curve of the actual device test 实 ;
[0015] S34: Calculate S 仿真 With S 实 The overlap ratio is used to determine the accuracy of the short-circuit failure model and whether it conforms to the actual short-circuit failure characteristics of the device.
[0016] In some embodiments, in step S31, the safe operating area includes: a collector maximum rated current limiting region and a collector-emitter maximum rated voltage limiting region.
[0017] In some embodiments, in step S34, the degree of overlap is P. S 重 The area of overlap between the phase plane curves of the simulation model test and the actual device test is P. The closer P is to 1, the higher the accuracy of the short-circuit failure model.
[0018] In some embodiments, S 重 It is obtained through the following steps.
[0019] Take multiple intersection points of the two phase plane curves from the simulation model test and the actual device test. Find the center of a circle in the overlapping area enclosed by the two phase plane curves. Then, connect the center of the circle with the intersection points of the two phase plane curves to form line segments L1, L2, and so on until L... n It can be divided into n regions, namely S1, S2, up to S... n ;
[0020] When i=1, the boundary and line segment L inside region S1 n The region formed by line segment L1 is the region with the lower area in both simulation and actual testing, which is the overlapping area of this region.
[0021] When i≥2, any region S i The inner boundary and line segment L i-1 Line segment L i The region that forms the boundary is the area with the lower area in the simulation test and the actual test, which is the overlapping area of the region.
[0022] Finally, S1, S2, ..., S n The sum of the overlapping areas of the two curves is the area S of overlap. 重 .
[0023] In some embodiments, the principle for selecting the center of the circle is that any straight line passing through the center of the circle can only divide the simulation curve into two non-intersecting parts, and at the same time can also divide the actual test curve into two non-intersecting parts.
[0024] Compared with the prior art, the present invention has the following beneficial effects:
[0025] This invention addresses the lack of quantitative indicators in the time-domain evaluation of short-circuit failure models. It proposes using the collector-emitter voltage V during the short-circuit process, based on the safe operating region of the IGBT device. ce and collector current I c The overlap of the areas of the curves formed is used as a quantitative indicator of the consistency between the short-circuit characteristics tested by the short-circuit failure model and the short-circuit characteristics under actual operating conditions.
[0026] Compared to the current method of manually comparing short-circuit characteristic curves, this invention proposes clear quantitative indicators, which improves the evaluation capability of IGBT short-circuit failure models, provides better support for the full-condition design and selection of devices such as frequency converters, improves design efficiency, and reduces the R&D cycle and cost.
[0027] This invention provides a method based on the safe operating region of an IGBT device, using the collector-emitter voltage V during short-circuit failure. ce and collector current I c The overlap of the area of the curves formed is used as a quantitative indicator for evaluating short-circuit failure models, which improves the evaluation capability of IGBT short-circuit failure models.
[0028] This invention provides better support for the design and selection of devices such as frequency converters under all operating conditions, improves design efficiency, and reduces the development cycle and cost. Attached Figure Description
[0029] Figure 1 This invention provides a simulation and measured voltage and current waveform of an IGBT device during the short-circuit failure process.
[0030] Figure 2 The short-circuit characteristic phase plane diagram within the safe operating region of the short-circuit failure process provided by this invention;
[0031] Figure 3 The present invention provides a method for dividing the overlapping area of the phase plane diagrams of the simulated curve and the measured curve within the safe operating area of the short-circuit failure process;
[0032] Figure 4 This is a flowchart of the present invention. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] A time-domain evaluation method for short-circuit failure models based on the safe operating region of IGBT devices includes:
[0035] S1: Obtain the voltage V obtained from simulation model testing and actual device testing during the short-circuit failure process of the IGBT device. ce and current I c .
[0036] After building a short-circuit failure simulation model in mathematical calculation software or power electronics simulation software, given specific operating conditions, the corresponding voltage and current signals can be obtained using the probe model in the software.
[0037] In the IGBT short-circuit failure model, the short-circuit process is controlled by the IGBT base, which can be understood as a short-circuit process switch, and the voltage and current signals are measured during the short-circuit process.
[0038] Figure 1 The figure shows the transient curves of the short-circuit failure process of the IGBT device, including V obtained from simulation model tests and actual device tests. ce and I c .
[0039] S2: Based on the voltage V in S1 ce and current I c The voltage V obtained from the simulation model test and the actual device test is obtained. ce With current I c The phase plane curves formed.
[0040] A phase plane curve is a continuous curve formed by the continuous changes of two sets of physical quantities in a rectangular coordinate system over a period of time, with each point corresponding to a unique moment.
[0041] In the phase plane curves of this invention, the continuous curves formed by the voltage and current during the IGBT short-circuit process, which correspond one-to-one in time, within the short-circuit safe operating region of the IGBT device are specifically referred to.
[0042] S3: The area enclosed by the phase plane curves tested according to the simulation model. 仿真 The area S enclosed by the phase plane curve of the actual device test 实 The degree of overlap is used to determine the accuracy of the short-circuit failure model.
[0043] Step S3 specifically includes:
[0044] S31: Determine the safe operating area of the IGBT device during the short-circuit failure process in the phase plane curve coordinate system.
[0045] Figure 2 This is within the device's short-circuit safe operating area. Figure 1 The curve obtained under simulation and real test conditions V ce with I c The phase plane curve is composed of two segments. The short-circuit safe operating region of the device consists of segment AB (the maximum rated collector current limiting region) and segment BC (the maximum rated collector-emitter voltage limiting region). The trajectory of the phase plane curve not exceeding this region is safe for device failure. Under this premise, this patent proposes S... 仿真 With S 实The higher the degree of overlap, the higher the accuracy of the short-circuit failure model, and the better it matches the actual short-circuit failure characteristics of the device.
[0046] S32: If the voltage V in the simulation model test and the actual device test is different... ce With current I c If the phase plane curve is within the safe operating area, proceed to the next step.
[0047] S33: Calculate the area S enclosed by the phase plane curves of the simulation model test. 仿真 And the area S enclosed by the phase plane curve of the actual device test 实 .
[0048] Figure 3 The diagram illustrates the method for calculating the overlap ratio during a short-circuit failure. In the phase plane curves, multiple intersection points of the simulated and actual test curves are selected. A suitable center is chosen within the overlapping area enclosed by the two curves. For ease of subsequent calculation of the overlapping area, the principle for selecting the center is that any straight line passing through the center can divide both the simulated and actual test curves into two non-intersecting parts. Then, line segments L1, L2, and so on are formed by connecting the center and the intersection points of the two curves. n It can be divided into n regions, namely S1, S2, up to S... n When i=1, the boundary and line segment L inside region S1 n The region formed by line segment L1 is the region with the lower area in both simulation and actual testing, i.e., the overlapping area of this region; when i≥2, any region S i The inner boundary and line segment L i-1 Line segment L i The region formed is the area with the lower area in both simulation and actual testing, which is the overlapping area of this region. Finally, S1, S2, ..., S n The sum of the overlapping areas of the two curves is the area S of overlap. 重 .
[0049] S34: Calculate S 仿真 With S 实 The overlap ratio is used to determine the accuracy of the short-circuit failure model and whether it conforms to the actual short-circuit failure characteristics of the device.
[0050] Overlapping area S 重 Divide by the area S enclosed by the actual test curve 实 It refers to the degree of overlap, P.
[0051] (1)
[0052] This invention primarily focuses on time-domain evaluation of short-circuit failure models for semiconductor IGBT devices. For short-circuit failure models of other similar semiconductor devices, including those with different packaging forms, voltage levels, and capacity levels, the method provided in this patent can be referenced.
[0053] This invention uses a certain type of IGBT as the experimental object and establishes an IGBT short-circuit failure model. This model has sufficient simulation capability for the short-circuit failure characteristics of IGBTs. The time-domain evaluation method of the IGBT short-circuit failure simulation model proposed in this patent is used for evaluation.
[0054] The actual voltage and current waveforms of the device under short circuit conditions, as well as the simulation model, are as follows: Figure 1 As shown, the phase plane curves of voltage and current under short circuit of IGBT are plotted within the short-circuit safe operating area of this type of IGBT according to the method proposed in this patent.
[0055] When calculating the area of the phase plane curve under short-circuit conditions, according to the method of this invention, the area of the curve at the intersection of the measured and simulated phase plane curves can be divided into S1 to S6, such as... Figure 3 As shown, S 实测 The area is 4.243e6, S 仿真 The area is 3.753e6, S 重合 The area is 3.424e6, therefore P is 0.807.
[0056] Ultimately, the calculated accuracy P of the short-circuit failure model is 0.807. Since the model is effective, the validity of the accuracy P of the short-circuit model is verified, and a quantitative indicator of the extent to which the model is effective is provided.
[0057] The accuracy P of the short-circuit model can obviously be used to directly determine the model with poor simulation effect of IGBT short-circuit failure, so experimental data will not be listed.
[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A time-domain evaluation method for short-circuit failure models based on the safe operating region of IGBT devices, characterized in that, include: S1: Obtain the voltage V obtained from simulation model testing and actual device testing during the short-circuit failure process of the IGBT device. ce and current I c ; S2: Based on the voltage V in S1 ce and current I c The voltage V obtained from the simulation model test and the actual device test is obtained. ce With current I c The phase plane curves formed; S3: The area enclosed by the phase plane curves tested according to the simulation model. 仿真 The area S enclosed by the phase plane curve of the actual device test 实 The degree of overlap is used to determine the accuracy of the short-circuit failure model; Step S3 specifically includes: S31: Determine the safe operating area of the IGBT device short-circuit failure process in the phase plane curve coordinate system; S32: If the voltage V in the simulation model test and the actual device test is different... ce With current I c If the phase plane curve is within the safe operating area, proceed to the next step; S33: Calculate the area S enclosed by the phase plane curves of the simulation model test. 仿真 And the area S enclosed by the phase plane curve of the actual device test 实 ; S34: Calculate S 仿真 With S 实 The degree of overlap is used to determine the accuracy of the short-circuit failure model and whether it conforms to the short-circuit failure model of the device. The degree of overlap is P. S 重 The area of overlap between the phase plane curves of the simulation model test and the actual device test is P. The closer P is to 1, the higher the accuracy of the short-circuit failure model. S 重 It is obtained through the following steps. Take multiple intersection points of the two phase plane curves from the simulation model test and the actual device test. Find the center of a circle in the overlapping area enclosed by the two phase plane curves. Then, connect the center of the circle with the intersection points of the two phase plane curves to form line segments L1, L2, and so on until L... n It can be divided into n regions, namely S1, S2, up to S... n ; When i=1, the boundary and line segment L inside region S1 n The region formed by line segment L1 is the region with the lower area in both simulation and actual testing, i.e., the overlapping area of this region; when i≥2, any region S i The inner boundary and line segment L i-1 Line segment L i The region formed is the area with the lower area in both simulation and actual testing, i.e., the overlapping area of this region; finally, S1, S2, ..., S... n The sum of the overlapping areas of the two curves is the area S of overlap. 重 .
2. The time-domain evaluation method for short-circuit failure model based on the safe operating area of IGBT devices according to claim 1, characterized in that, In step S3, the area S enclosed by the phase plane curve tested by the simulation model 仿真 The area S enclosed by the phase plane curve of the actual device test 实 The higher the degree of overlap, the higher the accuracy of the short-circuit failure model, and the better it matches the short-circuit failure model of the device.
3. The time-domain evaluation method for short-circuit failure model based on the safe operating area of IGBT devices according to claim 2, characterized in that, In step S31, the safe operating area includes: the collector maximum rated current limiting area and the collector-emitter maximum rated voltage limiting area.
4. The time-domain evaluation method for short-circuit failure model based on the safe operating area of IGBT devices according to claim 1, characterized in that, The principle for selecting the center of the circle is: any straight line passing through the center of the circle can divide the simulated curve into two non-intersecting parts, and at the same time, it can also divide the actual test curve into two non-intersecting parts.