Bitstream testing method, device, computer equipment, storage medium and program product

Abstract

The invention relates to the field of electronic technology, and discloses a bitstream testing method, a device, a computer device, a storage medium and a program product. The bitstream testing method generates an excitation signal corresponding to the input variable by reading parameter information of the input variable in a test case table; parses a wiring file to obtain pin information of each input variable and a corresponding output variable; generates a simulation excitation file based on a reference model, the pin information of each input variable, the excitation signal and the pin information of the corresponding output variable, thereby ensuring the accuracy of the simulation excitation file, reducing the possibility of manual operation errors, effectively improving the efficiency of the bitstream test, making the test result more reliable, and ensuring that the generated excitation signal meets the test requirements and specifications.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to bit current testing methods, apparatus, computer equipment, storage media, and program products. Background Technology

[0002] Bitstream testing verifies the functionality of binary bitstream files generated by Electronic Design Automation (EDA) software through simulation, ensuring that the software can correctly generate bitstream files with the expected functions and guaranteeing software quality. For a test case's Register Transfer Level (RTL) file, which contains specific test functions, the bitstream testing execution process can be mainly divided into the following three steps:

[0003] 1) Generate bitstream file: Run the test case in EDA software to generate the corresponding Bitstream file and Route result file.

[0004] 2) Write the bitstream test TestBench file: Write the test case TestBench file based on the test case RTL file and the Route file generated by the EDA software.

[0005] 3) Run the bitstream test platform: The bitstream test platform loads and executes the test case files TestBench and Bitstream, and returns the test results of the Bitstream file.

[0006] Writing test cases in the TestBench file is a crucial step in bitstream testing. The TestBench file primarily comprises three parts: input / output pin mapping, test case stimulus assignment, and a reference model. The input / output pin mapping section maps input / output variables to the actual pin coordinates of the DUT (Device Under Test) on the chip test platform, ensuring the simulation environment can correctly input stimulus signals to the corresponding pins. Test case stimulus assignment assigns different signals to the input variables in the test cases, ensuring comprehensive test coverage of the tested functionality. The reference model is used to obtain the expected values ​​of the test case functionality. Given the same input stimulus, the output of the bitstream simulation is compared with the output of the reference model to determine the correctness of the bitstream.

[0007] Traditional bitstream test TestBench files are typically written manually by testers, requiring significant time and effort. Furthermore, for complex designs, manually written TestBench files are prone to syntax and logical errors, leading to inaccurate or incorrect test execution. Additionally, manually written TestBench files may lack flexibility and are difficult to maintain when faced with changes to test case function files. Summary of the Invention

[0008] In view of this, the present invention provides a bitstream testing method, apparatus, computer equipment, storage medium, and program product to solve the problems of inaccurate testing and difficulty in maintenance caused by manually writing simulation stimulus files in related technologies.

[0009] In a first aspect, the present invention provides a bitstream testing method, the method comprising: acquiring a test case table, a bitstream file, a routing file, and a reference model for test cases, wherein the test case table is used to characterize parameter information of multiple input variables, and the routing file is used to characterize the connection information of logic blocks and pins of the chip under test; reading the parameter information of each input variable in the test case table and generating excitation signals for the corresponding input variables; parsing the routing file to obtain pin information of each input variable and the corresponding output variable; generating a simulation excitation file based on the reference model, the pin information of each input variable, the excitation signals, and the pin information of the corresponding output variable; and performing bitstream testing based on the simulation excitation file and the bitstream file to obtain bitstream test results.

[0010] This invention provides a bitstream testing method that generates excitation signals for corresponding input variables by reading parameter information of each input variable from a test case table; parses the routing file to obtain pin information for each input variable and its corresponding output variable; generates a simulation excitation file based on a reference model, the pin information of each input variable, the excitation signals, and the pin information of the corresponding output variable; and performs bitstream testing based on the simulation excitation file and the bitstream file to obtain the bitstream test results. This method ensures the accuracy of the simulation excitation file, reduces the possibility of manual operation errors, effectively improves bitstream testing efficiency, and ensures that the generated excitation signals meet test requirements and specifications.

[0011] In one optional implementation, the steps of obtaining the test case table, bitstream file, routing file, and reference model of the test cases include: obtaining the RTL file of the test cases, wherein the RTL file is used to represent a file containing preset test functions; running the RTL file of the test cases in a preset functional module to obtain the bitstream file, netlist file, and routing file; and generating a reference model using the netlist file.

[0012] In one optional implementation, the step of reading the parameter information of each input variable in the test case table and generating the corresponding excitation signal for the input variable includes: reading the initial value, special value, random value and random number of each input variable in the test case table; and generating the corresponding excitation signal for the input variable based on the initial value, special value, random value and random number of each input variable.

[0013] The method provided in this optional implementation generates excitation signals for corresponding input variables by using the initial values, special values, random values, and random number of times of each input variable, ensuring that the generated excitation signals meet the test requirements and specifications.

[0014] In one optional implementation, the step of parsing the routing file to obtain the pin information of each input variable and the corresponding output variable includes: parsing the routing information of each input variable and the corresponding output variable in the routing file; and determining the pin information of each input variable and the corresponding output variable based on the routing information of each input variable and the corresponding output variable.

[0015] The method provided in this optional implementation determines the pin information of each input variable and corresponding output variable by parsing the routing information of each input variable and corresponding output variable in the routing file, thereby ensuring the accuracy of the pin information of each input variable and corresponding output variable.

[0016] In one alternative implementation, the step of generating a reference model using a netlist file includes: obtaining a preset library behavior model, which is used to characterize a behavior model with the same functionality and behavior as the RTL file of the test case; and generating a reference model using the preset library behavior model and the netlist file.

[0017] Secondly, the present invention provides a bitstream testing device, comprising: an acquisition module for acquiring a test case table, a bitstream file, a routing file, and a reference model, wherein the test case table is used to characterize parameter information of multiple input variables, and the routing file is used to characterize the connection information of logic blocks and pins of the chip under test; a reading module for reading the parameter information of each input variable in the test case table and generating excitation signals for the corresponding input variables; a parsing module for parsing the routing file to obtain pin information of each input variable and the corresponding output variable; a determination module for generating a simulation excitation file based on the reference model, the pin information of each input variable, the excitation signals, and the pin information of the corresponding output variable; and a testing module for performing bitstream testing based on the simulation excitation file and the bitstream file to obtain bitstream test results.

[0018] In one optional implementation, the acquisition module includes: a first acquisition submodule, used to acquire the RTL file of the test cases, the RTL file being used to characterize a file containing preset test functions; a run submodule, used to run the RTL file of the test cases in a preset function module to obtain a bitstream file, a netlist file, and a routing file; and a first determination submodule, used to generate a reference model using the netlist file.

[0019] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the bit stream testing method of the first aspect or any corresponding embodiment described above.

[0020] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the bitstream testing method of the first aspect or any corresponding embodiment thereof.

[0021] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the bitstream testing method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a bitstream testing method according to an embodiment of the present invention;

[0024] Figure 2 This is a flowchart illustrating another stream testing method according to an embodiment of the present invention;

[0025] Figure 3 This is a flowchart illustrating the reference model generation process according to an embodiment of the present invention;

[0026] Figure 4 This is a flowchart illustrating the process of generating an excitation signal according to an embodiment of the present invention;

[0027] Figure 5 This is a flowchart illustrating another bitstream testing method according to an embodiment of the present invention;

[0028] Figure 6 This is a flowchart illustrating the process of determining the pin information of each input variable and the corresponding output variable according to an embodiment of the present invention.

[0029] Figure 7 This is a flowchart illustrating a specific example of the bitstream testing method in this invention.

[0030] Figure 8 This is a structural block diagram of a bitstream testing device according to an embodiment of the present invention;

[0031] Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In related technologies, bitstream test TestBench files are typically written manually by testers, which consumes a significant amount of time and effort. Secondly, for complex designs, manually writing TestBench files can easily introduce syntax and logical errors, leading to inaccurate tests or tests that fail to run correctly. Furthermore, manually written TestBench files may lack flexibility and are difficult to maintain when faced with changes to test case function files.

[0034] In view of this, the bitstream testing method provided in this application can be applied to a server to implement bitstream testing. The method provided by this invention generates excitation signals for the corresponding input variables by reading the parameter information of the input variables in the test case table; it parses the routing file to obtain the pin information of each input variable and the corresponding output variable; and it generates a simulation excitation file based on the reference model, the pin information of each input variable, the excitation signals, and the pin information of the corresponding output variables. This ensures the accuracy of the simulation excitation file, reduces the possibility of manual operation errors, effectively improves the efficiency of bitstream testing, and ensures that the generated excitation signals meet test requirements and specifications.

[0035] According to an embodiment of the present invention, a bit stream testing method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0036] This embodiment provides a bitstream testing method, which can be used in the aforementioned server. Figure 1 This is a flowchart of a bitstream testing method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0037] Step S101: Obtain the test case table, bitstream file, routing file, and reference model of the test cases.

[0038] For example, a test case is a file that can implement a preset test function. The test case table is used to characterize the parameter information of multiple input variables, the routing file is used to characterize the connection information of the logic blocks and pins of the chip under test, and the bitstream file contains configuration instructions and configuration data for the Field Programmable Gate Array (FPGA) chip, used to program the FPGA design into the hardware. The size of the configuration data depends on the FPGA model and the scale of the design. The file mainly includes two parts: 1) Header information: contains some metadata information, such as file type, version number, FPGA model, etc.; 2) Stream data: contains a series of configuration instructions and data, stored in binary form. The test case table contains five columns of data: test case name, variable initial value, random variable, stimulus delay time, and random number of times. Among them, the test case name column is the file name of the test case, the variable initial value column records the initial value of the variable whose initial value is not 0, the random variable column records the name of the variable that needs to be randomly stimulated in each test case, the stimulus delay time column records the delay time after each stimulus assignment, and the random number of times column records the number of stimulus values ​​that need to be given in each test case. For each test case, there is a corresponding row of data in the test case table, used to automatically generate stimulus signals. The routing file (Route result file) contains the coordinates of the I / O ports corresponding to the input and output variables in the test case. The Route function in EDA software is the process of connecting logic blocks at certain locations to I / O ports. By reading the Route result file, the pins corresponding to the input and output variables can be obtained.

[0039] Step S102: Read the parameter information of each input variable in the test case table and generate the corresponding excitation signal for the input variable.

[0040] For example, in this embodiment of the application, the parameter information of the input variables is obtained by reading the test case table, and the corresponding excitation signal of the variable is generated.

[0041] Step S103: Parse the wiring file to obtain the pin information of each input variable and the corresponding output variable.

[0042] For example, the pin information of each input variable and the pin information of the corresponding output variable are determined by examining the wiring file.

[0043] Step S104: Generate a simulation stimulus file based on the reference model, the pin information of each input variable, the excitation signal, and the pin information of the corresponding output variable.

[0044] For example, in the embodiments of this application, a simulation stimulus file (TestBench file) is generated based on the reference model, the pin information of each input variable, the excitation signal, and the pin information of the corresponding output variable.

[0045] Step S105: Perform bitstream testing based on the simulation stimulus file and bitstream file to obtain bitstream test results.

[0046] For example, in this embodiment of the application, a TestBench file and a Bitstream file are loaded and executed on a bitstream testing platform, and the test results of the Bitstream file are returned.

[0047] The bitstream testing method provided in this embodiment generates excitation signals for the corresponding input variables by reading the parameter information of the input variables in the test case table; it parses the routing file to obtain the pin information of each input variable and the corresponding output variable; and it generates a simulation excitation file based on the reference model, the pin information of each input variable, the excitation signals, and the pin information of the corresponding output variables. This ensures the accuracy of the simulation excitation file, reduces the possibility of manual operation errors, effectively improves the efficiency of bitstream testing, makes the test results more reliable, and ensures that the generated excitation signals meet the test requirements and specifications.

[0048] This embodiment provides a bitstream testing method, which can be used in the aforementioned mobile terminals, such as mobile phones and tablet computers. Figure 2 This is a flowchart of a bitstream testing method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0049] Step S201: Obtain the test case table, bitstream file, routing file, and reference model for the test cases. The test case table is used to represent the parameter information of multiple input variables, and the routing file is used to represent the connection information of the logic blocks and pins of the chip under test. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0050] Specifically, step S201 includes:

[0051] Step S2011: Obtain the RTL file of the test case. The RTL file is used to represent the file containing the preset test functions.

[0052] For example, in this application embodiment, the RTL file of the test case represents an RTL file that implements a specific function.

[0053] Step S2012: Run the RTL file of the test case in the preset functional module to obtain the bitstream file, netlist file and routing file.

[0054] For example, in this embodiment of the application, the preset functional module may include, but is not limited to, EDA software. The test case RTL file is executed in the EDA software, including five steps: synthesis, mapping, placement, routing, and bitstream generation, to generate a bitstream file, a netlist file, and a routing file. The netlist file is the file generated after the test case RTL file is synthesized and mapped by the EDA software. It is stored in Verilog format. This file is instantiated from the basic logic units in the primitive library. The input and output variables are the same as those in the test case RTL file, and the logic functions in the file are also the same as those in the user-designed RTL file. The routing file is the file generated after routing. In the EDA software, routing is the process of connecting logic blocks at certain locations to I / O ports. The routing file contains the I / O port coordinates corresponding to the input and output variables in the test case RTL file. By reading the routing file, the pins corresponding to the input and output variables can be obtained.

[0055] Step S2013: Generate a reference model using the netlist file.

[0056] In some optional implementations, step S2013 above includes:

[0057] Step a1: Obtain the preset library behavior model. The preset library behavior model is used to represent the behavior model with the same functions and behaviors as the RTL file of the test case.

[0058] For example, in this embodiment of the application, the preset library behavior model can be a Primitive library behavior model. Primitives are a series of low-level logic functional units provided by the FPGA software integrated development environment, used to implement basic operations and functions in digital logic circuits. These primitives are the smallest functional units on the FPGA chip, directly mapped to hardware resources. Each primitive in the Primitive library corresponds to a behavior model, and the behavior model uses Verilog language to describe the function and behavior of different primitives in the logic circuit.

[0059] Step a2: Generate a reference model using the preset library behavior model and netlist file.

[0060] For example, in this embodiment of the application, in order to determine the correctness of the test case Bitstream file, a reference model needs to be written for each test case. The function of the reference model is the same as that of the test case to be tested, thereby ensuring that the same stimulus is input to both the platform and the reference model. The test result of the test case can be generated by comparing whether the outputs of the test platform and the reference model are the same. The generation process of the reference model can be as follows: Figure 3 As shown, the specific process is as follows:

[0061] (1) First, store the Primitive library behavior model file corresponding to the chip in a fixed file directory DIR to facilitate the generation of references to the Primitive library behavior model file. The file name and module name in the Primitive library behavior model file are the same as the Primitive interface.

[0062] (2) Traverse the Map netlist file of the test cases and read the instantiated module names in the file. The module names in the netlist file are the same as the file names of the Primitive behavioral models.

[0063] (3) Based on the traversed list of module names and file directory DIR, automatically generate references to the corresponding behavior model files, and combine the contents of the netlist file to generate the reference model corresponding to the use case.

[0064] (4) Define output variables in the TestBench file of the test cases, instantiate the modules in the reference model, the input variables are the input variables defined in the test case table, and the output variables are newly defined.

[0065] The above steps can automatically generate the corresponding reference model from the netlist file of the test case and automatically instantiate it in the TestBench file of the test case to be tested. Since the reference model and the test platform use the same input variable signals, the consistency of the input between the two is guaranteed, which makes it easy to compare the output of the two to obtain the test results.

[0066] Step S202: Read the parameter information of each input variable in the test case table and generate the corresponding excitation signal for the input variable.

[0067] Specifically, step S202 includes:

[0068] Step S2021: Read the initial value, special value, random value, and random number of times each input variable is entered in the test case table.

[0069] Step S2022: Generate excitation signals for the corresponding input variables based on the initial values, special values, random values, and random number of times of each input variable.

[0070] For example, in the embodiments of this application, the generation process of the excitation signal can be as follows: Figure 4 As shown, the specific steps are as follows:

[0071] (1) Automatically read the initial value column of the variable corresponding to the test case in the test case table, divide its content according to a specific format, obtain each variable name and its corresponding initial value, and generate the initialization code of the corresponding variable according to the Verilog language format.

[0072] (2) Traverse all variables in the initial value column to find variables containing the characters CLK and RST, and generate the corresponding excitation assignment code according to the rules of clock signal and reset signal.

[0073] (3) Read the output of the three columns: random variable column, excitation delay time, and random number of times, to generate the code for assigning random excitation values ​​to the variables. First, generate the number of times to loop in the for loop structure in the code based on the size of the number in the random number of times; second, generate the time of each excitation delay based on the content of the excitation delay time, which is mainly divided into three types: fixed time, rising edge of a certain signal, and falling edge of a certain signal; finally, read the variable name and variable data width in the random variable column, and generate the code for the random variable part based on the data width of the variable.

[0074] By reading the characteristics of input variables in the test case table, the system automatically initializes and assigns values ​​to the input variables in the test cases, and automatically generates the stimulus assignment code in the TestBench file. This automated process helps improve testing efficiency, reduces the possibility of manual operation errors, and ensures that the generated stimulus signals meet the test requirements and specifications.

[0075] Step S203: Parse the wiring file to obtain the pin information of each input variable and its corresponding output variable. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0076] Step S204: Generate a simulation stimulus file based on the reference model, pin information of each input variable, excitation signals, and pin information of the corresponding output variables. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0077] Step S205: Perform bitstream testing based on the simulation stimulus file and bitstream file to obtain the bitstream test results. For details, please refer to [link to relevant documentation]. Figure 1 Step S105 of the illustrated embodiment will not be described again here.

[0078] This embodiment provides a bitstream testing method, which can be used in the aforementioned mobile terminals, such as mobile phones and tablet computers. Figure 5 This is a flowchart of a bitstream testing method according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0079] Step S501: Obtain the test case table, bitstream file, routing file, and reference model for the test cases. The test case table is used to represent the parameter information of multiple input variables, and the routing file is used to represent the connection information of the logic blocks and pins of the chip under test. For details, please refer to [link to relevant documentation]. Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0080] Step S502: Read the parameter information of each input variable in the test case table and generate the corresponding excitation signal for the input variable. For details, please refer to [link to relevant documentation]. Figure 2 Step S202 of the illustrated embodiment will not be described again here.

[0081] Step S503: Parse the wiring file to obtain the pin information of each input variable and the corresponding output variable.

[0082] Specifically, step S503 includes:

[0083] Step S5031: Parse the routing information of each input variable and corresponding output variable in the wiring file.

[0084] Step S5032: Determine the pin information of each input variable and its corresponding output variable based on the routing information of each input variable and its corresponding output variable.

[0085] For example, in the embodiments of this application, the pin information of each input variable and the corresponding output variable can be obtained through, as follows: Figure 6 The process shown is defined and includes the following steps:

[0086] (1) Read the use case Route result file and parse the NET names and routing information corresponding to each NET in the file. The Route result file records the NET routing information corresponding to all variables of the use case, and also includes the NET routing information corresponding to input and output variables. The NET names in the file are usually generated according to specific rules based on the variable names. According to the specific rules, the variable name corresponding to each NET in the RTL can be parsed in reverse. At the same time, the routing information corresponding to each NET in the file includes the routing information from the pin of one logic block to the pin of another logic block. For the NET of input and output variables, its routing information corresponds to connecting from the input IO to the logic block or from the logic block to the output IO.

[0087] (2) Determine whether a NET is an input / output variable based on the routing information corresponding to each NET. The routing information of the NETs of input / output variables all contain IO-related keywords. Determine whether the routing information corresponding to each NET contains the IO-related keyword ioblock to determine whether the NET is an input / output variable.

[0088] (3) Parse the routing information corresponding to the input and output variables, perform regular expression matching based on keywords, and obtain the XY coordinates corresponding to each input and output variable. These coordinates are the coordinates of the entire floorplan of the chip.

[0089] (4) Convert the XY coordinates of the input and output variables into the physical location of the PAD. The XY coordinates are the coordinates of the IO Site module on the entire chip, while the physical location of the PAD refers to its specific position in the IO section. The conversion relationship between the two positions is related to the specific floorplan of the chip.

[0090] (5) Generate code defining input and output variables in the TestBench file according to specific rules.

[0091] a. The rules for input variables are as follows: First, define a wire type variable with the same data width as the test case RTL file. Second, define an "initial begin...end" module to assign the variable to its corresponding IO physical location.

[0092] b. The rules for output variables are as follows: First, define a wire type variable with the same data width as the output variable in the test case RTL file. Second, convert the physical coordinates corresponding to the output variable into pad_bank and assign them to the defined output variable.

[0093] Step S504: Generate a simulation stimulus file based on the reference model, pin information of each input variable, excitation signals, and pin information of the corresponding output variables. For details, please refer to [link to relevant documentation]. Figure 2 Step S204 of the illustrated embodiment will not be described again here.

[0094] Step S505: Perform bitstream testing based on the simulation stimulus file and bitstream file to obtain the bitstream test results. For details, please refer to [link to relevant documentation]. Figure 2 Step S205 of the illustrated embodiment will not be described again here.

[0095] The bitstream testing method provided by the present invention will be described below through a specific embodiment.

[0096] Example:

[0097] The method provided in this embodiment has the following overall architecture: Figure 7 As shown, the process includes the following parts: input data preparation, pin parsing, automatic generation of test case reference models, and automatic generation of stimulus signals. First, in the test case file generation step, the test cases to be tested are loaded into the EDA software to execute FLOW, generating and saving the result file. The result file and the test case table serve as the input data for the method. Next, based on the information in the input data, the specific pins corresponding to the input and output variables in the test cases are parsed, and the reference models and stimulus signals for the test cases are automatically generated, generating the TestBench file for the test cases. Finally, the TestBench and Bitstream files are loaded into the bitstream testing platform to obtain the test results.

[0098] In this embodiment, the automatically generated TestBench file for bitstream test cases can significantly reduce the time testers spend manually writing test cases, alleviate manpower burden, improve testing efficiency, and avoid errors in the TestBench file due to human error, making test results more reliable and easier to compare and analyze. Simultaneously, the automatically generated TestBench file is easier to integrate with automated testing tools, facilitating automated testing processes and improving test execution speed.

[0099] This embodiment also provides a bitstream testing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0100] This embodiment provides a bitstream testing device, such as... Figure 8 As shown, it includes:

[0101] The acquisition module 801 is used to acquire the test case table, bit stream file, routing file and reference model of the test cases. The test case table is used to characterize the parameter information of multiple input variables, and the routing file is used to characterize the connection information of the logic blocks and pins of the chip under test.

[0102] The reading module 802 is used to read the parameter information of each input variable in the test case table and generate the corresponding excitation signal for the input variable;

[0103] The parsing module 803 is used to parse the wiring file to obtain the pin information of each input variable and the corresponding output variable;

[0104] The determination module 804 is used to generate a simulation stimulus file based on the reference model, the pin information of each input variable, the excitation signal, and the pin information of the corresponding output variable.

[0105] Test module 805 is used to perform bitstream testing based on simulation stimulus files and bitstream files to obtain bitstream test results.

[0106] In some optional implementations, the acquisition module 801 includes:

[0107] The first acquisition submodule is used to acquire the RTL file of the test cases. The RTL file is used to represent a file containing preset test functions.

[0108] The run submodule is used to run the RTL files of the test cases in the preset functional modules to obtain bitstream files, netlist files and routing files;

[0109] The first determination submodule is used to generate a reference model using the netlist file.

[0110] In some alternative implementations, the reading module 802 includes:

[0111] The read submodule is used to read the initial values, special values, random values, and random number of times each input variable in the test case table;

[0112] The second determining submodule is used to generate excitation signals for the corresponding input variables based on the initial values, special values, random values, and random number of times each input variable is selected.

[0113] In some alternative implementations, the parsing module 803 includes:

[0114] The parsing submodule is used to parse the routing information of each input variable and corresponding output variable in the wiring file;

[0115] The third determination submodule is used to determine the pin information of each input variable and its corresponding output variable based on the routing information of each input variable and its corresponding output variable.

[0116] In some alternative implementations, the first determining submodule includes:

[0117] The acquisition unit is used to acquire the preset library behavior model, which is used to represent the behavior model with the same function and behavior as the RTL file of the test case;

[0118] The defined unit is used to generate a reference model using a pre-defined library behavior model and a netlist file.

[0119] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0120] In this embodiment, the bitstream testing device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0121] This invention also provides a computer device having the above-described features. Figure 8 The bitstream testing device shown.

[0122] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0123] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0124] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0125] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0126] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0127] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0128] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0129] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0130] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A bit stream testing method, characterized in that: The method comprises: Obtaining a test case table, a bitstream file, a wiring file, and a reference model of a test case, wherein the test case table is used to characterize parameter information of multiple input variables, and the wiring file is used to characterize connection information between a logic block and a pin of a chip to be tested; Read parameter information of each input variable in the test case table and generate a stimulus signal corresponding to the input variable; Parsing the wiring file to obtain pin information of each input variable and the corresponding output variable; Generate a simulation stimulus file based on the reference model, the pin information of each input variable, the stimulus signal and the pin information of the corresponding output variable; Performing a bitstream test based on the simulation stimulus file and the bitstream file to obtain a bitstream test result; The step of reading parameter information of each input variable in the test case table and generating a stimulus signal corresponding to the input variable comprises: Read the initial value, special value, random value and random number of each input variable in the test case table; Based on the initial value, special value, random value and random number of the input variables, an excitation signal corresponding to the input variable is generated.

2. The method according to claim 1, characterized in that The steps of obtaining a test case table, a bitstream file, a wiring file, and a reference model of a test case include: Obtain an RTL file of a test case, wherein the RTL file is used to represent a file containing a preset test function; Run the RTL file of the test case in a preset functional module to obtain a bitstream file, a netlist file, and a wiring file; The reference model is generated using the netlist file.

3. The method according to claim 1, characterized in that The step of parsing the wiring file to obtain pin information of each input variable and the corresponding output variable includes: Parsing routing information of each input variable and corresponding output variable in the wiring file; The pin information of each input variable and the corresponding output variable is determined based on the routing information of each input variable and the corresponding output variable.

4. The method according to claim 2, characterized in that: The step of generating the reference model by using the netlist file comprises: Obtaining a preset library behavior model, wherein the preset library behavior model is used to represent a behavior model with the same function and behavior as the RTL file of the test case; The reference model is generated using the preset library behavior model and the netlist file.

5. A bit stream testing device, characterized in that: The device comprises: An acquisition module, used to acquire a test case table, a bitstream file, a wiring file, and a reference model of a test case, wherein the test case table is used to characterize parameter information of multiple input variables, and the wiring file is used to characterize connection information between a logic block and a pin of a chip to be tested; A reading module, used to read parameter information of each input variable in the test case table and generate an excitation signal corresponding to the input variable; A parsing module, used to parse the wiring file to obtain pin information of each input variable and the corresponding output variable; A determination module, used to generate a simulation stimulus file based on the reference model, the pin information of each input variable, the stimulus signal and the pin information of the corresponding output variable; A test module, used for performing a bitstream test based on the simulation stimulus file and the bitstream file to obtain a bitstream test result; The step of reading parameter information of each input variable in the test case table and generating a stimulus signal corresponding to the input variable includes: Read the initial value, special value, random value and random number of each input variable in the test case table; Based on the initial value, special value, random value and random number of the input variables, an excitation signal corresponding to the input variable is generated.

6. The device according to claim 5, characterized in that The acquisition module comprises: A first acquisition submodule is used to acquire an RTL file of a test case, wherein the RTL file is used to represent a file containing a preset test function; A running submodule is used to run the RTL file of the test case in a preset functional module to obtain a bitstream file, a netlist file and a wiring file; The first determination submodule is used to generate the reference model using the netlist file.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the bit stream testing method according to any one of claims 1 to 4 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the bit stream testing method according to any one of claims 1 to 4.

9. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the bit stream testing method according to any one of claims 1 to 4.

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