An oxide array substrate with low parasitic capacitance effect and a manufacturing method thereof

Abstract

The application provides an oxide array substrate with low parasitic capacitance effect and a preparation method thereof. The array substrate comprises a glass substrate, a bottom gate, a first insulating layer, a semiconductor layer, a second insulating layer, a top gate and a driving circuit trace, a first intermediate insulating layer, a transparent conductive layer and a third metal layer. Two ends of a first semiconductor unit of the semiconductor layer are respectively provided with a conductor layer, a second semiconductor unit corresponds to the bottom gate, and a third semiconductor unit is wholly conductorized and is arranged as a pixel electrode. The top gate is above the first semiconductor unit. A first source and a first drain of the third metal layer are connected with corresponding conductor layers, a second source and a second drain are connected with the second semiconductor unit, one end of the second drain is connected with the pixel electrode, and a metal unit one is connected with the driving circuit trace. The semiconductor layer after being conductorized is arranged as the pixel electrode, so that the film layer can be saved, the process is simplified, only one intermediate insulating layer can be arranged, and the light transmittance is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal display, in particular to an oxide array substrate with low parasitic capacitance effect and a preparation method thereof. BACKGROUND

[0002] In the field of liquid crystal display, FFS (Fringe Field Switching) technology is a liquid crystal display technology that makes liquid crystal molecules between electrodes and directly above the electrodes rotate in the plane parallel to the glass substrate through the edge electric field generated between the top strip pixel electrode and the bottom COM electrode (Bottom COM) or the top COM pixel electrode and the bottom strip pixel electrode (Bop COM) on the TFT substrate. The liquid crystal panel using FFS pixel structure has the characteristics of high transmittance, high viewing angle, high contrast, high color gamut, etc., and is the main pixel structure type of current high-end liquid crystal display panel.

[0003] Thin film transistors (Mox-TFT) prepared by metal oxide semiconductor materials have become one of the important development technologies of array substrate in display panel due to their small leakage current, high field effect mobility, good area uniformity and other advantages. The existing array substrate prepared by metal oxide semiconductor materials generally adopts bottom gate structure TFT, such as etching stop layer (ESL), back channel etching (BCE), or top gate structure TFT, such as self-aligned top gate (Self-Top Gate). Different types of TFTs applied in array substrate have their own structural advantages. Back channel etching bottom gate structure TFT has the advantages of simple structure, short process flow, low cost and high yield, but due to the large overlapping area of gate and source / drain in bottom gate structure and the small spacing distance between gate and source / drain only separated by gate insulating layer, the parasitic capacitance between upper and lower metal lines is large, the power consumption is increased, which is not conducive to the development of high resolution and high refresh rate display panel. In the self-aligned top gate TFT structure, there is basically no overlapping area between the gate and the source / drain, and a thicker intermediate insulating layer is provided between the upper and lower metals, so the overall structure has smaller parasitic capacitance. However, the self-aligned top gate TFT structure is relatively complex, and the preparation process is more complicated. In the liquid crystal display panel, an additional light shielding layer is also needed to reduce the light leakage effect of the semiconductor material on the backlight, which is only used as a light shielding layer. The process is time-consuming but the film utilization rate is low, which is not conducive to cost reduction. SUMMARY

[0004] One of the technical problems to be solved by the present application is to provide an oxide array substrate with low parasitic capacitance effect, which sets the semiconductor layer after being conductorized as a pixel electrode, can save film layers and simplify the process, can only set one intermediate insulating layer, has higher light transmittance, can improve the problems of large parasitic capacitance and single function of the light shielding layer in the existing structure, and has the advantages of low cost and high film utilization rate.

[0005] It can improve the problems of large parasitic capacitance and single function of the light shielding layer in the existing structure, and also has the advantages of low cost, simple structure and high film utilization rate.

[0006] The present application is to solve one of the above technical problems:

[0007] An oxide array substrate with low parasitic capacitance effect, characterized in that the oxide array substrate comprises: a glass substrate,

[0008] A first metal layer is arranged on the glass substrate, and the first metal layer comprises a bottom gate;

[0009] A first insulating layer is arranged on the first metal layer;

[0010] A semiconductor layer is arranged on the first insulating layer, and the semiconductor layer comprises a first semiconductor unit, a second semiconductor unit and a third semiconductor unit, both ends of the first semiconductor unit are conductorized to form conductor areas, the position of the second semiconductor unit corresponds to the position of the bottom gate, and the third semiconductor unit is conductorized as a pixel electrode as a whole;

[0011] A second insulating layer is arranged on the semiconductor layer;

[0012] A second metal layer is arranged on the second insulating layer, and the second metal layer comprises a top gate and a driving circuit trace, and the top gate is located above the first semiconductor unit;

[0013] A first intermediate insulating layer is arranged on the second metal layer, and the first intermediate insulating layer is provided with a first through hole, a second through hole, a third through hole and a fourth through hole, the first through hole has two, the two first through holes are located on both sides of the top gate, respectively downwardly penetrating the second insulating layer, and respectively exposing the upper surfaces of the conductor areas at both ends of the first semiconductor unit; the second through hole has two, the two second through holes are located above the second semiconductor unit, respectively downwardly penetrating the second insulating layer, and exposing the upper surfaces of the second semiconductor unit; the third through hole is located above the pixel electrode, downwardly penetrating the second insulating layer, and exposing the upper surface of the pixel electrode; and the fourth through hole is located above the driving circuit trace, exposing the upper surface of the driving circuit trace;

[0014] a transparent conductive layer disposed on the first intermediate insulating layer, the transparent conductive layer comprising a common electrode;

[0015] a third metal layer disposed on the first intermediate insulating layer, the third metal layer comprising a first source electrode, a first drain electrode, a second source electrode, a second drain electrode and a metal unit one, the first source electrode and the first drain electrode being connected to the corresponding conductor region through the corresponding first via hole; the second source electrode and the second drain electrode being connected to the two ends of the second semiconductor unit through the corresponding second via hole; the other end of the second drain electrode being connected to the pixel electrode through the third via hole, one end of the metal unit one being overlapped with the common electrode, and the other end being connected to the driving circuit trace through the fourth via hole;

[0016] the film layer structure corresponding to the top gate is a driving circuit region TFT, the film layer structure corresponding to the bottom gate is a display region TFT, and the film layer structure corresponding to the driving circuit trace is a metal line region.

[0017] Further, the non-channel region at the two ends of the first semiconductor unit and the third semiconductor unit are subjected to ion doping treatment to make the region conductive, forming a conductor region.

[0018] Further, the oxide array substrate further comprises a second intermediate insulating layer disposed between the transparent conductive layer and the third metal layer, and the second intermediate insulating layer is further provided with a fifth via hole, and one end of the metal unit one is connected to the common electrode through the fifth via hole.

[0019] The first via hole, the second via hole, the third via hole and the fourth via hole all penetrate the second intermediate insulating layer upward.

[0020] The second aspect of the technical problem to be solved by the present application is to provide a preparation method of an oxide array substrate with low parasitic capacitance effect, which sets the conductive semiconductor layer as a pixel electrode, thereby saving film layers, simplifying the process, setting only one intermediate insulating layer, having higher light transmittance, and improving the problems of large parasitic capacitance and single function of the light shielding layer in the existing structure, and having the advantages of low cost and high film utilization rate.

[0021] The present application solves the second aspect of the technical problem as follows:

[0022] A preparation method of an oxide array substrate with low parasitic capacitance effect, the method steps are as follows:

[0023] Step 1: forming a first metal layer on a glass substrate to prepare a bottom gate and related driving signal lines;

[0024] Step 2, forming a first insulating layer on the first metal layer; the first insulating layer in the display area as a bottom gate TFT gate insulating layer, the first insulating layer in the driving circuit area as a buffer layer under the active layer, i.e., the first semiconductor unit;

[0025] Step 3, forming a semiconductor layer on the first insulating layer, and preparing a first semiconductor unit, a second semiconductor unit, and a third semiconductor unit, and then conducting the first semiconductor unit left and right ends and the third semiconductor unit; after the two ends of the first semiconductor unit are respectively conducted, a conductor area is formed, and after the third semiconductor unit is conducted as a whole, it is set as a pixel electrode;

[0026] Step 4, forming a second insulating layer on the semiconductor layer as a top gate TFT gate insulating layer;

[0027] Step 5, forming a second metal layer on the second insulating layer, and preparing a top gate and a driving circuit trace, or other signal traces, the top gate being located above the first semiconductor unit;

[0028] Step 6, forming a first intermediate insulating layer on the second metal layer;

[0029] Step 7, forming a transparent conductive layer on the first intermediate insulating layer, and preparing a common electrode; and preparing a first via hole, a second via hole, a third via hole, and a fourth via hole on the first intermediate insulating layer, respectively exposing the conductor area at the two ends of the first semiconductor unit, the second semiconductor unit, the pixel electrode, and the upper surface of the driving circuit trace;

[0030] Step 8, forming a third metal layer on the transparent conductive layer, and preparing a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a metal unit one; wherein the first source electrode and the first drain electrode are respectively connected to the corresponding conductor area through the corresponding first via hole; the second source electrode and the second drain electrode are respectively connected to the two ends of the second semiconductor unit through the corresponding second via hole; one end of the second drain electrode is also connected to the pixel electrode through the third via hole; one end of the metal unit one is overlapped with the common electrode, and the other end is connected to the driving circuit trace through the fourth via hole.

[0031] Further, when the oxide array substrate further comprises a second intermediate insulating layer, the second intermediate insulating layer is arranged between the transparent conductive layer and the third metal layer, and a fifth via hole is further arranged on the second intermediate insulating layer, one end of the metal unit one is connected to the common electrode through the fifth via hole;

[0032] The first via hole, the second via hole, the third via hole and the fourth via hole are all prepared from the second intermediate insulating layer, that is, the first via hole, the second via hole and the third via hole all penetrate the second intermediate insulating layer, the first intermediate insulating layer and the second insulating layer downwards; and the fourth via hole penetrates the second intermediate insulating layer and the first intermediate insulating layer.

[0033] Further, the first metal layer, the second metal layer and the third metal layer are selected from one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten, form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0034] Further, the first insulating layer, the second insulating layer, the first intermediate insulating layer and the second intermediate insulating layer are single-layer or multi-layer structures, and the material is selected from inorganic oxides or insulating compounds.

[0035] Further, the material of the transparent conductive layer is ITO.

[0036] The present application has the following advantages:

[0037] In the array substrate structure of the present application, the semiconductor layer after being made conductive is used as a pixel electrode, and the use of a transparent conductive film layer is omitted, thereby further simplifying the process and reducing the cost. The two ends of the semiconductor layer at the position of the top-gate TFT are made conductive, thereby reducing the contact resistance of the source-drain contact area. Only one intermediate insulating layer is provided, thereby further simplifying the film layer structure, having higher light transmittance and lower preparation cost.

[0038] Meanwhile, in the array substrate structure of the present application, the top-gate structure and the bottom-gate structure TFT devices are respectively arranged at the positions corresponding to the driving circuit area and the display area, so that the array substrate structure not only has the low parasitic capacitance driving advantage of the top-gate structure, but also overcomes the single-function disadvantage of the added light shielding layer in the existing structure, and has the benefit advantage of low manufacturing cost, and is suitable for the low-cost development of high-resolution and high-refresh-rate display panels. BRIEF DESCRIPTION OF DRAWINGS

[0039] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0040] Figure 1 FIG. 1 is a structural diagram of an oxide array substrate with low parasitic capacitance effect according to the present application.

[0041] Figure 2 FIG. 2 is another structural diagram of an oxide array substrate with low parasitic capacitance effect according to the present application.

[0042] Figure 3Flow chart of steps 1-4 of the method for preparing an oxide array substrate with low parasitic capacitance effect according to the present application.

[0043] Figure 4 Flow chart of steps 5-8 of the method for preparing an oxide array substrate with low parasitic capacitance effect according to the present application.

[0044] Explanation of reference signs:

[0045] Glass substrate 1;

[0046] First metal layer 2, bottom gate 21;

[0047] First insulating layer 3;

[0048] Semiconductor layer 4, first semiconductor unit 41, second semiconductor unit 42, third semiconductor unit 43, conductor region 411, pixel electrode 431;

[0049] Second insulating layer 5;

[0050] Second metal layer 6, top gate 61, drive circuit trace 62;

[0051] First intermediate insulating layer 7, first via 71, second via 72, third via 73, fourth via 74;

[0052] Transparent conductive layer 8, common electrode 81;

[0053] Third metal layer 9, first source 91, first drain 92, second source 93, second drain 94, metal unit 95;

[0054] Second intermediate insulating layer 10, fifth via 101;

[0055] Drive circuit region TFT 100, display region TFT 200, metal line region 300.

DETAILED DESCRIPTION

[0056] The technical solutions of the present application will be described below in conjunction with the accompanying drawings and the detailed description. Figures 1-4 The technical solutions of the present application will be described below in conjunction with the accompanying drawings and the detailed description.

[0057] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0058] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0059] Please refer to Figure 1 The present application relates to an oxide array substrate with low parasitic capacitance effect, which comprises a glass substrate 1,

[0060] A first metal layer 2 is arranged on the glass substrate 1, and the first metal layer 2 comprises a bottom gate 21;

[0061] A first insulating layer 3 is arranged on the first metal layer 2;

[0062] A semiconductor layer 4 is arranged on the first insulating layer 3, and the semiconductor layer 4 comprises a first semiconductor unit 41, a second semiconductor unit 42 and a third semiconductor unit 43, both ends of the first semiconductor unit 41 are conductive to form a conductor area 411, the position of the second semiconductor unit 42 corresponds to the position of the bottom gate 21, and the third semiconductor unit 43 is integrally conductive and arranged as a pixel electrode 431;

[0063] A second insulating layer 5 is arranged on the semiconductor layer 4;

[0064] A second metal layer 6 is arranged on the second insulating layer 5, and the second metal layer 6 comprises a top gate 61 and a driving circuit trace 62, and the top gate 61 is located above the first semiconductor unit 41;

[0065] A first intermediate insulating layer 7 is arranged on the second metal layer 6, and the first intermediate insulating layer 7 is provided with a first through hole 71, a second through hole 72, a third through hole 73 and a fourth through hole 74. The first through hole 71 has two first through holes 71, and the two first through holes 71 are respectively located on both sides of the top gate 61 and downwardly penetrate the second insulating layer 5 and respectively expose the conductor area 411 upper surface at both ends of the first semiconductor unit 41. The second through hole 72 has two second through holes 72, and the two second through holes 72 are respectively located above the second semiconductor unit 42 and downwardly penetrate the second insulating layer 5 and expose the upper surface of the second semiconductor unit 42. The third through hole 73 is located above the pixel electrode 431 and downwardly penetrates the second insulating layer 5 and exposes the upper surface of the pixel electrode 431. The fourth through hole 74 is located above the drive circuit trace 62 and exposes the upper surface of the drive circuit trace 62.

[0066] A transparent conductive layer 8 is arranged on the first intermediate insulating layer 7, and the transparent conductive layer 8 includes a common electrode 81.

[0067] A third metal layer 9 is arranged on the first intermediate insulating layer 7, and the third metal layer 9 includes a first source electrode 91, a first drain electrode 92, a second source electrode 93, a second drain electrode 94 and a metal unit 95. The first source electrode 91 and the first drain electrode 92 are respectively connected with the corresponding conductor area 411 through the corresponding first through hole 71. The second source electrode 93 and the second drain electrode 94 are respectively connected with both ends of the second semiconductor unit 42 through the corresponding second through hole 72. The other end of the second drain electrode 94 is also connected with the pixel electrode 431 through the third through hole 73. One end of the metal unit 95 is overlapped with the common electrode 81, and the other end of the metal unit 95 is connected with the drive circuit trace 62 through the fourth through hole 74.

[0068] The film layer structure corresponding to the top gate 61 is a drive circuit area TFT 100, the film layer structure corresponding to the bottom gate 21 is a display area TFT 200, and the film layer structure corresponding to the drive circuit trace 62 is a metal wire area 300.

[0069] In a specific implementation, a preferred embodiment is that the non-channel region at both ends of the first semiconductor unit 41 and the third semiconductor unit 43 are subjected to ion doping treatment to make the region conductive to form a conductor area.

[0070] Referring to Figure 2In a specific implementation, a preferred embodiment is as follows: when the oxide array substrate further includes a second intermediate insulating layer 10, the second intermediate insulating layer 10 is disposed between the transparent conductive layer 8 and the third metal layer 9, and a fifth through hole 101 is further disposed on the second intermediate insulating layer 10, and one end of the metal unit 95 is connected to the common electrode 81 through the fifth through hole 101;

[0071] The first through hole 71 , the second through hole 72 , the third through hole 73 and the fourth through hole 74 all pass upward through the second intermediate insulating layer 10 .

[0072] See Figures 3-4 As shown, the present invention also relates to a method for preparing the above-mentioned oxide array substrate with low parasitic capacitance effect, and the method steps are as follows:

[0073] Step 1: forming a first metal layer 2 on a glass substrate 1 to prepare a bottom gate 21 and related driving signal lines;

[0074] Step 2: forming a first insulating layer 3 on the first metal layer 2; the first insulating layer 3 in the display area serves as a bottom-gate TFT gate insulating layer, and the first insulating layer 3 in the driving circuit area serves as an active layer, i.e., a buffer layer below the first semiconductor unit 41;

[0075] Step 3: Forming a semiconductor layer 4 on the first insulating layer 3 to form a first semiconductor unit 41, a second semiconductor unit 42, and a third semiconductor unit 43. Conductivity treatment is then performed on the left and right ends of the first semiconductor unit 41 and the third semiconductor unit 43. The two ends of the first semiconductor unit 41 are each conductively conductive to form a conductive region 411. The entire third semiconductor unit 43 is conductively conductive to form a pixel electrode 431.

[0076] Step 4: forming a second insulating layer 5 on the semiconductor layer 4 as a gate insulating layer of the top-gate TFT;

[0077] Step 5: forming a second metal layer 6 on the second insulating layer 5 and preparing a top gate 61 and a drive circuit trace 62 or other signal traces. The top gate 61 is located above the first semiconductor unit 41.

[0078] Step 6: forming a first intermediate insulating layer 7 on the second metal layer 6;

[0079] Step 7: Form a transparent conductive layer 8 on the first intermediate insulating layer 7 and prepare a common electrode 81; and form a first through hole 71, a second through hole 72, a third through hole 73, and a fourth through hole 74 on the first intermediate insulating layer 7, respectively exposing the upper surfaces of the conductor regions 411 at both ends of the first semiconductor unit 41, the second semiconductor unit 42, the pixel electrode 431, and the drive circuit trace 62;

[0080] Step 8, a third metal layer 9 is formed on the transparent conductive layer 8, and a first source electrode 91, a first drain electrode 92, a second source electrode 93, a second drain electrode 94 and a metal unit one 95 are prepared; the first source electrode 91 and the first drain electrode 92 are connected with the corresponding conductor region 411 through the corresponding first via hole 71; the second source electrode 93 and the second drain electrode 94 are connected with the two ends of the second semiconductor unit 42 through the corresponding second via hole 72; the other end of the second drain electrode 94 is also connected with the pixel electrode 431 through a third via hole 73; one end of the metal unit one 95 is overlapped with the common electrode 81, and the other end is connected with the driving circuit trace 62 through a fourth via hole 74.

[0081] Referring to Figure 2 In a specific implementation, preferably, one embodiment is that when the oxide array substrate further comprises a second intermediate insulating layer 10, the second intermediate insulating layer 10 is arranged between the transparent conductive layer 8 and the third metal layer 9, and a fifth via hole 101 is further arranged on the second intermediate insulating layer 10, and one end of the metal unit one 95 is connected with the common electrode 81 through the fifth via hole 101.

[0082] The first via hole 71, the second via hole 72, the third via hole 73 and the fourth via hole 74 are all prepared from the second intermediate insulating layer 10, that is, the first via hole 71, the second via hole 72 and the third via hole 73 all downwardly penetrate the second intermediate insulating layer 10, the first intermediate insulating layer 7 and the second insulating layer 5; and the fourth via hole 74 penetrates the second intermediate insulating layer 10 and the first intermediate insulating layer 7.

[0083] In a specific implementation, preferably, one embodiment is that the first metal layer 2, the second metal layer 6 and the third metal layer 9 are selected from one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten, form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0084] In a specific implementation, preferably, one embodiment is that the first insulating layer 3, the second insulating layer 6, the first intermediate insulating layer 7 and the second intermediate insulating layer 10 are single-layer or multi-layer structures, and the material is selected from inorganic oxides or insulating compounds.

[0085] In a specific implementation, preferably, one embodiment is that the material of the transparent conductive layer 8 is ITO.

[0086] In summary, in the array substrate structure of the present application, the process of conductorizing the semiconductor layer is used, the conductorized semiconductor layer is arranged as the pixel electrode, the use of a transparent conductive film layer is omitted, the process is further simplified and the cost is reduced, the two ends of the semiconductor layer at the top gate TFT position are conductorized, the contact resistance of the source and drain contact area can be reduced, only one intermediate insulating layer can be arranged, the film layer structure is further simplified, the light transmittance is higher and the preparation cost is lower;

[0087] Meanwhile, in the array substrate structure of the present application, the top gate structure TFT device and the bottom gate structure TFT device are respectively arranged at the corresponding positions of the driving circuit area and the display area, therefore, the array substrate structure not only has the low parasitic capacitance driving advantage of the top gate structure, overcomes the single function of the added light shielding layer in the prior art structure, has the benefit advantage of low manufacturing cost, and is suitable for the low cost development of high resolution and high refresh rate display panels.

[0088] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. An oxide array substrate having low parasitic capacitance effects, characterized by: The oxide array substrate comprises a glass substrate, a first metal layer disposed on the glass substrate, the first metal layer comprising a bottom gate; a first insulating layer disposed on the first metal layer; a semiconductor layer disposed on the first insulating layer, the semiconductor layer comprising a first semiconductor unit, a second semiconductor unit and a third semiconductor unit, both ends of the first semiconductor unit being respectively conductorized to form a conductor region, the second semiconductor unit being located corresponding to the position of the bottom gate, and the third semiconductor unit being wholly conductorized to be disposed as a pixel electrode; a second insulating layer disposed on the semiconductor layer; a second metal layer disposed on the second insulating layer, the second metal layer comprising a top gate and a driving circuit trace, the top gate being located above the first semiconductor unit; a first intermediate insulating layer disposed on the second metal layer, the first intermediate insulating layer being provided with a first through hole, a second through hole, a third through hole and a fourth through hole, the first through hole being two, the two first through holes being respectively located on both sides of the top gate, and downwardly penetrating the second insulating layer and respectively exposing the upper surfaces of the conductor regions at both ends of the first semiconductor unit, the second through hole being two, the two second through holes being respectively located above the second semiconductor unit, and downwardly penetrating the second insulating layer and exposing the upper surfaces of the second semiconductor unit, the third through hole being located above the pixel electrode, and downwardly penetrating the second insulating layer and exposing the upper surface of the pixel electrode, and the fourth through hole being located above the driving circuit trace and exposing the upper surface of the driving circuit trace; a transparent conductive layer disposed on the first intermediate insulating layer, the transparent conductive layer comprising a common electrode; a third metal layer disposed on the first intermediate insulating layer, the third metal layer comprising a first source electrode, a first drain electrode, a second source electrode, a second drain electrode and a metal unit one, the first source electrode and the first drain electrode being respectively connected with the corresponding conductor regions through the corresponding first through holes; the second source electrode and the second drain electrode being respectively connected with both ends of the second semiconductor unit through the corresponding second through holes; the other end of the second drain electrode being further connected with the pixel electrode through the third through hole, one end of the metal unit one being overlapped with the common electrode, and the other end being connected with the driving circuit trace through the fourth through hole; the film layer structure corresponding to the top gate is a driving circuit area TFT, the film layer structure corresponding to the bottom gate is a display area TFT, and the film layer structure corresponding to the driving circuit trace is a metal wire area.

2. The oxide array substrate with low parasitic capacitance effect according to claim 1, wherein: The non-channel region at both ends of the first semiconductor unit and the third semiconductor unit are subjected to ion doping treatment to make the region conductorized to form a conductor region.

3. The oxide array substrate with low parasitic capacitance effect according to claim 1, wherein: When the oxide array substrate further comprises a second intermediate insulating layer disposed between the transparent conductive layer and the third metal layer, the second intermediate insulating layer is further provided with a fifth through hole, and one end of the metal unit one is connected with the common electrode through the fifth through hole; the first through hole, the second through hole, the third through hole and the fourth through hole all upwardly penetrate the second intermediate insulating layer.

4. A method for fabricating an oxide array substrate having a low parasitic capacitance effect, comprising the steps of: The array substrate prepared by the method is an oxide array substrate with low parasitic capacitance effect according to claim 1 or 2, and the method comprises the following steps: ​ Step 1, forming a first metal layer on a glass substrate to prepare a bottom gate and a related driving signal line; Step 2, forming a first insulating layer on the first metal layer; The first insulating layer in the display area serves as a bottom gate TFT gate insulating layer, and the first insulating layer in the driving circuit area serves as a buffer layer under an active layer, i.e., a first semiconductor unit; Step 3, forming a semiconductor layer on the first insulating layer to prepare a first semiconductor unit, a second semiconductor unit and a third semiconductor unit, and then conducting processing on the left and right ends of the first semiconductor unit and the third semiconductor unit; after the two ends of the first semiconductor unit are respectively conducted, a conductor area is formed, and after the third semiconductor unit is wholly conducted, a pixel electrode is formed; Step 4, forming a second insulating layer on the semiconductor layer as a top gate TFT gate insulating layer; Step 5, forming a second metal layer on the second insulating layer to prepare a top gate and a driving circuit trace, or other signal traces, and the top gate is located above the first semiconductor unit; Step 6, forming a first intermediate insulating layer on the second metal layer; Step 7, forming a transparent conductive layer on the first intermediate insulating layer to prepare a common electrode, and forming a first via hole, a second via hole, a third via hole and a fourth via hole on the first intermediate insulating layer to respectively expose the conductor area at the two ends of the first semiconductor unit, the second semiconductor unit, the pixel electrode and the upper surface of the driving circuit trace; Step 8, forming a third metal layer on the transparent conductive layer to prepare a first source electrode, a first drain electrode, a second source electrode, a second drain electrode and a metal unit one; the first source electrode and the first drain electrode are respectively connected with the corresponding conductor area through the corresponding first via hole; the second source electrode and the second drain electrode are respectively connected with the two ends of the second semiconductor unit through the corresponding second via hole; one end of the second drain electrode is further connected with the pixel electrode through the third via hole; one end of the metal unit one is overlapped with the common electrode, and the other end is connected with the driving circuit trace through the fourth via hole.

5. The method of claim 4, wherein the method further comprises: When the oxide array substrate further comprises a second intermediate insulating layer arranged between the transparent conductive layer and the third metal layer, a fifth via hole is further arranged on the second intermediate insulating layer, and one end of the metal unit one is connected with the common electrode through the fifth via hole; ​ The first via hole, the second via hole, the third via hole and the fourth via hole are all prepared from the second intermediate insulating layer, i.e., the first via hole, the second via hole and the third via hole all downwardly penetrate the second intermediate insulating layer, the first intermediate insulating layer and the second insulating layer; the fourth via hole penetrates the second intermediate insulating layer and the first intermediate insulating layer.

6. The method of claim 4, wherein the method further comprises: The first metal layer, the second metal layer and the third metal layer are selected from one of aluminum, molybdenum, titanium, nickel, copper, silver and tungsten to form a single-layer structure, a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

7. The method of claim 4, wherein the method further comprises: depositing a first oxide layer on the substrate; and depositing a second oxide layer on the first oxide layer. The first insulating layer, the second insulating layer, the first intermediate insulating layer and the second intermediate insulating layer are single-layer or multi-layer structures, and the material is selected from inorganic oxides or compounds with insulating properties.

8. The method of claim 4, wherein the method further comprises: depositing a first oxide layer on the substrate; and depositing a second oxide layer on the first oxide layer. The material of the transparent conductive layer is ITO.

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