A low power Schmitt trigger structure

Abstract

The present invention discloses a low-power Schmitt trigger structure, which belongs to the field of integrated circuits. A first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, and a third NMOS tube constitute a Schmitt inverter input stage; a fourth NMOS tube and a fourth PMOS tube constitute an inverter output stage. The present invention reduces the dynamic power consumption of the Schmitt trigger while only changing the connection; the gate end of the NMOS tube and the gate end of the PMOS tube in the inverter output stage are separately connected to different signals, and lower power consumption is achieved without affecting the logical function and flip threshold of the Schmitt trigger. The dynamic power consumption of the Schmitt trigger is reduced without increasing the complexity of the circuit, providing significant advantages for low-power applications.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power Schmitt trigger structure. Background Art

[0002] The Schmitt trigger is a circuit structure that is triggered by the input level and has two threshold voltages. The Schmitt trigger uses a Schmitt inverter as the input stage and a normal inverter as the output stage. When the input level of the Schmitt trigger changes from a low level (ground) to a high level (power supply voltage), the output is equal to V th_h When the input level changes from high to low, the output voltage is equal to V th_l When it flips from high level to low level. Generally, V th_h >V th_ l.

[0003] The operating power consumption of a Schmitt trigger can be used as one of the criteria for judging its performance. The operating power consumption of a Schmitt trigger includes static power consumption and dynamic power consumption, and dynamic power consumption accounts for the vast majority of the total power consumption. Dynamic power consumption can be divided into switching power consumption and internal power consumption. Summary of the invention

[0004] The object of the present invention is to provide a low-power Schmitt trigger structure to solve the problems in the background technology.

[0005] To solve the above technical problems, the present invention provides a low-power Schmitt trigger structure, including a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

[0006] The gate end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the first NMOS tube and the gate end of the second NMOS tube are all connected to the input signal Vin;

[0007] The source end of the first PMOS tube is connected to the power supply voltage Vdd, the drain end of the first PMOS tube is connected to the source end of the second PMOS tube; the drain end of the second PMOS tube is connected to the drain end of the second NMOS tube, the source end of the second NMOS tube is connected to the drain end of the first NMOS tube, and the source end of the first NMOS tube is grounded;

[0008] The source end of the third PMOS tube is connected to the drain end of the first PMOS tube and the source end of the second PMOS tube at the same time, the gate end of the third PMOS tube is connected to the drain end of the second PMOS tube and the drain end of the second NMOS tube at the same time, and the drain end of the third PMOS tube is grounded;

[0009] The source end of the third NMOS tube is connected to the source end of the second NMOS tube and the drain end of the first NMOS tube at the same time, the gate end of the third NMOS tube is connected to the drain end of the second PMOS tube and the drain end of the second NMOS tube at the same time, and the drain end of the third NMOS tube is connected to the power supply voltage Vdd;

[0010] The source terminal of the fourth PMOS tube is connected to the power supply voltage Vdd, the gate terminal of the fourth PMOS tube is simultaneously connected to the drain terminal of the first PMOS tube, the source terminal of the second PMOS tube and the source terminal of the third PMOS tube, the drain terminal of the fourth PMOS tube is connected to the drain terminal of the fourth NMOS tube, the gate terminal of the fourth NMOS tube is simultaneously connected to the drain terminal of the first NMOS tube, the source terminal of the second NMOS tube and the source terminal of the third NMOS tube, and the source terminal of the fourth NMOS tube is grounded.

[0011] A low-power Schmitt trigger structure provided by the present invention reduces the dynamic power consumption of the Schmitt trigger while only changing the connection; the dynamic power consumption of the Schmitt trigger is reduced without increasing the complexity of the circuit, providing significant advantages for low-power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention provides a schematic diagram of a low-power Schmitt trigger structure. DETAILED DESCRIPTION

[0013] The following is a further detailed description of a low-power Schmitt trigger structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0014] The present invention provides a low-power Schmitt trigger structure, such as Figure 1As shown, it includes PMOS tubes MP1-MP4 and NMOS tubes MN1-MN4; the source end of the PMOS tube MP1 is connected to the power supply voltage Vdd, the drain end of the PMOS tube MP1 is connected to the source end of the PMOS tube MP2; the drain end of the PMOS tube MP2 is connected to the drain end of the NMOS tube MN2, the source end of the NMOS tube MN2 is connected to the drain end of the NMOS tube MN1, and the source end of the NMOS tube MN1 is grounded; the gate end of the PMOS tube MP1, the gate end of the PMOS tube MP2, the gate end of the NMOS tube MN1 and the gate end of the NMOS tube MN2 are all connected to the input signal Vin. The source end of the PMOS tube MP3 is simultaneously connected to the drain end of the PMOS tube MP1 and the source end of the PMOS tube MP2, the gate end of the PMOS tube MP3 is simultaneously connected to the drain end of the PMOS tube MP2 and the drain end of the NMOS tube MN2, and the drain end of the PMOS tube MP3 is grounded. The source end of the NMOS tube MN3 is connected to the source end of the NMOS tube MN2 and the drain end of the NMOS tube MN1 at the same time, the gate end of the NMOS tube MN3 is connected to the drain end of the PMOS tube MP2 and the drain end of the NMOS tube MN2 at the same time, and the drain end of the NMOS tube MN3 is connected to the power supply voltage Vdd. The source end of the PMOS tube MP4 is connected to the power supply voltage Vdd, the gate end of the PMOS tube MP4 is connected to the drain end of the PMOS tube MP1, the source end of the PMOS tube MP2 and the source end of the PMOS tube MP3 at the same time, the drain end of the PMOS tube MP4 is connected to the drain end of the NMOS tube MN4, the gate end of the NMOS tube MN4 is connected to the drain end of the NMOS tube MN1, the source end of the NMOS tube MN2 and the source end of the NMOS tube MN3 at the same time, and the source end of the NMOS tube MN4 is grounded.

[0015] Here’s how it works:

[0016] 1. Schmitt inverter input stage. PMOS tubes MP1, MP2, MP3 and NMOS tubes MN1, MN2, MN3 form the Schmitt inverter input stage. When the input Vin is low level, Vschm = Vschm_p = Vdd, Vschm_n = Vdd-Vthn, Vthn is the threshold voltage of the NMOS tube. When the input Vin is high level, Vschm = Vschm_n = GND, Vschm_p = Vthp, Vthp is the threshold voltage of the PMOS tube. When the input Vin flips from low level to high level, the output flipped V th_h Ratio to PMOS tube MP1 and PMOS tube MP3 (W / L) MP1 / (W / L) MP3 Related, where (W / L) MP1 is the width-to-length ratio of the PMOS tube MP1, (W / L) MP3 is the width-to-length ratio of the PMOS tube MP3; when the input Vin flips from a high level to a low level, the output flipped Vth_l Ratio to NMOS tube MN1 and NMOS tube MN3 (W / L) MN1 / (W / L) MN3 , where (W / L) MN1 is the width-to-length ratio of the NMOS tube MN1, (W / L) MN3 The switching power consumption of the Schmitt inverter driving the PMOS tube MP4 is 0.5*F*C*(Vdd-Vthp) 2 , the switch power consumption of driving NMOS tube MN4 is 0.5*F*C*(Vdd-Vthn) 2 Where F is the input signal switching frequency, and C is the equivalent total capacitance at the gate of the PMOS tube MP4.

[0017] 2. Inverter output stage. PMOS tube MP4 and NMOS tube MN4 constitute the inverter output stage. Note that the gate end of PMOS tube MP4 is simultaneously connected to the drain end of PMOS tube MP1, the source end of PMOS tube MP2, and the source end of PMOS tube MP3; the gate end of NMOS tube MN4 is simultaneously connected to the drain end of NMOS tube MN1, the source end of NMOS tube MN2, and the source end of NMOS tube MN3. When Vin flips from a low level to a high level, Vschm_n will first flip from a high level Vdd-Vthn to a low level GND, turning off NMOS tube MN4; after a certain delay TD1, Vschm_p will flip from a high level Vdd to a low level Vthp, turning on PMOS tube MP4 and flipping the output Vout from a low level to a high level. Similarly, when Vin flips from high level to low level, Vschm_p will first flip from low level Vthp to high level Vdd, turning off PMOS tube MP4; after a certain delay TD2, Vschm_n will flip from low level GND to high level Vdd-Vthn, turning on NMOS tube MN4 and flipping output Vout from high level to low level. Due to the existence of delays TD1 and TD2, the time when NMOS tube MN4 and PMOS tube MP4 are turned on at the same time is reduced, thereby reducing the short-circuit power consumption of the output inverter.

[0018] The present invention uses a new Schmitt trigger structure, and connects the gate end of the NMOS tube and the gate end of the PMOS tube in the inverter output stage to different signals separately, thereby achieving lower power consumption without affecting the logical function and flip threshold of the Schmitt trigger.

[0019] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low power Schmitt trigger structure, characterized in that: It includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; The gate end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the first NMOS tube and the gate end of the second NMOS tube are all connected to the input signal Vin; The source end of the first PMOS tube is connected to the power supply voltage Vdd, the drain end of the first PMOS tube is connected to the source end of the second PMOS tube; the drain end of the second PMOS tube is connected to the drain end of the second NMOS tube, the source end of the second NMOS tube is connected to the drain end of the first NMOS tube, and the source end of the first NMOS tube is grounded; The source end of the third PMOS tube is connected to the drain end of the first PMOS tube and the source end of the second PMOS tube at the same time, the gate end of the third PMOS tube is connected to the drain end of the second PMOS tube and the drain end of the second NMOS tube at the same time, and the drain end of the third PMOS tube is grounded; The source end of the third NMOS tube is connected to the source end of the second NMOS tube and the drain end of the first NMOS tube at the same time, the gate end of the third NMOS tube is connected to the drain end of the second PMOS tube and the drain end of the second NMOS tube at the same time, and the drain end of the third NMOS tube is connected to the power supply voltage Vdd; The source terminal of the fourth PMOS tube is connected to the power supply voltage Vdd, the gate terminal of the fourth PMOS tube is simultaneously connected to the drain terminal of the first PMOS tube, the source terminal of the second PMOS tube and the source terminal of the third PMOS tube, the drain terminal of the fourth PMOS tube is connected to the drain terminal of the fourth NMOS tube, the gate terminal of the fourth NMOS tube is simultaneously connected to the drain terminal of the first NMOS tube, the source terminal of the second NMOS tube and the source terminal of the third NMOS tube, and the source terminal of the fourth NMOS tube is grounded.

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