Circuitry for identifying the contents of Ethernet auto-negotiation frames

Abstract

The present application relates to the technical field of integrated circuits, and discloses a circuit for identifying the content of Ethernet auto-negotiation frames, including: a first calculation module, used to receive an input signal from a SerDes receiving end and identify the respective positions of a high level and a low level from the input signal; a signal edge detection module, used to identify the position where the high-low level jump occurs for the first time in each sampling cycle according to the respective positions of the identified high level and low level, and mark the jump position where the low level jumps to the high level first when it is continuously identified as a low level in each sampling cycle, and the jump position where the high level jumps to the low level first when it is continuously identified as a high level; a judgment addition and deletion module, used to determine whether to make an addition judgment and a deletion judgment according to whether the jump position changes; a second calculation and judgment output module, used to calculate the intermediate position according to the jump position and the addition judgment and the deletion judgment, and output the intermediate position as the judgment result. The present application can correctly identify the content of the auto-negotiation frame.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a circuit for identifying the content of Ethernet auto-negotiation frames. Background Art

[0002] Auto-Negotiation refers to the ability of network devices to automatically exchange information and determine the best communication parameters, including speed, duplex mode, and other related features, in an Ethernet connection. This process allows devices to negotiate the parameters that are best suited for communication between them when connected, resulting in more efficient data transmission. During the auto-negotiation process, when two devices are first connected or when the network configuration changes, they exchange a series of special frames to negotiate communication parameters. These frames contain the speed and duplex mode options supported by the devices, as well as other related features. Devices communicate based on each other's capabilities and preferences to ultimately determine the best communication parameters.

[0003] Auto-negotiation can effectively ensure compatibility between devices and can automatically adjust communication parameters when network configuration changes without manual intervention. This allows network administrators to manage the network more easily while ensuring optimal performance and reliability between network devices. This places high demands on the recognition of auto-negotiation frame content. Whether the frame content can be correctly identified within the required time becomes the key to the problem.

[0004] IEEE802.3 CL73 and other standards specify the format of Auto-Negotiation frames. The main content is to stipulate that the duration of each bit is 3.2ns (312.5Mbps) so that the peer device can communicate freely before the negotiation result is reached. This requires that the SerDes must be able to send and receive 312.5Mbps signals regardless of the working rate. Since they work on different crystal oscillators, there must be a frequency deviation between the clock frequency of the local device and the clock frequency of the peer device. At present, the common practice is to fix the local clock to an integer multiple of 312.5M (for example, SerDes works at 10.3125G, 33 times of 312.5M), and then use Bang-Bang clock data recovery (CDR) to lock the local clock to the input data for correct judgment. There are three problems with this approach. The first problem is that the influence of inter-symbol interference (ISI) caused by long 0 or long 1 at the corresponding 0 / 1 switching will cause the judgment error during switching (for example, SerDes may jump back and forth when switching 0 / 1). Problem 2 requires that the CDR performance should be stable and should not lose lock during operation, because the occurrence of bit leakage or multiple bits will cause the judgment of the frame content to be directly wrong. Problem 3 is that for high-speed SerDes, it is also necessary to support a relatively low rate for automatic negotiation, which will cause additional costs, and it is necessary to perform a rate switch before and after automatic negotiation to make the SerDes work in normal rate mode. The present invention proposes a circuit with a high recognition rate of automatic negotiation frames, which can correctly recognize the frame content 100% under normal circumstances.

[0005] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. The description herein is not admitted to be prior art as disclosed by inclusion in this section. Summary of the invention

[0006] The purpose of the present application is to provide a circuit for identifying the content of Ethernet auto-negotiation frames, and to correctly identify the content of the auto-negotiation frames.

[0007] The present application discloses a circuit for identifying Ethernet auto-negotiation frame content, comprising:

[0008] A first calculation module, configured to receive an input signal from a SerDes receiving end and identify respective positions of a high level and a low level from the input signal;

[0009] A signal edge detection module is used to identify the position where the high-low level jump occurs for the first time in each sampling period according to the respective positions of the identified high level and low level, and mark the jump position where the low level jumps to the high level first when it is continuously identified as the low level and the jump position where the high level jumps to the low level first when it is continuously identified as the high level in each sampling period;

[0010] A judgment module for adding or deleting is used to determine whether to make an addition judgment or a deletion judgment according to whether the jump position changes; and

[0011] The second calculation and decision output module is used to calculate the intermediate position according to the jump position and the addition decision and the deletion decision, and output the intermediate position as the decision result.

[0012] In a preferred example, the clock of the SerDes receiving end is M times the clock of the SerDes transmitting end, and the middle position is the position of the current jump position pushed back by floor(1 / 2*M) or floor(1 / 2*M)+1 bits, where M is a positive integer.

[0013] In a preferred example, M is 33.

[0014] In a preferred example, if no high-low level jump occurs in the current sampling cycle, the signal edge detection module maintains the jump position of the previous sampling cycle as the jump position of the current cycle.

[0015] In a preferred example, if the difference between the jump position of the current sampling cycle and the jump position of the previous sampling cycle is greater than a first predetermined value, the deletion decision includes deleting the middle position in the current sampling cycle calculated based on the jump position of the previous sampling cycle.

[0016] In a preferred example, the first predetermined value is 20.

[0017] In a preferred example, if the jump position changes from 0 to a maximum value, the addition and deletion judgment module determines to make a deletion judgment, and the deletion judgment includes deleting the middle position calculated based on the jump position of 0.

[0018] In a preferred example, if the difference between the jump position of the current sampling period and the jump position of the previous sampling period is less than a second predetermined value, the decision addition and deletion module determines to make an addition decision, and the addition decision includes adding an intermediate position by pushing the jump position of the current sampling period forward by floor(1 / 2*M) or floor(1 / 2*M)+1 bits, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end.

[0019] In a preferred example, the second predetermined value is -20.

[0020] In a preferred example, if the jump position changes from the maximum value to 0, the decision addition and deletion module determines to make an addition decision, and the addition decision includes adding an intermediate position by pushing the jump position of the maximum value back by floor(1 / 2*M) or floor(1 / 2*M)+1 bits, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end.

[0021] In the implementation mode of the present application, the position of long 0 (low level) or long 1 (high level) is not detected, but the position of 0 / 1 transition is detected, and the intermediate position is calculated according to the oversampling multiple using this transition position, and the recognition result of the intermediate position is output as the judgment result of this signal. Because there is enough margin available for oversampling, the problem of inter-symbol interference is avoided, and the content of the automatic negotiation frame can be 100% correctly identified.

[0022] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a block diagram of a circuit for identifying Ethernet auto-negotiation frame content according to an embodiment of the present application.

[0024] Figure 2 It is a schematic diagram of SerDes output according to one embodiment of the present application.

[0025] Figure 3 It is a schematic diagram of deletion judgment according to an embodiment of the present application.

[0026] Figure 4It is a schematic diagram of adding a judgment according to an embodiment of the present application.

[0027] In the accompanying drawings, the symbols are as follows:

[0028] 101- a first computing module;

[0029] 102-signal edge detection module;

[0030] 103-judgment addition and deletion module;

[0031] 104-a second calculation and decision output module;

[0032] 105-SerDes receiving end. DETAILED DESCRIPTION

[0033] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0034] Description of some concepts:

[0035] SerDes is the abbreviation of SERializer / DESerializer. It is a mainstream time division multiplexing (TDM) and point-to-point (P2P) serial communication technology. That is, multiple low-speed parallel signals are converted into high-speed serial signals at the sending end, and then passed through the transmission media (optical cable or copper wire), and finally the high-speed serial signals are converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology makes full use of the channel capacity of the transmission media, reduces the number of transmission channels and device pins required, and increases the transmission speed of the signal, thereby greatly reducing the communication cost.

[0036] The SerDes (Serializer / Deserializer) receiver is a component used to receive a serial data stream from a remote device and convert it into parallel data. The SerDes (Serializer / Deserializer) transmitter is a component used to convert parallel data into a serial data stream and send it. In high-speed serial communications, SerDes transmitters are often used to convert parallel data into serial signals suitable for transmission, such as in network equipment, storage systems, and communication systems.

[0037] The floor() function rounds a real number down to the nearest integer that is not greater than the original real number.

[0038] The cell() function rounds a real number up to the nearest integer that is not less than the original real number.

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0040] In one embodiment of the present application, a circuit for identifying the content of an Ethernet auto-negotiation frame is provided, and its block diagram is shown as follows: Figure 1 As shown, the circuit includes a first calculation module 101, a signal edge detection module 102, a decision addition and deletion module 103, and a second calculation and decision output module 104. The input of the first calculation module 101 is coupled to the SerDes receiving end (RX) 105. The output of the first calculation module 101 is coupled to the signal edge detection module 102 and the second calculation and decision output module 104. The output of the signal edge detection module 102 is coupled to the decision addition and deletion module 103. The output of the decision addition and deletion module 103 is coupled to the second calculation and decision output module 104.

[0041] The first calculation module 101 is used to receive an input signal from a SerDes receiving end (RX) 105 and identify the respective positions of a high level (expressed as "1") and a low level (expressed as "0") from the input signal. In one embodiment, the sampling clock of the SerDes RX 105 is 33 times the working clock of the SerDes transmitting end (not shown in the figure). For example, the working clock of the transmitting end is 312.5MHz, and the SerDes RX works at a frequency of 10.3125GHz, which is 33 times of 312.5MHz). When the voltage value of the input signal received by the first calculation module 101 from the SerDes RX 105 is higher than a preset threshold, the corresponding input signal is considered to be 1, and when the voltage value of the input signal received by the first calculation module 101 from the SerDes RX 105 is lower than the preset threshold, the corresponding input signal is considered to be 0. Accordingly, the first calculation module 101 identifies the input signal received from the SerDes RX 105 and determines the positions of each 1 and 0.

[0042] In one embodiment, the clock of the SerDes receiving end is M times the clock of the SerDes transmitting end, where M is a positive integer. In one embodiment, M is 33. It should be understood that in this application, M is 33 as an example for illustration, and it should be understood that in other embodiments of the application, M is not limited to this value, and can also be set to any other positive integer, such as any integer between 20 and 100.

[0043] Figure 2 Schematic diagram of SerDes input and output according to an embodiment of the present application, the transmitting end sends a "010" signal at 312.5MHz ( Figure 2When the signal a) in the middle reaches the SerDes RX 105, the ideal sampling and output result of the SerDes RX 105 is 33 0s, 33 1s, and 33 0s, such as Figure 2 As shown in the signal b. However, due to inter-symbol interference, a jump occurs when switching between 0 and 1. Therefore, the signal edge detection module 102 is used to identify the position where the high and low level jump occurs in each sampling period (or called a beat) from the input signal according to the respective positions of the identified high level and low level, and further identify the position where the 1 and 0 jump occurs according to the positions of 1 and 0 identified by the first calculation module 101, such as the position where the jump occurs from 1 to 0 or the position where the jump occurs from 0 to 1. In addition, the jump position where the low level first jumps to the high level when it is continuously identified as a low level is marked, and the jump position where the high level first jumps to the low level when it is continuously identified as a high level is marked (indicated as p1). For example, refer to Figure 2 As shown in the dotted box, the signal c has more than one transition from 0 to 1 or from 1 to 0, respectively. In this embodiment, only the position where the first transition from 0 to 1 or from 1 to 1 occurs in each sampling period is marked. When the first calculation module 101 continuously identifies 0, the signal edge detection module 102 marks the position where the first transition from 0 to 1 occurs. When the first calculation module 101 continuously identifies 1, the signal edge detection module 102 marks the position where the first transition from 1 to 0 occurs, and both are marked as p1.

[0044] It should be understood that the term "jump position p1" refers to the bit number corresponding to the position where the jump occurs in the current sampling period. The jump position p1 changes dynamically. For the "010" signal, a p1 jump position occurs every sampling period. It should be noted that only the position where the jump occurs for the first time is marked in each sampling period, that is, each sampling period has only one jump position p1.

[0045] In one embodiment, if no high-low level jump occurs in the current sampling cycle (i.e., the p1 position is not identified), the signal edge detection module maintains the jump position of the previous sampling cycle as the jump position of the current cycle. For example, if the jump position p1 of the previous sampling cycle is 0, if no 0 / 1 level jump occurs in the current sampling cycle, the jump position of the current sampling cycle defaults to p1=0, and the value of the jump position p1 is stored in the register and does not change.

[0046] The second calculation and judgment output module 104 calculates the middle position (expressed as p2) according to the jump position p1 and outputs the middle position as the judgment result. The middle position p2 is the position of floor(1 / 2*M) or floor(1 / 2*M)+1 bits pushed back from the current jump position p1. Wherein, floor() means rounding down. Taking M as 33 as an example, each week includes 33 bits, for example, in sequence from the 32nd bit to the 0th bit. floor(1 / 2*33)=16. It should be understood that the middle position p2 is the position of cell(1 / 2*M) or cell(1 / 2*M)+1 bits pushed back from the current jump position p1. Wherein, cell() means rounding up. For example, the middle position p2 is the current transition position p1 pushed back by floor(1 / 2*M) bits (i.e., 16 bits). When the current transition position corresponds to the 0th bit, the middle position can select the position corresponding to the 16th bit of the next cycle. When the current transition position corresponds to the 31st bit, the middle position can select the position corresponding to the 15th bit of the current cycle. It should be noted that there is only one middle position p2 in each sampling period.

[0047] Continue to refer Figure 1 As shown, the judgment adding and deleting module 103 is used to determine whether to make an adding judgment and a deleting judgment according to whether the jump position changes, and the second calculation and judgment output module 104 further calculates the middle position (expressed as p2) according to the jump position and the adding judgment and the deleting judgment and outputs the middle position as the judgment result. The adding judgment indicates adding an middle position, and the deleting judgment indicates deleting an middle position. If the jump position p1 changes, it indicates that there is a frequency deviation between the clock of the SerDes receiving end and the clock of the SerDes transmitting end.

[0048] Specifically, if the difference between the jump position of the current sampling period and the jump position of the previous sampling period is greater than the first predetermined value, the judgment addition and deletion module determines to make a deletion judgment, and the deletion judgment includes deleting the middle position in the current sampling period calculated according to the previous sampling period. In one embodiment, the first predetermined value can be 20. It should be understood that in other embodiments of the present application, the first predetermined value is not limited to this value, and can also be set to any other positive integer, such as any integer between 15 and M-1 (for example, 32). If the difference between the jump position of the current sampling period and the jump position of the previous sampling period is greater than the first predetermined value (for example, 20), it means that the data of the current period has a positive offset, and the middle position calculated according to the previous sampling period should be discarded.

[0049] In one embodiment, if the difference between the jump position of the current sampling period and the jump position of the previous sampling period is less than the second predetermined value, the judgment addition and deletion module determines to make an addition judgment, and the addition judgment includes adding an intermediate position to the jump position of the current sampling period by pushing the floor (1 / 2*M) or floor (1 / 2*M) + 1 bit position forward, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end. In one embodiment, the second predetermined value can be -20. It should be understood that in other embodiments of the present application, the second predetermined value is not limited to this value, and can also be set to any other positive integer, such as any integer between -15 and -(M-1) (for example, -32). If the difference between the jump position of the current sampling period and the jump position of the previous sampling period is less than the second predetermined value (for example, -20), it means that the data of the current period is negatively offset, and the current sampling period will lack an intermediate position, and the intermediate position needs to be supplemented and calculated.

[0050] In a specific embodiment, if the jump position changes from 0 to a maximum value, the addition and deletion decision module determines to make a deletion decision, and the deletion decision includes deleting the middle position calculated based on the jump position of 0.

[0051] In a specific embodiment, if the jump position changes from a maximum value to 0, the decision addition and deletion module determines to make an addition decision, and the addition decision includes adding an intermediate position by pushing the jump position of 0 forward by floor(1 / 2*M) or floor(1 / 2*M)+1 bits, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end.

[0052] It should be noted that the sampling order of each cycle is from the 32nd bit to the 0th bit, and the term "pushing back" means to calculate from the 32nd bit of the current cycle to the 0th bit in sequence, and it is possible to calculate to the next cycle. The term "pushing forward" means to calculate from the 0th bit of the current cycle to the 32nd bit in sequence, and it is possible to calculate to the previous cycle.

[0053] Figure 3It is a schematic diagram of deletion judgment according to an embodiment of the present application. The identification results of the high and low levels and their jump positions of 4 sampling cycles are shown respectively. In the first cycle, a jump occurs at the 0th bit, then p1=0. In the second cycle, the middle position inferred from p1=0 in the first cycle is the position of the 16th bit, p2=16. Moreover, the second cycle is all 1, and there is no jump position, so the jump position of the first cycle remains unchanged, that is, p1=0. In the third cycle, the middle position inferred from p1=0 in the second cycle is the position of the 16th bit, p2=16, and in addition, a 1 / 0 jump occurs at the 31st bit, then p1=31 exists, so the middle position inferred from p1=31 is the position of the 15th bit, p2=15. In the fourth cycle, a jump occurs at the 30th bit, then p1=30 exists, so the middle position inferred from p1=30 is the position of the 14th bit, p2=14. It can be found that two intermediate positions p2 are calculated in the third cycle. The correct intermediate position should be the position p2=15 calculated based on the actual 1 / 0 jump. Therefore, the intermediate position p2=16 estimated based on p1=0 in the second cycle is deleted. Figure 3 Deleted line indicates.

[0054] Figure 4 This is a schematic diagram of adding judgments according to an embodiment of the present application. The recognition results of the high and low levels and their jump positions of the four sampling cycles are shown respectively. In the first cycle, a jump occurs at the 31st bit, then p1=31, and the middle position inferred from it is the position of the 15th bit, p2=15. The second cycle is similar to the first cycle. In the third cycle, a jump occurs at the 0th bit, then p1=0, and the middle position inferred from it is the position of the 16th bit of the next cycle (the fourth cycle). In the fourth cycle, a jump occurs at the 0th bit, then p1=0 exists, so based on p1=0, the middle position of the next cycle is inferred to be the position of the 16th bit (not shown). It can be found that there is a lack of an intermediate position p2 in the third cycle, so the jump position p1=0 of the third cycle is pushed forward 16 bits to add an intermediate position p2=16, as shown Figure 4 Shown in the dashed box.

[0055] For problem 1, the idea of ​​the above circuit structure is not to detect the position of long 0 or long 1 ( Figure 2 Instead of detecting the first 0 / 1 change position ( Figure 2 p1 in , use this position to push back 1 / 2 bits of the oversampling multiple ( Figure 2Assuming that the SerDes operates at 10.3125G and has 33 times oversampling, the decision of 16 bits pushed back after finding the 0 / 1 change point is the desired decision result. In this way, there is no need to find the exact position of the 0 / 1 change point, because the 33 times oversampling behind has enough margin available, thus bypassing the inter-symbol interference problem mentioned above.

[0056] For the second problem, the present invention adds frequency deviation detection and processing. During the processing, the position p1 of the 0 / 1 jump is always detected. When the position of p1 in the parallel data is detected to have changed, it indicates that there is a frequency deviation between the input signal and the sampling clock. The positive or negative frequency deviation can also be determined from the increase or decrease of this position. If the position of p1 is within a data parallelism, it does not affect the judgment. When p1 jumps from 0 to the maximum, it indicates that there is a data deviation of 1 beat ( Figure 3 As shown), at this time, the data of this shot needs to be discarded ( Figure 3 p2=16 needs to be thrown away), on the contrary, if p1 jumps from the maximum to 0 ( Figure 4 As shown) this means that there is 1 beat of extra data that needs to be judged ( Figure 4 p2=14 in the figure needs to be supplemented).

[0057] Compared with question three, we only need to calculate an oversampling rate based on the clock frequency of the SerDes receiver and 312.5M to fully adapt to the circuit structure of this application.

[0058] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0059] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0060] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0061] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A circuit for identifying the content of an Ethernet auto-negotiation frame, characterized in that: include: A first calculation module, configured to receive an input signal from a SerDes receiving end and identify respective positions of a high level and a low level from the input signal, wherein a clock of the SerDes receiving end is M times a clock of the SerDes transmitting end; A signal edge detection module is used to identify the position where the high-low level jump occurs in each sampling period according to the respective positions of the identified high level and low level, and mark the jump position where the low level first jumps to the high level when it is continuously identified as the low level in each sampling period, and the jump position where the high level first jumps to the low level when it is continuously identified as the high level; A judgment module for adding or deleting is used to determine whether to make an addition judgment or a deletion judgment according to whether the jump position changes; as well as The second calculation and judgment output module is used to calculate the intermediate position according to the jump position and the addition judgment and the deletion judgment, and output the intermediate position as the judgment result, wherein the intermediate position is the position of the current jump position pushed back by floor(1 / 2*M) or floor(1 / 2*M)+1 bits, where M is a positive integer.

2. The circuit according to claim 1, characterized in that Each sampling period has only one toggle position, and each sampling period has only one intermediate position.

3. The circuit according to claim 1, characterized in that The M is 33.

4. The circuit according to claim 1, characterized in that If no high-low level jump occurs in the current sampling cycle, the signal edge detection module maintains the jump position of the previous sampling cycle as the jump position of the current cycle.

5. The circuit according to claim 1, characterized in that If the difference between the jump position of the current sampling cycle and the jump position of the previous sampling cycle is greater than a first predetermined value, the decision adding and deleting module determines to make a deletion decision, and the deletion decision includes deleting the middle position in the current sampling cycle calculated based on the jump position of the previous sampling cycle.

6. The circuit according to claim 5, characterized in that The first predetermined value is an integer of 20.

7. The circuit according to claim 5, characterized in that The first predetermined value is any integer between 15 and M-1.

8. The circuit according to claim 1, characterized in that If the difference between the jump position of the current sampling cycle and the jump position of the previous sampling cycle is less than a second predetermined value, the decision addition and deletion module determines to make an addition decision, and the addition decision includes adding an intermediate position by pushing the jump position of the current sampling cycle forward by floor(1 / 2*M) or floor(1 / 2*M)+1 bits.

9. The circuit according to claim 8, characterized in that The second predetermined value is an integer of -20.

10. The circuit according to claim 8, characterized in that The second predetermined value is any integer between -15 and -(M-1).

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