Method and apparatus for forming a wideband PRN signal

Abstract

A device for forming a broadband pseudo-random noise signal, comprising: a group of channels, each channel including a PRN code generator and an NCO with controlled frequency and phase, the NCO generating a gating pulse output to the PRN code generator. The PRN code generator forms a new +1 or -1 sequence element according to the gating pulse. The device also includes: a first modulator, the first modulator having a plurality of weight coefficients; a plurality of multipliers, each multiplied by one of the weight coefficients; an adder, the adder outputting the sum of the output signals of the plurality of multipliers; and a mixer having an orthogonal output signal, the mixer multiplies the output of the adder by a sine of a low intermediate frequency and the output of the adder by a cosine of a low intermediate frequency. The device also includes: a processor, the processor controlling a group of channels; a transceiver module, the transceiver module for receiving an orthogonal signal and / or transmitting an orthogonal signal; and an interface, the interface connecting the output of the mixer to the transceiver module.

Description

Technical Field

[0001] The present disclosure relates generally to methods and apparatus for generating signals, and in particular, to forming wideband pseudo-random noise signals for various applications. Background Art

[0002] Navigation equipment for industrial applications generally includes a satellite navigation receiver for receiving satellite signals, which can be used to determine the location of the receiver with a certain level of accuracy. These navigation devices are generally supplemented with additional hardware modules for generating additional navigation signals. These additional navigation signals can be similar to the received satellite signals and used for operations such as calibration or modification of the received satellite signals. The additional navigation signals can also be used as supplementary navigation signals to improve the accuracy of the positioning determination based on the received satellite signals. Therefore, the generated signal can be used to calibrate the receiving RF front end, to subtract the interference signal (from itself or the interference signal next to the transmitter) from the received signal, for local positioning of other receivers, millimeter wave radar, etc. The applications described above are generally implemented in the same device, although these applications are generally not used and / or operated at the same time. Generally speaking, the additional navigation signal generated is a broadband pseudo-random noise ("PRN") signal.

[0003] If the generated additional navigation signal is used as a subtraction signal to be subtracted from the received signal to eliminate unwanted echo signals or to solve the near-far problem in the case of code division multiple access ("CDMA"), the amplitude, carrier phase and code phase of the subtraction signal should be accurately adjusted. This accurate adjustment of the subtraction signal is performed so that the generated additional navigation signal is as close as possible to the unwanted signal that needs to be eliminated by the subtraction operation. For direct sequence CDMA ("DS-CDMA") signals based on PRNs with known code sequences, an accurate representation of the signal shape means the reproduction of the end-to-end characteristics of the RF front end through which the received signal passes. Typically, it is a low pass filter ("LPF").

[0004] In other cases, when a CDMA signal is an additional navigation signal generated for global or local positioning, the generated signal may appear as a sum of multiple signals based on different PRN codes with different amplitudes, chip rates, and subcarriers.

[0005] There are known satellite signals generated as a sum of different codes. For example, the Galileo Composite Binary Offset Carrier ("CBOC") is a satellite signal generated as a sum of different codes. Some components of the CBOC signal are transmitted with a larger amplitude than other components. A feature of the device that generates such a CBOC signal is the availability of a single numerically controlled oscillator ("NCO"), which causes the leading edge of all transitions of the signal level. In other words, all added signal components have the same code phase. The device does not adjust the phase using an arbitrary value. Such a device cannot be used to generate signals to subtract these signals from the received signal, and therefore, it cannot be used to attenuate interfering signals.

[0006] The known method and device for obtaining a code phase with an accurately generated leading edge by means of an interpolator at the output of a PRN generator are similar to the method described above. The interpolator is a set of transversal filters. In order to interpolate the multi-level signal at the output of the generator, all multiplication operations in the interpolator are multi-bit. The advantage of this embodiment is the quality representation of the signal in the case of subtracting the unwanted signal. The main disadvantage is the relatively high cost of the interpolator, which usually occupies a large area in the microchip. In addition, the added interpolator cannot be used to generate a composite signal for a local positioning system. In order to generate a multi-level composite signal, it is necessary to combine with a device as described above, which may require additional expenses for additional hardware.

[0007] Another method to solve the near-far problem is by subtracting a copy of the unwanted signal from the received signal. This subtraction is performed at the output of the correlator. The subtracted value is taken from a table of cross-correlation functions of the interfering unwanted signal and the desired signal containing all possible code phases and Doppler shifts. This method allows the desired signal to be corrected by eliminating the interference effect on the correlation result level. The disadvantage of this method is that a large table for each possible pair of unwanted and desired signals needs to be stored and applied. Some signals (for example, signals that are not currently being tracked because they have not yet been found) cannot be corrected by this method.

[0008] The method and device described above make it possible to solve the problems associated with generating wideband PRN signals to a certain extent. However, solving multiple functions in the same device requires additional hardware, which may be cost-prohibitive. Summary of the invention

[0009] In one embodiment, a device for forming a pseudo-random broadband signal includes: a group of channels, each channel includes a numerically controlled oscillator ("NCO") with controlled frequency and phase and a pseudo-random number ("PRN") code generator, the NCO generates a strobe pulse output to the PRN code generator. The PRN code generator forms a new +1 or -1 sequence element in response to the strobe pulse. The device also includes: a first modulator, the first modulator having a plurality of weight coefficients; a plurality of multipliers, each multiplied by one of the weight coefficients; an adder, the adder outputting the sum of the plurality of multiplier output signals; and a mixer having an orthogonal output signal, the mixer multiplies the output of the adder by a sine of a low intermediate frequency and the output of the adder by a cosine of a low intermediate frequency. The device also includes: a processor, the processor controlling the group of channels; a transceiver module, the transceiver for receiving and / or transmitting orthogonal signals; and an interface connecting the output of the mixer to the transceiver module.

[0010] In one embodiment, the interface includes a quadrature DAC, the input of which is connected to the quadrature mixer output, and the output of which is connected to the RF channel. Alternatively, the interface may include a quadrature ADC, the input of which is connected to the RF front end, and the output of which is added to the output of the quadrature mixer.

[0011] In one embodiment, the interface also includes an orthogonal ADC and an orthogonal DAC, the input of the orthogonal ADC and the output of the orthogonal DAC are connected to the RF front end, the signal from the output of the orthogonal DAC is converted to an intermediate frequency or a radio frequency in the transmitting part of the RF front end and then converted back to zero frequency or near zero frequency in the receiving part of the RF front end, and the signal is added to the broadcast radio signal received from the antenna at a radio frequency or replaces the broadcast radio signal received from the antenna.

[0012] In one embodiment, the device may be part of a transmitter or receiver for local positioning signals or part of a GNSS receiver.

[0013] A method for forming a pseudo-random broadband signal is also disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 shows a schematic diagram of a wideband pseudo-random noise ("WPRN") former according to one embodiment;

[0015] Figure 2A Shows Figure 1 Details of one embodiment of an interface for local positioning shown in to subtract third party interference signals from the received signal.

[0016] Figure 2BShows Figure 1 Details of one embodiment of an interface for global navigation satellite system ("GNSS") receiver calibration as shown in;

[0017] Figure 2C Shows Figure 1 Details of one embodiment of an interface for local positioning in a transmitter as shown in;

[0018] Figure 2D Shows Figure 1 Details of one embodiment of the interface shown in which a signal is transmitted to an antenna and the near-end echo of the transmitter is subtracted from the signal received from the antenna or another antenna in a millimeter range radar;

[0019] Figure 3 A specific case of using a channel with a code generator according to one embodiment is shown;

[0020] Figure 4 shows a WPRN former including additional components according to an embodiment;

[0021] Figure 5 shows a block diagram of an embodiment including a digital combiner;

[0022] Figure 6 A schematic diagram showing a WPRN former for use with a navigation receiver; and

[0023] Figure 7 A schematic diagram of a time code multiplexer and navigation channels is shown according to an embodiment. DETAILED DESCRIPTION

[0024] A wideband pseudo-random noise former (WPRN former) is used to accomplish multiple tasks, including: calibrating the Global Navigation Satellite System ("GNSS") radio frequency ("RF") front end via pseudo-satellite signals; generating a composite signal for local positioning; transmitting a signal from a nearby transmitter and further subtracting it from the received signal, which partially solves the near-far problem; and generating signals for truck platooning, millimeter-range radar, total station prism direction finding, etc.

[0025] In one embodiment, the basic WPRN former includes:

[0026] (a) a set of channels with code generators, each channel including a PRN code generator and an NCO with controlled frequency and phase, the output of the NCO generates a strobe pulse, the strobe pulse is sent to the PRN code generator, and the PRN code generator generates new +1 and -1 sequence elements according to the received strobe pulse;

[0027] (b) a modulator, the modulator comprising:

[0028] (1) Multiple weight coefficients,

[0029] (2) a plurality of multipliers that multiply a weight coefficient by an output of one of the PRN code generators,

[0030] (3) an adder which outputs the sum of the outputs of the multipliers,

[0031] (4) A mixer with quadrature outputs that multiplies the output of the adder by a near-zero intermediate frequency (low IF) sine and the output of the adder by a near-zero intermediate frequency (low IF)

[0032] cosine;

[0033] (c) a processor that controls the set of channels having the code generator;

[0034] (d) a receiving-transmitting device, the receiving-transmitting device is used to receive orthogonal signals / transmit orthogonal signals, the receiving-transmitting device includes an RF front end and an antenna; and

[0035] (e) An interface that connects the output of the quadrature mixer to a receiving-transmitting device to receive a quadrature signal / transmit a quadrature signal.

[0036] In one embodiment, the output of the mixer of the WPRN former transmits a broadcast quadrature signal converted to radio frequency, and / or combines the quadrature signal output from the mixer with the received broadcast signal converted to zero frequency or near zero frequency by the quadrature signal, or replaces the received orthogonal signal converted to zero frequency or near zero frequency with the quadrature signal output from the mixer. In one embodiment, the number of channels in the set of channels is an integer multiple of the number of weight coefficients in the plurality of weight coefficients, and the bandwidth of the signal transmitted and / or received by the antenna in the transceiver module is the same integer multiple of the NCO clock rate.

[0037] Figure 1 A schematic diagram of a wideband pseudo-random noise ("WPRN") former 10 is shown in accordance with one embodiment. Figure 1A WPRN former 10 is shown, which includes a CPU 100, a channel 101 (1) ... 101 (N) with a code generator, a code rate numerically controlled oscillator ("CRNCO") 102, a code generator 103, a data buffer 104, an XOR 105, a PRN code S106, a data synchronization signal S107, data S108, a one-bit pseudo-random sequence S109 with data, a modulator 110, a weight multiplexer 112 (1) ... 112 (N), multiplier units 113 (1) ... 113 (N), 115, 116, weight coefficients 114 (1) ... 114 (N), an intermediate frequency NCO ("IFNCO") 117, a cosine unit 118, a sine unit 119, a signal S120 with cosine modulation, a signal S121 with sine modulation, an interface 122, an RF path 123, an antenna 124, and an adder unit 125. In one embodiment, a digital quadrature mixer (ie, a mixer with quadrature outputs) includes unit 115 , unit 116 , IFNCO 117 , cosine unit 118 , and sine unit 119 .

[0038] In one embodiment, prior to operation, CPU 100 initializes the code rate and initial phase of CRNCO 102 , code generator 103 , data buffer 104 , weight coefficients 114 ( 1 ) . . . 114 (N), the intermediate frequency of IFNCO 117 , and interface 122 .

[0039] The CRNCO 102 generates a strobe pulse at a code rate. The strobe pulse is input to the code generator 103. The code generator 103 generates a PRN code S106 input to the XOR 105. The code generator 103 generates a data synchronization signal S107 input to the data buffer 104. The data buffer 104 outputs a signal S108 input to the XOR 105. According to the signal S107, the data in the signal S108 output from the data buffer 104 is modified. If necessary, the CPU 100 writes new data to the data buffer 104. The XOR 105 outputs a one-bit pseudo-random sequence S109 with data.

[0040] S109(1)…S109(N) are output from the channel 101(1)…101(N) with the code generator and are input to the modulator 110. In the modulator 110, the signal S109(1)…S109(N) is input to the control input of the weight multiplexer 112(1)…112(N). If S109 is valid, the value -1 is input to the output unit 112, and if S109 is invalid, the value +1 is input to the output unit 112. The output of the output unit 112(1)…112(N) is input to the multiplier 113(1)…113(N). The output of the weight coefficient 114(1)…114(N) is input to the multiplier 113(1)…113(N). The output of output unit 112 and the output of output unit 114 are multiplied in multiplier 113 and input to adder 125 , and multiplication results 113 ( 1 ) . . . 113 (N) are added in adder 125 . The output of adder 125 is input to multiplier unit 115 and multiplier unit 116 .

[0041] IFNCO 117 generates an intermediate frequency phase, which is input to cosine unit 118 and sine unit 119. The output of cosine unit 118 is input to multiplier unit 115. The output of sine unit 119 is input to multiplier unit 116.

[0042] In the multiplier unit 115 , the output of the adder unit 125 is multiplied by the output of the cosine unit 118 , ie, the output of the adder unit 125 is modulated by the output of the cosine unit 118 .

[0043] In the multiplier unit 116, the output of the adder unit 125 is multiplied by the output of the sinusoidal unit 119, that is, the output of the adder unit 125 is modulated by the output of the sinusoidal unit 119. In one embodiment, the multiplier unit 115 and the multiplier unit 116 are used as an orthogonal mixer in the modulator 110. The output of the multiplier unit 115 is a signal S120. The output of the multiplier unit 116 is a signal S121. The signal S120 and the signal S121 from the output of the modulator 110 are input to the interface 122. The output of the interface 122 is input to the RF unit 123, and the RF unit 123 outputs the signal to the antenna 124.

[0044] During operation, the CPU 100 controls the code frequency and phase in the CRNCO 102, the data buffer 104, the weight coefficients 114(1) ... 114(N), and the frequency and phase in the IFNCO 117. The channels 101(1) ... 101(N) with code generators generate signals S109(1) ... S109(N) which are superpositions of the code signal S106 and the data S108, and the S109 may be offset in time (phase) relative to each other.

[0045] In the modulator 110 , the signals S109 ( 1 )…S109 (N) are assigned a positive or negative sign, and the signals S109 ( 1 )…S109 (N) are scaled by weight coefficients 114 ( 1 )…114 (N), then added, and modulated in the cosine unit 118 and the sine unit 119 .

[0046] This arrangement enables the generation of complex multi-level composite signals, as well as the interpolation and smoothing of leading edges without the classical interpolator with its complex control schematics and large number of multi-bit data multiplications. Both functions are implemented using several NCOs, where different code phases and weight coefficients are preset and the results are summed. Because the weight coefficients are multiplied by +1 or -1, this multiplication operation can be implemented with compact multipliers that take up less space than multi-bit multipliers.

[0047] The signal at the output of the adder unit 125 can be brought to an intermediate frequency by multiplying the sine and the cosine. In one embodiment, this operation is required for most of the solved tasks.

[0048] Depending on the problem to be solved, different implementations of the interface 122 may be used in the device. Such implementations may be modified by reconfiguration of the interface so that the same device may be used for different applications. Figure 2A , Figure 2B , Figure 2C and Figure 2D Different implementations of interface 122 are shown.

[0049] Figure 2AAn interface 122 is shown, which includes: an analog-to-digital converter ("ADC") 205 and adder units 130 and 131. The signal is fed from the RF 123 front end to the ADC 205 and digitized, and then the digitized quadrature signal is input to the adder unit 130 and adder unit 131, where the digitized quadrature signal is added with the signal of the multiplier unit (also called quadrature mixer) 115 and the signal of the multiplier unit (also called quadrature mixer) 116. The output of the adder unit 130 and adder unit 131 is input to the signal processor 126 for further processing. This interface implementation can be used for local positioning to subtract the interference signal of a third party from the received signal.

[0050] Figure 2B An interface 122 is shown, which includes: a digital-to-analog converter ("DAC") 202 and an ADC 205. The output of the orthogonal mixer 115 and the output of the orthogonal mixer 116 are input to the DAC 202 and then converted to an intermediate radio frequency in the transmit portion of the RF 123 front end. The intermediate radio frequency is then shifted to zero frequency or near zero frequency in the receive portion of the RF 123, where the signal is added to or replaces the broadcast radio signal received from the antenna 124. This embodiment can be applied to GNSS receiver calibration. In some embodiments, the RF front end is calibrated before the GNSS receiver starts searching and tracking satellite signals. In such an embodiment, during the calibration phase, the signal from the antenna is replaced by the generated signal with the help of an RF switch. After the calibration phase, the RF switch is reconfigured to provide a path for the satellite signal from the antenna. In other embodiments, the RF front end is calibrated while the satellite signal is being received. In this embodiment, the generated signal with relatively weak power is added to the signal from the antenna. Combiners, differential operational amplifiers, or other RF components may be used to sum the signals.

[0051] In some embodiments, the signal output by the transmit portion of the RF 123 front end is a calibration signal. In some embodiments, the calibration signal is similar to a GNSS navigation signal. In some embodiments, the calibration signal is a specific signal having characteristics that are not similar to the characteristics of a GNSS navigation signal. In some embodiments, the characteristics of the specific signal are periodically modified during the calibration process.

[0052] Figure 2CAn interface 122 including a DAC 202 is shown. The output signal of the quadrature mixer 115 and the output signal of the quadrature mixer 116 pass through the DAC 202 and are then converted to an intermediate radio frequency in the transmit portion of the RF 123. Such an implementation can be used for local positioning of the transmitter. In some embodiments, the code phase and / or carrier phase of the generated signal is adjusted according to the corresponding code and / or carrier phase of the main transmitter or according to a GNSS reference signal. In other embodiments, the parameters are adjusted according to a reference signal locally connected to the transmitter.

[0053] Figure 2D An interface 122 is shown which includes a subtractor 206, a DAC 202 and an ADC 205. The output signal from the modulator 110(1) passes through the DAC 202 and is then converted to an intermediate frequency in the transmit portion of the RF 123. Another mode of operation is also possible. In this other mode of operation, where the broadcast signal is input to the receive portion of the RF 123 (where it is converted to zero frequency or near zero frequency), the signal is then digitized and in the subtractor 206 the digitized signal is added to the signal from the modulator 110(2) or subtracted from the signal according to the modulator 110(2). This implementation allows a signal to be transmitted to an antenna and the near-end echo of the transmitter of the implementation itself is subtracted from the received signal from this antenna or another antenna in the millimeter range radar.

[0054] Figure 3 A specific case is shown in which channels 101(1), 101(2), 101(3), 101(4) and 101(5) with code generators generate signals S109(1), S109(2), S109(3), S109(4) and S109(5). At the same time, PRN code S106( Figure 1 ) are phase shifted relative to each other by Tdelta. Tdelta is used when specifying the phase offset of the code frequency in CRNCO 102 during initialization. Weight coefficients 114(1), 114(2), 114(3), 114(4) and 114(5) are set equal to a value of +1, and weight coefficient (6) ... weight coefficient (N) is equal to a value of 0. At the output of adder 125, a multi-level PRN code with slanted edges is generated.

[0055] Figure 4 An embodiment of a WPRN former including additional components is shown. In one embodiment, the WPRN former 40 may be implemented with two antennas (transmit antenna 124(1), receive antenna 124(2)), or with a single receive-transmit antenna 124 (not shown).

[0056] The following components are added to Figure 1 The embodiment shown in FIG. 1 is assembled into Figure 4 A more complex implementation of the WPRN former 40 is shown: digital combiner 201 ( 1 )…201 ( 2 ), DAC 202 ( 1 )…202 ( 2 ), analog summing unit 203 , subtractor multiplexer 204 , ADC 205 , subtractor unit 206 , navigation receiver 207 and decimator 208 .

[0057] exist Figure 4 In the complex implementation shown in , the number of the following units increases: modulators 110(1)...110(8), RF paths 123(1)...123(2), antennas 124(1)...124(2), channels 101(1)..101(N*2) with code generators.

[0058] The WPRN former 40 operates at synchronous clock speeds CLKsend and CLKch. In one embodiment, CLKsend and CLKch may have the same rate. For example, the rate of CLKch may also be 1 / 2 (or 1 / 2^M) of the rate of CLKsend.

[0059] The following components of the WPRN former 40 operate at the CLKsend clock speed: channel code generator 101 (1) ... 101 (N*2), modulator 110 (1) ... 110 (8), digital combiner 201 (1) ... 201 (2), DAC 202 (1) ... 202 (2), subtractor multiplexer 204, and part of the decimator 208. The following components of the WPRN former 40 operate at the CLKch clock speed: part of the decimator 208, subtractor 206, navigation receiver 207, and ADC 205.

[0060] Before operation, CPU 100 adjusts the following components: channel code generator 101 (1)...101 (N*2), modulator 110 (1)...110 (8), digital combiner 201 (1)...201 (2), subtractor multiplexer 204, extractor 208, subtractor 206, navigation receiver 207 and the ratio of clocks CLKsend and CLKch.

[0061] Channel 101 with code generator generates signal S109. Output signals S109(1)...S109(N) from channels 101(1)...101(N) with code generator are input to modulators 110(1)...110(4), where S109(1)...S109(N) are scaled and down-converted to an intermediate frequency. Signals S120 and S121 from the outputs of modulators 110(1)...110(4) are input to digital combiner 201(1) and further converted. The output from digital combiner 201(1) is fed to the input of DAC 202(1) and subtractor multiplexer 204.

[0062] Back to Figure 1 In various implementations, the interface 122 includes:

[0063] (1) quadrature DAC 202(1) and quadrature DAC 202(2), DAC 202(2) being clocked with a half-cycle delay relative to DAC 202(1);

[0064] (2) a splitter circuit having two quadrature inputs and two quadrature outputs to convert the quadrature outputs of the mixers of modulators 110(1) ... 110(8) connected to the inputs of DAC 202(1) and DAC 202(1);

[0065] (3) An analog component smart addition module, which is used for two orthogonal signals to obtain an orthogonal signal. The splitter generates an orthogonal output of the mixer, so that after addition in the analog component smart addition module, there is a signal shaped into a DAC double clock rate signal (DAC double clock rate signal), in which the even samples are the output signals of the mixer of one modulator, and the odd samples are the output signals of the mixer of another modulator. The output of the analog component smart addition module is connected to the RF front end, and the output of the RF front end is connected to the transmitting antenna. The device is part of the local positioning transmitter of the signal. In one embodiment, the splitter is part of the digital combiner 201.

[0066] Back to Figure 4, the signals S109(N+1)…S109(N*2) from the outputs of the channels 101(N+1)…101(N*2) with the code generators are input to the modulators 110(5)…110(8), in which the signals S109(N+1)…S109(N*2) are modulated. The signals S120 and S121 from the outputs of the modulators 110(5)…110(8) are input to the digital combiner 201(2) and converted in the digital combiner 201(2). The output signal from the digital combiner 201(2) is input to the DAC 202(2) and the subtractor multiplexer 204.

[0067] The signals from the outputs of DAC 202 (1) ... DAC (2) are added in analog summation 203 and further input to RF path 123 (1). An operational amplifier may be used as analog summation 203. After passing through RF path 123 (1), the signal is transmitted to antenna 124 (1).

[0068] The output of the subtractor multiplexer 204 is input to the decimator 208. In the decimator 208, the signal is decimated according to the preset rate of the clock speeds CLKsend and CLKch. The output signal from the decimator 208 is input to the subtractor 206.

[0069] The signal from antenna 124(2) is input to RF path 123(2). Once through RF path 123(2), the signal is input to ADC 205. The digitized signal from the output of ADC 205 is input to subtractor 206.

[0070] In the subtractor 206, if necessary (eg, assigned by the CPU 100), the signal from the output of the decimator 208 is subtracted from the sampled signal from the output of the ADC 205, and the subtracted signal is input to the navigation receiver 207. In the navigation receiver 207, the signal is processed.

[0071] In one embodiment, in operation, the CPU 100 controls the following components: channels 101(1)…101(N*2) with code generators, modulators 110(1)…110(8), digital combiners 201(1)…201(2), subtractor multiplexer 204, extractor 208, subtractor 206 and navigation receiver 207.

[0072] Figure 5A block diagram of an embodiment including a digital combiner circuit is shown. In one embodiment, the digital combiner includes: multiplexers 310 (1) ... 310 (4), multiplexers 311 (1) ... 311 (4), multiplexer 306, adder 320, adder 321, subtraction units 330, 331 in digital combiner 201, splitter signals S350, S351, S360, S361 and DAC input signals S340, S341.

[0073] In one embodiment, CPU 100 starts and controls the following components: modulators 110(1) ... 110(8) and subtractor multiplexer 204. Prior to operation, CPU 100 adjusts multiplexers 310(1) ... 310(4), multiplexers 311(1) ... 311(4) and multiplexer 306. Digital combiner 201(1) and digital combiner 201(2) are paired.

[0074] The signals S120 and S121 from the outputs of the modulators 110(1) ... 101(4) are input to the digital combiner 201(1). The signals S120 and S121 from the outputs of the modulators 110(5) ... 110(8) are input to the digital combiner 201(2).

[0075] The signal S120 is input to the multiplexers 310(1)...310(4). If the signal at the control input of the multiplexers 310(1)...310(4) is valid, the signal S120 is present at the output, and if the signal at the control input of the multiplexers 310(1)...310(4) is invalid, the value 0 is present at the output. The output signals of the multiplexers 310(1)...310(4) are input to the adder unit 320, and the output signals of the multiplexers 310(1)...310(4) are added. The output signal of the adder unit 320 is input to the subtraction unit 330 and the multiplexer 306.

[0076] The signal S121 is input to the multiplexers 311 (1) ... 311 (4). If the signal at the control input of the multiplexers 311 (1) ... 311 (4) is valid, the signal S121 is present at the output, and if the signal at the control input of the multiplexers 311 (1) ... 311 (4) is invalid, the value 0 is present at the output. The output signals of the multiplexers 311 (1) ... 311 (4) are input to the adder unit 321, and the output signals of the multiplexers 311 (1) ... 311 (4) are added. The output signal of the adder unit 321 is input to the subtraction unit 331 and the multiplexer 306.

[0077] Signal S350 is signal S360 from paired digital combiner 201. Signal S350 is input to subtraction unit 330 and adder unit 320. In subtraction unit 330, signal S350 is subtracted from the output signal of adder unit 320. The output signal of subtraction unit 330 is signal S360. S360 is fed to the input of multiplexer 306 and paired digital combiner 201. In some embodiments, digital combiner 201(1) has a delay of signal S360.

[0078] Signal S351 is signal S361 from paired digital combiner 201. Signal S351 is input to subtractor unit 331 and adder unit 321. In subtractor unit 331, signal S351 is subtracted from the output signal of adder unit 321. The output signal of subtractor unit 331 is signal S361. Signal S361 is input to multiplexer 306 and paired digital combiner 201. In some embodiments, digital combiner 201(1) has a delay of signal S361.

[0079] If the signal at the control input of multiplexer 306 is invalid, signal S360 is fed to the output and signal S340 becomes equal to S360.

[0080] If the signal at the control input of the multiplexer 306 is invalid, the signal S361 is fed to the output and the signal S341 becomes equal to S361.

[0081] If the signal at the control input of the multiplexer 306 is active, the output signal of the cell 320 is fed to the output and the signal S340 becomes equal to the output signal of the cell 320 .

[0082] If the signal at the control input of the multiplexer 306 is active, the output signal of the adder unit 321 is fed to the output and the signal S341 takes the value of the output signal of the adder unit 321 .

[0083] Signals S340 and S341 from the output of the digital combiner 201 ( 2 ) are input to the DAC 202 ( 2 ) and the subtractor multiplexer 204 .

[0084] The signals S120 and S121 from the outputs of the modulators 110(1) ... 110(4) are input to the digital combiner 201(1). The digital combiner 201(1) operates in a similar mode to the digital combiner 201(2). The signals S340 and S341 from the outputs of the digital combiner 201(1) are input to the DAC 202(1) and the subtractor multiplexer 204.

[0085] Figure 6An embodiment of a complex embodiment using the WPRN former 60 with a navigation receiver is shown. In this embodiment, instead of the channel 101 with the code generator there is a navigation channel 400. This embodiment also includes time code multiplexers 401 (1) ... 401 (2). Also, in this embodiment, the rate of the clock CLKch is 1 / 2 the rate of CLKsend.

[0086] In this embodiment, navigation channels 400(1) ... 400(N*4) are used to generate signal S109, and the remaining navigation channels 400 (wherein the number is greater than N*4 to N*4+K. Wherein K is the limit number of navigation signals to be received, which is a sufficient number of channels to receive the required signals) process the signal arriving from the subtractor 206. The time code multiplexers 401(1) ... 401(2) operate at a clock rate CLKsend.

[0087] In one embodiment, prior to operation, the CPU 100 adjusts the following components: navigation channels 400(1)...400(N*4), modulators 110(1)...110(8), digital combiners 201(1)...201(2), subtractor multiplexer 204, decimator 208, subtractor 206, navigation receiver 207 (for channel numbers greater than N*4 to N*4+K), and the ratio of clock speeds of CLKsend and CLKch.

[0088] In this embodiment, navigation channels 400(1)...400(N*4) generate signals S109(1)...S109(N*4). Signals S109(1)...S109(N*2) from the outputs of navigation channels 400(1)...400(N*2) are input to a time code multiplexer 401(1), where signal S109 is selected in time. The output of the time code multiplexer 401(1) is input to modulators 110(1)...110(4), where the output signals of the time code multiplexer 401(1) are scaled and down-converted to an intermediate frequency. Signals S120 and S121 from the outputs of modulators 110(1)...110(4) are input to a digital combiner 201(1) for further conversion. The signal from the output of the digital combiner 201 ( 1 ) is input to the DAC 202 ( 1 ) and the subtractor multiplexer 204 .

[0089] Signals S109(N*2+1)…S109(N*4) from the outputs of navigation channels 400(N*2+1)…400(N*4) are input to a time code multiplexer 401(2), in which signal S109 is selected in time. The output of the time code multiplexer 401(2) is input to modulators 110(5)…110(8), in which the output of the time code multiplexer 401(2) is scaled and down-converted to an intermediate frequency. Signals S120 and S121 from the outputs of modulators 110(5)…110(8) are input to a digital combiner 201(2) for further conversion. The signal from the output of the digital combiner 201(2) is input to a DAC 202(2) and a subtractor multiplexer 204.

[0090] DAC 202 ( 2 ) operates with a clock that has a half-cycle delay relative to the clock of DAC 202 ( 1 ).

[0091] The signals from the DAC 202 (1) ... DAC (2) outputs are added to the analog summation 203, and the resulting signal is close in value to a signal having twice the clock rate of the DAC, and the resulting signal is fed to the RF path 123 (1). In one embodiment, an operational amplifier can be used as the analog summation 203. The RF 123 (1) path outputs a signal, which is then input to the antenna 124 (1).

[0092] The signal from the selected digital combiner 201(1)...201(2) passes through the subtractor multiplexer 204. The output signal of the subtractor multiplexer 204 is input to the decimator 208. In the decimator 208, the signal is decimated according to the preset clock ratio of CLKsend to CLKch. The output signal of the decimator 208 is input to the subtractor 206.

[0093] The antenna signal 124(2) is input to the RF path 123(2). After the RF path 123(2), the signal is input to the ADC 205. The sampled (digitized) signal from the output of the ADC 205 is then input to the subtractor 206. In the subtractor 206, if the CPU 100 allocates it, the signal at the output of the decimator 208 is subtracted from the sampled signal from the output of the ADC 205 and the subtracted signal is fed to the input of the navigation receiver 207 where it is processed.

[0094] In one embodiment, during operation, the CPU 100 controls the following components: navigation channels 400(1)...400(N*4), modulators 110(1)...110(8), digital combiners 201(1)...201(2), subtractor multiplexer 204, extractor 208, subtractor 206 and navigation receiver 207 (the number of channels 400 is greater than N*4 to N*4+K).

[0095] Figure 7 A schematic diagram of a time code multiplexer and a navigation channel according to an embodiment is shown. In this embodiment, a navigation channel 400 is used instead of a channel 101 with a code generator. The rate of the clock CLKch is 1 / 2 of the rate of CLKsend. The embodiment includes: a multiplexer 500, a time control multiplexer 501, a CRNCO 502, a code generator 503, an auxiliary code buffer 504, an XOR 505, a PRN code signal S506, a data synchronization signal S507, an auxiliary code signal S508, a one-bit pseudo-random sequence S509 with data, an integration cycle counter 510, a navigation channel intermediate frequency NCO 511 and a correlator 512. The auxiliary code buffer 504 is used to generate an auxiliary code signal S508, and data is transmitted via the auxiliary code signal. In one embodiment, the auxiliary code buffer 504 is used as a data buffer 104.

[0096] In one embodiment, the CPU 100 starts and controls the modulators 110 (1) ... 100 (4) and the subtractor 206. Before operation, the CPU 100 initializes the following units in the navigation channels 400 (1) ... 400 (N*2): code frequency and initial phase in the CRNCO 502, code generator 503 and auxiliary code buffer 504. In one embodiment, during operation, the following units are not used in the navigation channels 400 (1) ... 400 (N*4): integration period counter 510, navigation channel intermediate frequency NCO 511 and correlator 512. In one embodiment, before operation, the CPU 100 initializes the navigation channels (greater than N*4 to N*4+K), and during operation, the CPU 100 controls the navigation channels 400.

[0097] The CRNCO 502 generates a code frequency that is input to the code generator 503. The code generator 503 forms a PRN code S506, which is input to the XOR 505. The code generator 503 generates a data synchronization signal S507, which is then input to the auxiliary code buffer 504. The auxiliary code signal S508 is output from the auxiliary code buffer 504 and is input to the XOR 505. The auxiliary code signal S508 at the output of the auxiliary code buffer 504 is modified according to the signal S507. The CPU 100 can additionally write new data to the auxiliary code buffer 504. A one-bit pseudo-random sequence S509 with data is output from the XOR 505.

[0098] In one embodiment, signal S509 is the same as signal S109. Signal S109 from navigation channels 400 (1) ... 400 (N*4) is fed to the time code multiplexer 401 (1) and fed to the input of the multiplexer 500. Signal S109 (S509) is generated with clock CLKch. The time code multiplexer 401 (1) operates with CLKsend which is twice as large as CLKch. The time control multiplexer 501 generates a meander signal at the output of the time code multiplexer 401 (1), which changes at each clock pulse of the clock CLKsend. The output signal of the time control multiplexer 501 is input to the control input of the multiplexer 500. If the state of the control input terminal of the multiplexer 500 is invalid, the output signal is S109 (1) ... S109 (N), and if the state of the control input terminal of the multiplexer 500 is valid, the output signal is S109 (N + 1) ... S109 (N * 2). The signal from the output of the unit 401 (1) is input to the modulator 110 (1) ... 110 (4). The navigation channel 400 (greater than N * 4 to N * 4 + K) processes the signal from the output of the subtractor 206.

[0099] In one embodiment, a method for forming a pseudo-random broadband signal includes the following steps: controlling the frequency and phase of a plurality of NCOs, each NCO being associated with a corresponding one of a group of channels; generating a strobe pulse output to a PRN code generator by one of the plurality of NCOs; forming a new +1 or -1 sequence element by the PRN code generator in response to the strobe pulse; multiplying an output of the PRN code generator by one of a plurality of weight coefficients by one of a plurality of multipliers; outputting the sum of the output signals of the plurality of multipliers from an adder; multiplying the output of the adder by a low intermediate frequency sine and a low intermediate frequency cosine by a mixer having an orthogonal output signal; receiving the orthogonal signal by a transceiver module; and transmitting the orthogonal signal by the transceiver module; wherein the transceiver module converts the orthogonal signal output from the mixer into a radio frequency for transmission, and the transceiver module adds the orthogonal signal to the orthogonal signal received from the antenna and converted to zero frequency or near zero frequency, or replaces the orthogonal signal received from the antenna and converted to zero frequency or near zero frequency with the orthogonal signal. In one embodiment of the method, the method steps eliminate unwanted signals from one of the transceiver module or a transmitter within the transmission range of the transceiver module, the unwanted signals being received from the antenna along with the navigation signal. In one embodiment of the method, the method steps form a combined signal including the signal received from the antenna and the locally generated signal, the combined signal being processed by the GNSS receiver to obtain the position of the GNSS receiver, the combined signal being processed into a calibration signal to calibrate the receiver RF front end while the satellite signal is being received.

[0100] The foregoing detailed description should be understood to be illustrative and exemplary in all respects, rather than restrictive, and the scope of the inventive concept disclosed herein is not determined based on the detailed description, but is determined by the claims interpreted to the full extent permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concept, and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept. Various other feature combinations may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept.

Claims

1. A device for forming a pseudo-random broadband signal, the device comprising: (a) a set of channels, each channel comprising a PRN code generator and an NCO with controlled frequency and phase, the NCO being configured to generate a strobe pulse, the strobe pulse being output to the PRN code generator, and the PRN code generator being configured to form a new +1 or -1 sequence element in response to the strobe pulse; (b) a first modulator, the first modulator comprising: (1) Multiple weight coefficients; (2) a plurality of multipliers, each multiplier being configured to multiply an output of the PRN code generator by one of the plurality of weight coefficients; (3) an adder configured to output a sum of output signals of a plurality of the multipliers; and (4) a mixer having quadrature output signals, the mixer being configured to multiply the output of the adder by the sine of a low intermediate frequency (low IF) and to multiply the output of the adder by the cosine of a low intermediate frequency (low IF); (c) a processor configured to control the set of channels; (d) a transceiver module configured to receive an orthogonal signal and / or transmit an orthogonal signal, the transceiver comprising an RF front end and an antenna; and (e) an interface configured to connect the output of the mixer to the transceiver module, The transceiver module is configured to convert the orthogonal signal output from the mixer into a radio frequency for transmission, or the transceiver module is configured to add the orthogonal signal output from the mixer to the orthogonal signal received from the antenna and converted into zero frequency or near-zero frequency, or to replace the orthogonal signal received from the antenna and converted into zero frequency or near-zero frequency with the orthogonal signal output from the mixer.

2. The device according to claim 1, wherein: The interface includes a quadrature DAC having an input connected to an output of the mixer and an output of the quadrature DAC connected to the RF front end.

3. The device according to claim 1, wherein: The interface includes a quadrature ADC having an input connected to the RF front end and an output of the quadrature ADC added to an output of the mixer.

4. The device according to claim 1, wherein the interface further comprises: A quadrature ADC and a quadrature DAC, the input of the quadrature ADC and the output of the quadrature DAC being connected to the RF front end, the signal from the output of the quadrature DAC being converted to an intermediate frequency or a radio frequency in the transmit portion of the RF front end and then converted back to zero frequency or near zero frequency in the receive portion of the RF front end, the signal being added at a radio frequency to or replacing a broadcast radio signal received from an antenna.

5. The device according to claim 2, wherein: The output of the RF front end is sent to the antenna, the device being part of the transmitter of the local positioning signal.

6. The device according to claim 3, wherein: The input of the RF front end is connected to the antenna, the device being part of a receiver of a local positioning signal.

7. The device according to claim 4, wherein: The input of the receiving part of the RF front end is connected to the antenna, the device being part of a GNSS receiver.

8. The apparatus of claim 1, further comprising a second modulator.

9. The apparatus of claim 8, wherein the interface further comprises a quadrature ADC and a quadrature DAC, the output of a mixer of one of the modulators being subtracted from the signal output by the ADC, the output of a mixer of the other of the modulators being connected to a transmit portion of the RF front end across the quadrature DAC, the output of the transmit portion of the RF front end being connected to a receive-transmit antenna, the receive-transmit antenna being further connected to a receive portion of the RF front end, the output of the receive portion of the RF front end being connected to the quadrature ADC, and the apparatus being part of a radar.

10. The device according to claim 1, wherein: The number of channels in the set of channels is an integer multiple of the number of weight coefficients in the plurality of weight coefficients, and the bandwidth of a signal transmitted and / or received by the antenna in the transceiver module is the same integer multiple of an NCO clock rate.

11. The apparatus according to claim 8, wherein the interface further comprises: (1) a first DAC and a second DAC, the second DAC being configured to operate at a clock speed having a half-cycle delay relative to the first DAC; (2) a splitter having two quadrature inputs and two quadrature outputs, the splitter being configured to convert the mixer quadrature outputs of the first modulator and the mixer quadrature outputs of the second modulator, the quadrature outputs of the splitter being connected to the inputs of the first DAC and the inputs of the second DAC; as well as (3) a module for analog adding two quadrature signals from two DACs to obtain a single quadrature signal; Wherein, the splitter converts the orthogonal outputs of the mixers so that after adding the outputs of the mixers, the following signal is generated, which is shaped into a signal with a double DAC clock rate and in which the even samples are samples of the mixer output from one modulator and the odd samples are the mixer output of the other modulator, the output of the analog adding module is connected to the RF front end, the output of the RF front end is connected to the transmitting antenna, and the entire device is part of the transmitter of the local positioning signal.

12. The device according to claim 11, wherein The analog adding module in the interface is implemented using a differential operational amplifier.

13. The device according to claim 11, wherein: The analog adding module in the interface is implemented using a combiner.

14. The apparatus of claim 1, further comprising a further modulator, a mixer output of the further modulator being input to a quadrature adder, and an output of the quadrature adder being input to the interface.

15. The device according to claim 1, wherein: The navigation channel can be used as one channel in the set of channels.

16. A method for forming a pseudo-random broadband signal, the method comprising: controlling the frequency and phase of a plurality of NCOs, each NCO being associated with a corresponding one of a group of channels; A strobe pulse is generated by one of the plurality of NCOs, and the strobe pulse is output to a PRN code generator; forming a new +1 or -1 sequence element by the PRN code generator in response to the strobe pulse; multiplying, by one of the plurality of multipliers, one of the plurality of weight coefficients by an output of the PRN code generator; outputting a sum of output signals of the plurality of multipliers from an adder; multiplying the output of the adder by the sine of a low intermediate frequency and multiplying the output of the adder by the cosine of a low intermediate frequency by a mixer having quadrature output signals; receiving the orthogonal signal by the transceiver module; as well as transmitting an orthogonal signal by the transceiver module; The transceiver module converts the orthogonal signal output from the mixer into radio frequency and transmits it, and the transceiver module adds the orthogonal signal output from the mixer to the orthogonal signal received from the antenna and converted into zero frequency or near-zero frequency, or replaces the orthogonal signal received from the antenna and converted into zero frequency or near-zero frequency with the orthogonal signal output from the mixer.

17. The method according to claim 16, wherein: The steps of the method eliminate unwanted signals from one of the transceiver module or a transmitter located within a transmission range of the transceiver module, the unwanted signals being received from the antenna along with the navigation signal.

18. The method according to claim 16, wherein: The steps of the method form a combined signal, the combined signal comprising a signal received from the antenna and a locally generated signal, the combined signal being processed by a GNSS receiver to obtain the position of the GNSS receiver, the combined signal being processed into a calibration signal to calibrate the receiver RF front end while satellite signals are being received.

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