A monolithically integrated all-GaN cascode field-effect transistor and its fabrication method

Abstract

This application relates to the field of semiconductor device technology, and particularly to a monolithically integrated all-GaN cascode field-effect transistor and its fabrication method. The transistor includes a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The barrier layer includes a first region and a second region. A gate under-gated groove penetrating the barrier layer is formed on the first region. A gate under-gated enhancement layer and a first gate are sequentially disposed within the gate under-gated groove. The gate under-gated enhancement layer has a trench-like structure. The first gate is located above the gate under-gated enhancement layer, and the gate under-gated enhancement layer covers the bottom surface and part of the side surface of the first gate. The bottom surface of the gate under-gated enhancement layer is flush with the bottom surface of the barrier layer. A second gate is disposed on the second region. Source and drain electrodes are disposed on both the first and second regions. This application uses enhancement-mode GaN devices to replace Si MOSFETs, thereby solving the problem of unwanted oscillations during fast switching and improving switching speed. Simultaneously, since the high-voltage portion of the device is handled by depletion-mode GaN, the device exhibits high reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a monolithically integrated all-GaN cascode field-effect transistor and its fabrication method. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) based on AlGaN / GaN are widely used due to their advantages such as high electron mobility, high critical electric field strength, and wide bandgap. To achieve enhanced performance, cascaded GaN depletion-mode circuits and Si MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely adopted and have gained industry acceptance. In practical applications, their advantages of high gate voltage, reduced Miller effect, and simple fabrication make them strong candidates for high-voltage applications. However, the differences in material properties between Si and GaN lead to output capacitance mismatch, performance degradation, complex packaging, and higher cost.

[0003] The traditional GaN Cascode structure connects a normally off low-voltage Si MOSFET device and a normally open high-voltage GaN HEMT device through interconnects to form a common-source, common-gate structure. The Si MOSFET device determines the threshold voltage of the Cascode FET device, and the device gains enhanced characteristics while retaining a series of advantages of GaN HEMT devices.

[0004] Existing Cascode FET device layouts consist of a high-voltage depletion-mode GaN device and a low-voltage enhancement-mode Si device connected in series. The introduction of the Si device limits the performance of Cascode FET devices to some extent. Furthermore, the interconnects introduced by the cascaded packaging generate additional parasitic inductance, causing unwanted oscillations during fast switching. Additionally, due to the intrinsic capacitance mismatch between the Si and GaN devices and the body diode in the Si MOSFET, the Si device is prone to being driven into avalanche mode, resulting in additional switching energy losses. Moreover, under high-current operation, the mismatched capacitance and parasitic inductance can cause large oscillations during turn-off. Summary of the Invention

[0005] This application provides a monolithically integrated all-GaN cascode field-effect transistor and its fabrication method. By replacing the Si MOSFET with an enhancement-mode GaN device, the problem of unwanted oscillations during fast switching is solved, and the switching speed is improved. At the same time, since the high-voltage part of the device is handled by depletion-mode GaN, the device has high reliability.

[0006] To address the aforementioned technical problems, this application provides a monolithically integrated all-GaN cascode field-effect transistor, comprising: a substrate and a nucleation layer, a buffer layer, a channel layer, and a barrier layer sequentially stacked on the substrate; the barrier layer includes a first region and a second region; a gate undergrowth groove penetrating the barrier layer is formed on the first region, and a gate undergrowth enhancement layer and a first gate are sequentially disposed within the gate undergrowth groove; the gate undergrowth enhancement layer has a trench-like structure, the first gate is located above the gate undergrowth enhancement layer, and the gate undergrowth enhancement layer covers the bottom surface and part of the side surface of the first gate; the bottom surface of the gate undergrowth enhancement layer is flush with the bottom surface of the barrier layer, and a second gate is disposed in the second region; a source and a drain are disposed on both the first and second regions, the first gate is located between the source and drain of the first region, and the second gate is located between the source and drain of the second region, and the bottoms of the first gate and the second gate form Schottky contacts with the barrier layer; the source and drain respectively form ohmic contacts with the two-dimensional electron gas in the channel layer.

[0007] In some exemplary embodiments, the under-gate enhancement layer includes an extension layer extending in a width direction away from the first gate, the extension layer partially covering the top surface of the barrier layer in contact with it.

[0008] In some exemplary embodiments, the two sidewalls of the gate under-gate reinforcement layer are flush with the surfaces of the barrier layer they are in contact with.

[0009] In some exemplary embodiments, the material of the under-gate reinforcement layer includes silicon nitride and aluminum oxide.

[0010] In some exemplary embodiments, a passivation layer is provided between the first gate and the source of the first region, and between the first gate and the drain of the first region, and the passivation layer covers the surface of the barrier layer and the under-gate enhancement layer.

[0011] In some exemplary embodiments, the second gate is located on the surface of the second region of the barrier layer; a passivation layer is provided between the second gate and the source of the second region, and between the second gate and the drain of the second region.

[0012] In some exemplary embodiments, a passivation layer is provided between the drain of the first region and the source of the second region.

[0013] In some exemplary embodiments, the drain of the first region is connected to the source of the second region; the second gate is connected to the source of the first region.

[0014] In some exemplary embodiments, the field-effect transistor described above further includes an insertion layer for improving carrier mobility, the insertion layer being located between the barrier layer and the channel layer.

[0015] On the other hand, embodiments of this application also provide a method for fabricating a monolithically integrated all-GaN cascode field-effect transistor, comprising: providing a substrate; forming a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially on the substrate; etching a first groove and a second groove penetrating the barrier layer on the barrier layer; the second groove being located in the middle of the barrier layer, and the first groove being located between one side edge of the barrier layer and the second groove; using the second groove as a boundary, the side on the barrier layer where the first groove is formed is a first region, and the side where the first groove is not formed is a second region; forming a gate under-reinforcement layer in the first groove, the gate under-reinforcement layer having a groove-like structure, the bottom surface of the gate under-reinforcement layer being flush with the ground surface of the gate under-reinforcement layer. The bottom surface of the barrier layer is flush with the ground surface. A mask is fabricated on the barrier layer to form an ohmic window, and the source and drain are formed on the first and second regions. A mask is fabricated on the barrier layer and the under-gate enhancement layer to form a gate window, and a first gate is formed in the first region. The first gate is located above the under-gate enhancement layer, and the under-gate enhancement layer covers the bottom surface and part of the side surface of the first gate. A second gate is formed in the second region. A passivation material layer is formed above the barrier layer, the source, the drain, and the gate. An aperture is made in the passivation material layer above the source, the drain, and the gate to bring out electrodes, and the drain of the first region is interconnected with the source of the second region, and the source of the first region is interconnected with the gate of the second region to obtain a transistor.

[0016] The technical solution provided in this application has at least the following advantages:

[0017] This application provides a monolithically integrated all-GaN cascode field-effect transistor and its fabrication method. The transistor includes: a substrate and a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially on the substrate; the barrier layer includes a first region and a second region; a gate undergrowth groove penetrating the barrier layer is formed on the first region, and a gate undergrowth enhancement layer and a first gate are sequentially disposed in the gate undergrowth groove. The gate undergrowth enhancement layer has a groove structure, and the first gate is located above the gate undergrowth enhancement layer, and the gate undergrowth enhancement layer covers the bottom surface and part of the side surface of the first gate; the bottom surface of the gate undergrowth enhancement layer is flush with the bottom surface of the barrier layer, and a second gate is disposed in the second region; a source and a drain are disposed on both the first region and the second region, the first gate is located between the source and drain of the first region, and the second gate is located between the source and drain of the second region, and the bottom of both the first gate and the second gate forms a Schottky contact with the barrier layer; the source and drain respectively form ohmic contacts with the two-dimensional electron gas in the channel layer.

[0018] This application provides a monolithically integrated all-GaN cascode FET, replacing the Si MOSFET with an enhancement-mode GaN device, thereby solving the problem of unwanted oscillations during fast switching and improving switching speed. Since the depletion-mode GaN device lacks a body diode, avalanche phenomena in low-voltage devices during turn-off are avoided. Furthermore, parasitic inductance can be minimized through monolithic integration, reducing oscillations during turn-off and improving parallel operation. Under high-voltage operation, the high-voltage portion of the device is handled by the depletion-mode GaN, resulting in higher device reliability. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 A schematic diagram of the structure of a monolithically integrated all-GaN cascode field-effect transistor provided in an embodiment of this application;

[0021] Figure 2 A circuit diagram of a monolithically integrated all-GaN cascode field-effect transistor provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram of the structure of a monolithically integrated all-GaN cascode field-effect transistor is provided for another embodiment of this application;

[0023] Figure 4 A schematic flowchart illustrating a method for fabricating a monolithically integrated all-GaN cascode field-effect transistor according to an embodiment of this application;

[0024] Figure 5 A schematic flowchart illustrating a method for fabricating a monolithically integrated all-GaN cascode field-effect transistor according to an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a monolithically integrated all-GaN cascode field-effect transistor, provided as another embodiment of this application. Detailed Implementation

[0026] As can be seen from the background technology, the existing Cascode FET device layout consists of a high-voltage depletion-mode GaN device and a low-voltage enhancement-mode Si device connected in series. The introduction of Si devices has limited the performance of Cascode FET devices to some extent.

[0027] Existing Cascode FET devices, due to the interconnects introduced by cascaded packaging, generate additional parasitic inductance, causing unwanted oscillations during rapid switching. Si devices are susceptible to avalanche mode due to intrinsic capacitance mismatch between Si and GaN devices and the body diode in Si MOSFETs, resulting in additional switching energy losses. Furthermore, under high-current operation, mismatched capacitance and parasitic inductance can cause large oscillations during turn-off.

[0028] To address the aforementioned technical problems, this application provides a monolithically integrated all-GaN cascode field-effect transistor, comprising: a substrate and a nucleation layer, a buffer layer, a channel layer, and a barrier layer sequentially stacked on the substrate; the barrier layer includes a first region and a second region; a gate undergrowth groove penetrating the barrier layer is formed on the first region, and a gate undergrowth enhancement layer and a first gate are sequentially disposed within the gate undergrowth groove; the gate undergrowth enhancement layer has a trench-shaped structure, the first gate is located above the gate undergrowth enhancement layer, and the gate undergrowth enhancement layer covers the bottom surface and part of the side surface of the first gate; the bottom surface of the gate undergrowth enhancement layer is flush with the bottom surface of the barrier layer, and a second gate is disposed in the second region; a source and a drain are disposed on both the first region and the second region, the first gate is located between the source and drain of the first region, and the second gate is located between the source and drain of the second region, and the bottoms of the first gate and the second gate form Schottky contacts with the barrier layer; the source and drain respectively form ohmic contacts with the two-dimensional electron gas in the channel layer. This application uses an enhancement-mode GaN device to replace the Si MOSFET, thereby solving the problem of unwanted oscillations during fast switching and improving the switching speed.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] refer to Figure 1 This application provides a monolithically integrated all-GaN cascode field-effect transistor, comprising: a substrate 101 and a nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 sequentially stacked on the substrate 101; the barrier layer 105 includes a first region 105a and a second region 105b. Figure 5(As shown in the diagram), a gate under-gated groove penetrating the barrier layer 105 is formed on the first region 105a. A gate under-gated enhancement layer 109 and a first gate 106a are sequentially arranged within the gate under-gated groove. The gate under-gated enhancement layer 109 has a groove-shaped structure. The first gate 106a is located above the gate under-gated enhancement layer 109, and the gate under-gated enhancement layer 109 covers the bottom surface and part of the side surface of the first gate 106a. The bottom surface of the gate under-gated enhancement layer 109 is flush with the bottom surface of the barrier layer 105. A second gate 106b is provided in the second region 105b. Both region 105a and region 105b are provided with source 107 and drain 108. First gate 106a is located between source 107 and drain 108 in first region 105a, and second gate 106b is located between source 107 and drain 108 in second region 105b. The bottom of first gate 106a and second gate 106b are both connected to the barrier layer 105 to form Schottky contacts. Source 107 and drain 108 are respectively connected to the two-dimensional electron gas in channel layer 104 to form ohmic contacts.

[0031] The monolithically integrated all-GaN cascode field-effect transistor provided in this application can be used in enhancement-mode circuits. This application addresses the technical problem of "cascode FET devices generating unwanted oscillations during fast switching" by providing a monolithically integrated all-GaN cascode field-effect transistor, the circuit principle of which is as follows: Figure 2 As shown. The all-GaN monolithically integrated Cascode device provided in this application involves fabricating depletion-mode and enhancement-mode portions separately on a single device and interconnecting the corresponding electrodes. For example... Figure 1 As shown, it includes: a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, a gate under-gate enhancement layer 109 located in the gate under-gate groove, two sources 107, two drains 108, two gates 106 (i.e., the first gate 106a and the second gate 106b), and a passivation layer 110. The sources 107 and drains 108 are in ohmic contact with the two-dimensional electron gas, and the gates 106 are in Schottky contact with the barrier layer 105.

[0032] It should be noted that, as Figure 1 As shown, the under-gate enhancement layer 109 is located in the under-gate groove below the first gate 106a. The under-gate enhancement layer 109 covers the bottom surface of the first gate 106a and part of the side surfaces on both sides of the first gate 106a. Its purpose is to alleviate the peak electric field, improve breakdown, and reduce current collapse.

[0033] In some embodiments, the under-gate enhancement layer 109 includes an extension layer extending in a width direction away from the first gate 106a, the extension layer partially covering the top surface of the barrier layer 105 in contact with it. For example... Figure 1As shown, the under-gate reinforcement layer 109 also includes two extension layers extending out of the under-gate recess, which can also be referred to as the two wings of the under-gate reinforcement layer 109; the two wings of the under-gate reinforcement layer 109 cover the top surface of the barrier layer 105. Typically, due to manufacturing limitations, the fabricated under-gate reinforcement layer 109 includes, as shown... Figure 1 The two wings shown can further alleviate the peak electric field and improve the breakdown resistance.

[0034] It is understandable that the under-gate reinforcement layer 109 can also be a groove-shaped structure excluding the two wings. For example... Figure 3 As shown, the under-gate enhancement layer 109 can be a groove-shaped structure that includes only the bottom surface and two side surfaces. The under-gate enhancement layer 109 wraps the bottom surface and part of the side surfaces of the first gate 106a, and its sidewalls do not extend out of the under-gate groove.

[0035] In some embodiments, the two sidewalls of the under-gate reinforcement layer 109 are flush with the surfaces of the barrier layer 105 it contacts. For example... Figure 3 As shown, along the thickness direction of the barrier layer 105, the upper surfaces of the two sidewalls of the under-gate reinforcement layer 109 are flush with the upper surface of the barrier layer 105, and the lower surfaces of the two sidewalls of the under-gate reinforcement layer 109 are also flush with the lower surface of the barrier layer 105. It can be understood that the length, thickness, and height of the under-gate reinforcement layer 109 are all adjustable.

[0036] In some embodiments, along the direction from the substrate 101 to the barrier layer 105, the thickness of the bottom layer of the under-gate enhancement layer 109 is 1% to 20% of the thickness of the barrier layer 105; the height of the sidewall of the under-gate enhancement layer 109 can be equal to or higher than the height of the barrier layer 105. For example, the height of the bottom layer of the under-gate enhancement layer 109 can be 1%, 5%, 10%, 15%, or 20% of the height of the barrier layer 105. Figure 1 This illustrates the case where the height of the sidewall of the under-gate reinforcement layer 109 is higher than that of the barrier layer 105; Figure 3 This shows the case where the height of the sidewall of the gate under-gate reinforcement layer 109 is flush with the upper surface of the barrier layer 105.

[0037] In some embodiments, the length of the bottom layer of the gate under-gate enhancement layer 109 along the direction from the source 107 to the drain 108 is 1 μm to 3 μm. The length of the bottom layer of the gate under-gate enhancement layer 109 depends on the opening size of the gate under-gate recess. Preferably, the length of the gate under-gate recess is 2 μm. When the gate under-gate enhancement layer 109 includes two wings extending out of the gate under-gate recess, the length of the two extended wings can be 1 μm.

[0038] In some embodiments, the material of the under-gate reinforcement layer 109 includes one of silicon nitride (SiN) and aluminum oxide (Al2O3).

[0039] In some embodiments, a passivation layer 110 is provided between the first gate 106a and the source 107 of the first region 105a, and between the first gate 106a and the drain 108 of the first region 105a, and the passivation layer 110 covers the surface of the barrier layer 105 and the under-gate enhancement layer 109.

[0040] In some embodiments, the second gate 106b is located on the surface of the second region 105b of the barrier layer 105; a passivation layer 110 is provided between the second gate 106b and the source 107 of the second region 105b, and between the second gate 106b and the drain 108 of the second region 105b.

[0041] In some embodiments, a passivation layer 110 is provided between the drain 108 of the first region 105a and the source 107 of the second region 105b.

[0042] It should be noted that a passivation layer 110 is provided above the barrier layer 105 in both the first region 105a and the second region 105b. The height of the passivation layer 110 above the barrier layer 105 in the first region 105a can be equal to or unequal to the height of the passivation layer 110 above the barrier layer 105 in the second region 105b. Typically, since the passivation layers 110 above the barrier layer 105 in the first region 105a and the second region 105b are fabricated simultaneously, the height of the passivation layer 110 above the barrier layer 105 in the first region 105a is equal to the height of the passivation layer 110 above the barrier layer 105 in the second region 105b.

[0043] In some embodiments, such as Figure 6 As shown, the drain 108 of the first region 105a is connected to the source 107 of the second region 105b; the second gate 106b is connected to the source 107 of the first region 105a. Figure 6 The dashed line in the middle represents the interconnection relationship.

[0044] In some embodiments, such as Figure 1 , Figure 3 , Figures 5 to 6 As shown, the monolithically integrated all-GaN cascode field-effect transistor further includes an insertion layer (located at the dashed line in the structure diagram) for improving carrier mobility. The insertion layer is situated between the barrier layer 105 and the channel layer 104. The insertion layer is used to improve carrier mobility, and the material of the insertion layer includes, but is not limited to, AlN, InAlN, and AlGaN.

[0045] In some embodiments, the material of the substrate 101 includes one of sapphire, silicon carbide (SiC), silicon (Si), and gallium nitride (GaN). The direction from the lower surface of the substrate 101 to the upper surface of the substrate 101 is defined as the thickness direction, and the thickness of the substrate 101 is 100 nm to 1000 μm. It should be noted that the thicknesses mentioned in the following embodiments of this application refer to the thickness of each film layer in this thickness direction.

[0046] In some embodiments, the material of the nucleation layer 102 includes one of gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (AlGaN). Preferably, the material of the nucleation layer 102 is AlN; the thickness of the nucleation layer 102 is 25 nm to 500 nm.

[0047] In some embodiments, the material of the buffer layer 103 includes one or more of gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (AlGaN). Preferably, the material of the buffer layer 103 is GaN; the thickness of the buffer layer 103 is 0.5 μm to 5 μm.

[0048] In some embodiments, the channel layer 104 is made of one of gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (AlGaN). Preferably, the channel layer 104 is made of GaN. The thickness of the channel layer 104 is 50 nm to 500 nm.

[0049] In some embodiments, the barrier layer 105 is made of AlN or wurtzite-structured AlGaN. Specifically, when the barrier layer 105 is made of wurtzite-structured AlGaN, the material of the barrier layer 105 is Al x Ga (1-x) N. When the barrier layer is 105 Al x Ga (1-x) In the case of N, the composition of Al (value of x) is 0.1~1.0. The thickness of the barrier layer 105 is 10nm~60nm.

[0050] In some embodiments, the source 107 and drain 108 may be made of a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au, so that the source 107 and drain 108 respectively form ohmic contacts with the barrier layer 105.

[0051] In some embodiments, the gate 106 is made of a metal that can form a Schottky contact with the barrier layer 105.

[0052] In some embodiments, the passivation layer 110 is made of one of silicon oxide (SiO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4); the materials of the passivation layer 110 above the first region 105a barrier layer 105 and the passivation layer 110 above the second region 105b barrier layer 105 can be the same or different. For example, the height of the passivation layer 110 is 20 nm to 500 nm.

[0053] See Figure 4 This application also provides a method for fabricating a monolithically integrated all-GaN cascode field-effect transistor, comprising the following steps:

[0054] Step S1: Provide a substrate and form a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially on the substrate.

[0055] Step S2: Etch a first groove and a second groove through the barrier layer. The second groove is located in the middle of the barrier layer, and the first groove is located between one side edge of the barrier layer and the second groove. Taking the second groove as the boundary, the side on the barrier layer where the first groove is formed is the first region, and the side where the first groove is not formed is the second region.

[0056] Step S3: A gate under-reinforcement layer is formed in the first groove. The gate under-reinforcement layer has a groove-shaped structure, and the bottom surface of the gate under-reinforcement layer is flush with the bottom surface of the barrier layer.

[0057] Step S4: Fabricate a mask on the barrier layer to form an ohmic window, and form the source and drain on the first and second regions.

[0058] Step S5: Fabricate a mask on the barrier layer and the under-gate enhancement layer to form a gate window, form a first gate in the first region, the first gate is located above the under-gate enhancement layer, and the under-gate enhancement layer covers the bottom surface and part of the side surface of the first gate; and form a second gate in the second region.

[0059] Step S6: Form a passivation material layer above the barrier layer, source, drain and gate.

[0060] Step S7: Open holes in the passivation material layer above the source, drain, and gate, bring out electrodes, interconnect the drain of the first region with the source of the second region, and interconnect the source of the first region with the gate of the second region to obtain a transistor.

[0061] Specifically, in fabricating a high electron mobility transistor, a substrate 101 is first provided, and a nucleation layer 102, a buffer layer 103, a channel layer 104 and a barrier layer 105 are formed on the substrate 101 in sequence. Before forming the stacked films on substrate 101, substrate 101 is first pretreated and heat-treated. Substrate 101 is immersed in hydrofluoric acid (HF) solution for 1 min, and then ultrasonically cleaned in acetone solution, anhydrous ethanol solution and deionized water for 10 min each to eliminate dangling bonds on the surface of substrate 101. After cleaning and drying, substrate 101 is heat-treated at 1050°C for 10 min in a hydrogen (H2) atmosphere reaction chamber to remove surface contaminants. Then, substrate 101 is placed in a metal-organic chemical vapor deposition (MOCVD) system. The process parameters of the MOCVD system are: pressure of 10 Torr~100 Torr, Al source flow rate of 10 sccm~100 sccm, ammonia flow rate of 3000 sccm~6000 sccm, hydrogen flow rate of 1000 sccm~2000 sccm, and temperature of 900°C. Preferably, the reaction chamber pressure is 10 Torr and the temperature is 900°C. An Al source with a flow rate of 30 sccm, hydrogen gas with a flow rate of 1000 sccm, and ammonia gas with a flow rate of 3000 sccm are simultaneously introduced into the reaction chamber. A nucleation layer 102 with a height of approximately 30 nm is deposited and grown using MOCVD technology. Preferably, the material of the nucleation layer 102 is AlN; the thickness of the substrate 101 is 100 nm, and the thickness of the nucleation layer 102 is 25 nm.

[0062] Next, a buffer layer 103 is deposited sequentially on the nucleation layer 102 using an MOCVD process. During the deposition of the buffer layer 103, the reaction chamber pressure in the MOCVD process is 10 Torr to 100 Torr, the Ga source flow rate is 50 μmol / min to 100 μmol / min, the ammonia flow rate is 3000 sccm to 6000 sccm, the hydrogen flow rate is 1000 sccm to 2000 sccm, and the temperature is 900°C. Preferably, the reaction chamber pressure of the MOCVD process for depositing the nucleation layer 102 is 10 Torr, the temperature is 900°C, and a Ga source with a flow rate of 50 μmol / min, hydrogen with a flow rate of 1000 sccm, and ammonia with a flow rate of 3000 sccm are simultaneously introduced into the reaction chamber to form the buffer layer 103. Preferably, the material of the buffer layer 103 is GaN, and the thickness of the buffer layer 103 is 0.5 μm.

[0063] Next, a 50 nm channel layer 104 is sequentially deposited on the buffer layer 103 using an MOCVD process. The MOCVD process parameters are: reaction chamber pressure of 10 Torr, temperature of 900 °C, and simultaneous introduction of a Ga source at a flow rate of 50 μmol / min, hydrogen at a flow rate of 1000 sccm, and ammonia at a flow rate of 3000 sccm into the reaction chamber. Preferably, the material of the channel layer 104 is GaN, and the thickness of the channel layer 104 is 50 nm.

[0064] On the channel layer 104, a barrier layer 105 is deposited using the MOCVD process; preferably, the material of the barrier layer 105 is Al. x Ga (1-x) N, where x is between 0.1 and 0.2. In this embodiment, the Al composition is 0.1, and the deposition thickness is 40 nm. During the deposition of the barrier layer 105, the reaction chamber pressure in the MOCVD process is 10 Torr to 100 Torr, the Al source flow rate is 10 μmol / min to 30 μmol / min, the Ga source flow rate is 30 μmol / min to 90 μmol / min, the ammonia flow rate is 3000 sccm to 6000 sccm, the hydrogen flow rate is 1000 sccm to 2000 sccm, and the temperature is 900°C. Preferably, the MOCVD process parameters for depositing the barrier layer 105 are: reaction chamber pressure of 10 Torr, temperature of 900°C, and simultaneous introduction of Al source at a flow rate of 10 μmol / min, Ga source at a flow rate of 30 μmol / min, hydrogen at a flow rate of 1000 sccm, and ammonia at a flow rate of 3000 sccm into the reaction chamber to form the barrier layer 105. The thickness of the barrier layer 105 is 40 nm.

[0065] Next, as Figure 5 As shown, two grooves (notches) are etched into the AlxGa(1-x)N barrier layer 105 using an etching process to form a first region 105a and a second region 105b. The width of the first groove 111 (left notch) is 2μm, and the width of the second groove 112 (right notch) is 4μm. The second groove 112 is located in the middle of the barrier layer 105, and the first groove is located between one edge of the barrier layer and the second groove; with the second groove 112 as the boundary, one side of the first groove 111 is formed on the barrier layer 105 (… Figure 5 The left side of the intermediate barrier layer 105 is the first region 105a, the side where the first groove 111 is not formed ( Figure 5 The right side of the middle barrier layer 105 is the second region 105b.

[0066] Next, an Al2O3 under-gate groove was fabricated on the left notch using atomic layer deposition (ALD) technology, and the surface was treated with oxygen plasma. The surface-treated wafer was then placed into the ALD cavity, with TMA and deionized water as the Al and O sources respectively, and N2 as the carrier gas. A 5 nm Al2O3 thin film was deposited at 300°C to form the under-gate enhancement layer 109. Figure 6 As shown, the under-gate reinforcement layer 109 has a groove structure, and the bottom surface of the under-gate reinforcement layer 109 is flush with the bottom surface of the barrier layer 105.

[0067] A mask was fabricated on the barrier layer 105 to form an ohmic window. The mask was then placed in an E-Beam electron beam evaporation apparatus and two source electrodes 107 and two drain electrodes 108 were deposited using electron beam evaporation. Ti / Al / Ni / Au metal was used as the source and drain electrodes. The electron beam evaporation rate was 0.1 nm / s, and the mask was annealed at 850 °C for 30 s.

[0068] Preferably, the source electrode 107 and the drain electrode 108 are made of a Ti / Al / Ni / Au metal combination, wherein the thickness of the Ti metal is 20nm~100nm, the thickness of the Al metal is 100nm~300nm, the thickness of the Ni metal is 20nm~200nm, and the thickness of the Au metal is 20nm~200nm. In the embodiments of this application, the thickness of the Ti metal is 20nm, the thickness of the Al metal is 100nm, the thickness of the Ni metal is 20nm, and the thickness of the Au metal is 20nm.

[0069] A mask is fabricated on the under-gate enhancement layer 109 (at the under-gate recess) and the AlxGa(1-x)N barrier layer 105 to form a gate window. The sample with the window formed is placed in an electron beam evaporation reaction chamber. Using nickel and gold targets with a purity of 99.999%, metal Ni / Au is deposited in the gate window as two gates 106 (first gate 106a and second gate 106b) using an electron beam evaporation process. Specifically, the first gate 106a is formed in the first region 105a of the barrier layer 105, and the first gate 106a is located above the under-gate enhancement layer 109, with the under-gate enhancement layer 109 covering the bottom surface and part of the side surface of the first gate 106a; and the second gate 106b is formed on the second region 105b of the barrier layer 105. The thickness of Ni is 20 nm, and the thickness of Au is 50 nm; if a different metal than the gate is used, a mask can be fabricated separately.

[0070] The sample, after completing the above steps, is placed in a plasma-enhanced chemical vapor deposition (PECVD) reaction chamber. The PECVD process deposits a passivation material layer of 50 nm to 400 nm thickness on top of the barrier layer 105, gate 106, source 107, and drain 108. During the PECVD process for depositing the passivation material layer, the reaction chamber pressure is 0.5 Pa to 30 Pa, the reaction chamber temperature is 200 °C to 350 °C, and 20 sccm of silane (SiH4) and 100 sccm of nitrous oxide (N2O) gas, or silane and ammonia gas, are simultaneously introduced into the reaction chamber. In some embodiments, the passivation material layer material includes one of SiO2, Al2O3, and Si3N4.

[0071] In this embodiment, the material of the passivation layer 110 is SiO2; the thickness of the passivation layer 110 is 50nm; the parameters of the PECVD process are set as follows: the reaction chamber pressure is 0.5Pa, the temperature is 200℃, and SiH4 with a flow rate of 20sccm and N2O with a flow rate of 100sccm are simultaneously introduced into the reaction chamber.

[0072] Finally, holes are made in the passivation layer 110 above the gate 106, source 107, and drain 108 to bring out electrodes. The left drain 108 is interconnected with the right source 107, and the left source 107 is interconnected with the right gate 106, thus obtaining the transistor. Figure 6 As shown.

[0073] The purpose of this application is to propose a fully GaN monolithically integrated cascode device. By integrating enhancement-mode GaN and depletion-mode GaN into a single device, compared to current Si and GaN cascode solutions, parasitic inductance is reduced, the fabrication process is simplified, and packaging costs are lowered. Simultaneously, the enhancement-mode is fabricated using a gate-under-groove metal-insulator-semiconductor (MIS) structure, which requires only lower voltage stress in practical applications. This overcomes the poor high-voltage stress reliability of conventional grooved MIS structures, allowing the device to achieve enhancement characteristics while retaining a series of advantages of GaN HEMT devices.

[0074] It should be noted that the MIS in under-gate groove MIS includes PECVD, ALD growth, and in-situ dielectric growth to improve reliability. Furthermore, enhancement-mode GaN is not limited to under-gate grooves; it can also be achieved through other methods, such as P-GaN technology, F-ion implantation technology, and thin-layer barriers.

[0075] It is understood that the fabrication process, size, and material structure of the Cascode device provided in this application, which is entirely GaN monolithically integrated, are not limited to the examples mentioned above.

[0076] Based on the above technical solutions, this application provides a monolithically integrated all-GaN cascode field-effect transistor and its fabrication method. The transistor includes: a substrate 101 and a nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 sequentially stacked on the substrate; the barrier layer 105 includes a first region 105a and a second region 105b; a gate under-groove is formed in the first region 105a, penetrating the barrier layer 105, and a gate under-reinforcement layer 109 and a first gate 106a are sequentially disposed in the gate under-groove. The gate under-reinforcement layer 109 has a groove structure, and the first gate 106a is located above the gate under-reinforcement layer 109, and the gate under-reinforcement layer 109 covers the first gate. The bottom surface and part of the side surface of electrode 106a; the bottom surface of the gate under enhancement layer 109 is flush with the bottom surface of the barrier layer 105, and the second region 105b is provided with a second gate 106b; both the first region 105a and the second region 105b are provided with a source 107 and a drain 108, the first gate 106a is located between the source 107 and the drain 108 of the first region 105a, and the second gate 106b is located between the source 107 and the drain 108 of the second region 105b, and the bottom of the first gate 106a and the second gate 106b are both in Schottky contact with the barrier layer 105; the source 107 and the drain 108 are respectively in ohmic contact with the two-dimensional electron gas in the channel layer 104.

[0077] This application provides a monolithically integrated all-GaN cascode field-effect transistor (FET) that replaces the Si MOSFET with an enhancement-mode GaN device, thereby solving the problem of unwanted oscillations during fast switching and improving switching speed. Since the depletion-mode GaN device lacks a body diode, avalanche phenomena in low-voltage devices during turn-off are avoided. Furthermore, parasitic inductance can be minimized through monolithic integration, reducing oscillations during turn-off operations and improving parallel operation. Under high-voltage operation, the high-voltage portion of the device is handled by the depletion-mode GaN, resulting in higher device reliability.

[0078] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A monolithically integrated all-GaN cascode field effect transistor, characterized by, The application relates to a semiconductor device, and discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate and a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked on the substrate. The barrier layer comprises a first region and a second region; a gate-under recess is formed in the first region and penetrates the barrier layer; a gate-under enhancement layer and a first gate are sequentially arranged in the gate-under recess; the gate-under enhancement layer is in a groove-shaped structure; the first gate is located above the gate-under enhancement layer, and the gate-under enhancement layer covers the bottom surface and part of the side surface of the first gate; the bottom surface of the gate-under enhancement layer is flush with the bottom surface of the barrier layer; and the second region is provided with a second gate. The source and the drain are arranged on the first region and the second region; the first gate is located between the source and the drain of the first region; the second gate is located between the source and the drain of the second region; the bottom of the first gate and the bottom of the second gate are in Schottky contact with the barrier layer; and the source and the drain are in Ohmic contact with two-dimensional electron gas in the channel layer. The drain of the first region is connected with the source of the second region; and the second gate is connected with the source of the first region.

2. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, The gate-under enhancement layer comprises an extension layer which extends in a direction away from the width of the first gate; and the extension layer partially covers the top surface of the barrier layer which is in contact with the extension layer.

3. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, The two side walls of the gate-under enhancement layer are flush with the surfaces of the barrier layer which are in contact with the two side walls.

4. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, The material of the gate-under enhancement layer comprises one of silicon nitride and aluminum oxide.

5. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, A passivation layer is arranged between the first gate and the source of the first region and between the first gate and the drain of the first region, and the passivation layer covers the surfaces of the barrier layer and the gate-under enhancement layer.

6. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, The second gate is located on the surface of the second region of the barrier layer; a passivation layer is arranged between the second gate and the source of the second region and between the second gate and the drain of the second region.

7. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, A passivation layer is arranged between the drain of the first region and the source of the second region.

8. The monolithically integrated all-GaN cascode field effect transistor of claim 1, wherein, The application further discloses a semiconductor device and a manufacturing method thereof. An insertion layer for improving carrier mobility is arranged between the barrier layer and the channel layer.

9. A method for fabricating a monolithically integrated all-GaN cascode field effect transistor, the method being for fabricating a monolithically integrated all-GaN cascode field effect transistor as claimed in any one of claims 1 to 8, characterized in that, The application discloses a semiconductor device and a manufacturing method thereof. A substrate is provided, and a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially stacked on the substrate. A first recess and a second recess are etched in the barrier layer and penetrate the barrier layer; the second recess is located in the middle of the barrier layer, and the first recess is located between one side edge of the barrier layer and the second recess; the first recess is arranged on one side of the barrier layer with the second recess as a boundary, and the other side of the barrier layer is a second region without the first recess; A gate-under enhancement layer is formed in the first recess; the gate-under enhancement layer is in a groove-shaped structure; and the bottom surface of the gate-under enhancement layer is flush with the bottom surface of the barrier layer. A mask is made on the barrier layer to form an Ohmic window, and a source and a drain are formed on the first region and the second region; A mask is made on the barrier layer and the gate-under enhancement layer to form a gate window, a first gate is formed on the first region, the first gate is located above the gate-under enhancement layer, and the gate-under enhancement layer covers the bottom surface and part of the side surface of the first gate; and a second gate is formed on the second region. A passivation material layer is formed above the barrier layer, the source, the drain and the gate; A passivation material layer is formed above the source, the drain and the gate; and A passivation material layer is formed above the source, the drain and the gate; and

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