Chip testing method and chip testing equipment

Abstract

The present invention relates to the field of chip testing, and in particular to a chip testing method and a chip testing device. The method comprises the following steps: performing chip layout structure analysis on a chip to generate a chip layout structure diagram; marking key nodes of the chip based on the chip layout structure diagram; performing infrared light focusing irradiation processing on key nodes of the chip to obtain node optical signal data; obtaining dynamic stripe vibration distribution data based on the node optical signal data; performing vibration frequency peak calculation on the dynamic stripe vibration distribution data to generate vibration frequency peak; performing abnormal node identification on the vibration frequency peak based on a preset frequency distribution curve, marking abnormal component nodes; performing multi-frequency transient voltage excitation on abnormal component nodes to generate transient feature data; performing dynamic voltage evolution mining processing on transient feature data to obtain non-steady-state voltage rate distribution data. The present invention realizes efficient and accurate chip testing.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a chip testing method and a chip testing device. Background Art

[0002] In recent years, with the continuous development of chip technology, chip nodes are constantly shrinking, and circuit structures are becoming increasingly complex. Traditional fixed test modes are difficult to meet the testing needs of modern chips. Traditional chip testing processes rely on a large number of preset test cases, and the testing efficiency is low. As the scale of transistors increases, traditional testing methods are difficult to effectively discover hidden defects under extreme conditions. There are often problems with low chip testing accuracy and low efficiency. Therefore, an intelligent chip testing method is needed. Summary of the invention

[0003] In order to solve the above technical problems, the present invention proposes a chip testing method and a chip testing device to solve at least one of the above technical problems.

[0004] To achieve the above object, the present invention provides a chip testing method, comprising the following steps:

[0005] Step S1: performing chip layout structure analysis on the chip to generate a chip layout structure diagram; marking key nodes of the chip based on the chip layout structure diagram;

[0006] Step S2: performing infrared light focusing irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; and obtaining the dynamic stripe vibration distribution data based on the optical signal data of the nodes;

[0007] Step S3: Calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify abnormal nodes of the vibration frequency peak value based on a preset frequency distribution curve, and mark abnormal component nodes;

[0008] Step S4: performing multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; performing dynamic voltage evolution mining processing on the transient characteristic data to obtain non-steady-state voltage rate distribution data;

[0009] Step S5: performing electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; performing electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes;

[0010] Step S6: construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; perform abnormal node fault prediction on the abnormal node feature map to construct a chip optimization decision strategy to perform chip testing operations.

[0011] The present invention can obtain the positional relationship between the components and nodes inside the chip by analyzing the layout structure of the chip. Marking key nodes is helpful for subsequent analysis and test positioning. Focused infrared light irradiation can obtain the optical signal data of the node, including the vibration information of the node. Through optical interference analysis, dynamic stripe vibration distribution data can be obtained to help understand the vibration of the node. By calculating the vibration frequency peak, the main vibration frequency of the node can be determined. Using the preset frequency distribution curve, the vibration frequency peak can be used to identify abnormal nodes and mark the component nodes that may have problems. By performing multi-frequency transient voltage excitation on the abnormal component node, the transient characteristic data of the node can be obtained. By performing dynamic voltage evolution mining processing on these data, non-steady-state voltage rate distribution data can be obtained to help understand the voltage change of the node. By analyzing the non-steady-state voltage rate distribution data, the electromagnetic response characteristics of the node can be understood. On this basis, the electromagnetic compatibility analysis of the abnormal component node is performed to generate the electromagnetic compatibility data of the node to help evaluate the stability and reliability of the node in the electromagnetic environment. By combining the non-steady-state voltage rate distribution data and the node electromagnetic compatibility data, an abnormal node feature map is constructed. Based on this graph, abnormal node failure prediction can be performed to help determine the reliability and potential failure risk of the node. This information can be used to formulate chip optimization decision strategies and perform corresponding chip testing operations to improve chip quality and performance.

[0012] Preferably, step S1 comprises the following steps:

[0013] Step S11: performing component identification on the chip to obtain chip component data;

[0014] Step S12: performing component distribution analysis on the chip component data to obtain component distribution position data;

[0015] Step S13: performing line connection path identification on the component distribution position data to obtain component connection line data;

[0016] Step S14: performing chip layout structure analysis based on the component connection line data to generate a chip layout structure diagram;

[0017] Step S15: Identify the cross-connection points of the circuits based on the chip layout structure diagram to mark the key nodes of the chip.

[0018] The present invention can accurately identify and record the type and characteristic parameters of each component on the chip through component identification. These component data are very important for subsequent analysis and testing. Through component distribution analysis, the spatial layout of components in the chip, including the relative position and wiring between components, can be understood. These component distribution position data provide a basis for subsequent line connection analysis. Through line connection path identification, the connection relationship and connection path between components in the chip can be determined. After obtaining the component connection line data, the circuit structure and signal transmission path of the chip can be better understood. Through chip layout structure analysis, the component connection line data can be converted into an intuitive chip layout structure diagram, which can clearly show the layout relationship between components and connection lines in the chip, providing a visual reference for subsequent analysis and testing. Through line cross-connection point identification, the key nodes in the chip layout structure can be determined. These nodes have important functions and influences in the chip. Marking them is helpful for subsequent analysis, testing and fault location.

[0019] Preferably, step S2 comprises the following steps:

[0020] Step S21: performing infrared light focusing irradiation processing on key nodes of the chip to obtain optical signal data of the nodes;

[0021] Step S22: performing optical interference analysis on the node optical signal data to generate node optical fringe data;

[0022] Step S23: performing micro-optical vibration detection on the node optical fringe data to generate optical fringe offset data;

[0023] Step S24: performing optical flow tracking on the optical fringe offset data to generate dynamic fringe vibration distribution data.

[0024] The present invention can stimulate the key nodes of the chip to emit optical signals through infrared light focused irradiation processing. These optical signals contain the optical characteristics and vibration information of the nodes. Acquisition of these data provides a basis for subsequent analysis and testing. Through optical interference analysis, the node optical signals can be converted into optical fringe data. Optical fringes are special patterns produced by the interference effect of light waves. By analyzing these fringes, information such as the vibration and deformation of the nodes can be obtained. Through tiny optical vibration detection, the tiny displacement and change of the optical fringes can be measured. These optical fringe offset data reflect the tiny vibration of the nodes, providing important vibration characteristic data for subsequent analysis and testing. Through the optical flow tracking algorithm, the movement and change of the optical fringes can be analyzed, thereby generating dynamic fringe vibration distribution data. These data can display information such as the vibration mode, frequency and amplitude of the nodes, which is helpful for in-depth understanding of the vibration characteristics and performance of the chip.

[0025] Preferably, the specific steps of step S21 are:

[0026] Locating the key nodes of the chip, performing infrared light focusing irradiation treatment on the key nodes of the chip, and continuously acquiring image sequences;

[0027] Performing multi-frame photon tracing on the image sequence to extract an optical response feature sequence;

[0028] Performing time-frequency analysis on the optical response characteristic sequence to obtain optical fingerprint data of key nodes of the chip;

[0029] Node optical signal data is obtained based on the optical fingerprint data of the key nodes of the chip.

[0030] The present invention can accurately select and excite key nodes on the chip through positioning and infrared light focused irradiation processing. The continuously acquired image sequence can capture the changes in the optical response of the nodes over time, providing a data basis for subsequent analysis. The multi-frame photon tracking algorithm can track and extract the optical response characteristics of the key nodes in the image sequence. These optical response feature sequences reflect the dynamic change process of the nodes, including deformation, vibration, and optical signal intensity. Through time-frequency analysis, the optical response feature sequences can be converted into optical fingerprint data in the frequency domain and time domain. These optical fingerprint data contain information such as the frequency component, vibration mode and intensity change of the nodes, and can more comprehensively describe the optical characteristics of the nodes. By analyzing and interpreting the optical fingerprint data of the key nodes of the chip, the optical signal data of the nodes can be derived. These data include information such as the optical characteristics, vibration frequency, amplitude and phase of the nodes, providing an important basis for chip performance evaluation, fault analysis and optimization.

[0031] Preferably, the specific steps of step S3 are:

[0032] Step S31: performing frequency domain transfer processing on the dynamic fringe vibration distribution data to obtain optical fringe frequency component data;

[0033] Step S32: Calculating the vibration frequency peak value of the optical fringe frequency component data to generate a vibration frequency peak value;

[0034] Step S33: performing outlier vibration peak analysis on the vibration frequency peak based on a preset frequency distribution curve to obtain abnormal vibration frequency data;

[0035] Step S34: Identify abnormal nodes on the chip layout structure diagram based on the abnormal vibration frequency data and mark abnormal component nodes.

[0036] The present invention can convert dynamic stripe vibration distribution data into frequency domain data through frequency domain transfer processing, so that different frequency components in optical stripes can be analyzed, the frequency characteristics of node vibration can be understood, and a data basis can be provided for subsequent vibration frequency analysis. By calculating the peak values ​​in the optical stripe frequency component data, the main frequency of node vibration can be determined. These vibration frequency peak values ​​reflect the node vibration mode and the main vibration frequency, providing an important basis for abnormal node identification. By comparing with a preset frequency distribution curve, it can be analyzed whether the vibration frequency peak value belongs to the normal range. In this way, abnormal vibration frequencies, i.e., outlier vibration peak values, can be identified, and potential abnormal node information is provided. By analyzing the abnormal vibration frequency data, corresponding abnormal nodes can be identified in the chip layout structure diagram. These abnormal nodes may indicate components with potential problems or failures. By marking the abnormal nodes, engineers can be assisted in further troubleshooting and repair work.

[0037] Preferably, the specific steps of step S4 are:

[0038] Step S41: performing multi-frequency transient voltage excitation on the abnormal component node to obtain multi-frequency transient excitation data;

[0039] Step S42: Capturing transient features of the multi-frequency transient excitation data to generate transient feature data;

[0040] Step S43: performing multi-frequency time-series voltage analysis on the transient characteristic data to generate time-series voltage data;

[0041] Step S44: performing multi-time-frequency decomposition on the time series voltage data to obtain non-steady-state voltage data;

[0042] Step S45: performing dynamic voltage evolution mining processing on the non-steady-state voltage data to obtain non-steady-state voltage rate distribution data.

[0043] The present invention can induce a non-steady-state voltage response of the node by performing multi-frequency transient voltage excitation on the abnormal component node. The multi-frequency transient excitation data includes the voltage response information of the node at different frequencies, providing a data basis for subsequent transient feature capture. By performing transient feature analysis on the multi-frequency transient excitation data, the transient characteristics of the node voltage response can be captured. These transient feature data reflect the amplitude, rise time, fall time, peak value and other information of the node response, providing a data basis for subsequent sequential voltage analysis. Through multi-frequency sequential voltage analysis, the transient feature data can be converted into sequential voltage data. The sequential voltage data reflects the node voltage response as the node voltage changes. The time changes, including oscillation, attenuation, waveform shape and other information, provide a data basis for the subsequent time-frequency decomposition. Through multi-time-frequency decomposition technology, the time-series voltage data can be decomposed into components of different time-frequency scales, so that the changing characteristics of the node voltage at different frequencies and time scales can be analyzed, and the non-steady-state voltage data can be obtained, which provides a data basis for the subsequent dynamic voltage evolution mining. Through dynamic voltage evolution mining processing, the evolution law and rate distribution of non-steady-state voltage data can be analyzed. These non-steady-state voltage rate distribution data reflect the changing speed and distribution of the node voltage, which can help identify abnormal voltage change patterns and abnormal nodes.

[0044] Preferably, the specific steps of step S5 are:

[0045] Step S51: performing electromagnetic response analysis of adjacent nodes on abnormal component nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes;

[0046] Step S52: performing electromagnetic radiation interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic radiation interference data;

[0047] Step S53: performing electromagnetic conduction interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic conduction interference data;

[0048] Step S54: performing electromagnetic compatibility analysis of abnormal component nodes on the electromagnetic radiation interference data and the electromagnetic conduction interference data to generate node electromagnetic compatibility data.

[0049] By analyzing the non-steady-state voltage rate distribution data of the abnormal component node, the present invention can understand the electromagnetic response of the neighboring nodes around the node to it. The electromagnetic response data of the neighboring nodes reflects the electromagnetic interaction relationship between the node and the surrounding environment, providing a data basis for the subsequent electromagnetic interference analysis. Through the electromagnetic radiation interference analysis, the radiation interference generated by the electromagnetic response of the neighboring nodes on the surrounding environment can be analyzed. The electromagnetic radiation interference data reflects the intensity, frequency distribution, radiation direction and other information of the electromagnetic radiation of the node, providing a data basis for evaluating the electromagnetic compatibility of the node. Through the electromagnetic conduction interference analysis, the conduction interference generated by the electromagnetic response of the neighboring nodes on the surrounding environment can be analyzed. The electromagnetic conduction interference data reflects the conduction capability, transmission path, conduction mode and other information of the node's electromagnetic field, providing a data basis for evaluating the electromagnetic compatibility of the node. Through the analysis of the electromagnetic radiation interference data and the electromagnetic conduction interference data, the electromagnetic compatibility of the abnormal component node can be evaluated. The node electromagnetic compatibility data reflects the sensitivity, anti-interference capability, electromagnetic radiation and conduction risk and other information of the node in the electromagnetic environment, helping engineers to determine whether the node meets the electromagnetic compatibility requirements.

[0050] Preferably, the specific steps of step S6 are:

[0051] Step S61: performing node data learning through non-steady-state voltage rate distribution data and node electromagnetic compatibility data to generate an abnormal node sample database;

[0052] Step S62: performing situation evolution analysis on the abnormal node sample database to generate an abnormal node feature map;

[0053] Step S63: performing abnormal node fault prediction on the abnormal node feature map to generate abnormal node fault prediction data;

[0054] Step S64: Perform fault optimization decision analysis on abnormal node fault prediction data to construct a chip optimization decision strategy to execute chip testing operations.

[0055] The present invention can establish an abnormal node sample database by learning non-steady-state voltage rate distribution data and node electromagnetic compatibility data. The database contains the electromagnetic response characteristics of abnormal nodes and the electromagnetic compatibility data of nodes, providing a data basis for subsequent abnormal node fault prediction and optimization decision-making. By performing situation evolution analysis on the abnormal node sample database, the evolution law and characteristics of abnormal nodes can be revealed. The abnormal node feature map reflects the changes in the electromagnetic characteristics of the node at different time points or under different conditions, which helps to understand the dynamic behavior and failure mode of the abnormal node. By analyzing the abnormal node feature map, the failure probability or failure risk of the abnormal node can be predicted. The abnormal node fault prediction data provides predictive information on the node failure state, helps engineers evaluate the reliability and failure risk of the node, and provides a basis for optimization decision-making. By analyzing the abnormal node fault prediction data, fault optimization decision strategies can be formulated. These decision strategies can include selecting appropriate test methods, optimizing chip design or manufacturing processes, so as to reduce the failure probability of abnormal nodes or improve the electromagnetic compatibility of nodes. By executing these decisions, the reliability and performance of the chip can be improved and the failure risk can be reduced.

[0056] In this specification, a chip testing device is provided, which is used to perform the base chip testing method as described above, including:

[0057] The layout structure module is used to analyze the chip layout structure to generate a chip layout structure diagram; and mark the key nodes of the chip based on the chip layout structure diagram;

[0058] The optical interference module is used to perform infrared light focusing and irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; based on the optical signal data of the nodes, the dynamic stripe vibration distribution data is obtained;

[0059] The abnormal node module is used to calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify the abnormal node of the vibration frequency peak value based on the preset frequency distribution curve, and mark the abnormal component node;

[0060] The transient voltage module is used to perform multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; the transient characteristic data is subjected to dynamic voltage evolution mining to obtain non-steady-state voltage rate distribution data;

[0061] The electromagnetic compatibility module is used to perform electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; perform electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes;

[0062] The chip optimization module is used to construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; to predict abnormal node faults on the abnormal node feature map to build a chip optimization decision strategy to perform chip testing operations.

[0063] The present invention can generate a chip layout structure diagram by analyzing the layout structure of the chip through the layout structure module. The diagram provides the relative positions and connection relationships of the chip components, providing a basis for subsequent analysis and testing. The optical interference module can obtain node optical signal data by performing infrared light focusing irradiation processing on the key nodes of the chip. These data can be used for optical interference analysis to generate dynamic stripe vibration distribution data. These data reflect the vibration state and dynamic behavior of the node. The abnormal node module can generate a vibration frequency peak by calculating the vibration frequency peak of the dynamic stripe vibration distribution data. Based on the preset frequency distribution curve, the vibration frequency peak can be used to identify abnormal nodes and mark abnormal component nodes, which helps to quickly detect and locate abnormal nodes in the chip. The transient voltage module generates transient feature data after performing multi-frequency transient voltage excitation on the abnormal component nodes. These data can be used for dynamic voltage evolution mining and processing. In order to obtain the non-steady-state voltage rate distribution data, the non-steady-state voltage rate distribution data provides the dynamic characteristics of the node voltage change, which helps to understand the transient behavior and voltage response of the node. The electromagnetic compatibility module performs electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data, generates electromagnetic response data of adjacent nodes, and uses the electromagnetic response data of adjacent nodes to perform electromagnetic compatibility analysis of abnormal component nodes and generate node electromagnetic compatibility data. These data provide the response characteristics of the node in the electromagnetic environment and help evaluate the electromagnetic compatibility of the node. The chip optimization module constructs an abnormal node feature map through the non-steady-state voltage rate distribution data and the node electromagnetic compatibility data, and predicts abnormal node failures on the abnormal node feature map to construct chip optimization decision strategies. These strategies may include optimization measures for abnormal nodes, test methods or improvements to the manufacturing process. By implementing these strategies, the reliability and performance of the chip can be improved and the risk of failure can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of the steps of a chip testing method of the present invention;

[0065] Figure 2 Detailed implementation flow chart of step S1;

[0066] Figure 3 Detailed implementation flow chart of step S2;

[0067] Figure 4 Detailed implementation flow chart of step S3. DETAILED DESCRIPTION

[0068] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0069] The present application example provides a chip testing method and a chip testing device. The execution subjects of the chip testing method and the chip testing device include but are not limited to the following: mechanical equipment, data processing platform, cloud server node, network upload device, etc. that are equipped with the system can be regarded as the general computing node of the present application, and the data processing platform includes but is not limited to: at least one of an audio image management system, an information management system, and a cloud data management system.

[0070] See also Figures 1 to 4 The present invention provides a chip testing method, which comprises the following steps:

[0071] Step S1: performing chip layout structure analysis on the chip to generate a chip layout structure diagram; marking key nodes of the chip based on the chip layout structure diagram;

[0072] Step S2: performing infrared light focusing irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; and obtaining the dynamic stripe vibration distribution data based on the optical signal data of the nodes;

[0073] Step S3: Calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify abnormal nodes of the vibration frequency peak value based on a preset frequency distribution curve, and mark abnormal component nodes;

[0074] Step S4: performing multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; performing dynamic voltage evolution mining processing on the transient characteristic data to obtain non-steady-state voltage rate distribution data;

[0075] Step S5: performing electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; performing electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes;

[0076] Step S6: construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; perform abnormal node fault prediction on the abnormal node feature map to construct a chip optimization decision strategy to perform chip testing operations.

[0077] The present invention can obtain the positional relationship between the components and nodes inside the chip by analyzing the layout structure of the chip. Marking key nodes is helpful for subsequent analysis and test positioning. Focused infrared light irradiation can obtain the optical signal data of the node, including the vibration information of the node. Through optical interference analysis, dynamic stripe vibration distribution data can be obtained to help understand the vibration of the node. By calculating the vibration frequency peak, the main vibration frequency of the node can be determined. Using the preset frequency distribution curve, the vibration frequency peak can be used to identify abnormal nodes and mark the component nodes that may have problems. By performing multi-frequency transient voltage excitation on the abnormal component node, the transient characteristic data of the node can be obtained. By performing dynamic voltage evolution mining processing on these data, non-steady-state voltage rate distribution data can be obtained to help understand the voltage change of the node. By analyzing the non-steady-state voltage rate distribution data, the electromagnetic response characteristics of the node can be understood. On this basis, the electromagnetic compatibility analysis of the abnormal component node is performed to generate the electromagnetic compatibility data of the node to help evaluate the stability and reliability of the node in the electromagnetic environment. By combining the non-steady-state voltage rate distribution data and the node electromagnetic compatibility data, an abnormal node feature map is constructed. Based on this graph, abnormal node failure prediction can be performed to help determine the reliability and potential failure risk of the node. This information can be used to formulate chip optimization decision strategies and perform corresponding chip testing operations to improve chip quality and performance.

[0078] In the embodiment of the present invention, refer to Figure 1 , is a schematic flow chart of the steps of a chip testing method of the present invention. In this example, the steps of the chip testing method include:

[0079] Step S1: performing chip layout structure analysis on the chip to generate a chip layout structure diagram; marking key nodes of the chip based on the chip layout structure diagram;

[0080] In this embodiment, the design files or related documents of the chip are obtained, including schematics, physical layout files, etc. These files provide information about the relative positions and connection relationships of the internal components of the chip, and the physical design data of the chip is parsed to obtain the layout structure information of the chip. This can be achieved by parsing the layout data, hierarchy and connection relationships in the design files. According to the layout structure information obtained by the analysis, a layout structure diagram of the chip is drawn. The diagram should include various functional modules, components, connections, etc. of the chip to intuitively display the physical layout of the chip. According to the chip layout structure diagram, key nodes in the chip are identified. Key nodes are usually nodes that are crucial to the performance and function of the chip, such as control nodes, input / output nodes, etc. The key nodes can be determined according to the design specifications, circuit connection relationships and functional requirements, and the identified key nodes are marked on the chip layout structure diagram.

[0081] Step S2: performing infrared light focusing irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; and obtaining the dynamic stripe vibration distribution data based on the optical signal data of the nodes;

[0082] In this embodiment, an infrared light focusing irradiation device suitable for chip testing is obtained. This device usually includes a light source, a lens and a focusing mechanism, which is used to focus infrared light on the key nodes of the chip. The chip is placed on a test bench, and the infrared light focusing irradiation device is used to focus the infrared light on the key nodes of the chip to ensure that the light can accurately irradiate the target node, and the focusing mechanism is adjusted to obtain a clear optical image. Optical sensors or cameras and other devices are used to obtain node optical signal data after infrared light focusing irradiation processing. These data record the optical changes at the node and can be represented by parameters such as light intensity and color. Optical interference analysis is performed on the node optical signal data to obtain dynamic stripe vibration distribution data. The optical interference analysis can infer the vibration of the node by comparing the phase difference between different optical signals, the change of interference pattern, etc. According to the results of the optical interference analysis, dynamic stripe vibration distribution data is generated. These data describe the spatial distribution characteristics of the node vibration and can be used for subsequent frequency analysis and abnormal node identification.

[0083] Step S3: Calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify abnormal nodes of the vibration frequency peak value based on a preset frequency distribution curve, and mark abnormal component nodes;

[0084] In this embodiment, frequency analysis is performed on the dynamic stripe vibration distribution data to calculate the vibration frequency peak value. The frequency analysis can use Fourier transform or other spectrum analysis methods to extract the frequency components of the vibration signal. According to the chip design and expected performance characteristics, a frequency distribution curve is preset, which describes the distribution range of the vibration frequency of a normal node. The preset frequency distribution curve can be determined based on historical data, simulation analysis or empirical knowledge. The calculated vibration frequency peak value is compared with the preset frequency distribution curve. If the vibration frequency peak value falls in an area outside the preset curve, that is, exceeds the normal range, the node is marked as an abnormal component node. On the dynamic stripe vibration distribution data or the chip layout structure diagram, the identified abnormal component node is marked using symbols, colors or other marking methods, which facilitates subsequent fault analysis and processing.

[0085] Step S4: performing multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; performing dynamic voltage evolution mining processing on the transient characteristic data to obtain non-steady-state voltage rate distribution data;

[0086] In this embodiment, according to the characteristics and requirements of the abnormal component node, appropriate multi-frequency transient voltage excitation signals are selected. These signals can be pulses, square waves or other complex waveforms to simulate the voltage excitation conditions under actual working conditions. The selected multi-frequency transient voltage excitation signals are applied to the abnormal component nodes. This can be achieved by means of test equipment, power supplies or analog circuits, etc., to ensure that the amplitude, frequency and timing of the excitation signal meet the design requirements. Suitable measuring equipment is used to record the transient characteristic data of the abnormal component node under multi-frequency transient voltage excitation. These data may include non-steady-state electrical characteristics such as voltage waveforms, current waveforms, and power changes. Dynamic voltage evolution mining processing is performed on the transient characteristic data to obtain non-steady-state voltage rate distribution data. This can reveal the dynamic evolution law of voltage by analyzing parameters such as the rate of change of the voltage waveform and the rise / fall time. According to the results of the dynamic voltage evolution mining processing, non-steady-state voltage rate distribution data is obtained. These data describe the voltage change rate characteristics of the abnormal component node under multi-frequency transient voltage excitation, which is helpful to discover the situation of rapid voltage changes or abnormalities.

[0087] Step S5: performing electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; performing electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes;

[0088] In this embodiment, based on the non-steady-state voltage rate distribution data, an electromagnetic response analysis of adjacent nodes is performed, which can be achieved through electromagnetic field simulation software or electromagnetic field measurement equipment. The electromagnetic response of the adjacent nodes is analyzed, including electromagnetic radiation, electromagnetic induction, and electromagnetic coupling. According to the results of the electromagnetic response analysis of the adjacent nodes, electromagnetic response data of the adjacent nodes are generated. These data describe the electromagnetic response characteristics of the adjacent nodes under non-steady-state voltage excitation, including electromagnetic radiation intensity, induced voltage, coupling current, etc. Based on the electromagnetic response data of the adjacent nodes, an electromagnetic compatibility analysis of the abnormal component nodes is performed, which includes evaluating the impact of electromagnetic radiation, electromagnetic induction, and electromagnetic coupling caused by the abnormal nodes on the adjacent nodes. Electromagnetic compatibility analysis tools or methods can be used for analysis. According to the results of the electromagnetic compatibility analysis of the abnormal component nodes, electromagnetic compatibility data of the nodes are generated. These data describe the degree of impact of the abnormal component nodes on the electromagnetic compatibility of the adjacent nodes, which is helpful to evaluate the electromagnetic compatibility between nodes.

[0089] Step S6: construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; perform abnormal node fault prediction on the abnormal node feature map to construct a chip optimization decision strategy to perform chip testing operations.

[0090] In this embodiment, based on the integrated data, an abnormal node feature map is constructed, which can be achieved by combining the non-steady-state voltage rate distribution data with the node electromagnetic compatibility data. Each node in the map reflects the characteristics of the abnormal node and its electromagnetic compatibility impact on the adjacent nodes. The constructed abnormal node feature map is used to predict abnormal node faults. This can be achieved through machine learning, data mining or statistical analysis. According to the characteristics of the abnormal nodes and the electromagnetic compatibility data, a prediction model is established to predict the failure probability or occurrence time of the abnormal nodes. According to the results of the abnormal node fault prediction, a chip optimization decision strategy is formulated. According to the predicted abnormal node failure probability or occurrence time, it is determined whether it is necessary to perform optimization design, electromagnetic shielding, power supply interference suppression or other measures to improve the electromagnetic compatibility and reliability of the chip. According to the formulated chip optimization decision strategy, the corresponding chip testing operation is performed, which may include performing specific tests on the abnormal nodes, taking measures to improve their electromagnetic compatibility or verifying the effectiveness of the optimized design.

[0091] In this embodiment, refer to Figure 2 , is a flowchart of detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include:

[0092] Step S11: performing component identification on the chip to obtain chip component data;

[0093] Step S12: performing component distribution analysis on the chip component data to obtain component distribution position data;

[0094] Step S13: performing line connection path identification on the component distribution position data to obtain component connection line data;

[0095] Step S14: performing chip layout structure analysis based on the component connection line data to generate a chip layout structure diagram;

[0096] Step S15: Identify line cross-connection points based on the chip layout structure diagram to mark key nodes of the chip.

[0097] In this embodiment, the chip sample is imaged or scanned, and the image is analyzed and processed. By comparing with a known component library or a training model, each component on the chip is identified, and key information of the component, such as component type, number of pins, size, model, etc., is extracted from the component identification result. This information is organized into chip component data, and the obtained component position data is used to perform component distribution analysis, which includes determining the relative position between components, the arrangement of components, the logical area composed of components, etc. Key component distribution position data is extracted from the component distribution analysis results, which may include information such as absolute coordinates, relative coordinates, and area division of components to describe the layout distribution of components on the chip. The component distribution position data is analyzed and processed to identify the line connection path between components, which can be achieved by analyzing circuit topology, signal transmission rules, current paths, etc. The connection relationship between components and line path information are extracted from the connection path identification result, which may include a description of the connection relationship, the starting component and the ending component of the line, the direction of the line, The information such as line width is used to generate component connection line data, and the component connection line data is analyzed and processed to identify the layout structure of the chip. This can include the identification and analysis of component grouping, hierarchy, key connection points, etc. According to the layout structure analysis results, the layout structure diagram of the chip is generated. The layout structure diagram can be represented by a graphic to show the layout position, hierarchy, connection relationship and other information of the components to help further analysis and design decisions. Suitable line cross connection point identification technology is selected, such as graphic analysis, circuit topology analysis, network analysis, etc. According to the characteristics and requirements of the chip, a suitable method is selected to identify the line cross connection points. The chip layout structure diagram is analyzed and processed with the selected identification technology to identify the line cross connection points. This can be achieved by analyzing the line crossing situation, signal transmission rules, current paths, etc. According to the identification results of the line cross connection points, the key nodes in the chip are marked. The key nodes can be nodes with important functions or associated with multiple lines. Marking these nodes will help with subsequent design, optimization and troubleshooting.

[0098] In this embodiment, refer to Figure 3 , is a flowchart of detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include:

[0099] Step S21: performing infrared light focusing irradiation processing on key nodes of the chip to obtain optical signal data of the nodes;

[0100] Step S22: performing optical interference analysis on the node optical signal data to generate node optical fringe data;

[0101] Step S23: performing micro-optical vibration detection on the node optical fringe data to generate optical fringe offset data;

[0102] Step S24: performing optical flow tracking on the optical fringe offset data to generate dynamic fringe vibration distribution data.

[0103] In this embodiment, appropriate infrared light focusing equipment is configured, including an infrared light source, an optical lens, a focusing mechanism, etc., to ensure that the equipment can provide sufficient infrared light energy and can accurately focus on the key nodes of the chip, determine the node position that needs to be processed by light focusing, align the infrared light focusing system with the target node position, and perform light focusing irradiation processing to ensure that the light is fully focused on the node to obtain high-quality optical signal data, use appropriate optical sensors or detectors to collect infrared optical signals reflected or scattered from the node, these signals contain the optical characteristics and response information of the node, and pre-process the collected node optical signal data, including noise filtering, background correction, signal The optical fringe data of the node are extracted from the optical interference analysis results. These data describe the interference pattern and fringe distribution on the node surface. The tiny offset information of the optical fringe is extracted from the preprocessed optical fringe data. These offset data reflect the tiny optical vibration or deformation of the node. The extracted optical fringe offset data are further analyzed, which may include calculating the amplitude, frequency, phase and other parameters of the vibration to understand the vibration characteristics of the node. According to the analysis results, the optical fringe offset data are generated. These data can be presented in the form of images, data files or other forms for further processing and visualization.

[0104] In this embodiment, the specific steps of step S21 are:

[0105] Locating the key nodes of the chip, performing infrared light focusing irradiation treatment on the key nodes of the chip, and continuously acquiring image sequences;

[0106] Performing multi-frame photon tracing on the image sequence to extract an optical response feature sequence;

[0107] Performing time-frequency analysis on the optical response characteristic sequence to obtain optical fingerprint data of key nodes of the chip;

[0108] Node optical signal data is obtained based on the optical fingerprint data of the key nodes of the chip.

[0109] In this embodiment, an infrared light focusing system is configured, including an infrared light source, an optical lens, a focusing mechanism, etc., to ensure that the system can provide sufficient infrared light energy and can focus the light on the key nodes of the chip. The infrared light focusing system is aimed at the key nodes of the chip, and light focusing irradiation processing is performed to ensure that the light is focused on the nodes to obtain appropriate optical responses. An infrared camera is used to continuously acquire image sequences after light focusing irradiation. These image sequences will be used for subsequent multi-frame photon tracking. The pre-processed image sequences are processed, and the algorithm tracks the movement or changes of the optical features of the key nodes between consecutive frames. The optical response feature sequences are extracted from the results of the multi-frame photon tracing processing. These sequences describe the changes in the optical responses of the key nodes over time. A suitable time-frequency analysis algorithm is selected to perform optical response feature analysis on the optical response feature sequences. The common time-frequency analysis methods include short-time Fourier transform (STFT), wavelet transform, etc. The selected time-frequency analysis algorithm is used to process the optical response feature sequence. The algorithm can decompose the sequence in time and frequency to obtain the time-frequency characteristics of the signal. The optical fingerprint data of the key nodes of the chip are extracted from the results of the time-frequency analysis. The optical fingerprint data is a characteristic description of the optical signal of the node in the time-frequency domain, which can be used to uniquely identify and recognize the node. The optical fingerprint data is used as input to establish an appropriate model or representation. The model can be based on statistics, machine learning or other methods to describe the characteristics and properties of the node optical signal. The established model is used to generate the node optical signal data. These data are generated according to the analysis results of the optical fingerprint data and can be used for further analysis, testing or application.

[0110] In this embodiment, refer to Figure 4 , is a flowchart of detailed implementation steps of step S3. In this embodiment, the detailed implementation steps of step S3 include:

[0111] Step S31: performing frequency domain transfer processing on the dynamic fringe vibration distribution data to obtain optical fringe frequency component data;

[0112] Step S32: Calculating the vibration frequency peak value of the optical fringe frequency component data to generate a vibration frequency peak value;

[0113] Step S33: performing outlier vibration peak analysis on the vibration frequency peak based on a preset frequency distribution curve to obtain abnormal vibration frequency data;

[0114] Step S34: Identify abnormal nodes on the chip layout structure diagram based on the abnormal vibration frequency data and mark abnormal component nodes.

[0115] In this embodiment, a suitable sensor or device is used to obtain dynamic stripe vibration distribution data. This data can be a stripe image sequence obtained by an optical method, which reflects the vibration distribution on the chip. The dynamic stripe vibration distribution data is converted to the frequency domain. Common algorithms include Fourier transform or other frequency domain analysis methods. The dynamic stripe vibration distribution data is processed to obtain optical stripe frequency component data, which represents vibration components at different frequencies. The selected vibration frequency peak calculation algorithm is applied to process the optical stripe frequency component data to obtain a vibration frequency peak value, which represents a frequency value with significant vibration in the optical stripe. According to a preset standard or reference data, a preset frequency distribution curve is prepared, which describes the distribution range or mode of normal vibration frequency. The generated vibration frequency peak value is compared and analyzed with the preset frequency distribution curve, and a peak value that deviates greatly from the preset curve is identified and regarded as abnormal vibration frequency data. The abnormal vibration frequency data is matched with the elements in the chip layout structure diagram. According to the frequency information in the abnormal vibration frequency data, the corresponding element or node is found. Once the match is successful, the corresponding element or node is marked as an abnormal element node. Specific marks or symbols can be used on the chip layout structure diagram to represent the abnormal node.

[0116] In this embodiment, step S4 includes the following steps:

[0117] Step S41: performing multi-frequency transient voltage excitation on the abnormal component node to obtain multi-frequency transient excitation data;

[0118] Step S42: Capturing transient features of the multi-frequency transient excitation data to generate transient feature data;

[0119] Step S43: performing multi-frequency time-series voltage analysis on the transient characteristic data to generate time-series voltage data;

[0120] Step S44: performing multi-time-frequency decomposition on the time series voltage data to obtain non-steady-state voltage data;

[0121] Step S45: performing dynamic voltage evolution mining processing on the non-steady-state voltage data to obtain non-steady-state voltage rate distribution data.

[0122] In this embodiment, according to the design requirements and experimental conditions, transient voltage excitation signals of multiple frequencies are set. These excitation signals can be sine waves, square waves, etc., with different frequencies and amplitudes. The set multi-frequency transient voltage excitation signals are applied to the selected abnormal component nodes. A suitable voltage source or signal generator can be used to provide the excitation signal. The selected transient feature capture algorithm is applied to process the multi-frequency transient excitation data, which will extract transient feature data describing the excitation response characteristics, such as amplitude, rise time, fall time, etc. The selected multi-frequency time-series voltage analysis algorithm is applied to process the transient feature data, which will generate time-series voltage data describing the time-series voltage changes at different frequencies. The time-series voltage data is processed to obtain non-steady-state voltage data on different time-frequency scales, revealing the time-frequency characteristics of the voltage signal. The non-steady-state voltage data is processed to reveal the evolution process of the voltage signal, including the rate distribution and evolution trend of the voltage change.

[0123] In this embodiment, the specific steps of step S5 are:

[0124] Step S51: performing electromagnetic response analysis of adjacent nodes on abnormal component nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes;

[0125] Step S52: performing electromagnetic radiation interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic radiation interference data;

[0126] Step S53: performing electromagnetic conduction interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic conduction interference data;

[0127] Step S54: performing electromagnetic compatibility analysis of abnormal component nodes on the electromagnetic radiation interference data and the electromagnetic conduction interference data to generate node electromagnetic compatibility data.

[0128] In this embodiment, in the circuit layout structure diagram, nodes adjacent to the target abnormal component node are determined. These nodes are considered to be adjacent nodes that are potentially affected by the abnormal node. Electromagnetic response analysis is performed on the adjacent nodes, and the electromagnetic response data of the adjacent nodes is input into the selected algorithm using the finite element analysis method. The data is analyzed to evaluate the degree of electromagnetic radiation interference of the adjacent nodes to the surrounding environment, and data describing the degree of electromagnetic radiation interference is generated, such as radiation electric field strength, spectrum distribution, etc., and the degree of electromagnetic conduction interference of the adjacent nodes to the adjacent lines or devices is evaluated, and data describing the degree of electromagnetic conduction interference is generated, such as conduction current, conduction power, etc., and the electromagnetic compatibility of the abnormal component node is evaluated, including the degree of influence of the electromagnetic radiation interference and electromagnetic conduction interference on the surrounding environment, and data describing the electromagnetic compatibility of the node is generated, such as compatibility index, sensitivity analysis, etc.

[0129] In this embodiment, the specific steps of step S6 are:

[0130] Step S61: performing node data learning through non-steady-state voltage rate distribution data and node electromagnetic compatibility data to generate an abnormal node sample database;

[0131] Step S62: performing situation evolution analysis on the abnormal node sample database to generate an abnormal node feature map;

[0132] Step S63: performing abnormal node fault prediction on the abnormal node feature map to generate abnormal node fault prediction data;

[0133] Step S64: Perform fault optimization decision analysis on abnormal node fault prediction data to construct a chip optimization decision strategy to execute chip testing operations.

[0134] In this embodiment, the data of each node in the non-steady-state period is statistically analyzed, and the characteristic parameters of its rate change, such as fluctuation amplitude and change rate, are extracted. The multi-dimensional characteristic parameters of each node are combined into a sample example, and it is marked whether the node is abnormal. A large number of samples are collected to build an abnormal node sample database covering various load scenarios. A machine learning classifier is trained on the sample database to identify different types of abnormal characteristic parameter combination patterns. For each abnormal pattern, the descriptiveness and influence of its main characteristic parameters on the abnormality are extracted. With nodes as nodes and the correlation between characteristic parameters as edges, a characteristic network topology diagram of each abnormal pattern is constructed, and different pattern maps are analyzed. The similarities and differences of abnormal nodes are extracted, and the evolution feature maps of abnormal nodes in different stages are extracted. A large number of training samples are collected to train the prediction model to learn the feature rules. The non-steady-state period features collected in real time by the new input node are predicted to determine whether it will fail. Nodes with higher prediction values ​​are selected to form a target node set to constitute an abnormal node failure prediction report. Based on the prediction results, multimodal simulation is performed to analyze the possible failure modes and impact ranges, and the impact of different optimization countermeasures such as resetting the layout on cost and failure risk is evaluated. The optimization decision plan with the lowest risk and the best cost is selected according to priority, and the optimization effect is simulated on the digital version of the chip to confirm the decision execution strategy.

[0135] In this embodiment, a chip testing device is provided, which is used to perform the above-mentioned base chip testing method, including:

[0136] The layout structure module is used to analyze the chip layout structure to generate a chip layout structure diagram; and mark the key nodes of the chip based on the chip layout structure diagram;

[0137] The optical interference module is used to perform infrared light focusing and irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; based on the optical signal data of the nodes, the dynamic stripe vibration distribution data is obtained;

[0138] The abnormal node module is used to calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify the abnormal node of the vibration frequency peak value based on the preset frequency distribution curve, and mark the abnormal component node;

[0139] The transient voltage module is used to perform multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; the transient characteristic data is subjected to dynamic voltage evolution mining to obtain non-steady-state voltage rate distribution data;

[0140] The electromagnetic compatibility module is used to perform electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; perform electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes;

[0141] The chip optimization module is used to construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; to predict abnormal node faults on the abnormal node feature map to build a chip optimization decision strategy to perform chip testing operations.

[0142] The present invention can generate a chip layout structure diagram by analyzing the layout structure of the chip through the layout structure module. The diagram provides the relative positions and connection relationships of the chip components, providing a basis for subsequent analysis and testing. The optical interference module can obtain node optical signal data by performing infrared light focusing irradiation processing on the key nodes of the chip. These data can be used for optical interference analysis to generate dynamic stripe vibration distribution data. These data reflect the vibration state and dynamic behavior of the node. The abnormal node module can generate a vibration frequency peak by calculating the vibration frequency peak of the dynamic stripe vibration distribution data. Based on the preset frequency distribution curve, the vibration frequency peak can be used to identify abnormal nodes and mark abnormal component nodes, which helps to quickly detect and locate abnormal nodes in the chip. The transient voltage module generates transient feature data after performing multi-frequency transient voltage excitation on the abnormal component nodes. These data can be used for dynamic voltage evolution mining and processing. In order to obtain the non-steady-state voltage rate distribution data, the non-steady-state voltage rate distribution data provides the dynamic characteristics of the node voltage change, which helps to understand the transient behavior and voltage response of the node. The electromagnetic compatibility module performs electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data, generates electromagnetic response data of adjacent nodes, and uses the electromagnetic response data of adjacent nodes to perform electromagnetic compatibility analysis of abnormal component nodes and generate node electromagnetic compatibility data. These data provide the response characteristics of the node in the electromagnetic environment and help evaluate the electromagnetic compatibility of the node. The chip optimization module constructs an abnormal node feature map through the non-steady-state voltage rate distribution data and the node electromagnetic compatibility data, and predicts abnormal node failures on the abnormal node feature map to construct chip optimization decision strategies. These strategies may include optimization measures for abnormal nodes, test methods or improvements to the manufacturing process. By implementing these strategies, the reliability and performance of the chip can be improved and the risk of failure can be reduced.

[0143] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0144] The above is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A chip testing method, characterized in that: The following steps are involved: Step S1: performing chip layout structure analysis on the chip to generate a chip layout structure diagram; marking key nodes of the chip based on the chip layout structure diagram; The specific steps of step S1 are: Step S11: performing component identification on the chip to obtain chip component data; Step S12: performing component distribution analysis on the chip component data to obtain component distribution position data; Step S13: performing line connection path identification on the component distribution position data to obtain component connection line data; Step S14: performing chip layout structure analysis based on the component connection line data to generate a chip layout structure diagram; Step S15: Identify the circuit cross-connection points based on the chip layout structure diagram to mark the key nodes of the chip; the key nodes of the chip are specifically: nodes with important functions or associated with multiple circuits; Step S2: performing infrared light focusing irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; and obtaining the dynamic stripe vibration distribution data based on the optical signal data of the nodes; Step S3: Calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify abnormal nodes of the vibration frequency peak value based on a preset frequency distribution curve, and mark abnormal component nodes; The specific steps of step S3 are: Step S31: performing frequency domain transfer processing on the dynamic fringe vibration distribution data to obtain optical fringe frequency component data; Step S32: Calculating the vibration frequency peak value of the optical fringe frequency component data to generate a vibration frequency peak value; Step S33: performing outlier vibration peak analysis on the vibration frequency peak based on a preset frequency distribution curve to obtain abnormal vibration frequency data; wherein the preset frequency distribution curve specifically describes the distribution range or pattern of normal vibration frequency; Step S34: identifying abnormal nodes on the chip layout structure diagram based on the abnormal vibration frequency data, and marking abnormal component nodes; Step S4: performing multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; performing dynamic voltage evolution mining processing on the transient characteristic data to obtain non-steady-state voltage rate distribution data; The specific steps of step S4 are: Step S41: performing multi-frequency transient voltage excitation on the abnormal component node to obtain multi-frequency transient excitation data; Step S42: Capturing transient features of the multi-frequency transient excitation data to generate transient feature data; Step S43: performing multi-frequency time-series voltage analysis on the transient characteristic data to generate time-series voltage data; Step S44: performing multi-time-frequency decomposition on the time series voltage data to obtain non-steady-state voltage data; Step S45: performing dynamic voltage evolution mining processing on the non-steady-state voltage data to obtain non-steady-state voltage rate distribution data; Step S5: performing electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; performing electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes; Step S6: construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; perform abnormal node fault prediction on the abnormal node feature map to construct a chip optimization decision strategy to perform chip testing operations.

2. The chip testing method according to claim 1, characterized in that: The specific steps of step S2 are: Step S21: performing infrared light focusing irradiation processing on key nodes of the chip to obtain optical signal data of the nodes; Step S22: performing optical interference analysis on the node optical signal data to generate node optical fringe data; Step S23: performing micro-optical vibration detection on the node optical fringe data to generate optical fringe offset data; Step S24: performing optical flow tracking on the optical fringe offset data to generate dynamic fringe vibration distribution data.

3. The chip testing method according to claim 2, characterized in that: The specific steps of step S21 are: Locating the key nodes of the chip, performing infrared light focusing irradiation treatment on the key nodes of the chip, and continuously acquiring image sequences; Performing multi-frame photon tracing on the image sequence to extract an optical response feature sequence; Performing time-frequency analysis on the optical response characteristic sequence to obtain optical fingerprint data of key nodes of the chip; Node optical signal data is obtained based on the optical fingerprint data of the key nodes of the chip.

4. The chip testing method according to claim 1, characterized in that: The specific steps of step S5 are: Step S51: performing electromagnetic response analysis of adjacent nodes on abnormal component nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; Step S52: performing electromagnetic radiation interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic radiation interference data; Step S53: performing electromagnetic conduction interference analysis on the electromagnetic response data of the adjacent nodes to generate electromagnetic conduction interference data; Step S54: performing electromagnetic compatibility analysis of abnormal component nodes on the electromagnetic radiation interference data and the electromagnetic conduction interference data to generate node electromagnetic compatibility data.

5. The chip testing method according to claim 1, characterized in that: The specific steps of step S6 are: Step S61: performing node data learning through non-steady-state voltage rate distribution data and node electromagnetic compatibility data to generate an abnormal node sample database; Step S62: performing situation evolution analysis on the abnormal node sample database to generate an abnormal node feature map; Step S63: performing abnormal node fault prediction on the abnormal node feature map to generate abnormal node fault prediction data; Step S64: Perform fault optimization decision analysis on abnormal node fault prediction data to construct a chip optimization decision strategy to execute chip testing operations.

6. A chip testing device, characterized in that: Used to perform the chip testing method as claimed in claim 1, comprising: The layout structure module is used to analyze the chip layout structure to generate a chip layout structure diagram; and mark the key nodes of the chip based on the chip layout structure diagram; The optical interference module is used to perform infrared light focusing and irradiation processing on the key nodes of the chip to obtain the optical signal data of the nodes; based on the optical signal data of the nodes, the dynamic stripe vibration distribution data is obtained; The abnormal node module is used to calculate the vibration frequency peak value of the dynamic stripe vibration distribution data to generate the vibration frequency peak value; identify the abnormal node of the vibration frequency peak value based on the preset frequency distribution curve, and mark the abnormal component node; The transient voltage module is used to perform multi-frequency transient voltage excitation on abnormal component nodes to generate transient characteristic data; the transient characteristic data is subjected to dynamic voltage evolution mining to obtain non-steady-state voltage rate distribution data; The electromagnetic compatibility module is used to perform electromagnetic response analysis of adjacent nodes based on the non-steady-state voltage rate distribution data to generate electromagnetic response data of adjacent nodes; perform electromagnetic compatibility analysis of abnormal component nodes based on the electromagnetic response data of adjacent nodes to generate electromagnetic compatibility data of nodes; The chip optimization module is used to construct an abnormal node feature map through non-steady-state voltage rate distribution data and node electromagnetic compatibility data; to predict abnormal node faults on the abnormal node feature map to build a chip optimization decision strategy to perform chip testing operations.

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