Chip-scale packaged semiconductor devices and their manufacturing methods

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. In particular, this disclosure relates to a chip-scale packaged semiconductor device comprising: a semiconductor wafer having a first main surface and an opposing second main surface, the semiconductor wafer including at least two terminals disposed on the second main surface; a carrier including the first main surface and an opposing second main surface, wherein the first main surface of the semiconductor wafer is mounted on the opposing second main surface of the carrier; and a molding material partially encapsulating the semiconductor wafer and the carrier, wherein the first main surface of the carrier extends and is exposed through the molding material, and the at least two terminals are exposed through the molding material on a second side of the device.

Description

[0001] This application is a divisional application of patent application No. 2017113834698, filed on December 20, 2017, entitled "Chip-level packaged semiconductor device and manufacturing method thereof". Technical Field

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same. In particular, this disclosure relates to a chip-scale packaged semiconductor device and a related manufacturing method. Background Technology

[0003] Chip-scale packaged (CSP) semiconductor devices are becoming increasingly important for applications requiring small footprints. CSPs are commonly used in mobile communication devices, such as mobile phones and portable electronic devices. When CSPs include power semiconductor devices such as transistors or diodes, they require high-performance thermal capacity and heat dissipation because they need to drain large currents to ground or other rails to protect connected devices from damage. On the other hand, power devices face the challenge of increasing structural compactness, requiring both a very small footprint and package height, and protection through packaging materials. Packaging materials are necessary to protect devices from environmental factors such as moisture. Furthermore, packaging materials prevent the solder paste used to mount the device onto a printed circuit board from contacting the body of the semiconductor die and potentially causing a short circuit. This setup typically has molding material on all six sides of the device and is referred to as a six-sided protected CSP device.

[0004] Figure 1 This is a cross-sectional view of a conventional six-sided protected CSP device 100. The semiconductor device 100 has a top main surface 102 and an opposing bottom main surface 104. On the bottom main surface 104, the CSP semiconductor device 100 includes a plurality of contacts 106, 108. The contacts 106, 108 are electrically connected to the bottom surface of the semiconductor wafer 110 and to a connection such as a printed circuit board (PCB).

[0005] External circuit components (not shown). Contacts 106 and 108 are formed on the surface of semiconductor wafer 110.

[0006] The semiconductor device 100 is encapsulated in a molding material 116 using any suitable molding compound, such as an epoxy-based material. The molding material 116 is arranged to cover all six sides of the semiconductor wafer 110 except for the contacts 106, 108.

[0007] Compared to conventional CSP semiconductor devices without molding compounds, conventional six-sided protected CSP devices are plagued by the problem of how to dissipate the heat generated in the semiconductor wafer during operation. This is of particular concern when the semiconductor chip is a power device. Summary of the Invention

[0008] According to an embodiment, a chip-scale packaged semiconductor device is provided, comprising: a semiconductor wafer having a first main surface and an opposing second main surface, the semiconductor wafer including at least two terminals disposed on the second main surface; a carrier including the first main surface and the opposing second main surface, wherein the first main surface of the semiconductor wafer is mounted on the opposing second main surface of the carrier; and a molding material that partially encapsulates the semiconductor wafer and the carrier, wherein the first main surface of the carrier extends and is exposed through the molding material, and the at least two terminals are exposed through the molding material on a second side of the device.

[0009] The carrier may extend on the opposite sidewalls of the device and be exposed through the molding material.

[0010] The first main surface of the carrier may be coplanar with the molding material on the top main surface of the device.

[0011] The opposing second primary surface of the carrier may be arranged as a recess in the carrier. The recess may be arranged to mountably receive the semiconductor wafer. The recess may be arranged to receive an adhesive layer for mounting the semiconductor wafer to the carrier.

[0012] The top main surface of the packaged semiconductor device may include the carrier, and the second opposing main surface of the packaged semiconductor device may include the terminal and the molding material.

[0013] According to an embodiment, a method for manufacturing a chip-scale packaged semiconductor device is provided, the method comprising: providing a semiconductor wafer having a first main surface and an opposing second main surface, the semiconductor wafer including at least two terminals disposed on the second main surface; providing a carrier including the first main surface and the opposing second main surface; mounting the first main surface of the semiconductor wafer onto the opposing second main surface of the carrier; and partially encapsulating the semiconductor wafer and the carrier in a molding material, wherein the first main surface of the carrier extends and is exposed through the molding material, and the at least two terminals are exposed through the molding material on a second side of the device.

[0014] The semiconductor wafer and the carrier can be encapsulated such that the first main surface of the carrier is coplanar with the molding material on the top main surface of the device.

[0015] The first main surface of the semiconductor wafer can be mounted in a recess on the opposite second main surface of the carrier.

[0016] The CSP semiconductor device according to the embodiments provides improved heat dissipation and structural integrity without increasing the overall package height. The CSP device according to the embodiments is therefore suitable for high-power transistor devices. Attached Figure Description

[0017] To provide a detailed understanding of the features of this disclosure, a more specific description is given with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be considered as limiting the scope thereof. These drawings are intended to aid in understanding this disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings, wherein the same reference numerals are used to denote the same elements, and wherein:

[0018] Figure 1 It is a cross-sectional view of a known chip-scale packaged semiconductor device;

[0019] Figure 2a This is a cross-sectional view of a chip-scale packaged semiconductor device according to an embodiment;

[0020] Figure 2b This is a side view of a chip-scale packaged semiconductor device according to an embodiment;

[0021] Figure 2c This is a schematic diagram of a chip-scale packaged semiconductor device according to an embodiment;

[0022] Figure 2d This is a top view of a chip-scale packaged semiconductor device according to an embodiment;

[0023] Figure 3a This is a side view of a semiconductor device comprising multiple semiconductor wafers according to an embodiment;

[0024] Figure 3b This is a side view of a chip-scale packaged semiconductor device according to an embodiment;

[0025] Figure 4a The steps of arranging a frame on a carrier belt according to an embodiment are illustrated;

[0026] Figure 4b A framework of a carrier matrix arranged as repeating according to an embodiment is shown;

[0027] Figure 4c The steps of arranging a semiconductor wafer on a carrier according to an embodiment are shown;

[0028] Figure 4d The steps of attaching a package to a carrier semiconductor wafer according to an embodiment are illustrated;

[0029] Figure 4e The steps for removing the package after encapsulation according to an embodiment are shown;

[0030] Figure 4f The steps of deburring after removing the tape according to the embodiment are shown;

[0031] Figure 4g The steps for product marking according to an embodiment are shown;

[0032] Figure 4h An example product label on a carrier according to an embodiment is shown;

[0033] Figure 5a An overmolding process for encapsulating a CSP according to an embodiment is shown; and

[0034] Figure 5b The grinding process following overmolding according to an embodiment is shown. Detailed Implementation

[0035] Figure 2a This is a cross-sectional view of a six-sided protected chip-scale package (CSP) semiconductor device 200 according to an embodiment. The CSP semiconductor device 200 has a top main surface 202 and an opposing bottom main surface 204. On the bottom main surface 204, the CSP semiconductor device 200 includes a plurality of terminals or contacts 206, 208. The terminals 206, 208 are electrically connected to the bottom surface of the semiconductor wafer 210 of the CSP semiconductor device 200 and to external circuit components such as a printed circuit board (PCB) (not shown). The contacts 206, 208 are formed on the surface of the semiconductor wafer 210.

[0036] The top main surface 202 of the CSP semiconductor device 200 includes a metal (or plastic) carrier 212 for supporting the semiconductor wafer 210. The carrier 212 is fixedly mounted to the top surface of the semiconductor wafer 210 by any suitable means (e.g., an epoxy resin-based adhesive 214).

[0037] Although Figure 2a Two contacts 206, 208 formed on the bottom surface of semiconductor wafer 210 are shown; however, those skilled in the art will recognize that any number of contacts can be provided depending on the type and function of semiconductor wafer 210. For example, in the case of a field-effect transistor, the number of contacts can be three, with each contact connected to a corresponding source terminal, gate terminal, and drain terminal of semiconductor wafer 210. Alternatively, semiconductor wafer 210 can also be a bipolar junction transistor, thyristor, or two-terminal diode. Furthermore, a passivation layer 217 may be included on the surface of semiconductor wafer 210 having contacts 206, 208.

[0038] The CSP semiconductor device 200 is encapsulated in a molding material 216 using any suitable molding compound, such as an epoxy resin-based material. This molding material substantially covers the four secondary sides of the CSP semiconductor device 200. The molding material 216 can also be formed to cover the bottom main surface of the device 200, excluding contacts 206, 208. The molding material 216 can be disposed on the top main surface 202 of the device 200, thereby exposing the top surface of the carrier 212.

[0039] The carrier 212 may also include one or more metal tabs 218 extending from each side of the carrier 212 to protrude through the molding material 216, thereby exposing the opposite sides of the CSP semiconductor device 200. The tabs 218 are the product of the singulation process of the CSP semiconductor device 200, which will be discussed in more detail below.

[0040] Figure 2b The image shows a side view of a CSP semiconductor device 200, which shows a tab 218 protruding through the molding material 216 on the side of the device 200. Figure 2b One side of the device 200 is shown, and those skilled in the art will recognize that, due to the matrix arrangement of the carriers as described below, the corresponding opposite sides will have the same arrangement of tabs 218 protruding through the molding material 216.

[0041] Figure 2c A bottom view of the CSP semiconductor device 200 is shown, and contacts 206, 208 and molding material 216 arranged on the bottom surface 204 of the device 200 are shown. Figure 2d A top view of the CSP semiconductor device 200 is shown, and a carrier 212 protrudes through the molding material 216, exposing the carrier on the top surface 202 of the device 200. Optional chamfers 222 may be arranged on the carrier 212, which can be used to indicate contact polarity and assist in device orientation when the device is placed on a PCB.

[0042] The arrangement of the carrier 212 protruding through the top surface 202 of the device 200 and also through the opposing sidewalls provides improved thermal characteristics for the device 200. Since the carrier, acting as a heat sink, is exposed rather than covered by molding material, any heat generated in the wafer during device operation can be effectively dissipated from the semiconductor wafer 210. This can be particularly advantageous when the device is a high-power device.

[0043] Furthermore, as discussed in more detail below regarding the manufacturing method, the arrangement of the carrier 212 in device 200 is configured not to increase the overall package height of device 200 compared to conventional devices.

[0044] Furthermore, the carrier 212 also provides mechanical strength to the device 200 by supporting the semiconductor wafer 210. This is particularly advantageous when the device 200 is used in harsh environmental conditions (e.g., in automotive applications).

[0045] Figure 3a An embodiment of a multi-wafer CSP semiconductor device 300 is shown, wherein a plurality of semiconductor wafers 310a, 310b are arranged in the CSP semiconductor device 300. As in previous embodiments, the wafers are secured to a carrier 312 using, for example, an epoxy-based adhesive. A molding material 316 is arranged to separate the plurality of wafers 310a, 310b. This arrangement can be advantageous when the semiconductor wafers 310a, 310b are arranged in, for example, a cascode or half-bridge configuration.

[0046] Figure 3b One embodiment is shown, wherein the carrier 312 includes a recess for accommodating the upper portion of the adhesive 314 and / or the semiconductor wafer 310. Figure 3b In one embodiment, the recess of the carrier 312 is sized to receive the semiconductor wafer 310 and adhesive 314 disposed thereon. Alternatively, the recess 324 of the carrier 312 may be sized to receive the adhesive 314 disposed on the semiconductor wafer 310. Figure 3b This arrangement can help reduce the overall package height of device 300. Furthermore, by housing the adhesive 314 within the recess 324 of the carrier 312, adhesive leakage can be prevented. Those skilled in the art will also understand that... Figure 3b The embodiments are also applicable to, for example, Figure 3a The arrangement of multiple wafers.

[0047] Now, referring to the example processing steps shown... Figures 4a to 4h This describes an example processing flow for manufacturing a semiconductor device according to the above embodiments.

[0048] Reference Figure 4a A metal frame 411 is arranged on a carrier belt 413. The carrier belt 413 prevents the molding material from covering the carrier during the molding process and ensures (as described above) Figure 2a and Figure 2d The carrier 412 (under discussion) is exposed and protrudes through the top surface 402 of the device 400. The metal frame comprises a matrix of repeating carriers 412, wherein adjacent carriers are interconnected by connecting members 418 or tie rods. The carrier matrix interconnected by the connecting members 418 can be a linear matrix. Alternatively, and as... Figure 4b As shown in the plan view, the carrier matrix can be an n×m matrix, where n is the number of rows in the matrix and m is the number of columns in the matrix, where both n and m are positive integers, and adjacent carriers 412 are connected by connecting members 418. Figure 4b The example shows a connecting member 418 that connects adjacent carriers in any row or column. However, with Figure 2b As with the example, those skilled in the art will understand that the number of connecting members 418 on any side of the device can be greater than one.

[0049] like Figure 4c As shown, the semiconductor wafer 410 is then attached to its respective carrier 412 using a wafer attachment material 414 (e.g., an epoxy-based adhesive as previously mentioned, or any suitable solder or adhesive). In some applications, the wafer attachment material may be conductive to enable electrical connections from the carrier 412 to the semiconductor wafer 410. It should be noted that the semiconductor wafer 410 is attached to the carrier 412 from top to bottom. In other words, the top main surface of the semiconductor wafer 410 (i.e., the main surface opposite the surface having contacts 406, 408) is secured to the respective carrier using adhesive 414. The adhesive can then be fixed or cured by thermosetting.

[0050] After the attachment process of the semiconductor wafer 410 discussed above, the arrangement in which the semiconductor wafer is attached to the carrier is packaged. Figure 4d An encapsulation process known as film-assisted molding (FAM) is illustrated, in which a protective film 417 is applied to an attached or fixed wafer matrix. The matrix is ​​then loaded into a molding machine, where liquefied molding material is forced into a closed mold cavity formed by the protective film 417 and a carrier tape 413. The molding material is then solidified by curing.

[0051] When the molded matrix is ​​removed from the molding machine, the protective film 417 is also removed. After the molding process, the matrix can also undergo a process called post-molding curing to further solidify and solidify the liquefied molding material.

[0052] After molding and curing, such as Figure 4e As shown, the carrier tape is removed from the molding matrix through a process called de-taping. After de-taping, as... Figure 4f As shown, any excess molding material present on the contacts or exposed sides of the carrier is removed through a process called deburring. Once deburring is complete, as... Figure 4g As shown, device details (e.g., product type) can be marked on the exposed side of the carrier using, for example, a laser. Product markings on the carrier include, for example,... Figure 4h As shown.

[0053] As an alternative to the aforementioned FAM processing, the following can be used: Figure 5a and Figure 5bThe molding is achieved using an over-molding process. In this over-molding process, molding material 516 is arranged to completely cover the semiconductor wafer 510, including the contacts disposed thereon. After the molding material 516 has cured, a polishing process is used to remove the molding material until the contacts are exposed.

[0054] After marking, the individual CSP semiconductor devices 400 are separated from the matrix arrangement by slitting. Slitting is performed along the sidewalls of the semiconductor devices 400. To separate the devices 400, the slitting process can be any suitable cutting process, such as laser cutting, plasma cutting, sawing, or any combination thereof. The slitting step severs the connecting members 418 and molding material 416 of adjacent devices 400. This results in the situation described above regarding... Figure 2a The tab 218 under discussion extends through the molding material 416 at the sidewall of the device 400.

[0055] After separation, the devices can be electrically tested to ensure they were not damaged during the packaging process. Following testing, the devices can be placed on carrier tapes and loaded onto reels for transport.

[0056] The CSP semiconductor device according to the embodiments provides improved heat dissipation and structural integrity without increasing the overall package height. The CSP device according to the embodiments is therefore suitable for high-power transistor devices.

[0057] Specific and preferred aspects of the invention are set forth in the appended independent claims. Combinations of features from dependent and / or independent claims may be suitably combined, not only as set forth in the claims.

[0058] The scope of this disclosure includes any novel feature or combination of features explicitly or implicitly disclosed herein, or any generalization thereof, whether or not it relates to the claimed invention or alleviates any or all the problems solved by this invention. The applicant hereby notifies that new claims may be made for these features during the period of this application or any such further application derived therefrom. In particular, referring to the appended claims, features from dependent claims may be combined with features from independent claims, and features from individual independent claims may be combined in any suitable manner, not just the specific combinations listed in the claims.

[0059] Features described in the context of different embodiments may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for the sake of brevity may also be provided individually or in any suitable sub-combination.

[0060] The term "comprising" does not exclude other elements or steps, and the terms "a" or "an" do not exclude multiple. Reference numerals in the claims should not be construed as limiting the scope of the claims.

Claims

1. A chip-scale packaged semiconductor device, comprising: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die including a plurality of terminals, the plurality of terminals including a source and a drain, the source and the drain being directly disposed on the second major surface and on opposite sides of the semiconductor die to electrically connect the second major surface of the semiconductor die to external circuit components; a carrier including a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier, wherein the carrier does not form an electrode, wherein the opposing second major surface of the carrier is disposed as a recess in the carrier; and a molding material partially encapsulating the semiconductor die and the carrier of the chip-scale packaged semiconductor device, wherein the first major surface of the carrier extends on a first side of the chip-scale packaged semiconductor device and is exposed through the molding material, and the plurality of terminals are exposed on a second side of the chip-scale packaged semiconductor device through the molding material; the recess is disposed to mountably receive an upper portion of the semiconductor die, and an adhesive layer for mounting the semiconductor die to the carrier; the molding material includes an upper portion and a lower portion, the upper portion is disposed to surround a first portion of a sidewall of the carrier and is flush with the first major surface of the carrier, and the lower portion is disposed to surround a second portion of the sidewall of the carrier, the second portion surrounding an upper portion of the semiconductor die and the adhesive layer, the carrier includes a third portion between the first portion and the second portion, the third portion extending on opposite sidewalls of the chip-scale packaged semiconductor device and being exposed through the molding material.

2. The chip-scale packaged semiconductor device of claim 1, wherein the first major surface of the carrier is coplanar with the molding material on a top major surface of the chip-scale packaged semiconductor device.

3. The chip-scale packaged semiconductor device of claim 1, further comprising a top major surface and a second opposing major surface of the chip-scale packaged semiconductor device, wherein the top major surface includes the carrier, and wherein the second opposing major surface includes the plurality of terminals and the molding material.

4. The chip-scale packaged semiconductor device of claim 1, wherein the plurality of terminals extend orthogonally from the second major surface through the molding material such that the plurality of terminals are exposed on a second side of the chip-scale packaged semiconductor device.

5. A method of manufacturing a chip-scale packaged semiconductor device, the method comprising: providing a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die including a plurality of terminals, the plurality of terminals including a source and a drain, the source and the drain being directly disposed on the second major surface and on opposite sides of the semiconductor die and configured to electrically connect the second major surface of the semiconductor die to external circuit components; A carrier is provided that includes a first major surface and an opposing second major surface, wherein the carrier does not form an electrode, wherein the opposing second major surface of the carrier is arranged as a recess in the carrier; mounting the first major surface of the semiconductor die onto the opposing second major surface of the carrier; partially encapsulating the semiconductor die and the carrier of the chip-scale packaged semiconductor device in a molding material, wherein the first major surface of the carrier extends on a first side of the chip-scale packaged semiconductor device and is exposed through the molding material, and the plurality of terminals are exposed on a second side of the chip-scale packaged semiconductor device through the molding material to form a lateral chip-scale packaged semiconductor device; the recess is arranged to mountably receive an upper portion of the semiconductor die, and an adhesive layer for mounting the semiconductor die to the carrier; the molding material includes an upper portion and a lower portion, the upper portion is arranged to surround a first portion of a sidewall of the carrier and is flush with the first major surface of the carrier, and the lower portion is arranged to surround a second portion of the sidewall of the carrier, the second portion surrounds an upper portion of the semiconductor die and the adhesive layer, the carrier includes a third portion between the first portion and the second portion, the third portion extends on opposing sidewalls of the chip-scale packaged semiconductor device and is exposed through the molding material.

6. The method of claim 5, wherein the semiconductor die and the carrier are encapsulated such that the first major surface of the carrier is coplanar with the molding material on a top major surface of the chip-scale packaged semiconductor device.

7. The method of claim 5, wherein the plurality of terminals extend orthogonally from the second major surface through the molding material such that the plurality of terminals are exposed on a second side of the chip-scale packaged semiconductor device.

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