A multi-level circuit, printed circuit board and converter

Abstract

The application provides a multi-level circuit, a printed circuit board and a converter. The multi-level circuit comprises a plurality of bus capacitors and a plurality of switching devices, and the plurality of switching devices are connected in a multi-level topology. The multi-level circuit further comprises at least one film capacitor, the film capacitor is connected in parallel with the bus capacitors, and the film capacitor is connected between two switching devices. The volume of the film capacitor is smaller than that of the bus capacitors. The multi-level circuit has a plurality of selectively conducting current loops. The film capacitor is used to shorten the commutation path of the switching process from one current loop to another current loop, reduce the path stray inductance in the commutation process, and then reduce the inverse peak and improve the service life of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a multi-level circuit, a printed circuit board and a converter. BACKGROUND

[0002] A power converter refers to a kind of conversion device for converting one form of electric energy into another form of electric energy through the on and off actions of semiconductor power switching devices, and more specifically includes rectifiers, inverters and the like. Due to the advantages of multi-storey circuit such as small voltage stress of switching devices and low output voltage harmonic content, it is often used as a rectifier or inverter. In the working process, if the multi-level conversion circuit reaches the current limiting point, the switching of the current loop will occur, and a large reverse peak may occur in this process, which damages the switching devices in the multi-level conversion circuit, and is an urgent problem to be solved. SUMMARY

[0003] The present application provides a multi-level circuit, a printed circuit board and a converter.

[0004] The technical solution of the present application is implemented as follows:

[0005] In a first aspect, the embodiments of the present application provide a multi-level circuit, which comprises a plurality of bus capacitors and a plurality of switching devices, and the plurality of switching devices are connected in a multi-level topology; the multi-level circuit further comprises at least one film capacitor, the film capacitor is connected in parallel with the bus capacitor, and the film capacitor is connected between two of the switching devices, and the volume of the film capacitor is smaller than that of the bus capacitor; the multi-level circuit has a plurality of selectively conductive current loops, and the film capacitor is used to shorten the commutation path of the switching process from one current loop to another current loop.

[0006] In this way, by introducing the film capacitor, the commutation path in the commutation process can be shortened, so as to reduce the path stray inductance, and further reduce the reverse peak and improve the device life.

[0007] In some embodiments, the output of the multi-level circuit includes a first level, a middle level and a second level; after the multi-level circuit triggers a current limiting point, at least one main switch device is turned off, the multi-level circuit is switched from a current loop to a middle freewheeling loop, and at least one freewheeling switch device is turned off, the multi-level circuit is switched from the middle freewheeling loop to a reverse freewheeling loop through the thin film capacitor; wherein the switch device on the middle level channel is the freewheeling switch device, the switch device on the first level channel or the second level channel is the main switch device, when the current loop is the first level channel, the reverse freewheeling loop is a freewheeling loop through the second level channel, and when the current loop is the second level channel, the reverse freewheeling loop is a freewheeling loop through the first level channel.

[0008] In this way, during the process of switching the multi-level circuit from the middle freewheeling loop to the reverse freewheeling loop, part of the switch devices are in the limit voltage withstand state, but the thin film capacitor introduced can provide an additional path to switch the middle freewheeling loop to the reverse freewheeling loop, thereby reducing the reverse peak in the limit voltage withstand state, reducing the pressure on the switch device, and improving the service life of the device.

[0009] In some embodiments, the multi-level topology is a T-type three-level topology; the plurality of switch devices includes a first switch device, a second switch device, a third switch device and a fourth switch device, and the bus capacitor includes a first bus capacitor and a second bus capacitor; the first switch device and the fourth switch device are connected in series to form a vertical pipe bridge arm, the second switch device and the third switch device are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, wherein the common point of the first switch device and the fourth switch device is the output point, the common point of the first bus capacitor and the second bus capacitor is the neutral point, the two free ends of the vertical pipe bridge arm are connected in parallel to the two free ends of the capacitor bridge arm, the first end of the horizontal pipe bridge arm is connected to the neutral point, and the second end is connected to the output point; the thin film capacitor is connected across the free end of the vertical pipe bridge arm and the first end of the horizontal pipe bridge arm; the first switch device and the fourth switch device are the main switch devices, and the second switch device and the third switch device are the freewheeling switch devices; the first level channel refers to the channel from the free end of the first bus capacitor to the output point through the first switch device, the second level channel refers to the channel from the free end of the second bus capacitor to the output point through the fourth switch device, and the middle level channel refers to the channel from the neutral point to the output point through the horizontal pipe bridge arm.

[0010] In some embodiments, the multi-level topology is specifically a type-I three-level topology; the plurality of switching devices comprises a first switching module, a second switching device, a third switching device, a fourth switching device, a first diode and a second diode, the bus capacitor comprises a first bus capacitor and a second bus capacitor; the first switching device, the second switching device, the third switching device, the fourth switching device are sequentially connected in series to form a type-I bridge arm, the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, the first diode and the second diode are connected in series to form a diode bridge arm, wherein the common point of the first switching device and the second switching device is taken as a first connection point, the common point of the second switching device and the third switching device is taken as an output point, the common point of the third switching device and the fourth switching device is taken as a second connection point, the common point of the first bus capacitor and the second bus capacitor is taken as a midpoint, the two free ends of the type-I bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, the free ends of the diode bridge arm are connected with the first connection point and the second connection point respectively, and the common point of the diode bridge arm is connected with the midpoint; the thin film capacitor is connected between the free end of the type-I bridge arm and the common point of the diode bridge arm; the first switching device and the fourth switching device are taken as main switching devices, the second switching device and the third switching device are taken as freewheeling switching devices, the first level channel is from the free end of the first bus capacitor, the first switching device, the second switching device to the output point, the second level channel is from the free end of the second bus capacitor, the fourth switching device, the third switching device to the output point, and the mid-level channel is from the midpoint, the first diode, the second switching device to the output point or from the midpoint, the second diode, the third switching device to the output point.

[0011] In some embodiments, the capacitance of the thin film capacitor satisfies: the current division of the thin film capacitor for the anti-peak current ripple > the current division of the thin film capacitor for the power frequency ripple current, and the current division of the thin film capacitor for the anti-peak current ripple > the current division of the thin film capacitor for the switching frequency ripple.

[0012] In this way, the thin film capacitor has almost no current division for the power frequency ripple current, has extremely small current division for the switching frequency ripple current, and has relatively large current division for the anti-peak ripple current, so that the anti-peak ripple current can be efficiently absorbed without affecting the normal working current, and the anti-peak is reduced.

[0013] In a second aspect, the embodiments of the present application provide a printed circuit board for forming the multi-level circuit according to the first aspect.

[0014] In some embodiments, the printed circuit board comprises a core device region; for the multi-level circuit, the plurality of switching devices and the thin film capacitor are located in the core device region, and the plurality of bus capacitors are located outside the core device region.

[0015] Thus, since the thin film capacitor is located in the core device area, the current path of each switching device is shorter, thereby shortening the commutation path and reducing the reverse peak.

[0016] In some embodiments, the commutation path of the middle freewheeling loop of the multi-level circuit to the reverse freewheeling loop includes a first path passing through the thin film capacitor and a second path passing through the bus capacitor, and the length of the first path is less than that of the second path.

[0017] Thus, since the thin film capacitor can additionally provide a shorter commutation path, the path stray inductance is reduced, thereby reducing the reverse peak and improving the device life.

[0018] In some embodiments, the number of the multi-level circuits is multiple, the bus capacitors of the multiple multi-level circuits are connected in parallel to form a first bus capacitor array and a second bus capacitor array, each bus capacitor array includes multiple capacitors; the first bus capacitor array and the second bus capacitor array are alternately arranged on both sides of each multi-level circuit.

[0019] Thus, the bus capacitors can be arranged in different parts on the circuit board, and the commutation paths of each multi-level circuit are equal in length, and the current sharing degree is relatively high; at the same time, the bus capacitors are realized in the form of multiple small packaged capacitors connected in parallel, and the stray inductance of multiple small packaged capacitors is smaller than that of large capacitors, and at the same time, more layout freedom is left for other devices.

[0020] In a third aspect, the embodiments of the present application provide a converter, which includes the multi-level circuit of the first aspect; and / or the printed circuit board of any one of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of a T-type three-level topology provided by the embodiments of the present application;

[0022] Figure 2 A commutation schematic of a T-type three-level topology provided by the embodiments of the present application Figure 1 ;

[0023] Figure 3 A commutation schematic of a T-type three-level topology provided by the embodiments of the present application Figure 2 ;

[0024] Figure 4 A schematic diagram of an I-type three-level topology provided by the embodiments of the present application;

[0025] Figure 5 A position schematic of a thin film capacitor of an I-type three-level topology provided by the embodiments of the present application Figure 1;

[0026] Figure 6 Position diagram of film capacitor of I-type three-level topology provided for the embodiment of the present application Figure 2 ;

[0027] Figure 7 Commutation diagram of I-type three-level topology provided for the embodiment of the present application Figure 1 ;

[0028] Figure 8 Commutation diagram of I-type three-level topology provided for the embodiment of the present application Figure 2 ;

[0029] Figure 9 Structure diagram of I-type five-level topology provided for the embodiment of the present application

[0030] Figure 10 Structure diagram of printed circuit board provided for the embodiment of the present application

[0031] Figure 11 Structure diagram of printed circuit board under T-type layout provided for the embodiment of the present application

[0032] Figure 12 Structure diagram of printed circuit board under rectangular type layout provided for the embodiment of the present application

[0033] Figure 13 Structure diagram of printed circuit board under diamond type layout provided for the embodiment of the present application

[0034] Figure 14 Structure diagram of printed circuit board of a multi-phase multi-level circuit provided for the embodiment of the present application

[0035] Figure 15 Structure diagram of printed circuit board of I-type three-level topology provided for the embodiment of the present application DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described.

[0037] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor

[0038] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide-Semiconductor Field-Effect Transistor

[0039] BJT (Bipolar Junction Transistor): Bipolar Junction Transistor

[0040] HBT (Hetero Junction Bipolar Transistor): Hetero Junction Bipolar Transistor

[0041] The embodiments of the present application will be described in detail below with reference to the drawings.

[0042] In one embodiment, a multi-level circuit is provided, the multi-level circuit comprising a plurality of bus capacitors and a plurality of switching devices, the plurality of switching devices being connected in a multi-level topology; the multi-level circuit further comprising at least one thin film capacitor, the thin film capacitor being connected in parallel with a bus capacitor, and the thin film capacitor being connected between two of the switching devices, wherein the volume of the thin film capacitor is smaller than the volume of the bus capacitor; the multi-level circuit having a plurality of selectively conducting current loops, and the thin film capacitor being configured to shorten a commutation path of a switching process from one current loop to another current loop.

[0043] It should be noted that the multi-level circuit refers to a circuit with multiple levels of output, which can be used in inverters, rectifiers, converters, etc. Taking an inverter as an example, the multi-level circuit is specifically used to convert DC power into AC power, which can include three-level circuits, five-level circuits, seven-level circuits, etc. Here, they are not listed one by one.

[0044] Taking the application of the multi-level circuit in the inverter as an example, the bus capacitor in the multi-level circuit is mainly used to smooth the DC power of the inverter, reducing the fluctuation of the DC power to ensure the stability of the output AC power. Those skilled in the art understand that the bus capacitor refers to a capacitor installed on the bus for stabilizing voltage, reducing bus voltage fluctuation and reducing harmonics, which can adjust and balance voltage fluctuations in the power system and suppress and eliminate harmonics. Although the film capacitor is connected in parallel with the bus capacitor and also connected to the bus, it functions as a commutation path for shortening the switching process of a current loop to another current loop, i.e. the "film capacitor for shortening the commutation path of the switching process of a current loop to another current loop" in the case is two different function capacitors, and the "film capacitor for shortening the commutation path of the switching process of a current loop to another current loop" cannot be considered as a conventional bus capacitor.

[0045] When the multi-level circuit reaches the current limiting point (i.e. the current is too large), the switching of the current loop of the multi-level circuit can be performed through the bus capacitor by controlling the conduction or turn-off of the switching device. In this process, the current through some switching devices rapidly decreases to 0, and the extremely variable dI / dt (unit current change per unit time) when flowing through the system stray inductance will generate an induced voltage ΔV. The superposition of ΔV and bus voltage generates a negative peak, so that the switching device bears a higher voltage stress than usual, which may cause permanent damage to the switching device.

[0046] In the embodiments of the present application, a film capacitor is introduced in parallel with the bus capacitor. Since the volume of the film capacitor is smaller than that of the bus capacitor, the current path formed by the film capacitor itself will be shorter, thereby shortening the commutation path in the current loop switching process, reducing the stray inductance of the commutation path, and reducing the value of the induced voltage ΔV, thereby reducing the negative peak and avoiding damage to the switching device, which can prolong the service life of the multi-level circuit. In addition, due to the small volume, the physical space occupied is small, and in the physical layout, the film capacitor can be distributed near the periphery of the switching device, further shortening the commutation path in the current loop switching process.

[0047] It should be noted that for a three-level circuit, its output three levels can be represented by a positive level +V, a negative level -V and a zero level 0V. One of the positive level and the negative level is referred to as one of a first level or a second level, and the other of the positive level and the negative level is referred to as the other of the first level or the second level. The zero level is in the middle of the positive level and the negative level, and thus the zero level can also be referred to as a middle level.

[0048] For a five-level circuit, its output five levels can be simply represented by voltages in sequence as +2V, +V, 0V, -V and -2V, wherein +2V and 0V are respectively a first level and a second level, and 0V can be a middle level of +2V and -2V or +V and -V, and the first level and the second level can also be determined accordingly.

[0049] The same can be analogized for other types of multi-level circuits.

[0050] Thus, for any type of multi-level circuit, a first level, a middle level and a second level can be determined in the levels output by the multi-level circuit. After the multi-level circuit triggers a current limiting point, at least one main switching device is turned off, the multi-level circuit is switched from a current loop to a middle continuous current loop, and at least one continuous current switching device is turned off, the multi-level circuit is switched from the middle continuous current loop to a reverse continuous current loop through a thin film capacitor. The switching device on the middle level channel serves as a continuous current switching device, and the switching device on the first level channel or the second level channel serves as a main switching device. When the current loop is the first level channel, the reverse continuous current loop is a continuous current loop through the main switching device on the second level channel. When the current loop is the second level channel, the reverse continuous current loop is a continuous current loop through the main switching device on the first level channel. Those skilled in the art can know that the above-mentioned reverse continuous current loop refers to a current loop formed by a parasitic diode (in some embodiments, it can be an external diode connected in anti-parallel with the main switching device) through the main switching device, and for a current loop formed by a main switching part through the main switching device, it is referred to as a main current loop in the present case. The above-mentioned multi-level circuit has multiple current loops, specifically including a selectively conductive middle continuous current loop, a reverse continuous current loop and a main current loop.

[0051] In a specific embodiment, the first level and the middle level are connected through a first bus capacitor, the middle level and the second level are connected through a second bus capacitor, the thin film capacitor includes a first thin film capacitor and a second thin film capacitor, the first thin film capacitor is connected in parallel with the first bus capacitor, and the second thin film capacitor is connected in parallel with the second bus capacitor. The above is only an example, and the number of bus capacitors and the number of thin film capacitors can be selected according to actual use requirements.

[0052] The following will take the T-type three-level topology as an example to describe the specific structure and working principle of the multi-level circuit 10.

[0053] First, please refer to Figure 1 , the multi-level circuit 10 is specifically a T-type three-level topology; the plurality of switching devices in the multi-level circuit 10 includes the first switching device 11, the second switching device 12, the third switching device 13, and the fourth switching device 14, and the bus capacitor includes the first bus capacitor 15 and the second bus capacitor 16; the first switching device 11 and the fourth switching device 14 are connected in series to form a vertical pipe bridge arm, the second switching device 12 and the third switching device 13 are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor 15 and the second bus capacitor 16 are connected in series to form a capacitor bridge arm, wherein the common point of the first switching device 11 and the fourth switching device 14 is the output point, the common point of the first bus capacitor 15 and the second bus capacitor 16 is the midpoint O, the two free ends of the vertical pipe bridge arm are connected in parallel to the two free ends of the capacitor bridge arm, the first end of the horizontal pipe bridge arm is connected to the neutral point, and the second end is connected to the output point, and the two free ends of the capacitor bridge arm are also connected to the positive and negative ends of the power supply, and the thin film capacitor is connected across the free end of the vertical pipe bridge arm and the first end of the horizontal pipe bridge arm.

[0054] It should be noted that Figure 1 is shown by taking the first switching device 11 to the fourth switching device 14 as IGBT devices as an example, and in other embodiments, the first switching device 11 to the fourth switching device 14 can also be selected from other types of switching devices / switching device combinations, such as MOS, BJT, HBT, diode, etc. At the same time, each switching device can include a single transistor or multiple transistors.

[0055] At the same time, in Figure 1 , the thin film capacitor includes the first thin film capacitor 17 and the second thin film capacitor 18, the first thin film capacitor 17 and the first bus capacitor 15 are connected in parallel, and the second thin film capacitor 18 and the second bus capacitor 16 are connected in parallel, but this is only an example. The number of thin film capacitors can be more or less.

[0056] For the structure shown in Figure 1 , the first switching device 11 and the fourth switching device 14 are main switching devices, the second switching device 12 and the third switching device 13 are freewheeling switching devices, the first level channel refers to the channel from the free end of the first bus capacitor 15, the first switching device 11 to the output point, the second level channel is the channel from the free end of the second bus capacitor 16, the fourth switching device 14 to the output point, and the mid-level channel is the channel from the midpoint O, the horizontal pipe bridge arm to the output point. The reverse freewheeling circuit is a diode freewheeling channel flowing through the first switching device 11 or the fourth switching device 14.

[0057] Specifically, please refer to Figure 2 (a)~(c), which show the commutation operation of the multi-level circuit 10 after the trigger current-limiting point in a positive half cycle: specifically: Figure 2

[0058] Step one: before the trigger current-limiting point, the current loop of the multi-level circuit 10 is as shown in Figure 2 (a);

[0059] Step two: after the trigger current-limiting point, the vertical tube, i.e., the first switching device 11, is first turned off, please refer to Figure 2 (b), at this time, the current loop is switched to the mid-level channel, the horizontal tube, i.e., the second switching device 12, is turned on, and the parasitic diode of the third switching device 13 is turned on, at this time, the platform voltage borne by the first switching device 11 is half of the bus voltage (for example, 500V), and if the withstand voltage of the first switching device 11 is 1200V, at this time, it is in a non-limiting working condition;

[0060] Step three: after the second switching device 12 is stably turned on, the second switching device 12 is continuously turned off, please refer to Figure 2 (c), the parasitic diode of the fourth switching device 14 is turned on, at this time, the platform voltage borne by the first switching device 11 is the full bus voltage (for example, 1000V), and when the withstand voltage of the first switching device 11 is 1200V, at this time, there is only a margin of 200V, and once the induced voltage exceeds 200V, the reverse peak voltage formed by the superposition of the bus platform voltage exceeds 1200V, which exceeds the withstand voltage of the switching device and damages the switching device, i.e., the limiting working condition.

[0061] In this way, in the switching process from step two to step three, without setting the thin-film capacitor, the commutation loop is: the current loop from the midpoint O, the horizontal tube bridge arm, and the output point is switched to the path from the midpoint O, the second bus capacitor 16, the fourth switching device 14, and the output point, and due to the large capacity and volume of the bus capacitor, the path is long, and there is a high stray inductance (indicated by the inductance symbol in the figure), and a large voltage / current change acts on the stray inductance to generate a large reverse peak, which may break through the switching device; since the embodiment of the present application introduces a thin-film capacitor in parallel with the bus capacitor, the volume of the thin-film capacitor is smaller than the volume of the bus capacitor, and the thin-film capacitor can be connected between the first end of the horizontal tube bridge arm and the free end of the vertical tube bridge arm, so the commutation loop further includes the path of the second thin-film capacitor and the fourth switching device 14, and the sum of the paths at both ends of the thin-film capacitor is shorter than the sum of the paths at both ends of the bus capacitor, and the stray inductance therein is smaller, thereby reducing the reverse peak borne by the first switching device 11 and improving the service life of the multi-level circuit 10.

[0062] Please refer to Figure 3 (a)~(c), which show the commutation operation of the multi-level circuit 10 after the trigger current-limiting point in a positive half cycle: specifically: Figure 3 ​(c), which shows the commutation operation of the multi-level circuit 10 after the trigger current limiting point in the negative half cycle: in particular:

[0063] Step one: before the trigger current limiting point, the current loop of the multi-level inverter circuit is as shown in Figure 3 (a);

[0064] Step two: after the trigger current limiting point, the vertical tube, i.e. the fourth switching device 14, is first turned off, please refer to Figure 3 (b), at this time the current loop switches to the mid-level channel, the horizontal tube, i.e. the third switching device 13, is turned on, the parasitic diode of the second switching device 12 is turned on, at this time the platform voltage borne by the fourth switching device 14 is half of the bus voltage (for example, 500V), if the withstand voltage of the fourth switching device 14 is 1200V, at this time it is in a non-limiting working condition;

[0065] Step three: after the third switching device 13 is stably turned on, the third switching device 13 is continuously turned off, please refer to Figure 2 (c), the parasitic diode of the first switching device 11 is turned on, at this time the platform voltage borne by the fourth switching device 14 is the total bus voltage (for example, 1000V), and the withstand voltage of the fourth switching device 14 is 1200V, at this time there is only a margin of 200V, once the induced voltage exceeds 200V, the reverse peak voltage formed by the superposition of the bus platform voltage exceeds 1200V, exceeding the device withstand voltage and damaging the switching device, which is the limiting working condition.

[0066] In this way, in the switching process from step two to step three, without setting the thin film capacitor, the commutation loop is: the current loop from the midpoint O, the horizontal tube bridge arm, the output point is switched to the path of the midpoint O, the first bus capacitor 15, the first switching device 11, and the output point. Due to the large capacitance value and volume of the bus capacitor, the path is long, there is a high stray inductance, and a large voltage / current change acts on the stray inductance to generate a large reverse peak, which may break down the switching device; since the embodiment of the application introduces a thin film capacitor in parallel with the bus capacitor, the volume of the thin film capacitor is smaller than the volume value of the bus capacitor, and can be connected between the first end of the horizontal tube bridge arm and the free end of the vertical tube bridge arm, the path is shorter, so the commutation loop also includes the path passing through the thin film capacitor and the first switching device 11, the commutation loop is obviously shortened, and the stray inductance therein is smaller, thereby reducing the reverse peak borne by the fourth switching device 14 and improving the service life of the multi-level circuit 10.

[0067] Generally, the positive half cycle and the negative half cycle of the multi-level circuit are symmetrical, and the devices at the symmetrical position also select the same specification device, such as the first switch device of the positive half cycle and the second switch device of the negative half cycle both select the switch device with a withstand voltage of 1200V, and the positive half cycle and the negative half cycle are likely to trigger current limiting protection, therefore, generally, the first thin film capacitor and the second thin film capacitor need to be set at the same time, in some special cases, if the positive half cycle device and the negative half cycle device select different specification devices, such as the first switch device selects the switch with a withstand voltage of 1200V, and the fourth switch device selects the switch device with a withstand voltage of 2000V, because the fourth switch device has a larger withstand voltage margin and can withstand a larger reverse peak, therefore, only the second thin film capacitor can be set.

[0068] In another specific embodiment, please refer to Figure 4 In some embodiments, the multi-level circuit 10 is specifically a type I three-level topology; the plurality of switch devices includes a first switch device 11, a second switch device 12, a third switch device 13, a fourth switch device 14, a first diode 21 and a second diode 22, and the bus capacitor includes a first bus capacitor 15 and a second bus capacitor 16;

[0069] The first switch device 11, the second switch device 12, the third switch device 13 and the fourth switch device 14 are connected in series to form a type I bridge arm, the first bus capacitor 15 and the second bus capacitor 16 are connected in series to form a capacitor bridge arm, and the first diode 21 and the second diode 22 are connected in series to form a diode bridge arm, wherein the common point of the first switch device 11 and the second switch device 12 is the first connection point, the common point of the second switch device 12 and the third switch device 13 is the output point, the common point of the third switch device 13 and the fourth switch device 14 is the second connection point, the common point of the first bus capacitor 15 and the second bus capacitor 16 is the midpoint O, the two free ends of the type I bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, the two free ends of the diode bridge arm are connected with the first connection point and the second connection point, and the common point of the diode bridge arm is connected with the midpoint O;

[0070] The thin film capacitor is connected between the free end of the type I bridge arm and the common point of the diode bridge arm.

[0071] For example, the thin film capacitor includes a first thin film capacitor 17 and a second thin film capacitor 18, in a specific embodiment, please refer to Figure 5 The first thin film capacitor 17 is connected between the free end of the first switch device 11 and the anode of the first diode 21, and the second thin film capacitor 18 is connected between the free end of the fourth switch device 14 and the cathode of the second diode 22;

[0072] Alternatively, in another specific embodiment, please refer to Figure 6, the first thin-film capacitor 17 is connected between the free end of the first switching device 11 and the cathode of the second diode 22, and the second thin-film capacitor 18 is connected between the free end of the fourth switching device 14 and the anode of the first diode 21. Compared with the connection mode of the thin-film capacitor shown in Figure 5 , Figure 6 , the connection mode of the thin-film capacitor shown in may further shorten the commutation path and reduce the reverse peak.

[0073] Specifically, the first switching device 11 and the fourth switching device 14 are main switching devices, the second switching device 12 and the third switching device 13 are freewheeling switching devices, the first level channel is the free end of the first bus capacitor 15, the first switching device 11, the second switching device 12 to the output point, please refer to Figure 7 (b) in the figure, the second level channel is the free end of the second bus capacitor 16, the fourth switching device 14, the third switching device 13 to the output point, and the mid-level channel is the midpoint O, the first diode 21, the second switching device 12 to the output point, and the mid-level channel further includes the midpoint O, the second diode 22, the third switching device 13 to the output point. The reverse freewheeling circuit is a diode freewheeling circuit flowing through the first switching device 11 or the fourth switching device 14.

[0074] Taking the coupling capacitor shown in Figure 5 as an example, please refer to Figure 7 (a)-(c) in the figure, which shows the commutation process of the multi-level circuit 10 under the I-type three-level topology when the positive half-cycle trigger commutation point is triggered; please refer to Figure 8 (a)-(c) in the figure, which shows the commutation process of the multi-level circuit 10 under the I-type three-level topology when the negative half-cycle trigger commutation point is triggered. Similarly, since the embodiment of the application introduces a thin-film capacitor in parallel with the bus capacitor, and the volume of the thin-film capacitor is smaller than the volume of the bus capacitor, it can be connected between the first vertical tube bridge arm and the second vertical tube bridge arm, the path is shorter, thereby significantly shortening the commutation circuit, and the stray inductance is smaller, thereby reducing the reverse peak borne by the fourth switching device 14 and improving the service life of the multi-level circuit 10.

[0075] In another specific embodiment, please refer to Figure 9 , the multi-level circuit 10 is specifically a five-level topology. Please refer to Figure 9 , the multi-level circuit 10 includes eight switching devices and four bus capacitors, the first switching device 11 to the fourth switching device 14 are connected in series to form a vertical tube bridge arm, the fifth switching device 21' and the sixth switching device 22' are connected in series to form a horizontal tube bridge arm, and the first bus capacitor 15a, the second bus capacitor 15b, the fourth bus capacitor 16a and the third bus capacitor 16a are connected in series to form a capacitor bridge arm. The two free ends of the capacitor bridge arm and the two free ends of the vertical tube bridge arm are connected in parallel.

[0076] The common point of the second bus capacitor 15b and the fourth bus capacitor 16b is the midpoint O, one free end of the horizontal pipe bridge arm is connected to the midpoint O, the other free end of the horizontal pipe bridge arm is connected to the common point of the second switch device 12 and the third switch device 13, and the common point of the second switch device 12 and the third switch device 13 forms an alternating current end (i.e. an output point); one end of the seventh switch device 27 is connected to the common point of the first switch device 11 and the second switch device 12, the other end of the seventh switch device 27 is connected to the common point of the first bus capacitor 15a and the third bus capacitor 15b, one end of the eighth switch device 28 is connected to the common point of the third switch device 13 and the fourth switch device 14, the other end of the eighth switch device 28 is connected to the common point of the fourth bus capacitor 16b and the third bus capacitor 16a. The first decoupling capacitor 17 is connected between one end of the horizontal pipe bridge arm (away from the vertical pipe bridge arm) and the first free end of the vertical pipe bridge arm, and the second decoupling capacitor 18 is connected between one end of the horizontal pipe bridge arm (away from the vertical pipe bridge arm) and the second free end of the vertical pipe bridge arm.

[0077] The second switch device 12, the third switch device 13, the fifth switch device 21', and the sixth switch device 22' are all freewheeling switch devices, and the first switch device 11, the fourth switch device 14, the seventh switch device 27, and the eighth switch device 28 are all main switch devices.

[0078] Please refer to Figure 8 The midpoint freewheeling circuit refers to an electrical path between the second switch device 12 and the third switch device 13, via the fifth switch device 21' and the sixth switch device 22', through the second bus capacitor 15b and the fourth bus capacitor 16b.

[0079] The current loop switching process after the trigger current limiting point of the multi-level circuit 10 can be understood with reference to the switching process of the three-level I type topology, which will not be described here. In this way, the commutation loop of the commutation of the mid-level channel to the reverse freewheeling level channel is: the current loop of the midpoint O, the horizontal tube bridge arm, the output point is switched to the path of the midpoint O, the third bus capacitor 16a, the fourth bus capacitor 16b, the fourth switch device 14 to the output point, or the current loop of the midpoint O, the horizontal tube bridge arm, the output point is switched to the path of the midpoint O, the first bus capacitor 15a, the second bus capacitor 15b, the first switch device 11 to the output point; due to the large capacity and volume of the bus capacitor, the path is long, there is a high stray inductance, and a large voltage / current change acts on the stray inductance to generate a large reverse peak, which may break the switch device; since the embodiment of the application introduces a film capacitor in parallel with the bus capacitor, since the volume of the film capacitor is smaller than the volume of the bus capacitor, it can be connected between the first end of the horizontal tube bridge arm and the free end of the vertical tube bridge arm, the path is shorter, so the commutation loop further includes the path of the midpoint O, the first film capacitor 17, the first switch device 11, or the commutation loop further includes the path of the midpoint O, the second film capacitor 18, the fourth switch device 14, the commutation loop is obviously shortened, and the stray inductance is smaller, thereby reducing the reverse peak borne by the first switch device 11 or the fourth switch device 14, and improving the service life of the multi-level circuit 10. In other control sequences, the commutation loop may not be consistent with the above embodiment, and therefore the mid-level channel and the reverse freewheeling level channel may not be consistent, and therefore the commutation process is not limited to the above embodiment.

[0080] In the above description, the capacitance of the film capacitor satisfies: the ripple current division of the film capacitor for the reverse peak current > the current division of the film capacitor for the power frequency ripple current, and the ripple current division of the film capacitor for the reverse peak current > the current division of the film capacitor for the switching frequency ripple.

[0081] It should be noted that there are mainly three types of ripple currents in the multi-level circuit 10: (1) power frequency ripple current; (2) switching frequency ripple current; (3) reverse peak ripple current (which can also be called commutation current). The frequencies of the three types of ripple currents are different, the frequency of the power frequency ripple < the frequency of the switching frequency ripple < the frequency of the reverse peak ripple (generally, the frequency of the power frequency ripple is 50Hz or 60Hz and its multiple, the frequency of the switching frequency ripple is 10kHz-100kHz, and the frequency of the reverse peak ripple is 1MHz-10MHz), and it is found through experiments that different types and different capacitances of capacitors have different throughputs for the three types of different frequency ripples, and capacitors with small capacitances have a large throughput for high switching frequencies. The capacitance of the film capacitor needs to be able to well allow the reverse peak ripple current to pass through, while the throughputs of the power frequency ripple current and the switching frequency ripple current are small, so the capacitance of the film capacitor cannot be too large, otherwise too much switching frequency current will be divided, which will cause the capacitor to overheat.

[0082] In a specific scenario, the capacitance of the film capacitor for shortening the commutation path of the switching process from one current loop to another current loop is 0.47 microfarad, and the bus capacitor for absorbing the power frequency ripple current can have a capacitance of 470 microfarad, and an electrolytic capacitor is selected, which is large in size and is arranged in a more peripheral area, and can be multiple capacitors in parallel. The bus capacitor for absorbing the switching frequency ripple current can have a capacitance of 12 microfarad, which is larger in size than the film capacitor, and is also arranged in a more peripheral area, and can also be multiple capacitors in parallel. Through experimental verification, the 0.47 microfarad film capacitor has almost no current division for the power frequency ripple current, about 1% for the switching frequency ripple current, and about 99% for the anti-peak ripple current. The 12 microfarad bus capacitor has about 95% for the switching frequency ripple current, and about 1% for the anti-peak ripple current. The 0.47 microfarad film capacitor has almost no current division for the anti-peak ripple current, and about 99% for the power frequency ripple current. As can be seen, the anti-peak ripple current (i.e. commutation current) mainly passes through the film capacitor. The above capacitance values and test data are only a set of values obtained by the inventors during the test, and cannot limit the unique range of capacitance values of the present application, nor can they limit the division of different capacitors for different ripple currents. It should be understood in accordance with the inventive concept of the present application.

[0083] In summary, the embodiment of the present application provides a multi-level circuit, which can reduce the length of the commutation path in the switching process from the middle freewheeling loop to the reverse freewheeling loop by introducing a film capacitor, thereby reducing the anti-peak and prolonging the service life of the device.

[0084] In another embodiment of the present application, please refer to Figure 10 , which is a structural schematic diagram of a printed circuit board 30 provided by the embodiment of the present application. As Figure 10 indicated, the printed circuit board is used to form the aforementioned multi-level circuit 10.

[0085] Please refer to Figure 10 , the printed circuit board 30 includes a core device area; for the multi-level inverter circuit, a plurality of switching devices and film capacitors are located within the core device area, and a plurality of bus capacitors are located outside the core device area.

[0086] Therefore, the commutation path of the multi-level circuit from the middle freewheeling loop to the reverse freewheeling loop includes a first path passing through the film capacitor and a second path passing through the bus capacitor, and the length of the first path is shorter than that of the second path. That is, compared with the position of the bus capacitor, the film capacitor is closer to the switching device, so that the length of the commutation path passing through the film capacitor is shorter, and the anti-peak current is weakened.

[0087] The multilevel circuit is specifically a T-type three-level topology (i.e. Figure 1 Taking the structure shown below as an example, several specific layouts of the printed circuit board 30 are provided. The following layouts are also applicable to the type I three-level topology and can be used for reference and understanding.

[0088] For the first specific embodiment, please refer to Figure 11 The first switching device 11, the second switching device 12, the third switching device 13, and the fourth switching device 14 are arranged in a T-shape; the first switching device 11 and the fourth switching device 14 form the short side of the T-shape; the second switching device 12 and the third switching device 13 form the long side of the T-shape; the third switching device 13 is closer to the short side of the T-shape, and the second switching device 12 is farther away from the long side of the T-shape.

[0089] It should be noted that in the T-type layout, even the commutation path via the bus capacitor is relatively short, resulting in a lower reverse peak.

[0090] In addition, for the T-shaped layout, the first film capacitor 17 and the second film capacitor 18 are located between the first switching device 11, the fourth switching device 14 and the third switching device 13; one of the first bus capacitor 15 and the second bus capacitor 16 is located on the side of the first switching device 11 away from the fourth switching device 14, and the other of the first bus capacitor 15 and the second bus capacitor 16 is located on the side of the fourth switching device 14 away from the first switching device 11.

[0091] In this way, a first thin-film capacitor 17 is provided between the first switching device 11 and the third switching device 13, and a second thin-film capacitor 18 is provided between the fourth switching device 14 and the third switching device 13. Therefore, the commutation path through the first thin-film capacitor 17 and the commutation path through the second thin-film capacitor 18 are further shortened, thereby reducing the reverse peak.

[0092] As mentioned above, each switching device may include a single transistor or multiple transistors. For cases where each switching device includes multiple transistors, please refer to [link to relevant documentation]. Figure 11 The second switching device 12 includes four second transistors arranged in a trapezoidal pattern; the third switching device 13 includes four third transistors arranged in a 2×2 array; the first switching device 11 includes three first transistors arranged in a triangular pattern; the fourth switching device 14 includes three fourth transistors arranged in a triangular pattern (the specific shape of the triangle is not limited, such as a right triangle or an isosceles triangle); a first thin-film capacitor 17 and a second thin-film capacitor 18 are placed in the area surrounded by the first transistor at the apex of the triangle, the fourth transistor at the apex of the triangle, and the four third transistors.

[0093] In this way, the thin film capacitor does not occupy extra area, and the reverse peak is reduced.

[0094] In a specific embodiment, the first to fourth transistors are IGBT transistors, which have the advantages of high withstand voltage, high current, high switching frequency, low switching loss, and acceptable on-state loss.

[0095] In a second specific embodiment, referring to Figure 12 , the first to fourth switching devices 11, 12, 13, 14 are arranged in a rectangular layout; the first and fourth switching devices 11, 14 are arranged along a first direction, and the second and third switching devices 12, 13 are arranged along the first direction; the first and third switching devices 11, 13 are arranged along a second direction, and the second and fourth switching devices 12, 14 are arranged along the second direction.

[0096] The first and second thin film capacitors 17, 18 are located between the first to fourth switching devices 11, 12, 13, 14.

[0097] It should be noted that the commutation path of the rectangular layout is shorter than that of the T-shaped layout, and the first and second thin film capacitors 17, 18 are also added, so the reverse peak is smaller.

[0098] In a third specific embodiment, referring to Figure 13 , the first to fourth switching devices 11, 12, 13, 14 are arranged in a diamond layout; the first, third, and fourth switching devices 11, 13, 14 are arranged along a first direction, and the first, second, and fourth switching devices 11, 12, 14 are arranged along the first direction; the third and second switching devices 13, 12 are arranged along a second direction; the first thin film capacitor 17 is located between the second and third switching devices 12, 13 and is placed close to the first switching device 11; and the second thin film capacitor 18 is located between the second and third switching devices 12, 13 and is placed close to the fourth switching device 14.

[0099] As can be seen from the second and third embodiments described above, the core device region can be divided into a first core device region and a second core device region arranged adjacent to each other, and the plurality of switching devices constituting the multi-level circuit are divided into positive half-cycle devices (corresponding to the first and second switching devices 11, 12 in Figure 12 and Figure 13 ) and negative half-cycle devices (corresponding to the third and fourth switching devices 13, 14 in Figure 12 and Figure 13The fourth switch device 14 and the third switch device 13 in the first core device region, the positive half-cycle switch device and the first thin film capacitor are arranged in the first core device region, the negative half-cycle switch device and the second thin film capacitor are arranged in the second core device region, the switch device and the thin film capacitor in close relationship with each other are more closely arranged in layout, so that the connection path between the switch device and the thin film capacitor is shorter, the commutation path can be further shortened, the stray inductance is reduced, and the peak is reduced.

[0100] In other embodiments, the bus capacitor can be composed of a plurality of small capacitors in parallel, and the distribution position can be flexibly selected. For example Figure 11 Each small block in the bus capacitor can be regarded as a small capacitor, and a plurality of small capacitors are connected in parallel to form a bus capacitor with a preset capacitance. It should be noted that when the bus capacitor is composed of a plurality of small capacitors in parallel, the volume of the aforementioned thin film capacitor is smaller than the volume of the bus capacitor, which should not be understood as the volume of the thin film capacitor must be smaller than the volume of each small capacitor constituting the bus capacitor in parallel, but should be understood as the volume of the capacitor used for decoupling (i.e. the thin film capacitor) is smaller than the volume of the capacitor used for bus support (i.e. the bus capacitor).

[0101] In other embodiments, the number of multi-level circuits 10 is a plurality, each multi-level circuit constitutes a core device region, the bus capacitor includes a plurality of first bus capacitor arrays and a plurality of second bus capacitor arrays, each bus capacitor array includes a plurality of capacitors (the number of capacitors included in each bus capacitor can be the same or different); the first bus capacitor array and the second bus capacitor array are arranged on the two sides of each multi-level circuit 10 (i.e. each core device region), and the first bus capacitor array and the second bus capacitor array are arranged alternately.

[0102] For example Figure 14 The number of multi-level circuits 10 is three, i.e. a three-phase three-level inverter circuit is formed, at this time, the three multi-level circuits 10 are arranged in the first direction in sequence, and the first bus capacitor array and the second bus capacitor array are arranged on the two sides of each multi-level circuit 10. In this embodiment, the number of capacitors included in each bus capacitor array is different, and in other embodiments, the number of capacitors included in each bus capacitor array can be the same.

[0103] In this way, the bus capacitor can be arranged in different parts on the circuit board, the commutation path of each multi-level circuit 10 is equal, and the current sharing degree is relatively high; at the same time, the bus capacitor is realized in the form of a plurality of small packaged capacitors connected in parallel, and the stray inductance of the plurality of small packaged capacitors is smaller than that of the large capacitor, and at the same time, more layout freedom is left for other devices. Through simulation, the stray inductance of the capacitor under this layout is only 7% of the total stray inductance of the circuit.

[0104] In summary, the embodiment of the present application provides a printed circuit board 30 for implementing the aforementioned multi-level circuit 10, and provides the positions of the film capacitors in various layouts. Overall, the film capacitors are closer to the switching devices than the bus capacitors, so as to reduce the commutation path length in the switching process from the middle freewheeling circuit to the reverse freewheeling circuit, reduce the reverse peak, and prolong the service life of the devices.

[0105] Taking the multi-level circuit as an example, the multi-level circuit is specifically an I-type three-level topology (i.e., the circuit topology shown in FIG. 1), and a specific layout of the printed circuit board 30 is provided, as shown in FIG. 2. The core device region is divided into a first core device region and a second core device region. The first switching device 11, the second switching device 12, and the first diode 21 form an “I” type layout in the first core device region, and the first diode 21 is placed adjacent to the first switching device 11. The first decoupling capacitor 17 is arranged between the first diode 21 and the first switching device 11. The fourth switching device 14, the third switching device 13, and the second diode 22 form an “I” type layout in the second core device region, and the second diode 22 is placed adjacent to the fourth switching device 14. The second decoupling capacitor 18 is arranged between the second diode 22 and the fourth switching device 14. The first core device region and the second core device region are mirror-symmetric, in which the fourth switching device 14 corresponds to the first switching device 11, the third switching device 13 corresponds to the second switching device 12, the second diode 22 corresponds to the first diode 21, and the first decoupling capacitor 17 corresponds to the second decoupling capacitor 18. Figure 5 Figure 15 Meanwhile, the first pin (i.e., the pin connected to the first diode 21) of the first decoupling capacitor 17 is directed towards the first diode 21, and the second pin (i.e., the pin connected to the first switching device 11) of the first decoupling capacitor 17 is directed towards the first switching device 11. Similarly, the second decoupling capacitor 18 is mirror-symmetric to the first decoupling capacitor 17, so that the second pin (i.e., the pin connected to the second diode 22) of the second decoupling capacitor 18 is directed towards the second diode 22, and the second pin (i.e., the pin connected to the fourth switching device 14) of the second decoupling capacitor 18 is directed towards the fourth switching device 14.

[0106] In this layout embodiment, the advantages of shortening the commutation path and reducing the reverse peak are also achieved.

[0107] In this embodiment, in addition to the core device region, the first bus capacitor and the second bus capacitor are arranged. The bus capacitor can be composed of multiple small capacitors in parallel, and the distribution position can be flexibly selected. In this embodiment, the first bus capacitor and the second bus capacitor can each include multiple bus capacitors,

[0108] In this embodiment, in addition to the core device region, the first bus capacitor and the second bus capacitor are arranged. The bus capacitor can be composed of multiple small capacitors in parallel, and the distribution position can be flexibly selected. In this embodiment, the first bus capacitor and the second bus capacitor can each include multiple bus capacitors, Figure 15 ​Each small circle and each small square can be regarded as a small bus capacitor, and the plurality of small bus capacitors are connected in parallel to form the first bus capacitor or the second bus capacitor with a preset capacitance value. The specific distribution of the first bus capacitor and the second bus capacitor is not limited herein. The bus capacitor can be arranged on one side of the core device region as a whole, or part of the bus capacitor can be arranged as a plurality of arrays on multiple sides of the core device region.

[0109] Referring to Figure 15 When the number of three-level circuits is multiple, the part of bus capacitors constituting the first bus capacitor includes a plurality of first bus capacitor arrays, and the part of bus capacitors constituting the second bus capacitor includes a plurality of second bus capacitor arrays. Each bus capacitor array includes a plurality of capacitors (such as small squares in the figure), which are connected in parallel. Figure 15 It can be seen that each three-level circuit forms a core device region, and the first bus capacitor array and the second bus capacitor array are arranged on two sides of each core device region, and the first bus capacitor array and the second bus capacitor array are arranged alternately.

[0110] Specifically, the number of three-level circuits 10 is three, that is, a three-phase three-level inverter circuit is formed. At this time, the three three-level circuits 10 are arranged in the first direction in sequence, and the first bus capacitor array and the second bus capacitor array are arranged on two sides of each three-level circuit 10. The two first bus capacitor arrays are connected in parallel to form the first bus capacitor in the circuit, and the two second bus capacitor arrays are connected in parallel to form the second bus capacitor in the circuit. In this way, the bus capacitor can be arranged in different parts on the circuit board, the commutation path of each three-level circuit 10 is equal in length, and the current sharing degree is relatively high. At the same time, the bus capacitor is realized in the form of parallel connection of a plurality of small packaged capacitors, and the stray inductance of the plurality of small packaged capacitors is smaller than that of a large capacitor, and more layout freedom is left for other devices. Through simulation, the stray inductance of the capacitor under this layout is greatly reduced. In another embodiment of the present application, a converter is provided, which includes the aforementioned multi-level circuit 10 and / or the aforementioned printed circuit board 30.

[0111] The above merely describes preferred embodiments of the present application, but is not used to limit the protection scope of the present application. It should be explained that, in the present application, the terms “comprising”, “containing” or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of other identical elements in the process, method, article or device including the element. The above sequence number of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments or device embodiments. The above is merely a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A multi-level circuit, characterized by, The multi-level circuit comprises a plurality of bus capacitors and a plurality of switching devices, and the plurality of switching devices are connected in a multi-level topology; The multi-level circuit further comprises at least one thin film capacitor, which is connected in parallel with the bus capacitors and between two of the switching devices, and the volume of the thin film capacitor is smaller than that of the bus capacitors; The multi-level circuit has a plurality of current loops selectively turned on, and the thin film capacitor is used to shorten the commutation path of the switching process from one of the current loops to another of the current loops; The output of the multi-level circuit comprises a first level, a middle level and a second level; After the multi-level circuit triggers a current limiting point, at least one main switching device is turned off, the multi-level circuit is switched from a current loop to a middle freewheeling loop, and at least one freewheeling switching device is turned off, the multi-level circuit is switched from the middle freewheeling loop to a reverse freewheeling loop through the thin film capacitor; The switching device on the middle level channel is the freewheeling switching device, the switching device on the first level channel or the second level channel is the main switching device, when the current loop is the first level channel, the reverse freewheeling loop is a freewheeling loop through the main switching device on the second level channel, and when the current loop is the second level channel, the reverse freewheeling loop is a freewheeling loop through the main switching device on the first level channel; The capacitance of the thin film capacitor satisfies: The thin film capacitor is divided into a current for a reverse peak current ripple, a current for a power frequency ripple current, and a current for a switching frequency ripple, and the current for the reverse peak current ripple is greater than the current for the power frequency ripple current and the current for the switching frequency ripple.

2. The multi-level circuit of claim 1, wherein, The multi-level topology is a T-type three-level topology, the plurality of switching devices comprises a first switching device, a second switching device, a third switching device and a fourth switching device, and the bus capacitors comprise a first bus capacitor and a second bus capacitor; The first switching device and the fourth switching device are connected in series to form a vertical pipe bridge arm, the second switching device and the third switching device are connected in series to form a horizontal pipe bridge arm, and the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm, wherein the common point of the first switching device and the fourth switching device is an output point, the common point of the first bus capacitor and the second bus capacitor is a neutral point, and the two free ends of the vertical pipe bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, and the first end of the horizontal pipe bridge arm is connected to the neutral point and the second end is connected to the output point; The thin film capacitor is connected across the free end of the vertical pipe bridge arm and the first end of the horizontal pipe bridge arm; The first switching device and the fourth switching device are main switching devices, the second switching device and the third switching device are freewheeling switching devices, the first level channel is a channel from the free end of the first bus capacitor to the output point, the second level channel is a channel from the free end of the second bus capacitor to the output point, and the middle level channel is a channel from the neutral point to the output point.

3. The multi-level circuit of claim 1, wherein, The multi-level topology is specifically a type I three-level topology; the plurality of switching devices comprises a first switching device, a second switching device, a third switching device, a fourth switching device, a first diode, and a second diode; and the bus capacitor comprises a first bus capacitor and a second bus capacitor. The first switching device, the second switching device, the third switching device, and the fourth switching device are sequentially connected in series to form a type I bridge arm; the first bus capacitor and the second bus capacitor are connected in series to form a capacitor bridge arm; and the first diode and the second diode are connected in series to form a diode bridge arm, wherein a common point of the first switching device and the second switching device serves as a first connection point, a common point of the second switching device and the third switching device serves as an output point, a common point of the third switching device and the fourth switching device serves as a second connection point, a common point of the first bus capacitor and the second bus capacitor serves as a midpoint, two free ends of the type I bridge arm are connected in parallel to two free ends of the capacitor bridge arm, a free end of the diode bridge arm is connected to the first connection point, and another free end of the diode bridge arm is connected to the second connection point, and a common point of the diode bridge arm is connected to the midpoint. The thin film capacitor is connected between a free end of the type I bridge arm and a common point of the diode bridge arm. The first switching device and the fourth switching device serve as main switching devices, and the second switching device and the third switching device serve as freewheeling switching devices; the first level channel is from a free end of the first bus capacitor, the first switching device, the second switching device to the output point; the second level channel is from a free end of the second bus capacitor, the fourth switching device, the third switching device to the output point; and the mid-level channel is from the midpoint, the first diode, the second switching device to the output point or from the midpoint, the second diode, the third switching device to the output point.

4. A printed circuit board, characterized by The printed circuit board is used to form the multi-level circuit according to any one of claims 1-3.

5. The printed circuit board of claim 4, wherein, The printed circuit board comprises a core device region. For the multi-level circuit, the plurality of switching devices and the thin film capacitor are located in the core device region, and the plurality of bus capacitors are located outside the core device region.

6. The printed circuit board according to claim 5, wherein The commutation path of the mid-level freewheeling circuit to the reverse freewheeling circuit comprises a first path passing through the thin film capacitor and a second path passing through the bus capacitor, and the length of the first path is less than that of the second path.

7. The printed circuit board of claim 5, wherein, The number of the multi-level circuits is a plurality, the bus capacitors of the plurality of multi-level circuits are connected in parallel to form a first bus capacitor array and a second bus capacitor array, and each bus capacitor array comprises a plurality of capacitors. The two sides of each multi-level circuit are respectively provided with the first bus capacitor array and the second bus capacitor array, and the first bus capacitor array and the second bus capacitor array are alternately arranged.

8. A converter, characterized by The converter comprises the multi-level circuit according to any one of claims 1-3; and / or the printed circuit board according to any one of claims 4-7.

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