An elastic wave device, a chip packaging method, and a radio frequency module

Abstract

This invention discloses an elastic wave device, a chip packaging method, and a radio frequency module. The device includes a device chip, a support layer, a cover layer, a packaging substrate, and a packaging layer. The device chip includes a first solder contact layer and interdigital transducers. Both the first solder contact layer and the interdigital transducers are located on the main surface of the device chip. One side of the packaging substrate includes package wiring and solder bumps. The solder bumps are connected to the package wiring and the first solder contact layer, respectively. The support layer is located on the main surface of the device chip. The cover layer is located on one side of the support layer. The main surface of the device chip, the support layer, and the cover layer form a cavity. There are gaps between the solder bumps and the support layer and the cover layer. The packaging layer covers one side of the packaging substrate and the device chip. This application solves the problem of easy delamination between the bumps and the cover and support layers in traditional elastic wave devices with cavity structures, thus improving the reliability of the elastic wave device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to an elastic wave device, a chip packaging method, and a radio frequency module. Background Technology

[0002] As applications demand thinner and smaller integrated circuits, more and more chips are moving from traditional wire bonding to flip-chip assembly. Flip-chip packaging also allows for more input / output ports, lower parasitic inductance, and better heat dissipation.

[0003] Bumps, serving as the connection between the device chip and the packaging substrate in flip chip packaging, are an essential part of current flip chip packaging methods. In traditional elastic wave devices with cavity structures, bumps are typically formed in the form of copper pillars or solder balls within the through-holes of the support layer and capping layer to bond the device chip to the packaging substrate. When the elastic wave device is subjected to thermal shock, the mismatch in the thermal expansion coefficients of the materials can cause delamination between the bumps and the capping and support layers, thus affecting the reliability of the elastic wave device.

[0004] There is currently no effective solution to the problem of delamination between the bumps and the cover and support layers in traditional elastic wave devices with cavity structures. Summary of the Invention

[0005] This embodiment provides a layer-by-layer optimized automatic model quantization method, system, and storage medium to solve the problem in related technologies where the final neural network model has poor learning performance when compressed using model quantization methods.

[0006] This embodiment provides an elastic wave device to solve the problem of easy delamination between the protrusions and the cover and support layers in traditional elastic wave devices with cavity structures.

[0007] In the first aspect, this embodiment provides an elastic wave device, including a device chip, a support layer, a cover layer, a packaging substrate, and a packaging layer;

[0008] The device chip includes a first solder contact layer and an interdigital transducer; both the first solder contact layer and the interdigital transducer are located on the main surface of the device chip.

[0009] One side of the packaging substrate includes packaging wiring and solder bumps; the solder bumps are respectively connected to the packaging wiring and the first solder contact layer;

[0010] The support layer is located on the main surface of the device chip; the cover layer is located on one side of the support layer; the main surface of the device chip, the support layer, and the cover layer form a cavity;

[0011] There is a gap between the solder bump and the support layer and the cover layer;

[0012] The encapsulation layer covers one side of the encapsulation substrate and the device chip.

[0013] In some embodiments, the solder bumps are located outside the support layer and the cover layer.

[0014] In some embodiments, the distance between the solder bump and the support layer is greater than 25 μm.

[0015] In some embodiments, the spacing between two adjacent solder bumps is greater than 150 μm.

[0016] In some embodiments, the encapsulation layer fills the gap between the solder bumps and the support layer and the cover layer.

[0017] In some embodiments, the gap between the main surface of the device chip and one side of the packaging substrate is filled with filler.

[0018] The minimum particle size of the filler is smaller than the minimum particle size of the constituent material of the encapsulation layer.

[0019] Secondly, this embodiment provides a chip packaging method applicable to the elastic wave device described in any of the first aspects above, comprising:

[0020] A first welding contact layer is formed on the main surface of the device chip;

[0021] Based on the position of the first welding contact layer, a solder area is formed on one side of the packaging substrate; solder bumps are applied to the solder area;

[0022] The main surface of the device chip is mounted on one side of the packaging substrate, so that the first solder contact layer corresponds to the solder area; the main surface of the device chip is bonded to one side of the packaging substrate through the solder bumps;

[0023] An encapsulation layer is formed by covering one side of the encapsulation substrate and the device chip with a molding compound.

[0024] The packaging substrate and the packaging layer are cut to obtain a single packaged chip.

[0025] In some embodiments, mounting the main surface of the device chip onto one side of the packaging substrate includes:

[0026] The main surface of the device chip is attached to one side of the packaging substrate using a temporary bonding material.

[0027] In some embodiments, bonding the main surface of the device chip to one side of the package substrate via the solder bumps includes:

[0028] The solder bumps on one side of the packaging substrate are processed by reflow soldering to bond the main surface of the device chip to one side of the packaging substrate.

[0029] In some embodiments, after forming the solder area on one side of the packaging substrate, the method further includes:

[0030] A second solder contact layer is formed in the solder region of the packaging substrate.

[0031] Thirdly, this embodiment provides a radio frequency module, including a passive device and the elastic wave device described in the first aspect above.

[0032] Compared with related technologies, this embodiment provides an elastic wave device, a chip packaging method, and a radio frequency module. The device includes a device chip, a support layer, a cover layer, a packaging substrate, and a packaging layer. The device chip includes a first solder contact layer and interdigital transducers. Both the first solder contact layer and the interdigital transducers are located on the main surface of the device chip. One side of the packaging substrate includes packaging wiring and solder bumps. The solder bumps are connected to the packaging wiring and the first solder contact layer, respectively. The support layer is located on the main surface of the device chip. The cover layer is located on one side of the support layer. The main surface of the device chip, the support layer, and the cover layer form a cavity. There are gaps between the solder bumps and the support layer and the cover layer. The packaging layer covers one side of the packaging substrate and the device chip. This elastic wave device solves the problem of easy delamination between the bumps and the cover and support layers in traditional elastic wave devices with cavity structures, thus improving the reliability of the elastic wave device.

[0033] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0035] Figure 1This is a schematic diagram of the elastic wave device according to the first embodiment of this application;

[0036] Figure 2 This is a schematic diagram of a portion of a traditional elastic wave device with a cavity structure.

[0037] Figure 3 This is a top view of the cross-section of the elastic wave device according to the second embodiment of this application;

[0038] Figure 4 This is a flowchart of a chip packaging method according to the third embodiment of this application;

[0039] Figure 5 This is a schematic diagram of the chip packaging structure in step S201 of the third embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the chip packaging structure in step S202 of the third embodiment of this application;

[0041] Figure 7 This is a schematic diagram of the chip packaging structure in step S203 of the third embodiment of this application;

[0042] Figure 8 This is a schematic diagram of the chip packaging structure in step S204 of the third embodiment of this application.

[0043] In the figure: 10, device chip; 10a, main surface of device chip; 11, first solder contact layer; 12, interdigital transducer; 20, support layer; 30, cover layer; 40, packaging substrate; 40a, one side of packaging substrate; 42, solder bump; 43, packaging wiring; 50, packaging layer; 60, cavity; d1, first pitch; d2, second pitch; 70, bump; 80, passive device. Detailed Implementation

[0044] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0045] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning as understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these,” used in this application, do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” and “coupled,” used in this application, are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. The term “multiple” used in this application refers to two or more. The "and / or" operator describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: A alone, A and B simultaneously, and B alone. Typically, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," and "third," etc., used in this application are merely for distinguishing similar objects and do not represent a specific ordering of the objects.

[0046] Figure 1 This is a schematic diagram of the elastic wave device according to the first embodiment of this application, as shown below. Figure 1 As shown, the elastic wave device includes a packaging substrate 40, a device chip 10 mounted on the packaging substrate, and a packaging layer 50 covering the packaging substrate 40 and the device chip 10.

[0047] The device chip 10 includes one of the following: a filter consisting of a surface acoustic wave filter, a thin-film acoustic resonator, a duplexer, and a dual filter. Figure 1 A surface acoustic wave (SAW) chip is shown, in which interdigital transducers 12 (IDT electrodes) are formed on the main surface 10a of a piezoelectric material. The piezoelectric material may be, for example, lithium tantalate (LT) or lithium niobate (LN). According to other examples, the device chip 10 includes a substrate formed by bonding a piezoelectric substrate to a support substrate. For example, the support substrate is made of sapphire, silicon, alumina, spinel, crystal, or glass.

[0048] Specifically, in this embodiment, the interdigital transducer 12 serves as a functional element of the device chip 10, used to realize the mutual conversion between electrical energy and acoustic energy. The interdigital transducer 12 may use materials such as Al, Cu, Ni, Au, W, or Mo. Figure 1 In the diagram, the interdigital transducer 12 is shown in a simplified manner, but it actually forms multiple comb-shaped input-side, output-side, and reflective electrodes.

[0049] The first welding contact layer 11 is located on the main surface 10a of the device chip 10 and is composed of multiple metal thin films. The constituent materials of the metal thin films include metals such as titanium, copper, chromium, nickel, or gold. The first welding contact layer 11 can be prepared by sputtering or vapor deposition processes. It is used to ensure the adhesion between the solder bumps 42 and the substrate of the device chip 10 during subsequent welding, thereby preventing desoldering or cracking between the solder bumps 42 and the substrate of the device chip 10 due to the difference in thermal expansion coefficients during high-temperature reflow soldering. The first welding contact layer 11 is also used to prevent inter-diffusion of substances between the solder bumps 42 and the substrate of the device chip 10 in a high-temperature environment, thereby ensuring the reliability of the electrical performance of the packaged device chip 10. The first welding contact layer 11 also has good weldability and corrosion resistance, thus ensuring that the solder bumps 42 and the substrate of the device chip 10 can form a good welding interface during the subsequent packaging process, thereby ensuring the bonding effect between the device chip 10 and the packaging substrate 40. Therefore, the first welding contact layer 11 improves the adhesion and diffusion properties of the solder bumps 42 to the substrate of the device chip 10, ensuring the reliability and effectiveness of the device chip packaging.

[0050] One side 40a of the packaging substrate 40 includes packaging wiring (not on) Figure 1 (Shown in image) and solder bumps 42; solder bumps 42 are connected to the package wiring and the first solder contact layer 11, respectively. According to one example, the package substrate 40 is a printed circuit board (PCB) substrate or a high-temperature co-fired ceramic (HTCC) substrate. According to other examples, the package substrate 40 is a low-temperature co-fired ceramic (LTCC) multilayer substrate formed of multiple dielectric layers. According to other examples, any substrate with wiring electrodes through the substrate can also serve as the package substrate. Passive components such as capacitors and inductors can be disposed inside the package substrate.

[0051] Specifically, the encapsulation wiring is used for the transmission of electrical signals between the internal and external circuits of the elastic wave device. The solder bump 42 is made of solder sheet or solder paste suitable for reflow soldering process. It is fixed on the encapsulation substrate 40 and connected to the encapsulation wiring through processes such as stencil printing (e.g., solder paste printing), electroplating, chemical plating, and nanoimprinting. Then, it is connected to the first solder contact layer 11 through reflow soldering process, thereby realizing the bonding between the encapsulation substrate 40 and the device chip 10. It should be noted that the solder bump is made of metals such as tin, lead, silver, and copper, as well as alloying elements. The materials of the support layer and the cover layer are thermosetting resins such as epoxy resin. Since the coefficient of thermal expansion is related to the chemical composition, crystal state, crystal structure, and bond strength of the material, the coefficient of thermal expansion of the solder bump is different from that of the support layer and the cover layer.

[0052] Furthermore, the elastic wave device also includes a support layer 20 and a cover layer 30 located on the main surface 10a of the device chip 10. The cover layer 30 is located on one side of the support layer 20; the main surface 10a of the device chip 10, the support layer 20, and the cover layer 30 form a cavity 60. Preferably, the support layer 20 is electrically insulating, and the material of the support layer 20 is, for example, a synthetic resin such as epoxy resin or polyimide. The cover layer 30 is electrically insulating. The material of the cover layer 30 is, for example, a synthetic resin such as epoxy resin or polyimide. The main component of the material of the cover layer 30 is preferably the same as the material of the support layer 20.

[0053] Specifically, a cavity 60 is formed by the main surface 10a of the device chip 10, the support layer 20 and the cover layer 30. The cavity 60 can provide a relatively closed and controlled propagation environment for surface acoustic waves. The cavity 60 helps to reduce the interference of the external environment on the propagation of sound waves, such as reducing the reflection and scattering of stray sound waves, thereby improving the purity of the signal and the signal-to-noise ratio of the device.

[0054] There is a gap between the solder bump 42 and the support layer 20 and the cover layer 30; the encapsulation layer 50 covers one side 40a of the encapsulation substrate 40 and the device chip 10.

[0055] Specifically, Figure 2 This is a schematic diagram of a portion of a traditional elastic wave device with a cavity structure, such as... Figure 2As shown, in conventional elastic wave devices with cavity structures, through-holes are formed in the support layer 20 and the cover layer 30 to achieve bonding between the device chip and the packaging substrate. Bumps 70 are formed in these through-holes in the form of solder balls or copper pillars. When the elastic wave device is subjected to thermal shock, delamination occurs between the bumps 70 and the cover layer 30 and support layer 20 due to the mismatch in the coefficients of thermal expansion between the bumps 70 and the materials constituting the support layer 20 and cover layer 30. In this embodiment, however, the solder bumps 42 have gaps between them and the support layer 20 and cover layer 30, and do not contact them. This avoids the delamination problem caused by the mismatch in the coefficients of thermal expansion between the bumps 70 and the materials constituting the support layer 20 and cover layer 30 when the elastic wave device is subjected to thermal shock.

[0056] In summary, the elastic wave device of this application solves the problem of easy delamination between the bumps in the through holes and the cover and support layers in traditional elastic wave devices with cavity structures, thereby improving the reliability of the packaged elastic wave device.

[0057] In some of these embodiments, the solder bumps are located outside the support layer and the cover layer.

[0058] In some of these embodiments, the distance between the solder bumps and the support layer is greater than 25 μm.

[0059] Specifically, the solder bumps are located outside the support layer and the cover layer. Since the thermal expansion coefficient of the solder bumps is different from that of the support layer and the cover layer, in this embodiment, the distance between the solder bumps and the support layer is set to be greater than 25μm, preferably 25 to 100μm, such as 30μm, 35μm and 40μm, etc. This can effectively prevent the solder bumps and the support layer from contacting each other when they expand at high temperature, causing deformation of the support layer, thereby ensuring the reliability and effectiveness of the elastic wave device.

[0060] In some of these embodiments, the spacing between two adjacent solder bumps is greater than 150 μm.

[0061] Specifically, Figure 3 This is a top view of a cross-section of an elastic wave device according to an embodiment, the cross-section being parallel to one side of the packaging substrate, as shown below. Figure 3 As shown in the figure, reference numeral 42 represents a solder bump, reference numeral 30 represents a cover layer, d1 represents the first spacing between two adjacent solder bumps 42, and d2 represents the second spacing between two adjacent solder bumps 42. In order to prevent short circuits in the packaged chip due to the small spacing between solder joints, both the first spacing d1 and the second spacing d2 are greater than 150μm, thereby ensuring the effectiveness of the electrical performance of the packaged chip.

[0062] In some embodiments, the encapsulation layer fills the gap between the solder bumps and the support layer and the cover layer.

[0063] The encapsulation layer is composed of encapsulation materials such as epoxy resin, polyimide, or silicone. It is formed by covering one side of the encapsulation substrate and the device chip through molding, potting, or spray molding processes. This encapsulation layer fills the gaps between the solder bumps, support layer, and cover layer. This encapsulation layer has the following characteristics: good waterproof performance, preventing moisture from penetrating into the chip and causing electrochemical corrosion or short circuits; good mechanical strength and toughness; and certain thermal conductivity, helping to transfer heat generated inside the device chip to the surrounding environment through the encapsulation, reducing the operating temperature of the device chip and preventing overheating that could lead to performance degradation or shortened lifespan. The encapsulation layer is preferably composed of molding materials with matching coefficients of thermal expansion to reduce internal stress caused by temperature changes and prevent cracking of the encapsulation layer or solder joint failure. Therefore, the encapsulation layer ensures the waterproof performance, mechanical strength, and thermal conductivity of the elastic wave device.

[0064] In some embodiments, the gap between the main surface of the device chip and one side of the packaging substrate is filled with filler; the minimum particle size of the filler is smaller than the minimum particle size of the material constituting the packaging layer. Specifically, the gap between the main surface of the device chip and one side of the packaging substrate is filled with filler that has low stress, high fluidity, and good thermal conductivity, and the minimum particle size of the filler is smaller than the minimum particle size of the material constituting the packaging layer. By using filler, the gap between the main surface of the chip and one side of the packaging substrate is completely filled, thereby ensuring the reliability of the elastic wave device packaging.

[0065] The embodiments are described and illustrated below through preferred embodiments.

[0066] The elastic wave device of this preferred embodiment includes a device chip, a support layer, a cover layer, a packaging substrate, and a packaging layer;

[0067] The device chip includes a first solder contact layer and interdigital transducers; both the first solder contact layer and the interdigital transducers are located on the main surface of the device chip.

[0068] One side of the packaging substrate includes packaging wiring and solder bumps; the solder bumps are connected to the packaging wiring and the first solder contact layer respectively; the spacing between two adjacent solder bumps is greater than 150μm;

[0069] The support layer is located on the main surface of the device chip; the cover layer is located on one side of the support layer; the main surface of the device chip, the support layer, and the cover layer form a cavity.

[0070] Solder bumps are located outside the support layer and the cover layer, and the distance between the solder bumps and the support layer is 25-50 μm; the encapsulation layer covers one side of the encapsulation substrate and the device chip, and the encapsulation layer is made of materials such as epoxy resin, polyimide or silicone.

[0071] The gap between the main surface of the device chip and one side of the packaging substrate is filled with filler.

[0072] The minimum particle size of the filler is smaller than the minimum particle size of the material constituting the encapsulation layer.

[0073] The elastic wave device of this preferred embodiment solves the problem of easy delamination between the protrusions and the cover layer and support layer in traditional elastic wave devices with cavity structures, thereby improving the reliability of the elastic wave device.

[0074] The following embodiment provides a chip packaging method. Figure 4 This is a flowchart of a chip packaging method according to one embodiment. Figures 5 to 8 This is a schematic diagram of steps S201 to S204 of the chip packaging method in this embodiment, as shown below. Figure 4 As shown, the process includes the following steps:

[0075] Step S201: A first welding contact layer 11 is formed on the main surface 10a of the device chip 10.

[0076] Specifically, Figure 5 This is a schematic diagram of the chip packaging structure in step S201 of this embodiment, as shown below. Figure 5 As shown, in this embodiment, the first welding contact layer 11 is located on the main surface 10a of the device chip 10 and is composed of multiple layers of metal thin films. The constituent materials of the metal thin films are titanium, copper, chromium, nickel, or gold. This first welding contact layer 11 can be fabricated by sputtering or vapor deposition processes. The first welding contact layer 11 improves the adhesion and diffusion properties between the solder bumps 42 and the device chip 10, ensuring the reliability and effectiveness of the chip packaging. It should be noted that in some other embodiments, when the chip contains a passive device 80, it is not necessary to form the first welding contact layer 11 on the main surface 10a of the passive device 80, wherein the passive device 80 includes components such as resistors and capacitors.

[0077] Step S202: Based on the position of the first solder contact layer 11, a solder area is provided on one side 40a of the packaging substrate 40; solder bumps 42 are applied to the solder area.

[0078] Specifically, Figure 6This is a schematic diagram of the chip packaging structure in step S202 of this embodiment. Based on the position of the first solder contact layer 11 on the main surface 10a of the device chip 10, a solder area is correspondingly set on the packaging substrate 40. Solder bumps 42 are applied to the solder area through processes such as stencil printing (e.g., solder paste printing), electroplating, chemical plating, and nanoimprinting. These solder bumps 42 contact the package wiring 43. The solder bumps 42 can be solder sheets or solder paste suitable for reflow soldering processes. Compared to the existing chip flip-chip technology that forms both solder balls and copper pillars on the first solder contact layer of the chip, this application applies solder bumps 42 to the packaging substrate 40, eliminating the need to form solder balls and copper pillars on the first solder contact layer 11 of the device chip 10. This reduces chip packaging costs while improving the accuracy of subsequent soldering between the solder bumps 42 and the first solder contact layer 11.

[0079] In step S203, the main surface 10a of the device chip 10 is attached to one side 40a of the packaging substrate 40, so that the first solder contact layer 11 corresponds to the solder area; the main surface 10a of the device chip 10 is bonded to one side 40a of the packaging substrate 40 through the solder bump 42.

[0080] Specifically, Figure 7 This is a schematic diagram of the chip packaging structure in step S203 of this embodiment. An automatic pick-and-place machine is used to mount the main surface 10a of the device chip 10 and the passive device 80 onto one side 40a of the packaging substrate 40, ensuring that the first solder contact layer 11 corresponds one-to-one with the solder area, thereby bringing the device chip 10 and the passive device 80 into contact with the solder bumps 42. A reflow soldering process melts the solder, forming a liquid solder bridge, allowing the main surface 10a of the device chip 10 and the passive device 80 to bond with one side 40a of the packaging substrate 40. Finally, rapid cooling quickly solidifies the solder bumps, forming stable solder joints, thus ensuring the stability of the bonding between the device chip 10 and the packaging substrate 40. It should be noted that in some other embodiments, after mounting the main surface of the device chip 10 onto one side 40a of the packaging substrate 40, AOI (Automatic Optical Inspection) or manual visual inspection is performed to ensure the correct soldering position of the device chip 10 and the passive device 80.

[0081] In step S204, a packaging layer 50 is formed by covering one side 40a of the packaging substrate 40 and the device chip 10 with a molding compound.

[0082] Specifically, Figure 8 This is a schematic diagram of the chip packaging structure in step S204 of this embodiment, as shown below. Figure 8As shown, the aforementioned encapsulation material includes encapsulation materials such as epoxy resin, polyimide, or silicone, which are used to cover one side 40a of the encapsulation substrate 40 and the device chip 10 to form an encapsulation layer 50 through molding, potting, or spray molding processes.

[0083] Step S205: Cut the packaging substrate 40 and the packaging layer 50 to obtain a single packaged chip.

[0084] Specifically, the packaging substrate 40 and the packaging layer 50 are cut using methods such as laser cutting or mechanical cutting to obtain a single packaged chip. These steps ensure that the cut edges are neat and do not damage the interior of the packaged device.

[0085] In summary, this application achieves the following: a first solder contact layer 11 is formed on the main surface 10a of the device chip 10; a solder region is formed on one side 40a of the packaging substrate 40 according to the position of the first solder contact layer 11; solder bumps 42 are applied to the solder region; the main surface 10a of the device chip 10 is mounted onto one side 40a of the packaging substrate 40, so that the first solder contact layer 11 corresponds to the solder region; the main surface 10a of the device chip 10 is bonded to one side 40a of the packaging substrate 40 through the solder bumps 42; one side 40a of the packaging substrate 40 and the device chip 10 are covered with a molding compound to form a packaging layer 50; and the packaging substrate 40 and the packaging layer 50 are cut to obtain a single packaged chip. By using the chip packaging method of this application, the problem of high bump manufacturing cost in the existing flip chip packaging methods is solved, achieving both reliability and effectiveness in chip packaging while reducing chip packaging costs.

[0086] In some embodiments, the main surface of the device chip is mounted onto one side of the packaging substrate, including the following steps:

[0087] Step S301: Using temporary bonding material, the main surface of the device chip is attached to one side of the packaging substrate.

[0088] Specifically, temporary bonding materials include peelable bonding adhesives, polymer films, and low-melting-point metals, used to mount the main surface of the chip onto one side of the packaging substrate, thereby temporarily fixing the position of the chip and the packaging substrate. During subsequent high-temperature soldering, this temporary bonding material can be peeled off by chemical or mechanical means. Through the above steps, the accuracy of the bonding between the main surface of the chip and one side of the packaging substrate is ensured.

[0089] In some embodiments, solder bumps are used to bond the main surface of the device chip to one side of the package substrate, including the following steps:

[0090] Step S401: The solder on one side of the packaging substrate is processed by reflow soldering to bond the main surface of the device chip to one side of the packaging substrate.

[0091] Specifically, the reflow soldering process joins the main surface of the chip with one side of the packaging substrate. The solder joints at the joint have good consistency and high mechanical strength, which reduces the risk of electrical failure caused by incomplete soldering or defects and improves the reliability of the chip.

[0092] In some embodiments, the packaging substrate and packaging layer are cut, including the following steps:

[0093] Step S501: Cut the packaging substrate and packaging layer along the preset cutting path.

[0094] Specifically, the packaging substrate and packaging layer are precisely cut along a preset cutting path, ensuring the reliability of the resulting single packaged chip.

[0095] In some embodiments, after forming the solder area on one side of the packaging substrate, the following steps are further included:

[0096] Step S601: A second solder contact layer is formed in the solder area of ​​the packaging substrate.

[0097] Specifically, the second solder contact layer of the aforementioned packaging substrate can be made of OSP (Organic Solderability Preservative) to prevent the metal on the packaging substrate from being oxidized. During subsequent reflow soldering, the OSP film decomposes at high temperatures, thereby ensuring a good bond between the solder bumps and the packaging substrate. In other embodiments, the second solder contact layer can also be a metal or alloy such as copper, nickel, or gold, used to ensure a good bond between the solder bumps and the packaging substrate.

[0098] The present embodiment will now be described and illustrated through preferred embodiments.

[0099] The preferred embodiment of the chip packaging method includes the following steps:

[0100] Step S801: A first solder contact layer is formed on the main surface of the device chip.

[0101] Step S802: Based on the position of the first welding contact layer, a solder area is set on one side of the packaging substrate.

[0102] Step S803: Form a second solder contact layer in the solder area of ​​the package substrate; apply solder bumps in the solder area.

[0103] In step S804, the main surface of the device chip is attached to one side of the packaging substrate using temporary bonding material, so that the first solder contact layer corresponds to the solder area; the solder bumps on one side of the packaging substrate are processed by reflow soldering to bond the main surface of the device chip to one side of the packaging substrate.

[0104] Step S805: Fill the gap between the main surface of the device chip and one side of the packaging substrate with filler.

[0105] Step S806: A protective encapsulation layer is formed by covering one side of the encapsulation substrate and the device chip with a molding compound.

[0106] Step S807: Cut the packaging substrate and packaging protective layer along the preset cutting path to obtain a single packaged chip.

[0107] Compared to the existing flip-chip technology that forms solder balls and copper pillars on the first solder contact layer of the chip, the chip packaging method of this preferred embodiment applies solder to the packaging substrate and does not require the formation of solder balls and copper pillars on the first solder contact layer of the device chip. This achieves both the reliability and effectiveness of chip packaging while reducing chip packaging costs.

[0108] This embodiment also provides a radio frequency module, including passive devices and multiple elastic wave devices as described in the above embodiments;

[0109] Passive devices include capacitors, resistors, and inductors.

[0110] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0111] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0112] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0113] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. An elastic wave device, characterized in that, This includes the device chip, support layer, cover layer, packaging substrate, and packaging layer; The device chip includes a first solder contact layer and an interdigital transducer; both the first solder contact layer and the interdigital transducer are located on the main surface of the device chip. One side of the packaging substrate includes packaging wiring and solder bumps; the solder bumps are respectively connected to the packaging wiring and the first solder contact layer; The support layer is located on the main surface of the device chip; the cover layer is located on one side of the support layer; the main surface of the device chip, the support layer, and the cover layer form a cavity; There is a gap between the solder bump and the support layer and the cover layer; The encapsulation layer covers one side of the encapsulation substrate and the device chip.

2. The elastic wave device according to claim 1, characterized in that, The solder bumps are located outside the support layer and the cover layer.

3. The elastic wave device according to claim 1, characterized in that, The distance between the solder bump and the support layer is greater than 25 μm.

4. The elastic wave device according to claim 1, characterized in that, The spacing between two adjacent solder bumps is greater than 150 μm.

5. The elastic wave device according to claim 1, characterized in that, The encapsulation layer fills the gap between the solder bumps and the support layer and the cover layer.

6. The elastic wave device according to claim 1, characterized in that, The gap between the main surface of the device chip and one side of the packaging substrate is filled with filler; the minimum particle size of the filler is smaller than the minimum particle size of the constituent material of the packaging layer.

7. A chip packaging method, applicable to the elastic wave device according to any one of claims 1 to 6, characterized in that, include: A first welding contact layer is formed on the main surface of the device chip; Based on the position of the first welding contact layer, a solder area is provided on one side of the packaging substrate; Apply solder bumps to the solder area; The main surface of the device chip is mounted on one side of the packaging substrate, so that the first solder contact layer corresponds to the solder area; the main surface of the device chip is bonded to one side of the packaging substrate through the solder bumps; An encapsulation layer is formed by covering one side of the encapsulation substrate and the device chip with a molding compound. The packaging substrate and the packaging layer are cut to obtain a single packaged chip.

8. The chip packaging method according to claim 7, characterized in that, The step of mounting the main surface of the device chip onto one side of the packaging substrate includes: The main surface of the device chip is attached to one side of the packaging substrate using a temporary bonding material.

9. The chip packaging method according to claim 7, characterized in that, The step of bonding the main surface of the device chip to one side of the packaging substrate via the solder bumps includes: The solder bumps on one side of the packaging substrate are processed by reflow soldering to bond the main surface of the device chip to one side of the packaging substrate.

10. The chip packaging method according to claim 7, characterized in that, After setting the solder area on one side of the packaging substrate, the method further includes: A second solder contact layer is formed in the solder region of the packaging substrate.

11. A radio frequency module, characterized in that, Includes passive devices and the elastic wave device according to any one of claims 1 to 6; The passive devices include capacitors, resistors, and inductors.

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