A verification method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a verification method, device, electronic device and readable storage medium, the method comprising: obtaining data transmission parameters, benchmark test program and reference model corresponding to the design to be tested; burning the design to be tested into the programmable logic area of ​​the programmable logic chip, and loading the reference model into the processing system of the programmable logic chip; re-encoding each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions to obtain a target test program; controlling the design to be tested and the reference model to execute the target test program respectively; obtaining a first execution result of the design to be tested and a second execution result of the reference model; and determining that the design to be tested has an operation error when the first execution result and the second execution result do not match. The embodiment of the present invention simplifies the verification process of the design to be tested and improves the verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a verification method, device, electronic device and readable storage medium. Background Art

[0002] In the related art, the verification of High-Level Synthesis (HLS) design usually adopts the verification method of software simulation, and the speed of software simulation is often slow, in tens or hundreds of kilohertz, and debugging options such as waveform dump or debug information display will further reduce the simulation speed, and the overall verification efficiency is low. FPGA-based acceleration methods usually provide higher performance gains, usually running at tens or hundreds of megahertz. Therefore, the industry has widely adopted FPGA prototype verification as the standard method for pre-silicon verification. However, the design of FPGA prototypes is very cumbersome and the verification process is relatively complicated. Summary of the invention

[0003] The embodiments of the present invention provide a verification method, an apparatus, an electronic device and a readable storage medium, which can solve the problems of low verification efficiency and complex verification process for a design to be tested in the related art.

[0004] An embodiment of the present invention discloses a verification method, which is applied to a programmable logic chip. The method includes:

[0005] Obtain data transmission parameters, benchmark test programs and reference models corresponding to the design under test;

[0006] Burning the design to be tested into a programmable logic area of ​​the programmable logic chip, and loading the reference model into a processing system of the programmable logic chip;

[0007] Re-encode each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions to obtain a target test program; the communication control instructions are instructions defined according to the instruction set architecture of the programmable logic chip;

[0008] Control the design to be tested and the reference model to respectively execute the target test program;

[0009] Obtaining a first execution result of the design to be tested and a second execution result of the reference model;

[0010] When the first execution result and the second execution result do not match, it is determined that the design under test has an operation error.

[0011] Optionally, burning the design to be tested into a programmable logic area of ​​the programmable logic chip includes:

[0012] Obtaining port information of the design to be tested;

[0013] Generate a hardware wrapping structure according to the port information; the hardware wrapping structure is used to connect the design to be tested and the processor in the programmable logic chip;

[0014] Perform layout and routing on the design to be tested and the hardware package structure using integrated components to generate a bitstream file;

[0015] The design to be tested and the hardware package structure are burned into a programmable logic area of ​​the programmable logic chip based on the bitstream file.

[0016] Optionally, the communication control instruction includes a storage instruction and a loading instruction; the storage instruction is used to store the data generated by the design to be tested into a hardware storage module of the programmable logic area; the loading instruction is used to load the data in the hardware storage module into a first register of the programmable logic area;

[0017] The obtaining of the first execution result of the design to be tested and the second execution result of the reference model includes:

[0018] Inserting the storage instruction and the load instruction after each operation instruction in the target test program, so that after the design under test executes one operation instruction, the storage instruction and the load instruction are executed to store a first execution result corresponding to the operation instruction in the hardware storage module, and load the first execution result from the hardware storage module into the first register;

[0019] The first execution result is read from the first register.

[0020] Optionally, after obtaining the first execution result of the design to be tested and the second execution result of the reference model, the method further includes:

[0021] Writing the first execution result into a hardware buffer, and writing the second execution result into a software buffer;

[0022] Reading the first execution result from the hardware buffer, and reading the second execution result from the software buffer;

[0023] The first execution result is compared with the second execution result.

[0024] Optionally, the storage spaces of the hardware buffer and the software buffer are the same in size and are both first-in-first-out data buffer storage structures; the method further includes:

[0025] When the hardware buffer is full, the operation of the design to be tested is interrupted, and the reference model is waited for to write a second execution result to the software buffer.

[0026] Optionally, the method further comprises:

[0027] When the first execution result and the second execution result do not match, taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip;

[0028] The state information is imported into simulation software for simulation to debug the design under test.

[0029] On the other hand, an embodiment of the present invention discloses a verification device, which is applied to a programmable logic chip, and the device includes:

[0030] A first acquisition module is used to acquire data transmission parameters, benchmark test programs and reference models corresponding to the design to be tested;

[0031] A preprocessing module, used for burning the design to be tested into a programmable logic area of ​​the programmable logic chip, and loading the reference model into a processing system of the programmable logic chip;

[0032] An encoding module, used for re-encoding each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions, so as to obtain a target test program; the communication control instructions are instructions defined according to the instruction set architecture of the programmable logic chip;

[0033] A control module, used for controlling the design to be tested and the reference model to respectively execute the target test program;

[0034] A second acquisition module, used to acquire a first execution result of the design to be tested and a second execution result of the reference model;

[0035] A verification module is used to determine that the design under test has an operation error when the first execution result and the second execution result do not match.

[0036] Optionally, the preprocessing module includes:

[0037] A port information acquisition submodule, used to acquire the port information of the design to be tested;

[0038] A generating submodule, used for generating a hardware package structure according to the port information; the hardware package structure is used for connecting the design to be tested with the processor in the programmable logic chip;

[0039] A layout and routing submodule, used to perform layout and routing on the design to be tested and the hardware package structure using integrated components to generate a bitstream file;

[0040] The burning submodule is used to burn the design to be tested and the hardware package structure into the programmable logic area of ​​the programmable logic chip based on the bit stream file.

[0041] Optionally, the communication control instruction includes a storage instruction and a loading instruction; the storage instruction is used to store the data generated by the design to be tested into a hardware storage module of the programmable logic area; the loading instruction is used to load the data in the hardware storage module into a first register of the programmable logic area;

[0042] The second acquisition module includes:

[0043] an instruction insertion submodule, configured to insert the storage instruction and the load instruction after each operation instruction in the target test program, so that after the design under test executes an operation instruction, the storage instruction and the load instruction are executed to store a first execution result corresponding to the operation instruction in the hardware storage module, and load the first execution result from the hardware storage module into the first register;

[0044] A reading submodule is used to read the first execution result from the first register.

[0045] Optionally, the device further comprises:

[0046] A result writing module, used for writing the first execution result into a hardware buffer, and writing the second execution result into a software buffer;

[0047] A result reading module, used for reading the first execution result from the hardware buffer and reading the second execution result from the software buffer;

[0048] A result comparison module is used to compare the first execution result with the second execution result.

[0049] Optionally, the storage space sizes of the hardware buffer and the software buffer are the same, and both are first-in-first-out data buffer storage structures; the device further includes:

[0050] An interrupt module is used to interrupt the operation of the design to be tested when the hardware buffer is full, and wait for the reference model to write a second execution result to the software buffer.

[0051] Optionally, the device further comprises:

[0052] a snapshot module, configured to take a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip when the first execution result and the second execution result do not match;

[0053] The information import module is used to import the state information into the simulation software for simulation so as to debug the design to be tested.

[0054] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned verification method.

[0055] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned verification method.

[0056] The embodiments of the present invention include the following advantages:

[0057] The embodiment of the present invention provides a verification method, which can map the design to be tested and the reference model to the same FPGA chip for operation, and significantly improve the verification speed by using FPGA hardware acceleration. Moreover, compared with the traditional FPGA prototype verification method, the embodiment of the present invention does not need to design an FPGA prototype, nor does it need to perform complex configuration operations on the design to be tested. It only needs to recompile the benchmark test program into a target test program according to the data transmission parameters of the design to be tested and the instruction set architecture of the FPGA chip. According to the execution results of the design to be tested and the reference model on the target test program, it can be determined whether the design to be tested has an error in operation, which simplifies the verification process and improves the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0059] Figure 1 is a flowchart of steps of an embodiment of a verification method of the present invention;

[0060] Figure 2 It is a schematic diagram of the structure of a programmable logic chip of the present invention;

[0061] Figure 3is a structural block diagram of an embodiment of a verification device of the present invention;

[0062] Figure 4 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0065] Method Embodiment

[0066] Reference Figure 1 , shows a flowchart of a verification method embodiment of the present invention, the method may specifically include the following steps:

[0067] Step 101, obtaining data transmission parameters, benchmark test programs and reference models corresponding to the design to be tested;

[0068] Step 102: Burn the design to be tested into a programmable logic area of ​​a programmable logic chip, and load the reference model into a processing system of the programmable logic chip;

[0069] Step 103, re-encode each instruction in the benchmark test program according to the data transmission parameter and the encoding format corresponding to the preset communication control instruction to obtain a target test program; the communication control instruction is an instruction defined according to the instruction set architecture of the programmable logic chip;

[0070] Step 104, controlling the design to be tested and the reference model to respectively execute the target test program;

[0071] Step 105: Obtain a first execution result of the design to be tested and a second execution result of the reference model;

[0072] Step 106: When the first execution result and the second execution result do not match, determine that the design under test has an operation error.

[0073] The verification method provided in the embodiment of the present invention can be applied to a programmable logic chip, that is, a field programmable gate array (FPGA) chip. An FPGA chip (or FPGA system on chip) includes not only a programmable gate array circuit, but also one or more on-chip processors. Among them, the programmable gate array circuit is usually called programmable logic (PL); the on-chip processor is usually an ARM processor, which is called a processing system (PS).

[0074] The design under test (DUT) refers to the circuit design or implementation to be tested in prototype verification. Exemplarily, the design under test can be a register transfer level (RTL) circuit or other hardware design. It should be noted that the RTL circuit is a common hardware description level circuit. The RTL circuit describes the behavior and structure of the digital circuit and is represented using the abstract level of the register transfer level. The RTL circuit description is usually written in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, and SystemVerilog HDL. Designers can use the RTL level description to define and implement the required digital circuit functions, and then use synthesis tools to convert the RTL level description into a physical implementation in a field programmable gate array (FPGA). In the field of FPGA, chip design and verification, the RTL level description is very important for design, verification and debugging. It provides an abstract level that enables designers to describe circuit behavior at a higher level of abstraction, and use appropriate tools for simulation, verification and synthesis, and finally generate a bitstream file that can be configured into the FPGA chip to implement specific digital circuit functions.

[0075] The reference model is used to implement the same function as the design under test. During the verification of the design under test, the data generated when the reference model is called can be considered correct and used as reference data for comparison with the data generated by the design under test. It is understandable that different reference models are generated for different designs under test. As an example, before the design under test is subjected to high-level synthesis, a source design model of the design under test can be generated based on the design code of the design under test in C / C++ language. The source design model has the same algorithm function as the design under test and can be used as a reference model of the design under test.

[0076] In an embodiment of the present invention, the design to be tested that needs to be verified can be burned into the programmable logic area of ​​the FPGA chip, that is, the PL end; the reference model can be loaded into the processing system of the FPGA chip, that is, the PS end. Exemplarily, the reference model can be generated by a software simulator, and the reference model can be integrated into the software simulator, and the software simulator can be mounted on the PS end of the FPGA chip for operation. Among them, the software simulator (Emulator, EMU) is a software program written in a high-level language to simulate the operating state of the CPU. In an embodiment of the present invention, an integrated reference model such as NEMU and ISA simulator can be used.

[0077] The data transmission parameters of the design under test are used to indicate the information required for data communication between the design under test and the FPGA chip, which may specifically include the buffer address of the design under test, the data type required by the design under test, the data block size, the data block address, the checksum, and the like. Among them, the buffer address of the design under test refers to the address of the data required by the design under test in the buffer inside the design under test; the data block address refers to the base address of the data block stored in the hardware storage module of the FPGA chip; the data block size refers to the size of the data block to be transmitted between the design under test and the FPGA chip; the data type refers to the type of data to be transmitted between the design under test and the FPGA chip. The checksum refers to the value used to return the execution status of the control instruction (execute instruction), which is generally 0. As an example, the data transmission parameters of the design under test can be determined by parsing the C / C++ design port of the design under test.

[0078] The benchmark test program includes a series of programs for testing the performance or correctness of the design to be tested. In an embodiment of the present invention, each instruction in the benchmark test program can be re-encoded according to the data transmission parameters of the design to be tested and the encoding format corresponding to the preset communication control instructions to obtain a target test program. Among them, the preset communication control instructions in the embodiment of the present invention are instructions defined according to the instruction set architecture of the processor running on the FPGA chip. The instruction set architecture can be a RISC-V instruction set or an ARM instruction set.

[0079] It should be noted that the communication control instructions in the embodiment of the present invention may include a load instruction, a store instruction, and a control instruction. The load instruction is used to load the data in the hardware storage module of the FPGA chip into the design to be tested; the store instruction is used to store the data in the design to be tested into the hardware storage module of the FPGA chip; and the control instruction is used to start the control function of the design to be tested. The hardware storage module of the FPGA chip may include a cache on the PL side, a CPU memory, and the like.

[0080] According to the R-type RISC-V instruction set definition, the data transmission parameters of the design to be tested can be encoded into the source register, destination register and operation code of the communication control instruction. As an example, the data block address can be encoded into the first source register corresponding to the communication control instruction, the buffer address inside the design to be tested can be encoded into the second source register, and the first operation code can be encoded according to the data block size, and the second operation code can be encoded according to the data type. Exemplarily, referring to Table 1, the encoding format of a set of communication control instructions provided in an embodiment of the present invention is shown:

[0081] Table 1

[0082]

[0083] Among them, the custom_load instruction is a loading instruction, which is used to load the data in the hardware storage module of the FPGA chip into the design under test; the custom_store instruction is a storage instruction, which is used to store the data in the design under test into the hardware storage module of the FPGA chip; the custom_load_extend instruction is a large-capacity loading instruction, which has the same function as the custom_load instruction and can load a larger capacity of data; the custom_store_extend instruction is a large-capacity storage instruction, which has the same function as the custom_store instruction and can store a larger capacity of data; the custom_execute instruction is a control instruction, which is used to start the control function of the design under test.

[0084] It should be noted that in the R-type RISC-V instruction set, all operations read the rs1 and rs2 registers as source operands and write the results to register rd. {funct[4:2],rd} is used to encode the array size information of the load instruction and the store instruction. r d Used to encode the array size information of the load_extend instruction and the store_extend instruction; the funct[1:0] field is used to select the data type. gpr[rd] is used to instruct the execute instruction to write the checksum value back to the destination register.

[0085] Taking the custom_load instruction in Table 1 as an example, according to the R-type RISC-V instruction set definition, the buffer address inside the design to be tested can be encoded into rs2, the data block address in the hardware storage module of the FPGA chip can be encoded into rs1, the data block size can be encoded into funct[4:2],rd, and the data type can be encoded into funct[1:0].

[0086] The benchmark test program in the embodiment of the present invention may be a code in C / C++ language. In the embodiment of the present invention, the test cases in the benchmark test program may be converted into a target test program that can be used for the coordinated operation of software and hardware based on the general control instructions shown in Table 1. For example, in the benchmark test program, the encryption (aes) function of the design to be tested is tested by calling the following function:

[0087] aes256_encrypt_ecb(key,enckey,deckey,k,buf)

[0088] In an embodiment of the present invention, the data transmission parameters of the design under test, such as the data type and data block size required by the design under test, are determined by analyzing the design under test. Then, based on the data transmission parameters, the function calls in the benchmark test program can be automatically converted into a target test program that can be used for the coordinated operation of software and hardware:

[0089] ROCC_INTERFACE_LOAD(k_base,k,32,BT);

[0090] ROCC_INTERFACE_LOAD(key_base,key,32,BT);

[0091] ROCC_INTERFACE_LOAD(enckey_base,enckey,32,BT);

[0092] ROCC_INTERFACE_LOAD(deckey_base,deckey,32,BT);

[0093] ROCC_INTERFACE_LOAD(buf_base,buf,16,BT);

[0094] ROCC_INTERFACE_EXEC(checksum_inst);

[0095] ROCC_INTERFACE_STORE(buf_base,buf,16,BT)

[0096] The target test program in the embodiment of the present invention has the same functions as the benchmark test program, but the target test program can call the functions of the design under test through general control instructions, and the converted target test program can be directly run in the design under test and the software simulator or reference model at the same time.

[0097] After the target test program is generated, the design under test and the reference model can be run synchronously on the FPGA chip. The design under test and the reference model respectively execute the same target test program and obtain the first execution result of the design under test and the second execution result of the reference model. By comparing the execution results of the design under test and the reference model for the target test program, it is determined whether there are errors in the design under test, and then the errors are debugged and repaired.

[0098] It should be noted that, in an embodiment of the present invention, the first execution result may include the CPU state information generated when the design under test is running, and the second execution result may include the CPU state information generated when the reference model is running, for example, the CPU state information of the software simulator that calls the reference model. The design under test runs the same benchmark program, and the design under test and the reference model can maintain instruction-level operation synchronization through the on-chip bus. Among them, the CPU state information may include the value of the program pointer, the value of the general register, etc. In actual applications, the specific content of the CPU state information can be specified according to the actual situation and specific verification requirements.

[0099] The embodiment of the present invention maps the design to be tested and the reference model to the same FPGA chip for operation, and significantly improves the verification speed by using FPGA hardware acceleration. Moreover, compared with the traditional FPGA prototype verification method, the embodiment of the present invention does not need to design an FPGA prototype, nor does it need to perform complex configuration operations on the design to be tested. It only needs to recompile the benchmark test program into a target test program according to the data transmission parameters of the design to be tested and the instruction set architecture of the FPGA chip. According to the execution results of the design to be tested and the reference model on the target test program, it can be determined whether the design to be tested has an error in operation, which simplifies the verification process and improves the verification efficiency.

[0100] Further, in an embodiment of the present invention, before the design to be tested is burned into the FPGA chip, the chip code of the design to be tested can also be modified, the chip code of the design to be tested can be modified, and the data transmitted by each data interface of the design to be tested can be connected to the top-level module of the design to be tested, so as to collect the intermediate data of the design to be tested and the state value during the operation process. Specifically, the chip code of the design to be tested can be analyzed, and a data transmission path pointing to the top-level module can be added for each data interface of the design to be tested, so that the data transmitted by each data interface of the design to be tested can be connected to the top-level module without changing the original operation logic of the design to be tested, so that the external module or component of the design to be tested can obtain it. Among them, the top-level module is a module containing all other modules in the design to be tested, and the top-level module is not instantiated in any other module. After the data in the design to be tested is connected to the top-level module, the data to be verified can be drawn from the top-level module and connected to the verification system, so as to facilitate the analysis and verification of these data. Compared with the traditional FPGA prototype verification method, the embodiment of the present invention modifies the chip code of the design under test, connects the data transmitted by each data interface of the design under test to the top-level module of the design under test, and burns the design under test into the PL area of ​​the FPGA chip according to the modified chip code, so as to facilitate the collection and analysis of intermediate data and status values ​​generated during the operation of the design under test, and increase the visibility of the details of the design under test.

[0101] In an optional embodiment of the present invention, step 102 of burning the design to be tested into the programmable logic area of ​​the programmable logic chip includes:

[0102] Step S11, obtaining the port information of the design to be tested;

[0103] Step S12: generating a hardware package structure according to the port information; the hardware package structure is used to connect the design to be tested and the processor in the programmable logic chip;

[0104] Step S13, using integrated components to perform layout and routing on the design to be tested and the hardware package structure to generate a bitstream file;

[0105] Step S14: Burn the design to be tested and the hardware package structure into the programmable logic area of ​​the programmable logic chip based on the bitstream file.

[0106] In an embodiment of the present invention, the port information of the design to be tested can be analyzed, and a hardware package structure of the design to be tested can be generated based on the port information, which is used to connect the design to be tested with the processor of the FPGA chip to realize data interaction between the design to be tested and the processor core of the FPGA chip. The integrated components are used to perform layout and routing on the design to be tested and the hardware package structure to generate a bitstream file. Exemplarily, Vivado can be used to perform comprehensive layout and routing, and a programming tool can be used to convert it into a bitstream compatible with the FPGA chip, which contains information for programming and configuring the internal logic and interconnection resources of the FPGA. Finally, the design to be tested and the hardware package structure are burned to the PL end of the FPGA chip.

[0107] Reference Figure 2 , shows a schematic diagram of the structure of a programmable logic chip provided by an embodiment of the present invention. Figure 2 As shown, the FPGA chip includes a programmable logic area (PL end) and a processing system (PS end), wherein the PL end is provided with a hardware package structure, which can adopt a RoCC interface, and can use the chisel language to automatically add a decoding unit (for decoding communication instructions between the design to be tested and the CPU core of the FPGA chip), a finite state machine, a register bank, etc. outside the design to be tested, and can also include components such as a data bus conversion (for converting the RoCC cache bus to the interface protocol required by the accelerator). The hardware package structure can receive control instructions sent by the processor core of the FPGA chip and accept monitoring by the processor core. The data required by the design to be tested, as well as the first execution result generated during the operation, can be transmitted through the memory of the hardware package structure and the hardware storage structure of the FPGA chip.

[0108] In an embodiment of the present invention, a hardware package structure can be configured according to the port information of the design to be tested, such as the data type, data block size, and base address required by the design to be tested. Specifically, these parameters can be automatically configured by parsing the IP port information of the design to be tested, and a corresponding hardware package structure can be generated to achieve the connection between the RISC-V instruction extension accelerator and the RISC-V processor.

[0109] Optionally, the communication control instruction includes a storage instruction and a load instruction; the storage instruction is used to store the data generated by the design to be tested in the hardware storage module of the programmable logic area; the load instruction is used to load the data in the hardware storage module into the first register of the programmable logic area. Step 105 of obtaining the first execution result of the design to be tested and the second execution result of the reference model includes:

[0110] Step S21, inserting the storage instruction and the load instruction after each operation instruction in the target test program, so that after the design under test executes an operation instruction, the storage instruction and the load instruction are executed to store a first execution result corresponding to the operation instruction in the hardware storage module, and load the first execution result from the hardware storage module into the first register;

[0111] Step S22: Read the first execution result from the first register.

[0112] In an embodiment of the present invention, a storage instruction and a load instruction can be inserted after each operation instruction in the target test program, so that after the design to be tested executes the operation instruction to obtain the first execution result, the first execution result can be stored in the hardware storage module of the FPGA chip by executing the storage instruction, and the first execution result in the hardware storage module can be loaded into the first register by executing the load instruction, so that the checker ENCORE on the FPGA chip reads the first execution result from the first register and compares it with the second execution result of the reference model to verify whether the design to be tested has any operation error.

[0113] Among them, the checker can be configured at the PL end of the FPGA chip to collect test data and implement the detection of the design under test. The checker can realize the following functions: for the design under test and the reference model, monitor the specified key signals, and dynamically collect the execution results of the design under test and the reference model at runtime; support instruction-level synchronization between the design under test and the reference model to ensure that the execution results of the two are correctly compared after each instruction of the target test program is executed by the design under test and the reference model; compare the first execution result of the target test program of the design under test with the second execution result of the reference model, determine whether there is a mismatch between the first execution result and the second execution result, and issue an abnormal reminder when the first execution result and the second execution result do not match, etc.

[0114] Optionally, after obtaining the first execution result of the design to be tested and the second execution result of the reference model, the method further includes:

[0115] Step S31, writing the first execution result into a hardware buffer, and writing the second execution result into a software buffer;

[0116] Step S32, reading the first execution result from the hardware buffer, and reading the second execution result from the software buffer;

[0117] Step S33: compare the first execution result with the second execution result.

[0118] The embodiment of the present invention configures a buffer for the design to be tested and the reference model respectively. During the verification process, the operating data of the design to be tested, including intermediate results and final output results, are written into the hardware buffer; the operating data of the reference model is written into the software buffer.

[0119] In a possible implementation scenario, a hardware buffer can be configured in the checker for the design under test to record the running data of the design under test; a software buffer is also configured for the software simulator to record the running data of the software simulator. The design under test loads the target test program from the hardware storage module of the FPGA chip and executes it. After each instruction is executed, the first execution result is written to the hardware buffer. After being called, the reference model executes the target test program, and after each execution, the second execution result is written to the software buffer through the driver. The checker performs a differential comparison between the first execution result and the second execution result. If the first execution result and the second execution result do not match, that is, the design under test and the reference model have different execution results for the same instruction in the target test program, then the checker can determine that the design under test has an error in operation.

[0120] Optionally, the storage space sizes of the hardware buffer and the software buffer are the same, and both are first-in-first-out data buffer storage structures; the method also includes: when the hardware buffer is full, interrupting the operation of the design to be tested, and waiting for the reference model to write a second execution result to the software buffer.

[0121] First In, First Out (FIFO) is a common queue data structure management method. In FIFO, the first element to enter the queue will be taken out first, and the last element to enter the queue will be taken out last, just like the person at the front of the queue will leave the queue first. This data structure can be used to simulate various practical scenarios, such as queuing, processing requests, etc. FIFO queues are often used to manage shared resources, process tasks, cache management, etc.

[0122] The hardware buffer and software buffer in the embodiment of the present invention can adopt a first-in-first-out storage strategy. During the verification process, the execution process between the software and hardware can be scheduled by judging the empty and full status of the FIFOs on both sides of the software and hardware. Once the FIFO on one side is about to be full, the design on this side can be interrupted to pause and wait. Usually, the hardware operation speed is faster, and the hardware buffer will be filled before the software buffer. When the hardware buffer is full, the operation of the design to be tested can be interrupted to wait for data to be written in the software buffer. After comparing the data recorded in the two buffers, the data can be released so that new data can be written.

[0123] Optionally, the method further comprises:

[0124] Step S41: When the first execution result and the second execution result do not match, taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip;

[0125] Step S42: import the state information into simulation software for simulation to debug the design under test.

[0126] If the first execution result of the design under test does not match the second execution result of the reference model, it can be determined that the design under test has run into an error. In this case, a hardware snapshot of the entire FPGA chip can be taken to save the state information of the FPGA chip. Finally, the saved state information is imported into the simulation software for simulation, thereby debugging the design under test.

[0127] The state information of the FPGA may include state information of programmable logic function blocks, on-chip memory, DSP, external devices, etc. The external device in the embodiment of the present invention refers to a device mounted on the FPGA chip and not belonging to the PL side or the PS side, such as a double data rate synchronous dynamic random access memory (DDR) and other external storage devices.

[0128] Furthermore, after the debugging and repair of the design to be tested is completed, the debugged state data in the simulation software can be downloaded and written back to the external memory device of the FPGA, so as to modify the design parameters or state data of the design to be tested on the FPGA chip. When it is detected that the data in the simulation software has been written back to the external memory device and the design parameters or state data of the design to be tested have been modified, an interrupt release signal can be sent to the design to be tested and the software simulator to resume the operation of the design to be tested and the reference model, and continue to verify the design to be tested.

[0129] Furthermore, the programmable logic chip is also equipped with an external device, and the programmable logic area also includes a verification module, which is used to verify the design to be tested; during the operation of the design to be tested, it interacts with the external device and / or the verification module through an on-chip bus.

[0130] In an embodiment of the present invention, system-level verification of the hardware design can also be implemented on the FPGA chip, that is, the design to be tested can interact with other modules on the FPGA chip, such as a verification module, external devices such as DDR, etc., during operation and generate operation data. By comparing the operation data of the design to be tested with the reference model, it is determined whether there are errors in the design to be tested.

[0131] In summary, the embodiment of the present invention provides a verification method that can map the design to be tested and the reference model to the same FPGA chip for operation, and significantly improves the verification speed by using FPGA hardware acceleration. Moreover, compared with the traditional FPGA prototype verification method, the embodiment of the present invention does not need to design an FPGA prototype, nor does it need to perform complex configuration operations on the design to be tested. It only needs to recompile the benchmark test program into a target test program based on the data transmission parameters of the design to be tested and the instruction set architecture of the FPGA chip. According to the execution results of the design to be tested and the reference model on the target test program, it can be determined whether the design to be tested has an error in operation, which simplifies the verification process and improves the verification efficiency.

[0132] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0133] Device Embodiment

[0134] Reference Figure 3 , shows a structural block diagram of a verification device of the present invention, the device is applied to a programmable logic chip, and specifically may include:

[0135] The first acquisition module 301 is used to acquire data transmission parameters, benchmark test programs and reference models corresponding to the design to be tested;

[0136] A pre-processing module 302, used for burning the design to be tested into the programmable logic area of ​​the programmable logic chip, and loading the reference model into the processing system of the programmable logic chip;

[0137] The encoding module 303 is used to re-encode each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions to obtain a target test program; the communication control instructions are instructions defined according to the instruction set architecture of the programmable logic chip;

[0138] A control module 304, used to control the design to be tested and the reference model to respectively execute the target test program;

[0139] A second acquisition module 305 is used to acquire a first execution result of the design to be tested and a second execution result of the reference model;

[0140] The verification module 306 is used to determine that the design under test has an operation error when the first execution result and the second execution result do not match.

[0141] Optionally, the preprocessing module includes:

[0142] A port information acquisition submodule, used to acquire the port information of the design to be tested;

[0143] A generating submodule, used for generating a hardware package structure according to the port information; the hardware package structure is used for connecting the design to be tested with the processor in the programmable logic chip;

[0144] A layout and routing submodule, used to perform layout and routing on the design to be tested and the hardware package structure using integrated components to generate a bitstream file;

[0145] The burning submodule is used to burn the design to be tested and the hardware package structure into the programmable logic area of ​​the programmable logic chip based on the bit stream file.

[0146] Optionally, the communication control instruction includes a storage instruction and a loading instruction; the storage instruction is used to store the data generated by the design to be tested into a hardware storage module of the programmable logic area; the loading instruction is used to load the data in the hardware storage module into a first register of the programmable logic area;

[0147] The second acquisition module includes:

[0148] an instruction insertion submodule, configured to insert the storage instruction and the load instruction after each operation instruction in the target test program, so that after the design under test executes an operation instruction, the storage instruction and the load instruction are executed to store a first execution result corresponding to the operation instruction in the hardware storage module, and load the first execution result from the hardware storage module into the first register;

[0149] A reading submodule is used to read the first execution result from the first register.

[0150] Optionally, the device further comprises:

[0151] A result writing module, used for writing the first execution result into a hardware buffer, and writing the second execution result into a software buffer;

[0152] A result reading module, used for reading the first execution result from the hardware buffer and reading the second execution result from the software buffer;

[0153] A result comparison module is used to compare the first execution result with the second execution result.

[0154] Optionally, the storage space sizes of the hardware buffer and the software buffer are the same, and both are first-in-first-out data buffer storage structures; the device further includes:

[0155] An interrupt module is used to interrupt the operation of the design to be tested when the hardware buffer is full, and wait for the reference model to write a second execution result to the software buffer.

[0156] Optionally, the device further comprises:

[0157] a snapshot module, configured to take a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip when the first execution result and the second execution result do not match;

[0158] The information import module is used to import the state information into the simulation software for simulation so as to debug the design to be tested.

[0159] In summary, the embodiment of the present invention provides a verification device that can map the design to be tested and the reference model to the same FPGA chip for operation, and significantly improves the verification speed by using FPGA hardware acceleration. Moreover, compared with the traditional FPGA prototype verification method, the embodiment of the present invention does not need to design an FPGA prototype, nor does it need to perform complex configuration operations on the design to be tested. It only needs to recompile the benchmark test program into a target test program according to the data transmission parameters of the design to be tested and the instruction set architecture of the FPGA chip. According to the execution results of the design to be tested and the reference model on the target test program, it can be determined whether the design to be tested has an error in operation, which simplifies the verification process and improves the verification efficiency.

[0160] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0161] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0162] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0163] Reference Figure 4 , is a structural block diagram of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method of the aforementioned embodiment.

[0164] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0165] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0166] The memory can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0167] The embodiment of the present invention also provides a non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is able to execute Figure 1 The verification method shown.

[0168] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0169] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0170] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0171] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0172] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0173] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0174] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0175] The above is a detailed introduction to a verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A verification method, characterized in that: Applied to a programmable logic chip, the method comprises: Obtain data transmission parameters, benchmark test programs and reference models corresponding to the design under test; Burning the design to be tested into a programmable logic area of ​​the programmable logic chip, and loading the reference model into a processing system of the programmable logic chip; Re-encode each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions to obtain a target test program; the communication control instructions are instructions defined according to the instruction set architecture of the programmable logic chip; Control the design to be tested and the reference model to respectively execute the target test program; Obtaining a first execution result of the design to be tested and a second execution result of the reference model; In the case where the first execution result and the second execution result do not match, determining that the design under test runs incorrectly; Wherein, the data transmission parameters include: at least one of the buffer address of the design to be tested, the data type required by the design to be tested, the data block size, the data block address and the checksum; The design to be tested is connected to the processor in the programmable logic chip through a hardware wrapping structure; the data required by the design to be tested and the first execution result generated during the running process are transmitted through the memory of the hardware wrapping structure and the hardware storage structure of the programmable logic chip; the hardware wrapping structure is generated according to the port information of the design to be tested.

2. The method according to claim 1, characterized in that The step of burning the design to be tested into the programmable logic area of ​​the programmable logic chip comprises: Obtaining port information of the design to be tested; Generate a hardware wrapping structure according to the port information; the hardware wrapping structure is used to connect the design to be tested and the processor in the programmable logic chip; Perform layout and routing on the design to be tested and the hardware package structure using integrated components to generate a bitstream file; The design to be tested and the hardware package structure are burned into a programmable logic area of ​​the programmable logic chip based on the bitstream file.

3. The method according to claim 1, characterized in that The communication control instruction includes a storage instruction and a loading instruction; the storage instruction is used to store the data generated by the design to be tested into the hardware storage module of the programmable logic area; the loading instruction is used to load the data in the hardware storage module into the first register of the programmable logic area; The obtaining of the first execution result of the design to be tested and the second execution result of the reference model includes: Inserting the storage instruction and the load instruction after each operation instruction in the target test program, so that after the design under test executes one operation instruction, the storage instruction and the load instruction are executed to store a first execution result corresponding to the operation instruction in the hardware storage module, and load the first execution result from the hardware storage module into the first register; The first execution result is read from the first register.

4. The method according to claim 1, characterized in that: After obtaining the first execution result of the design to be tested and the second execution result of the reference model, the method further includes: Writing the first execution result into a hardware buffer, and writing the second execution result into a software buffer; Reading the first execution result from the hardware buffer, and reading the second execution result from the software buffer; The first execution result is compared with the second execution result.

5. The method according to claim 4, characterized in that The storage space sizes of the hardware buffer and the software buffer are the same, and both are first-in-first-out data buffer storage structures; the method further includes: When the hardware buffer is full, the operation of the design to be tested is interrupted, and the reference model is waited for to write a second execution result to the software buffer.

6. The method according to claim 1, characterized in that The method further comprises: When the first execution result and the second execution result do not match, taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip; The state information is imported into simulation software for simulation to debug the design under test.

7. A verification device, characterized in that: Applied to a programmable logic chip, the device comprises: A first acquisition module is used to acquire data transmission parameters, benchmark test programs and reference models corresponding to the design to be tested; A preprocessing module, used for burning the design to be tested into a programmable logic area of ​​the programmable logic chip, and loading the reference model into a processing system of the programmable logic chip; An encoding module, used for re-encoding each instruction in the benchmark test program according to the encoding format corresponding to the data transmission parameters and the preset communication control instructions, so as to obtain a target test program; the communication control instructions are instructions defined according to the instruction set architecture of the programmable logic chip; A control module, used for controlling the design to be tested and the reference model to respectively execute the target test program; A second acquisition module, used to acquire a first execution result of the design to be tested and a second execution result of the reference model; A verification module, used for determining that the design to be tested has an operation error when the first execution result and the second execution result do not match; Wherein, the data transmission parameters include: at least one of the buffer address of the design to be tested, the data type required by the design to be tested, the data block size, the data block address and the checksum; The design to be tested is connected to the processor in the programmable logic chip through a hardware wrapping structure; the data required by the design to be tested and the first execution result generated during the running process are transmitted through the memory of the hardware wrapping structure and the hardware storage structure of the programmable logic chip; the hardware wrapping structure is generated according to the port information of the design to be tested.

8. The device according to claim 7, characterized in that The preprocessing module comprises: A port information acquisition submodule, used to acquire the port information of the design to be tested; A generating submodule, used for generating a hardware package structure according to the port information; the hardware package structure is used for connecting the design to be tested with the processor in the programmable logic chip; A layout and routing submodule, used to perform layout and routing on the design to be tested and the hardware package structure using integrated components to generate a bitstream file; The burning submodule is used to burn the design to be tested and the hardware package structure into the programmable logic area of ​​the programmable logic chip based on the bit stream file.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the verification method as claimed in any one of claims 1 to 6.

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