A power-on control circuit and an operational amplifier circuit for an operational amplifier

Abstract

This application relates to a power-on control circuit and an operational amplifier circuit for an operational amplifier. Among them, the power-on control circuit includes a detection module and an enable signal generation module; the input end of the detection module is connected to the first node in the operational amplifier with the slowest power-on speed, and the output end is connected to the input end of the enable signal generation module; the detection module is used to output a control level to the enable signal generation module, and the polarity of the control level flips when the voltage value of the first node reaches the detection threshold; the enable signal generation module is used to obtain a fast power-on enable signal according to the control level and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal; the power-on control circuit of this application can avoid generating a large current pulse in the output stage circuit of the operational amplifier during the power-on process, thereby avoiding the circuit from being burned out and improving the reliability of the circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit technologies, and particularly to a power-on control circuit and an operational amplifier circuit for an operational amplifier. Background Art

[0002] An operational amplifier is an important basic analog circuit module. An operational amplifier generally consists of an input stage, a gain stage and an output stage, and can provide an analog signal amplification function. At the same time, a bias circuit is also required in the operational amplifier to provide a bias current and a bias voltage for the internal circuit of the operational amplifier to ensure that components such as transistors in the operational amplifier can work normally. The operational amplifier is usually used as a component module in a circuit system. When the system does not require the operational amplifier to work, the operational amplifier needs to be powered off to save power consumption; when the operational amplifier needs to work, the system can send an enable signal to control the bias circuit to power on the operational amplifier. During the power-on process, the bias current provided by the bias circuit needs to charge the circuit nodes in the operational amplifier to establish the local bias voltages required for the operation of each node. Therefore, the power-on of the operational amplifier usually takes a certain amount of time. Since the parasitic capacitances of each circuit node are usually different, when the operational amplifier is powered on again from the powered-off state, the power-on speeds of each node are not the same, which brings great uncertainty to the power-on transient process. The output transistor of the operational amplifier may generate a significant current overshoot during the power-on process, resulting in a current pulse. The magnitude of this current pulse is uncontrollable, and in severe cases, it may even burn out the circuit. Summary of the Invention

[0003] In view of this, the present application provides a power-on control circuit and an operational amplifier circuit for an operational amplifier, which can effectively avoid the generation of a large current pulse in the output stage circuit of the operational amplifier during the power-on process, thereby avoiding the circuit from being burned out and improving the circuit reliability.

[0004] According to an aspect of the present application, there is provided a power-on control circuit for an operational amplifier, including a detection module and an enable signal generation module; an input end of the detection module is connected to a first node in the operational amplifier; an output end of the detection module is connected to an input end of the enable signal generation module; the first node is the node with the slowest power-on speed in the operational amplifier; the detection module is configured to output a control level to the enable signal generation module, and the polarity of the control level is reversed when the voltage value of the first node reaches a detection threshold; the enable signal generation module is configured to obtain a fast power-on enable signal according to the control level and send the fast power-on enable signal to an output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal.

[0005] In a possible implementation, the detection module includes a first PMOS transistor group and a first NMOS transistor group; the first PMOS transistor group includes at least one PMOS transistor; the first NMOS transistor group includes at least one NMOS transistor; the number of PMOS transistors in the first PMOS transistor group and / or the number of NMOS transistors in the first NMOS transistor group is set according to the detection threshold.

[0006] In a possible implementation, the gate lines of the first PMOS transistor group are connected to the gate lines of the first NMOS transistor group to form the input end of the detection module; the drain lines of the first PMOS transistor group are connected to the drain lines of the first NMOS transistor group to form the output end of the detection module; the source lines of the first PMOS transistor group are connected to a high level; the source lines of the first NMOS transistor group are grounded.

[0007] In a possible implementation, the types of the first node include an NMOS bias node and a PMOS bias node; wherein, if the first node is the gate of an NMOS transistor in the operational amplifier, the type of the first node is an NMOS bias node; if the first node is the gate of a PMOS transistor in the operational amplifier, the type of the first node is a PMOS bias node.

[0008] In a possible implementation, when the first PMOS transistor group includes multiple PMOS transistors, the multiple PMOS transistors are connected in series; when the first NMOS transistor group includes multiple NMOS transistors, the multiple NMOS transistors are connected in series; if the type of the first node is an NMOS bias node, the number of PMOS transistors in the first PMOS transistor group is greater than the number of NMOS transistors in the first NMOS transistor group; if the type of the first node is a PMOS bias node, the number of NMOS transistors in the first NMOS transistor group is greater than the number of PMOS transistors in the first PMOS transistor group; or, when the first PMOS transistor group includes multiple PMOS transistors, the multiple PMOS transistors are connected in parallel; when the first NMOS transistor group includes multiple NMOS transistors, the multiple NMOS transistors are connected in parallel; if the type of the first node is an NMOS bias node, the number of NMOS transistors in the first NMOS transistor group is greater than the number of PMOS transistors in the first PMOS transistor group; if the type of the first node is a PMOS bias node, the number of PMOS transistors in the first PMOS transistor group is greater than the number of NMOS transistors in the first NMOS transistor group.

[0009] In a possible implementation, the enable signal generation module includes at least one inverter; when the enable signal generation module includes multiple inverters, the multiple inverters are connected in series; the input terminal of the first inverter in the at least one inverter is the input terminal of the enable signal generation module; the output terminal of the last inverter in the at least one inverter outputs the fast power-on enable signal.

[0010] In a possible implementation, if the type of the first node is an NMOS bias node, the detection threshold is less than the voltage value when the first node finishes power-on; if the type of the first node is a PMOS bias node, the detection threshold is greater than the voltage value when the first node finishes power-on.

[0011] In a possible implementation, the operational amplifier includes an input stage circuit, a gain stage circuit, an output stage circuit, a main bias circuit, and an output stage bias circuit; the input stage circuit is configured to receive an input signal; the gain stage circuit is configured to amplify the input signal to obtain an amplified signal; the output stage circuit is configured to output the amplified signal; the main bias circuit is configured to provide a bias current and / or a bias voltage required for starting to work for the input stage circuit and the gain stage circuit; the output stage bias circuit is configured to provide a bias current and / or a bias voltage required for starting to work for the output stage circuit after being turned on in response to the fast power-on enable signal.

[0012] According to another aspect of the present application, there is provided an operational amplifier circuit, including: an operational amplifier and a power-on control circuit; the power-on control circuit includes a detection module and an enable signal generation module; the input terminal of the detection module is connected to a first node in the operational amplifier; the output terminal of the detection module is connected to the input terminal of the enable signal generation module; the first node is the node with the slowest power-on speed in the operational amplifier; the detection module is configured to output a control level to the enable signal generation module, and the polarity of the control level is reversed when the voltage value of the first node reaches the detection threshold; the enable signal generation module is configured to obtain a fast power-on enable signal according to the control level and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal.

[0013] In a possible implementation, the operational amplifier includes an input stage circuit, a gain stage circuit, an output stage circuit, a main bias circuit, and an output stage bias circuit; the input stage circuit is configured to receive an input signal; the gain stage circuit is configured to amplify the input signal to obtain an amplified signal; the output stage circuit is configured to output the amplified signal; the main bias circuit is configured to provide a bias current and / or a bias voltage required for starting the operation of the input stage circuit and the gain stage circuit; the output stage bias circuit is configured to provide a bias current and / or a bias voltage required for starting the operation of the output stage circuit after being enabled in response to the fast power-on enable signal.

[0014] The power-on control circuit of the operational amplifier of the present application determines whether the first node with the slowest power-on speed in the operational amplifier has completed power-on by determining whether the voltage value of the first node reaches a detection threshold, and generates a power-on enable signal according to the power-on completion situation of the first node to control the output stage bias circuit of the operational amplifier to power on the output stage circuit. Therefore, by adjusting the power-on sequence of the nodes with slower power-on speed and the nodes with faster power-on speed inside the operational amplifier circuit, the current pulse generated in the output stage circuit of the operational amplifier during the power-on process can be reduced, thereby avoiding the burnout of the operational amplifier circuit and improving the reliability of the operational amplifier circuit.

[0015] According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present application will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings included in and constituting a part of this specification, together with the specification, illustrate the exemplary embodiments, features, and aspects of the present application and are used to explain the principles of the present application.

[0017] Figure 1 A schematic diagram showing the application of an operational amplifier in a feedback loop.

[0018] Figure 2 A schematic diagram showing the circuit structure of a Class-AB output stage operational amplifier.

[0019] Figure 3 A schematic diagram showing the power-on simulation result of a Class-AB output stage operational amplifier.

[0020] Figure 4 A schematic diagram showing the structure of a power-on control circuit of an operational amplifier according to an embodiment of the present application.

[0021] Figure 5 A schematic diagram showing the circuit structure of the detection module 401 according to an embodiment of the present application.

[0022] Figure 6Shows a schematic circuit diagram of the detection module 401 according to an embodiment of the present application.

[0023] Figure 7 Shows a schematic structural diagram of an operational amplifier circuit according to an embodiment of the present application.

[0024] Figure 8 Shows a schematic circuit diagram of an operational amplifier circuit according to an embodiment of the present application.

[0025] Figure 9 Shows a schematic diagram of the power-on simulation result of an operational amplifier circuit according to an embodiment of the present application. Detailed implementation manners

[0026] The following will describe in detail various exemplary embodiments, features, and aspects of the present application with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0027] The special term "exemplary" here means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" here does not necessarily have to be construed as superior to or better than other embodiments.

[0028] In addition, for a better description of the present application, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present application can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail so as to highlight the gist of the present application.

[0029] An operational amplifier can provide an analog signal amplification function. To maintain a high linearity between the output signal and the input signal, a high-gain operational amplifier is usually used in the feedback loop as an error amplifier. Figure 1 Shows a schematic diagram of applying an operational amplifier in a feedback loop, as Figure 1 shown, the operational amplifier includes an input stage circuit, a gain stage circuit, an output stage circuit, and a bias circuit. The input stage circuit, the gain stage circuit, and the output stage circuit can form a main operational amplifier circuit, which is used to amplify the input signal and output the amplified signal; the bias circuit is used to provide bias current and bias voltage for the input stage circuit, the gain stage circuit, and the output stage circuit to ensure that the components in each stage circuit can work properly. The feedback network is usually implemented by a passive voltage dividing network. By using the feedback network to feedback the output of the operational amplifier to the input terminal, the output signal can be adjusted to maintain the linear relationship between the output signal VOUT and the input signal VIN, thereby realizing a high-linearity signal amplification function.

[0030] The commonly used output stage circuits in operational amplifiers include Class-A output stage, Class-B output stage, Class-AB output stage, etc. The Class-AB output stage can be biased at a relatively small quiescent current. That is, when there is no signal input, the Class-AB output stage can operate at a lower quiescent current. Moreover, when the circuit requires a transient response, that is, when the output needs to change rapidly to adapt to the change of the input signal, the Class-AB output stage can quickly adjust its output current and can instantaneously provide an output current far exceeding its bias current to the load. Therefore, the Class-AB output stage has smaller quiescent power consumption and stronger output driving ability compared with other conventional output stage circuits and is widely used as the output stage circuit of operational amplifiers. An operational amplifier with a Class-AB output stage circuit can be called a Class-AB output stage operational amplifier.

[0031] Figure 2 Fig. shows a schematic circuit diagram of a Class-AB output stage operational amplifier, as Figure 2 shown, the Class-AB output stage operational amplifier may include a main operational amplifier circuit, a main bias circuit, and an output stage bias circuit. The main operational amplifier circuit includes an input stage circuit, a gain stage circuit, and an output stage circuit. The main bias circuit is used to bias the input stage circuit and the gain stage circuit, that is, to provide bias current and bias voltage for the input stage circuit and the gain stage circuit; the output stage bias circuit is used to bias the output stage circuit, that is, to provide bias current and bias voltage for the output stage circuit. Since the output stage circuit of this operational amplifier is a Class-AB output stage, this output stage bias circuit can be called a Class-AB bias circuit. MP3 and MN5 can form a floating current source to control the quiescent current of the output stage circuit; node B (i.e., the gate-drain short connection point of MN7) in the output stage bias circuit is connected to node B (i.e., the gate of MN5) in the main operational amplifier circuit, and node C (i.e., the gate-drain short connection point of MP5) in the output stage bias circuit is connected to node C (i.e., the gate of MP3) in the main operational amplifier circuit. MN7 and MN8 can provide a bias voltage for MN5, and MP5 and MP6 can provide a bias voltage for MP3. The Class-AB output stage includes two output transistors, namely output NMOS transistor MN6 and output PMOS transistor MP4, which are usually biased by a transconductance linear loop. NMOS transistors MN5, MN6, MN7, MN8 can form a transconductance linear loop, and PMOS transistors MP3, MP4, MP5, MP6 can form a transconductance linear loop. According to the Kirchhoff Voltage Laws (KVL) equation, the gate-source voltages of the MOS transistors in the transconductance linear loop have the following relationship:

[0032] V GSN5 +V GSN6 =VGSN7 +V GSN8 (1)

[0033] V GSP3 +V GSP4 =V GSP5 +V GSP6 (2)

[0034] Among them, V GSN5 represents the gate-source voltage of MN5, V GSN6 represents the gate-source voltage of MN6, V GSN7 represents the gate-source voltage of MN7, V GSN8 represents the gate-source voltage of MN8, V GSP3 represents the gate-source voltage of MP3, V GSP4 represents the gate-source voltage of MP4, V GSP5 represents the gate-source voltage of MP5, V GSP6 represents the gate-source voltage of MP6. When the differential input is 0, the currents flowing through MP3 and MN5 are equal, and the gate-source voltages of MP3 and MN5 are biased. According to formula (1) and formula (2), the gate voltages of the output transistors MP4 and MN6 are determined, and the static bias currents of MP4 and MN6 are determined.

[0035] According to the complexity of the internal circuit function of the operational amplifier, a bias circuit of corresponding scale is usually required. The current bias circuit has the ability of long-distance transmission and is insensitive to the power supply voltage. Therefore, it is often used as the bias circuit of the operational amplifier. A typical current bias circuit copies the root current through an NMOS current mirror or a PMOS current mirror, and copies the required bias current to the main op-amp circuit and other places where bias current is needed. As Figure 2 shown, the NMOS transistors MN1, MN2 and the PMOS transistor MP1 constitute a typical current mirror bias circuit. Among them, the root current IBIAS flows into MN1 to generate a local bias voltage vbn_1, and MP1 generates a local bias voltage vbp_1. Where bias current is needed, only the gate of the corresponding NMOS transistor or PMOS transistor needs to be connected to vbn_1 or vbp_1, and a bias current proportional to the root current can be obtained. In addition to the current mirror mirror bias, a local bias voltage can also be generated by a current flowing through a resistor or a CMOS device with a shorted gate-drain. The local bias voltage is usually connected to the gate of a cascode device for biasing the cascode device. Figure 2 The bias network in

[0036] According to the specific application scenario, an operational amplifier is usually a component module of a circuit system. When the system does not require the operational amplifier to work, the operational amplifier needs to be powered down. After powering down, the operational amplifier consumes almost no quiescent current, thus achieving the purpose of power consumption savings. The power-down operation is usually achieved by turning off the current bias circuit inside the operational amplifier, making its bias current disappear, and selectively pulling up the local bias voltage in the circuit to the power supply voltage or pulling it down to the ground potential. For example, Figure 2 the enable switches at the gates of MN1, MN6, and MN9 in Figure 2 can be pulled down to the ground potential VSS, and the enable switches at the gates of MP4 and MP7 can be pulled up to the power supply voltage VDD to power down the operational amplifier. When the operational amplifier needs to work, the system sends a power-on enable signal to the operational amplifier to control the bias circuit to power on the operational amplifier again. For example, in

[0037] Figure 2 Figure 2 , the power-on enable signal EN_OPA sent by the system to the operational amplifier can control the enable switches at the gates of MN1, MN6, MN9, MP4, and MP7 to be simultaneously turned off, and the main bias circuit and the Class-AB bias circuit are simultaneously turned on, and the operational amplifier starts to power on. During the power-on process, the bias current needs to recharge each circuit node again to re-establish the local bias voltage required for each node to work. Therefore, it usually takes a certain amount of time for the operational amplifier to power on.

[0037] Generally, in order to save power consumption, the root current of the bias circuit needs to be designed to a small value and is amplified proportionally by a current mirror to the main operational amplifier circuit. The parasitic capacitances of each node in the operational amplifier circuit are usually different, which means that when the operational amplifier is powered on again from the powered-down state, the power-on speeds of each node are not the same. As shown in the Class-AB output stage operational amplifier in Figure 2 , the parasitic capacitance at point A (i.e., the gate of NMOS transistor MN4) is relatively large, and the parasitic capacitances at points B and C are relatively small. During the power-on process, the power-on speed at point A is slower, and its bias voltage is established more slowly. The power-on speeds at points B and C are faster, and their bias voltages are established more quickly. When point C completes power-on (i.e., the voltage at point C reaches its required bias voltage), since the PMOS transistor MP3 in the transconductance linear loop is biased by the output branch current IOUT1 of the main operational amplifier circuit, IOUT1 needs to be stable after point A completes power-on (i.e., the voltage at point A reaches its required bias voltage), that is, the gate-source voltage V GSP3 of MP3 needs to be stable after point A completes power-on. Therefore, according to formula (2), the gate-source voltage V GSP4 of the output PMOS transistor MP4 is also in the middle of the power-on state, and V GSP4 needs to be stable after point A completes power-on. Similarly, the gate-source voltage V of the output NMOS transistor MN6GSN6 It also needs to be powered on at point A to be stable. Since the power-on speeds of points B and C are faster than that of point A, when points B and C are powered on, point A has not been powered on yet. At this time, V GSP4 and V GSN6 are in the middle state of power-on, and the transconductance linear loops where MP4 is located and the transconductance linear loops where MN6 is located are not established, resulting in a significant current overshoot process in the output transistor during power-on (that is, the current IOUT2 flowing through MP4 and MN6 will have a significant overshoot), thus generating current pulses. Since the driving ability of the output transistor is usually designed to be very strong, the magnitude of this current pulse is uncontrollable, and when the current pulse is too large, there is even a possibility of burning out the circuit.

[0038] Figure 3 shows a schematic diagram of the power-on simulation result of a Class-AB output stage operational amplifier, and this Class-AB output stage operational amplifier is the above-mentioned Figure 2 shown Class-AB output stage operational amplifier. Figure 3 shows the voltage change curve of point A, the voltage change curve of point C, and the change curve of current IOUT2 during the power-on process of this Class-AB output stage operational amplifier. As Figure 3 shown, when the power-on enable signal sent by the system to the operational amplifier changes from low level to high level, the Class-AB output stage operational amplifier starts to power on. The speed at which point C reaches its stable bias voltage is faster than the speed at which point A reaches its stable bias voltage. When point C is powered on and point A has not been powered on yet, the current IOUT2 provided by the output branch power supply to the output experiences an overshoot process of about 700 μA. After point A is powered on, IOUT2 slowly builds up to the static bias value of about 150 μA.

[0039] In order to avoid large current pulses generated in the output stage circuit of the operational amplifier during power-on, the embodiment of the present application proposes a power-on control circuit for an operational amplifier. By judging whether the node with the slowest power-on speed in the operational amplifier is powered on, and then controlling the output stage bias circuit to power on the output stage circuit after the node with the slowest power-on speed is powered on, the current pulses generated in the output stage circuit during power-on can be significantly reduced, thereby avoiding the circuit being burned out and improving the circuit reliability.

[0040] Figure 4 shows a schematic diagram of the structure of a power-on control circuit for an operational amplifier according to an embodiment of the present application. As Figure 4As shown, the circuit may include a detection module 401 and an enable signal generation module 402; the input end of the detection module 401 is connected to the first node in the operational amplifier; the output end of the detection module 401 is connected to the input end of the enable signal generation module 402; the first node is the node with the slowest power-up speed in the operational amplifier.

[0041] Exemplarily, the operational amplifier may include an input stage circuit, a gain stage circuit, an output stage circuit, a main bias circuit, and an output stage bias circuit; the input stage circuit can be used to receive an input signal; the gain stage circuit can be used to amplify the input signal to obtain an amplified signal; the output stage circuit can be used to output the amplified signal; the main bias circuit can be used to provide the bias current and / or bias voltage required for the input stage circuit and the gain stage circuit to start working; the output stage bias circuit can be used to provide the bias current and / or bias voltage required for the output stage circuit to start working.

[0042] Exemplarily, the power-up control circuit of the embodiments of the present application can be applied to a Class-AB output stage operational amplifier. For example, it can be applied to the Class-AB output stage operational amplifier as shown above Figure 2 shown Class-AB output stage operational amplifier.

[0043] Exemplarily, when the circuit system needs the operational amplifier to work, a slow power-up enable signal can be sent to the operational amplifier first to control the main bias circuit to provide the bias current and / or bias voltage for the input stage circuit and the gain stage circuit, that is, to control the main bias circuit to power up the input stage circuit and the gain stage circuit. Since the power-up speed of the nodes in the input stage circuit and the gain stage circuit is generally slower than that of the nodes in the output stage circuit, the node with the slowest power-up speed in the input stage circuit and the gain stage circuit can be regarded as the node with the slowest power-up speed in the operational amplifier (i.e., the first node).

[0044] The power-up speed of a node is related to the size of the parasitic capacitance of the node and the magnitude of the charging current. The larger the parasitic capacitance, the slower the power-up speed; the smaller the charging current, the slower the power-up speed. Exemplarily, the first node can be determined according to the size of the parasitic capacitance of each node in the operational amplifier circuit and the magnitude of the charging current. For example, Figure 2 in the shown Class-AB output stage operational amplifier, the device size at point A is the largest, that is, the parasitic capacitance is the largest, and the charging current is small. Therefore, the power-up speed of point A is the slowest, that is, point A is the first node.

[0045] The detection module 401 is configured to output a control level to the enable signal generation module 402, and the polarity of the control level is reversed when the voltage value of the first node reaches the detection threshold.

[0046] Exemplarily, the detection threshold may be close to the voltage value when the power-on of the first node is completed. In this way, the detection module 401 can detect the voltage value of the first node, input the voltage of the first node into the internal circuit of the detection module 401, and then control the level to remain unchanged or the polarity to flip in response to the voltage of the first node. Among them, since the control level flips in polarity when the voltage value of the first node reaches the detection threshold, it can be indicated whether the voltage value of the first node reaches the detection threshold by detecting whether the polarity of the control level output by the detection module 401 flips, and the determination of whether the first node has completed power-on is realized.

[0047] The enable signal generation module 402 is configured to obtain a fast power-on enable signal according to the control level and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal.

[0048] Exemplarily, when the fast power-on enable signal generated by the enable signal generation module 402 is an invalid power-on enable signal, the output stage bias circuit of the operational amplifier is in a closed state in response to the invalid power-on enable signal and does not provide a bias current and / or a bias voltage for the output stage circuit; when the fast power-on enable signal generated by the enable signal generation module 402 is a valid power-on enable signal, the output stage bias circuit of the operational amplifier is switched from a closed state to an open state in response to the valid power-on enable signal and provides a bias current and / or a bias voltage for the output stage circuit.

[0049] Exemplarily, when the detection module 401 determines that the voltage value of the first node reaches the detection threshold, the polarity of the control level output by the detection module 401 flips. At this time, the fast power-on enable signal generated by the enable signal generation module 402 can change from an invalid power-on enable signal to a valid power-on enable signal, and control the output stage bias circuit to enter the open state from the closed state in response to the change of the fast power-on enable signal. After the output stage bias circuit enters the open state, it can provide a bias current and / or a bias voltage for the output stage circuit, that is, the output stage circuit can be powered on.

[0050] The power-on control circuit of the operational amplifier in the embodiment of the present application determines whether the first node has completed power-on by detecting the voltage value of the first node with the slowest power-on speed in the operational amplifier and judging whether the voltage value of the first node reaches the detection threshold, and generates a fast power-on enable signal according to the power-on completion situation of the first node to control the output stage bias circuit of the operational amplifier to power on the output stage circuit with a faster power-on speed. Thus, by adjusting the power-on sequence of the node with a slower power-on speed and the node with a faster power-on speed inside the operational amplifier circuit, the current pulse generated during the power-on process of the output stage circuit can be reduced, the operational amplifier circuit can be prevented from being burned out, and the reliability of the operational amplifier circuit is improved.

[0051] Exemplarily, the types of the first node may include an NMOS bias node and a PMOS bias node; wherein, if the first node is the gate of an NMOS transistor in an operational amplifier, the type of the first node is an NMOS bias node; if the first node is the gate of a PMOS transistor in an operational amplifier, the type of the first node is a PMOS bias node.

[0052] Taking Figure 2 the operational amplifier shown as an example, Figure 2 point A in the main operational amplifier circuit is the gate of NMOS transistor MN4. If point A is set as the first node, then point A is an NMOS bias node; Figure 2 point C in the main operational amplifier circuit is the gate of PMOS transistor MP3. If point C is set as the first node, then point C is a PMOS bias node.

[0053] Exemplarily, if the type of the first node is an NMOS bias node, the initial power-on potential of the first node is the ground potential, that is, the voltage value of the first node increases from 0 to its required bias voltage value during the power-on process. At this time, the detection threshold can be slightly less than the voltage value when the first node finishes power-on. In this way, when the voltage value of the first node rises from 0 to the detection threshold, it can be determined that the first node has basically completed power-on; if the type of the first node is a PMOS bias node, the initial power-on potential of the first node is the power supply potential, that is, the voltage value of the first node decreases from the power supply voltage to its required bias voltage value during the power-on process. At this time, the detection threshold can be slightly greater than the voltage value when the first node finishes power-on. In this way, when the voltage value of the first node decreases from the power supply voltage to the detection threshold, it can be determined that the first node has basically completed power-on.

[0054] In a possible implementation manner, the detection module 401 may include a first PMOS transistor group and a first NMOS transistor group; the first PMOS transistor group includes at least one PMOS transistor; the first NMOS transistor group includes at least one NMOS transistor; the number of PMOS transistors in the first PMOS transistor group and / or the number of NMOS transistors in the first NMOS transistor group can be set according to the detection threshold.

[0055] Exemplarily, the gate lines of the first PMOS transistor group are connected to the gate lines of the first NMOS transistor group to form the input end of the detection module 401; the drain lines of the first PMOS transistor group are connected to the drain lines of the first NMOS transistor group to form the output end of the detection module 401; the source lines of the first PMOS transistor group are connected to a high level; the source lines of the first NMOS transistor group are grounded.

[0056] The circuit structure composed of the first PMOS transistor group and the first NMOS transistor group is equivalent to an inverter, which can be referred to as the first inverter. The first PMOS transistor group can realize the pull-up ability of the first inverter, and the first NMOS transistor group can realize the pull-down ability of the first inverter. The pull-up ability represents the ability of the first inverter to charge the output to a high potential, and the pull-down ability represents the ability of the first inverter to discharge the output to a low potential.

[0057] The pull-up ability of the first inverter is related to the equivalent on-resistance of the first PMOS transistor group (i.e., the pull-up resistor R P ). The smaller the value of R P , the smaller the impedance between the output node of the first inverter and the power supply, and the stronger the ability to pull up the output, that is, the stronger the pull-up ability of the first inverter; the pull-down ability is related to the equivalent on-resistance of the first NMOS transistor group (i.e., the pull-down resistor R N ). The smaller the value of R N , the smaller the impedance between the output node of the first inverter and the ground, and the stronger the ability to pull down the output, that is, the stronger the pull-down ability of the first inverter. Assuming that the power supply voltage of the first inverter is V P (i.e., the source of the first PMOS transistor group is connected to the voltage V P ), then the detection threshold V th can be approximately expressed as:

[0058] V th = R N / (R P + R N ) * V P (3)

[0059] Exemplarily, the pull-up ability and the pull-down ability of the first inverter can be different. According to the above formula, the smaller R P is compared with R N (i.e., the stronger the pull-up ability relative to the pull-down ability), the larger V th is; the smaller R N is compared with R P (i.e., the stronger the pull-down ability relative to the pull-up ability), the smaller V th is. Therefore, the larger the detection threshold, the stronger the pull-up ability of the first inverter needs to be set relative to the pull-down ability; the smaller the detection threshold, the stronger the pull-down ability of the first inverter needs to be set relative to the pull-up ability. The relative strength of the pull-up ability and the pull-down ability of the first inverter (i.e., the pull-up / pull-down relative ability) can be adjusted based on the detection threshold, so that after adjustment, the power supply voltage V P , the pull-up resistor R P , the pull-down resistor R N and the detection threshold V thIt can satisfy the above formula. The relative pull-up / pull-down ability of the first inverter can be achieved by adjusting the number of PMOS transistors in the first PMOS transistor group and / or the number of NMOS transistors in the first NMOS transistor group.

[0060] In one embodiment, when the first PMOS transistor group includes multiple PMOS transistors, the multiple PMOS transistors can be connected in series; when the first NMOS transistor group includes multiple NMOS transistors, the multiple NMOS transistors can be connected in series.

[0061] Figure 5 The circuit structure diagram of the detection module 401 according to an embodiment of the present application is shown, as Figure 5 shown, the PMOS transistors in the first PMOS transistor group can be connected in series, the NMOS transistors in the first NMOS transistor group can be connected in series, the gates of the PMOS transistors in the first PMOS transistor group are connected to form the gate line of the first PMOS transistor group, the gates of the NMOS transistors in the first NMOS transistor group are connected to form the gate line of the first NMOS transistor group, the gate line of the first PMOS transistor group is connected to the gate line of the first NMOS transistor group to form the input end of the detection module 401, and the input end is connected to the first node; the source line of the first PMOS transistor in the first PMOS transistor group is the source line of the first PMOS transistor group, and the source of the first PMOS transistor in the first PMOS transistor group is connected to a high level; the drain line of the last PMOS transistor in the first PMOS transistor group is the drain line of the first PMOS transistor group, the drain line of the first NMOS transistor in the first NMOS transistor group is the drain line of the first NMOS transistor group, the drain of the last PMOS transistor in the first PMOS transistor group is connected to the drain of the first NMOS transistor in the first NMOS transistor group to form the output end of the detection module 401; the source line of the last NMOS transistor in the first NMOS transistor group is the source line of the first NMOS transistor group, and the source of the last NMOS transistor in the first NMOS transistor group is grounded. The first PMOS transistor group and the first NMOS transistor group can form the first inverter. The PMOS transistors in the first PMOS transistor group and the NMOS transistors in the first NMOS transistor group can be MOS transistors with the same size. By increasing the number of PMOS transistors connected in series, the pull-down ability of the first inverter can be improved; by increasing the number of NMOS transistors connected in series, the pull-up ability of the first inverter can be improved. When the number of PMOS transistors connected in series is greater than the number of NMOS transistors connected in series, the pull-down resistance is less than the pull-up resistance, so that the pull-down ability of the first inverter can be stronger than the pull-up ability; when the number of NMOS transistors connected in series is greater than the number of PMOS transistors connected in series, the pull-up resistance is less than the pull-down resistance, so that the pull-up ability of the first inverter can be stronger than the pull-down ability. By adjusting the number of PMOS transistors connected in series and the number of NMOS transistors connected in series, the relative pull-up / pull-down ability of the first inverter can be adjusted.

[0062] If the type of the first node is an NMOS bias node, its voltage value is 0 at the start of power-on and generally stabilizes at a relatively low bias voltage value after power-on is completed. Therefore, the detection threshold is a relatively low voltage value. At this time, the number of PMOS transistors connected in series in the first PMOS transistor group can be greater than the number of NMOS transistors connected in series in the first NMOS transistor group, so that the pulling-down ability of the first inverter is stronger than the pulling-up ability, thereby enabling a lower detection threshold.

[0063] If the type of the first node is a PMOS bias node, its voltage value is the power supply voltage at the start of power-on and generally stabilizes at a relatively high bias voltage value after power-on is completed. This bias voltage value may be close to the power supply voltage. Therefore, the detection threshold is a relatively high voltage value. At this time, the number of NMOS transistors connected in series in the first NMOS transistor group can be greater than the number of PMOS transistors connected in series in the first PMOS transistor group, so that the pulling-up ability of the first inverter is stronger than the pulling-down ability, thereby enabling a higher detection threshold.

[0064] In another embodiment, when the first PMOS transistor group includes multiple PMOS transistors, the multiple PMOS transistors can be connected in parallel; when the first NMOS transistor group includes multiple NMOS transistors, the multiple NMOS transistors can be connected in parallel.

[0065] Figure 6 The circuit structure diagram of the detection module 401 according to an embodiment of the present application is shown in Figure 6As shown, the PMOS transistors in the first PMOS transistor group can be connected in parallel, and the NMOS transistors in the first NMOS transistor group can be connected in parallel. The gates of the PMOS transistors in the first PMOS transistor group are connected to form the gate line of the first PMOS transistor group, and the gates of the NMOS transistors in the first NMOS transistor group are connected to form the gate line of the first NMOS transistor group. The gate line of the first PMOS transistor group is connected to the gate line of the first NMOS transistor group to form the input terminal of the detection module 401, and the input terminal is connected to the first node; the sources of the PMOS transistors in the first PMOS transistor group are connected to form the source line of the first PMOS transistor group, and the source line of the first PMOS transistor group is connected to a high level; the drains of the PMOS transistors in the first PMOS transistor group are connected to form the drain line of the first PMOS transistor group, and the drains of the NMOS transistors in the first NMOS transistor group are connected to form the drain line of the first NMOS transistor group. The drain line of the first PMOS transistor group is connected to the drain line of the first NMOS transistor group to form the output terminal of the detection module 401; the sources of the NMOS transistors in the first NMOS transistor group are connected to form the source line of the first NMOS transistor group, and the source line of the first NMOS transistor group is grounded. The first PMOS transistor group and the first NMOS transistor group can form a first inverter. The PMOS transistors in the first PMOS transistor group and the NMOS transistors in the first NMOS transistor group can be MOS transistors with the same size. By increasing the number of parallel PMOS transistors, the pull-up ability of the first inverter can be improved; by increasing the number of parallel NMOS transistors, the pull-down ability of the first inverter can be improved. When the number of parallel PMOS transistors is greater than the number of parallel NMOS transistors, the pull-up resistance is less than the pull-down resistance, so that the pull-up ability of the first inverter can be stronger than the pull-down ability; when the number of parallel NMOS transistors is greater than the number of parallel PMOS transistors, the pull-down resistance is less than the pull-up resistance, so that the pull-down ability of the first inverter can be stronger than the pull-up ability. By adjusting the number of parallel PMOS transistors and the number of parallel NMOS transistors, the relative pull-up / pull-down ability of the first inverter can be adjusted.

[0066] If the type of the first node is an NMOS bias node, its voltage value is 0 at the beginning of power-on, and its voltage value generally stabilizes at a relatively low bias voltage value after power-on is completed. Therefore, the detection threshold is a relatively low voltage value. At this time, the number of parallel NMOS transistors in the first NMOS transistor group can be greater than the number of parallel PMOS transistors in the first PMOS transistor group, so that the pull-down ability of the first inverter is stronger than the pull-up ability, and thus a relatively low detection threshold can be achieved.

[0067] If the type of the first node is a PMOS bias node, its voltage value is the power supply voltage at the start of power-on, and generally stabilizes at a relatively high bias voltage value after power-on is completed. Therefore, the detection threshold is a relatively high voltage value. At this time, the number of PMOS transistors connected in parallel in the first PMOS transistor group can be greater than the number of NMOS transistors connected in parallel in the first NMOS transistor group, so that the pull-up ability of the first inverter is stronger than the pull-down ability, thus enabling a relatively high detection threshold to be achieved.

[0068] Exemplarily, the relative pull-up / pull-down ability of the first inverter can also be adjusted by adjusting the size of the PMOS transistors in the first PMOS transistor group and / or the size of the NMOS transistors in the first NMOS transistor group. By increasing the aspect ratio of the PMOS transistors, the pull-up resistance can be reduced, thereby improving the pull-up ability of the first inverter; by increasing the aspect ratio of the NMOS transistors, the pull-down resistance can be reduced, thereby improving the pull-down ability of the first inverter. When the number of PMOS transistors in the first PMOS transistor group is equal to the number of NMOS transistors in the first NMOS transistor group, and the connection manner of the PMOS transistors in the first PMOS transistor group is the same as the connection manner of the NMOS transistors in the first NMOS transistor group (for example, both are in series or both are in parallel), if the type of the first node is an NMOS bias node, the detection threshold is a relatively low voltage value. At this time, the aspect ratio of each NMOS transistor in the first NMOS transistor group can be made greater than the aspect ratio of each PMOS transistor in the first PMOS transistor group, so that the pull-down ability of the first inverter is stronger than the pull-up ability, thus enabling a relatively low detection threshold to be achieved; if the type of the first node is a PMOS bias node, the detection threshold is a relatively high voltage value. At this time, the aspect ratio of each PMOS transistor in the first PMOS transistor group can be made greater than the aspect ratio of each NMOS transistor in the first NMOS transistor group, so that the pull-up ability of the first inverter is stronger than the pull-down ability, thus enabling a relatively high detection threshold to be achieved.

[0069] In a possible implementation manner, the enable signal generation module 402 may include at least one inverter; when the enable signal generation module 402 includes multiple inverters, the multiple inverters are connected in series; the input terminal of the first inverter in the at least one inverter is the input terminal of the enable signal generation module 402; the output terminal of the last inverter in the at least one inverter outputs a fast power-on enable signal.

[0070] Exemplarily, the inverter in the enable signal generation module 402 may be referred to as a second inverter, and the second inverter may be a standard inverter with the same pull-up ability and pull-down ability.

[0071] Exemplarily, when the fast power-on enable signal generated by the enable signal generation module 402 is at a high level, it is a valid power-on enable signal, and when the fast power-on enable signal generated by the enable signal generation module 402 is at a low level, it is an invalid power-on enable signal.

[0072] Exemplarily, if the type of the first node is an NMOS bias node, the enable signal generation module 402 may include a second inverter. When the circuit system needs the operational amplifier to work, first, a slow power-on enable signal is sent to control the main bias circuit to power on the input stage circuit and the gain stage circuit of the operational amplifier. The voltage value of the first node rises from 0 during the power-on process. The PMOS transistors in the first PMOS transistor group in the detection module 401 are turned on, the control level output by the detection module 401 is high level, and the fast power-on enable signal output by the enable signal generation module 402 is low level. At this time, the fast power-on enable signal is an invalid power-on enable signal, and the output stage bias circuit is in the off state; when the voltage value of the first node rises to the detection threshold, the NMOS transistors in the first NMOS transistor group in the detection module 401 are turned on, the control level output by the detection module 401 flips from high level to low level, and the fast power-on enable signal output by the enable signal generation module 402 changes from low level to high level. At this time, the fast power-on enable signal is a valid power-on enable signal, and the output stage bias circuit enters the on state and starts to power on the output stage circuit.

[0073] Exemplarily, if the type of the first node is a PMOS bias node, the enable signal generation module 402 may include two serially connected second inverters. When the circuit system needs the operational amplifier to work, first, a slow power-on enable signal is sent to control the main bias circuit to power on the input stage circuit and the gain stage circuit of the operational amplifier. The voltage value of the first node drops from the power supply voltage during the power-on process. The NMOS transistors in the first NMOS transistor group in the detection module 401 are turned on, the control level output by the detection module 401 is low level, and the fast power-on enable signal output by the enable signal generation module 402 is low level. At this time, the fast power-on enable signal is an invalid power-on enable signal, and the output stage bias circuit is in the off state; when the voltage value of the first node drops to the detection threshold, the PMOS transistors in the first PMOS transistor group in the detection module 401 are turned on, the control level output by the detection module 401 flips from low level to high level, and the fast power-on enable signal output by the enable signal generation module 402 changes from low level to high level. At this time, the fast power-on enable signal is a valid power-on enable signal, and the output stage bias circuit enters the on state and starts to power on the output stage circuit.

[0074] Exemplarily, if the type of the first node is a PMOS bias node, the control level output by the control module 401 may also be directly used as the fast power-on enable signal and sent to the output stage bias circuit to control the output stage bias circuit to turn on or off.

[0075] The power-on control circuit of the operational amplifier according to the embodiment of the present application detects the voltage of the first node with the slowest power-on speed in the operational amplifier, uses a simple judgment circuit to determine whether the first node has completed power-on, generates a valid fast power-on enable signal after determining that the first node has completed power-on, and controls the output stage bias circuit to power on the output stage circuit with a faster power-on speed. The power-on control circuit according to the embodiment of the present application can control the power-on of the node with a faster power-on speed (i.e., the node in the output stage circuit) after the node with a slower power-on speed (i.e., the node in the input stage circuit and the gain stage circuit) in the operational amplifier has completed power-on, which can reduce the current pulse generated by the output stage circuit during the power-on process, avoid circuit burnout, and improve the reliability of the circuit.

[0076] It should be noted that the power-on control circuit according to the embodiment of the present application can be enabled when the operational amplifier needs to be powered on, and does not need to be enabled when the operational amplifier needs to be powered off. When the operational amplifier needs to be powered off, the circuit system can make the slow power-on enable signal and the fast power-on enable signal become invalid power-on enable signals at the same time, so as to control the power-off of the operational amplifier.

[0077] The embodiment of the present application also provides an operational amplifier circuit.

[0078] Figure 7 The structural schematic diagram of an operational amplifier circuit according to an embodiment of the present application is shown as Figure 7 shown. The circuit may include: an operational amplifier 701 and a power-on control circuit 702; the power-on control circuit 702 may include a detection module 7021 and an enable signal generation module 7022; the input end of the detection module 7021 is connected to the first node in the operational amplifier 701; the output end of the detection module 7021 is connected to the input end of the enable signal generation module 7022; the first node is the node with the slowest power-on speed in the operational amplifier 701; the detection module 7021 is configured to output a control level to the enable signal generation module 7022, and the polarity of the control level is reversed when the voltage value of the first node reaches the detection threshold; the enable signal generation module 7022 is configured to obtain a fast power-on enable signal according to the control level, and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal.

[0079] In a possible implementation, the operational amplifier 701 may include an input stage circuit, a gain stage circuit, an output stage circuit, a main bias circuit, and an output stage bias circuit. The input stage circuit can be used to receive an input signal. The gain stage circuit can be used to amplify the input signal to obtain an amplified signal. The output stage circuit can be used to output the amplified signal. The main bias circuit can be used to provide a bias current and / or a bias voltage required for starting the input stage circuit and the gain stage circuit. The output stage bias circuit can be used to provide a bias current and / or a bias voltage required for starting the output stage circuit after being enabled in response to a fast power-on enable signal.

[0080] Exemplarily, the operational amplifier 701 can be a Class-AB output stage operational amplifier. For example, it can be the Class-AB output stage operational amplifier as described above Figure 2 shown.

[0081] Exemplarily, the power-on control circuit 702 can be the power-on control circuit as described above Figure 4 shown. The detection module 7021 can be the same as the detection module 401 in the power-on control circuit as described above Figure 4 shown. The enable signal generation module 7022 can be the same as the enable signal generation module 402 in the power-on control circuit as described above Figure 4 shown.

[0082] In the operational amplifier circuit according to the embodiment of the present application, by using the power-on control circuit to detect the voltage of the first node with the slowest power-on speed in the operational amplifier and determine whether the first node has completed power-on. After determining that the first node has completed power-on, the power-on control circuit can generate a valid fast power-on enable signal to control the output stage bias circuit of the operational amplifier to power on the output stage circuit with a faster power-on speed. The operational amplifier circuit according to the embodiment of the present application can control the power-on of the node with a faster power-on speed after the node with a slower power-on speed inside the operational amplifier has completed power-on, which can reduce the current pulse generated by the output stage circuit of the operational amplifier during the power-on process, avoid the circuit from being burned out, and improve the reliability of the circuit.

[0083] Figure 8 shows a schematic circuit diagram of an operational amplifier circuit according to an embodiment of the present application. As Figure 8 shown, the operational amplifier in this operational amplifier circuit can be as described above Figure 2The Class-AB output stage operational amplifier shown. In this Class-AB output stage operational amplifier, point A is the node with the slowest power-on speed, and the input terminal of the power-on control circuit can be connected to point A. The power-on control circuit may include a detection module and an enable signal generation module. The detection module includes a first inverter composed of a first PMOS transistor group and a first NMOS transistor group. Since point A is an NMOS bias node and the detection threshold is a relatively low voltage value, the pull-down ability of the first inverter needs to be stronger than the pull-up ability. One NMOS transistor can be included in the first NMOS transistor group, and multiple PMOS transistors connected in series can be included in the first PMOS transistor group to achieve a stronger pull-down ability than the pull-up ability of the first inverter. The detection threshold can be set near the final voltage value when point A completes power-on and is less than the final voltage value when point A completes power-on. The relative pull-up / pull-down ability of the first inverter can be adjusted by adjusting the number of PMOS transistors connected in series in the first PMOS transistor group, thereby adjusting the detection threshold. For example, Figure 8 a lower detection threshold is achieved by using two PMOS transistors connected in series in the first PMOS transistor group and one NMOS transistor in the first NMOS transistor group. By increasing the number of PMOS transistors connected in series, the detection threshold can be reduced; by decreasing the number of PMOS transistors connected in series, the detection threshold can be increased. The enable signal generation module may include a second inverter with the same pull-up and pull-down abilities, and the second inverter can output a fast power-on enable signal EN_OPA_DELAY.

[0084] Figure 8 When the enable switches at the gate terminals of MN1, MP4, MN6, MP7, and MN9 in are closed, the Class-AB output stage operational amplifier is in a power-down state. When the circuit system requires the Class-AB output stage operational amplifier to work, the circuit system can first send a slow power-on enable signal EN_OPA to control the main bias circuit to power on the main operational amplifier circuit. EN_OPA can control Figure 8 the enable switches at the gate terminals of MN1, MP4, and MN6 in to open, enabling the input stage circuit and the gain stage circuit in the main operational amplifier circuit to start powering on. At this time, point A starts to power on slowly, and the first inverter can detect the voltage value of point A to determine whether point A has completed power-on. During the power-on process, the voltage value of point A rises from 0. When the voltage value of point A reaches the detection threshold, the output level of the first inverter flips from high level to low level, determining that point A has basically completed power-on. At this time, the fast power-on enable signal EN_OPA_DELAY output by the second inverter changes from low level to high level, controlling the output stage bias circuit to power on the output stage circuit. EN_OPA_DELAY can control Figure 8The enable switches of the gates of MP7 and MN9 are turned off, enabling the output stage circuit to start powering up. At this time, points B and C start to power up. Since point A has basically completed powering up before points B and C start to power up, during the power-up process of the output stage circuit, the deviation of the bias voltages of output transistors MP4 and MN6 can be significantly reduced, thereby avoiding large current pulses generated by incorrect biasing of the devices in the output stage circuit during the power-up process.

[0085] Figure 9 FIG. shows a schematic diagram of the power-up simulation result of an operational amplifier circuit according to an embodiment of the present application. The operational amplifier circuit is as described above Figure 8 shown, Figure 9 shows the voltage change curve of point A, the voltage change curve of point C, and the change curve of current IOUT2 during the power-up process of the Class-AB output stage operational amplifier in the operational amplifier circuit. As Figure 9 shown, when the slow power-up enable signal changes from low level to high level, point A starts to power up slowly. When the voltage value of point A reaches the detection threshold, the output level of the first inverter flips from high level to low level, and the fast power-up enable signal output by the second inverter changes from low level to high level, and the output stage bias circuit starts to power up the output stage circuit, and point C starts to power up. Since point A has basically completed powering up before point C starts to power up, during the power-up process of the output stage circuit, the overshoot process of current IOUT2 is significantly weakened, the current pulse is significantly reduced, and the peak current is only about 154 μA, approaching the static bias value of 150 μA. Compared with Figure 3 the large current pulses generated by the output stage circuit during the power-up process in, by applying a power-up control circuit during the power-up process of the operational amplifier in the embodiment of the present application, controlling the output stage bias circuit to power up the output stage circuit with a faster power-up speed after the node with a slower power-up speed has completed powering up, the current pulses generated by the output stage circuit during the power-up process can be significantly reduced, avoiding the circuit from being burned out and improving the reliability of the circuit.

[0086] The embodiments of the present application have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A power-on control circuit for an operational amplifier, wherein the power-on control circuit is enabled during the power-on period of the operational amplifier, characterized in that: It comprises a detection module and an enable signal generation module; the input end of the detection module is connected to a first node in an operational amplifier; the output end of the detection module is connected to an input end of the enable signal generation module; the first node is a node with the slowest power-on speed in an input stage circuit and a gain stage circuit of the operational amplifier; the types of the first node include an NMOS bias node and a PMOS bias node; wherein, if the first node is a gate of an NMOS tube in the operational amplifier, the type of the first node is an NMOS bias node; if the first node is a gate of a PMOS tube in the operational amplifier, the type of the first node is a PMOS bias node; The detection module is used to output a control level to the enable signal generation module, and the control level flips polarity when the voltage value of the first node reaches a detection threshold; wherein, if the type of the first node is an NMOS bias node, the detection threshold is less than the voltage value of the first node when power-on is completed; if the type of the first node is a PMOS bias node, the detection threshold is greater than the voltage value of the first node when power-on is completed; The enable signal generating module is used to obtain a fast power-on enable signal according to the control level, and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal; the output stage bias circuit is used to provide the output stage circuit of the operational amplifier with a bias current and / or bias voltage required for startup after being turned on in response to the fast power-on enable signal.

2. The circuit according to claim 1, characterized in that The detection module includes a first PMOS tube group and a first NMOS tube group; the first PMOS tube group includes at least one PMOS tube; the first NMOS tube group includes at least one NMOS tube; the number of PMOS tubes in the first PMOS tube group and / or the number of NMOS tubes in the first NMOS tube group are set according to the detection threshold.

3. The circuit according to claim 2, characterized in that The gate line of the first PMOS tube group is connected to the gate line of the first NMOS tube group, forming the input end of the detection module; the drain line of the first PMOS tube group is connected to the drain line of the first NMOS tube group, forming the output end of the detection module; the source line of the first PMOS tube group is connected to a high level; and the source line of the first NMOS tube group is grounded.

4. The circuit according to claim 2, characterized in that When the first PMOS tube group includes a plurality of PMOS tubes, the plurality of PMOS tubes are connected in series; when the first NMOS tube group includes a plurality of NMOS tubes, the plurality of NMOS tubes are connected in series; if the type of the first node is an NMOS bias node, the number of PMOS tubes in the first PMOS tube group is greater than the number of NMOS tubes in the first NMOS tube group; if the type of the first node is a PMOS bias node, the number of NMOS tubes in the first NMOS tube group is greater than the number of PMOS tubes in the first PMOS tube group; or, When the first PMOS tube group includes multiple PMOS tubes, the multiple PMOS tubes are connected in parallel; when the first NMOS tube group includes multiple NMOS tubes, the multiple NMOS tubes are connected in parallel; if the type of the first node is an NMOS bias node, the number of NMOS tubes in the first NMOS tube group is greater than the number of PMOS tubes in the first PMOS tube group; if the type of the first node is a PMOS bias node, the number of PMOS tubes in the first PMOS tube group is greater than the number of NMOS tubes in the first NMOS tube group.

5. The circuit according to claim 1, characterized in that The enable signal generation module includes at least one inverter; when the enable signal generation module includes multiple inverters, the multiple inverters are connected in series; the input end of the first inverter among the at least one inverter is the input end of the enable signal generation module; the output end of the last inverter among the at least one inverter outputs the fast power-on enable signal.

6. The circuit according to claim 1, characterized in that The operational amplifier comprises the input stage circuit, the gain stage circuit, the output stage circuit, a main bias circuit and the output stage bias circuit; The input stage circuit is used to receive an input signal; The gain stage circuit is used to amplify the input signal to obtain an amplified signal; The output stage circuit is used to output the amplified signal; The main bias circuit is used to provide the input stage circuit and the gain stage circuit with the bias current and / or bias voltage required for starting operation.

7. An operational amplifier circuit, characterized in that: include: An operational amplifier and a power-on control circuit; the power-on control circuit is enabled during the power-on period of the operational amplifier; the power-on control circuit includes a detection module and an enable signal generation module; the input end of the detection module is connected to a first node in the operational amplifier; the output end of the detection module is connected to the input end of the enable signal generation module; the first node is a node with the slowest power-on speed in the input stage circuit and the gain stage circuit of the operational amplifier; the types of the first node include an NMOS bias node and a PMOS bias node; wherein, if the first node is the gate of the NMOS tube in the operational amplifier, the type of the first node is an NMOS bias node; if the first node is the gate of the PMOS tube in the operational amplifier, the type of the first node is a PMOS bias node; The detection module is used to output a control level to the enable signal generation module, and the control level flips polarity when the voltage value of the first node reaches a detection threshold; wherein, if the type of the first node is an NMOS bias node, the detection threshold is less than the voltage value of the first node when power-on is completed; if the type of the first node is a PMOS bias node, the detection threshold is greater than the voltage value of the first node when power-on is completed; The enable signal generating module is used to obtain a fast power-on enable signal according to the control level, and send the fast power-on enable signal to the output stage bias circuit of the operational amplifier, so that the output stage bias circuit is turned on or off in response to the fast power-on enable signal; the output stage bias circuit is used to provide the output stage circuit of the operational amplifier with a bias current and / or bias voltage required for startup after being turned on in response to the fast power-on enable signal.

8. The circuit according to claim 7, characterized in that The operational amplifier comprises the input stage circuit, the gain stage circuit, the output stage circuit, a main bias circuit and the output stage bias circuit; The input stage circuit is used to receive an input signal; The gain stage circuit is used to amplify the input signal to obtain an amplified signal; The output stage circuit is used to output the amplified signal; The main bias circuit is used to provide the input stage circuit and the gain stage circuit with the bias current and / or bias voltage required for starting operation.

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