Coherent block read implementation

Abstract

A coherent memory fabric includes a plurality of coherence master controllers and a coherence slave controller. The plurality of coherence master controllers each include a response data buffer. The coherence slave controller is coupled to the plurality of coherence master controllers. The coherence slave controller sends a target request global order message to a selected coherence master controller and transmits response data in response to determining that a selected coherent block read command has only one data response guaranteed. The selected coherence master controller blocks any coherence probes for an address associated with the selected coherent block read command in response to receiving the target request global order message until receipt of the response data is requested client acknowledged.

Description

Background Technology

[0001] Computer systems utilize various peripheral components for different input / output and communication functions. A System-on-a-Chip (SoC) combines data processors such as a central processing unit (CPU) core and a graphics processing unit (GPU) with peripheral controllers and memory interfaces on a single integrated circuit chip and is well-suited for portable, battery-powered operation. For example, an SoC can combine a display controller, an image signal processor (ISP), and other peripheral controllers on the SoC to enable input and output of information to and from the computer system. In such multi-node SoCs, devices typically transfer data between resources such as memory via large on-chip routing circuitry or “data texture” routing access. In some systems, data texture is provided on the input / output (I / O) die, which includes a memory controller; however, multiple chiplets each contain processor cores. The chiplets and I / O dies are mounted to a network via high-speed interconnects such as wireless textures. TM (IF) Common package substrate for interconnect connection.

[0002] In such multi-node computer systems, consensus protocols are used to maintain the consistency of data used by different processing nodes. For example, if a processor attempts to access data at a certain memory address, it must first determine whether that memory is stored in another cache and has been modified. To implement such cache consensus protocols, caches typically contain multiple status bits to indicate the state of cache lines to maintain data consistency throughout the system. A common consensus protocol is called the "MOESI" protocol. According to the MOESI protocol, each cache line includes status bits indicating which MOESI state the line is in, including bits indicating that the cache line has been modified (M), that the cache line is exclusive (E) or shared (S), or that the cache line is invalid (I). An owned (O) state indicates that the line has been modified in one cache, a shared copy may exist in other caches, and the data in memory is stale. Transferring data between the cache subsystems of the first node and the cache subsystems of the second node typically involves multiple operations, each of which contributes to the transfer latency. Attached Figure Description

[0003] Figure 1 A block diagram illustrating the formation of a multi-CPU system according to the prior art is shown;

[0004] Figure 2 A data processor based on some specific implementations is illustrated in block diagram form;

[0005] Figure 3 A data processing system based on some specific implementations is illustrated in the form of a block diagram;

[0006] Figure 4 A portion of the data texture, based on some specific implementations, is illustrated in the form of a block diagram; and

[0007] Figure 5 A flowchart 500 is shown, illustrating a process for operating a memory system according to some specific implementations.

[0008] In the following description, the same reference numerals are used in different figures to indicate similar or identical items. Unless otherwise stated, the word “coupled” and its associated verb form include both direct connection and indirect electrical connection by means known in the art, and unless otherwise stated, any description of direct connection also implies an alternative specific embodiment using a suitable form of indirect electrical connection. Detailed Implementation

[0009] A consistent memory texture includes multiple consistent master controllers and consistent slave controllers. Each of the multiple consistent master controllers includes a response data buffer. A consistent slave controller is coupled to the multiple consistent master controllers. The consistent slave controller is operable to send a target request globally ordered message to the selected consistent master controller and transmit response data in response to determining that a selected consistent block read command from the selected consistent master controller has only one data response.

[0010] A method includes transmitting a consistent block read command from a consistent master controller to a consistent slave controller via a consistent data texture. At the consistent slave controller, the method includes sending a target request globally ordered message to the consistent master controller in response to determining that the consistent block read command guarantees only one data response, and transmitting response data via the consistent data texture.

[0011] A data processing system includes multiple data processors, volatile memory, and a consistent memory texture. The consistent memory texture includes multiple consistent master controllers and consistent slave controllers. Each of the multiple consistent master controllers includes a response data buffer. A consistent slave controller is coupled to the multiple consistent master controllers through the consistent memory texture. The consistent slave controller is operable to send a target request globally ordered message to the selected consistent master controller and transmit response data in response to determining that a selected consistent block read command from the selected consistent master controller guarantees that it has only one data response.

[0012] Figure 1A multi-CPU system 100 according to the prior art is illustrated in block diagram form. System 100 includes multiple CPUs 105A-105N. Each CPU 105A-105N may include any number of cores 108A-108N, wherein the number of cores varies depending on the specific implementation. Each CPU 105A-105N also includes a corresponding cache subsystem 110A-110N. Each cache subsystem 110A-110N may include any number of cache levels and any type of cache hierarchy structure.

[0013] Each CPU 105A-105N is connected to a corresponding consistency master block 115A-115N. The "consistency master block" is an agent that handles traffic flowing on the interconnect (e.g., bus / texture 118) and manages the consistency of the connected client processors. To manage consistency, the consistency master block receives and processes consistency-related messages and probes, and generates consistency-related requests and probes.

[0014] Each CPU 105A-105N is coupled to a pair of coherent slave blocks via a corresponding coherent master block 115A-115N and bus / texture 118. For example, CPU 105A is coupled to coherent slave blocks 120A-120B via coherent master block 115A and bus / texture 118. Coherent slave block (CS) 120A is coupled to memory controller (MC) 130A and coherent slave block 120B is coupled to memory controller 130B. Coherent slave block 120A is coupled to probe filter (PF) 125A, wherein probe filter 125A includes entries for memory regions having cache lines cached in system 100 for memory accessible through memory controller 130A. Probe filter 125A and each of the other probe filters may also be referred to as a "cache catalog". Similarly, consistency is coupled from block 120B to probe filter 125B, where probe filter 125B includes entries for a memory region having cache lines cached in system 100 for memory accessible via memory controller 130B. Each CPU 105A-105N may be connected to a number of memory controllers in addition to two.

[0015] In a configuration similar to that of CPU 105A, CPU 105B is coupled to coherence slave blocks 135A-135B via coherence master block 115B and bus / texture 118. Coherence slave block 135A is coupled to memory via memory controller 150A, and is also coupled to probe filter 145A to manage the coherence of cache lines corresponding to memory accessible through memory controller 150A. Coherence slave block 135B is coupled to probe filter 145B, and is also coupled to memory via memory controller 165B. Furthermore, CPU 105N is coupled to coherence slave blocks 155A-155B via coherence master block 115N and bus / texture 118. Coherence slave blocks 155A-155B are each coupled to probe filters 160A-160B, and are each coupled to memory via memory controllers 165A-165B. "Consistency from block" is an agent that manages consistency by processing received requests and probes targeting the corresponding memory controller. Additionally, "consistency probes" are messages passed from a consistency point to one or more caches in the computer system to determine whether the cache has a copy of the data block and optionally to indicate the state in which the cache should place the data block.

[0016] When a coherence slave block receives a memory request targeting its corresponding memory controller, the coherence slave block performs a parallel lookup of the corresponding early probe cache and the corresponding probe filter. Conversely, the coherence master block can perform an early probe. Each early probe cache in system 100 tracks a region of memory, where a region comprises multiple cache lines. The size of the tracked region may vary depending on the specific implementation. A “region” may also be referred to as a “page.” When a request is received by a coherence slave block, the coherence slave block determines the region that the request targets. Then, a lookup of the early probe cache for that region is performed in parallel with the lookup of the probe filter. The lookup of the early probe cache typically completes several loops before the lookup of the probe filter. If the lookup of the early probe cache results in a hit, the coherence slave block sends an early probe to the CPU identified in the hit entry. This facilitates early retrieval of data if the early probe cache identifies the correct target and reduces the latency associated with processing the memory request. It should be noted that additional connections may exist from bus / texture 118 to other components not shown to avoid obscuring the figures. For example, bus / texture 118 may include connections to one or more I / O interfaces and one or more I / O devices.

[0017] Figure 2A data processor 200 according to some specific embodiments is illustrated in block diagram form. The data processing system includes a package substrate 202, an input / output (I / O) die 204, and an eight-core CPU complex die (“CCD”) 206. In this specific embodiment, the CCD 206 and the I / O die 204 are mounted to the package substrate 204 and processed by high-speed infinite weaving. TM (IF) interconnects are used for connection. The package substrate 202 is packaged as a multi-chip module (MCM) for insertion into a socket (such as a pad grid array (LGA) socket) for connection to a printed circuit board (PCB) of a host data processing system.

[0018] In this specific embodiment, each CCD 206 includes multiple core complexes (CCXs), each core complex including multiple CPU cores and a shared L3 cache, wherein each CPU core includes L1 and L2 caches (not shown). Data textures are provided on I / O die 204, which includes a memory controller (also not shown), as further described below. While this specific embodiment shows a data processor configured as an MCM to illustrate a preferred embodiment of the data texture coherence protocol, in other embodiments, the features described herein may be embodied in a data processor implemented as a System-on-a-Chip (SoC).

[0019] Figure 3 A data processing system 300 according to some specific implementation is illustrated in block diagram form. The data processing system 300 typically includes components similar to... Figure 2 The data processor is constructed to include a multi-CPU core complex 311, a data texture 320, multiple memory controllers (“MCs”) 331, and multiple storage devices 341. Many other components typically present in actual data processing systems are irrelevant to understanding this disclosure and are not shown for ease of illustration. Figure 3 Example in.

[0020] Each CPU core complex 311 comprises a set of CPU cores, each of which is bidirectionally connected to the data texture 320. Each CPU core may be a single core that shares only the final cache with other CPU cores, or it may be combined with some, but not all, of the cores in the cluster. While multiple CPU core complexes 311 are depicted, other types of processors (not shown) are also typically connected to the data texture 320 as clients, such as GPU cores and display controllers.

[0021] Data texture 320 includes a set of consistency master controllers 321, each labeled "CM", a set of consistency slave controllers 323, each labeled "CS", interconnected via the texture transport layer 322, and multiple probe filters 324, each labeled "PF". The probe filters 324 can be of any suitable type. In some implementations, area probe filters are used, where areas that track multiple rows are used. Other implementations employ other types of probe filters, such as conventional row-based probe filters and their variants. As used herein, the consistency master controllers are considered master ports because they can be connected to a memory access agent capable of initiating a memory access request, regardless of whether the memory access request is a read or write access. Similarly, the consistency slave controllers are considered slave ports because they are connected to a memory access responder, such as a memory controller 311, capable of responding to a memory access request, regardless of whether the memory access request is a read or write access. The texture transport layer 322 includes crossbar routers or a series of switches for routing memory-mapped access requests and responses between its ports. Data texture 320 also includes a system memory map, typically defined by the Basic Input / Output System (BIOS), for determining the destination of memory accesses based on system configuration. Data texture 320 includes a coherence master controller for each attached memory access agent (such as CPU core complex 311). Each coherence master controller 321 has a bidirectional upstream port, a bidirectional downstream port, and control inputs, as well as its own internal buffer, which is used simultaneously for accesses received from clients via texture transport layer 223 and responses received from coherence slave blocks. Each coherence master controller 321 also has a control interface connected to its upstream port to provide backpressure signaling to the corresponding memory access agent, thereby avoiding exceeding its limited buffer space. Data texture 320 is also configured to have coherence slave controllers 323 for each of the memory controllers 331. Each coherence slave controller 323 has a buffer that allows memory access requests to be stored before or after processing via texture transport layer 322, depending on the direction.

[0022] Each of the memory controllers 331 has an upstream port connected to the data texture 320 via a corresponding coherent controller 323, and a downstream port connected to the corresponding storage device via a physical layer interface (PHY) (such as a Double Data Rate 5 (DDR5) PHY). In this embodiment, three of the memory controllers are connected to local memory channels and one memory controller (depicted on the right) is connected to a distributed memory module (such as a High Bandwidth Memory (HBM) module) via a Peripheral Component High Speed ​​Interface (PCIe) link. Thus, while the first three memory controllers 331 depicted reside on the same die as the data texture, a fourth memory controller is connected to the data texture 320 via a CXL PORT and resides on the memory module. The storage device 341 is preferably a Dynamic Random Access Memory (DRAM), such as Double Data Rate 5 (DDR5) DRAM, or a distributed memory module, such as an HBM module.

[0023] Data processing system 300 is a highly integrated, high-performance digital data processor that performs many functions associated with workstations, servers, etc. In operation, data processing system 300 implements a unified memory space, where all memories in the system are potentially visible to each memory access agent (such as CPU core complex 311). Data texture 320 is the medium that provides accesses initiated by memory access agents to memory access responders and returns responses from memory access responders to the initiating memory access agent. Data texture 320 uses a central texture transport layer 322 to multiplex accesses and responses between corresponding master and slave controllers based on system address mapping. The general operation of memory access agents (such as coherent master controller 321) is conventional and well-known in the art and will not be described further. Similarly, the general operation of memory access responders is well known and is usually specified by published standards, such as one or more of the Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) and HBM standards published by the Joint Electron Device Engineering Committee (JEDEC), and will not be described further except for the features introduced herein.

[0024] Figure 4 A portion of a data texture 400 according to some specific implementation is illustrated in block diagram form, which includes connections to data textures (such as...) Figure 3 The data texture is a consistent master controller 321 and a consistent slave controller 323.

[0025] The consistency master controller 321 includes controller and collector circuitry 402, a response data buffer 404 (“RSPQ”), a response data buffer counter 406 (“RSPQ CNT”), an output request queue 408 (“REQQ”), and a data port labeled “DP” connected to a client processor (such as a CPU core complex). The consistency master controller 321 may also include other buffers, such as write data buffers, which are not shown as they are not relevant to the description herein. The RSPQ 404 includes multiple entries 405 for storing data in response to memory requests on the data texture. The RSPQ CNT 406 is a counter that stores the values ​​of available entries 405. In operation, memory access requests are received from the client processor via the data port DP and stored in REQQ 408 in one of the entries 409 until they are implemented by the consistency master controller 321 through access to the appropriate consistency slave controller via the data texture 320. The consistency master controller 321 also processes consistency probes to its respective client processor. RSPQ CNT 406 increments as buffer entry 405 becomes available and decrements as a memory access request is acquired by the collector circuit 402 and the corresponding buffer entry 405 is allocated to receive data, as further described below.

[0026] The consistency slave controller 323 includes controller circuitry 420, a consistency slave data buffer 424 (“CSQ”), and a data port labeled “DP” connected to the memory controller. The consistency slave controller 323 may also include other buffers, such as write data buffers, which are not shown as they are not relevant to the description herein. As depicted, the consistency master controller 321 and the consistency slave controller 323 are connected via a data texture through two logical channels (command and data channel 410 and consistency probe channel 412). The CSQ 424 includes multiple entries 425 for storing response data received from the memory controller via the data port DP until the response data is sent to the consistency master controller 321 according to the specific protocol employed.

[0027] In operation, the consistency slave controller 323 receives memory access requests from the consistency master controller 321 and fulfills the requests by accessing the memory controller via its data port DP, or by accessing a consistency point at an address cached at another consistency point via a data texture. The controller circuitry 420 typically manages the implementation of read and write requests in the order they are received. Various consistency protocols are used in different implementations. In this implementation, a cached consistent non-uniform memory access (ccNUMA) architecture is employed, where the data ports connecting the various subsystems to the data texture are scalable data ports (SDPs), and a consistency hypertransport protocol is employed along with additional features described further below.

[0028] Figure 5 A flowchart 500 is shown illustrating a process for operating a memory system according to some specific implementation. The depicted process is applicable to... Figure 3 This is used in conjunction with the last-level cache and traffic monitor, or with other suitable memory systems including data textures with consistent slave controllers and consistent master controllers. The process begins at box 502, where it sends consistent block read commands from the consistent master controller (CM) to the consistent slave controller (CS) via the consistent data texture. This continues until sufficient buffer entries are in the consistent master controller's response data buffer (such as RSPQ 404). Figure 4 Commands are sent only when available at a certain point in the process. When a command is sent, the process allocates more than one buffer entry to receive the command's response data. More than one entry is needed because at this point in the process, it is unknown how many responses with response data will be provided from various coherent points on the memory system. For example, if the memory location targeted by a block read command is cached at more than one CPU, more than one response with response data can be expected.

[0029] At block 504, the consistency controller receives a consistency block read command and sends one or more consistency probes via data texture to determine the location where the most recent copy of the data for the target address of the command is stored, which may be somewhere in main memory or in various caches of the system. The consistency probe is a source (“RspToSrc”) type response indicating that the response will proceed to the requesting consistency block. In this implementation, the consistency protocol supports memory lines at various L1, L2, and L3 caches of the system CPU and GPU. Preferably, the consistency controller accesses probe filters (such as PF 324). Figure 3To accelerate consistency probe performance, the probe filter returns a set of potential probe targets to which the consistency probe is then sent by the consistency controller. Other probe filter arrangements, such as row-based probe filters, are used in some other implementations. In implementations where probe filters are not used, the consistency probe from the block is a predetermined set of targets specified for a particular memory address range.

[0030] When the consistency probe result is obtained at block 506, the process determines whether the result indicates that the consistent block read command has only one data response, or whether there may be more than one consistent point response data for the consistent block read command. If only one data response exists, the process proceeds to block 508; otherwise, the process proceeds to block 530. Preferably, the consistency determination is made from the block based on the result of a one-time probe. For example, in Figure 3 In this system, consistency probes from CS 323 to PF 324 may indicate that the target memory line is not cached by any of the CPU core complexes 311. In this case, only the response data from CS 323 (which may be obtained from storage device 341 or from the last-level cache between CS 323 and MC 331) will be provided to the requesting CM 321. In some cases, no consistency probe is sent at box 504 at all; for example, if the target memory region is marked as non-cacheable, then a consistency probe is not needed to determine that a consistent block read command has only one data response. In another scenario, the consistency probe indicates that only one cache is expected to return the probe result with data. In this case, the consistency controller also determines that only one consistency point will provide the response data, thus ensuring that the consistent block read command has only one data response.

[0031] At block 508, when the consistency slave controller implements the consistency block read command (typically in the order it is received), it receives response data from memory. Then, at block 510, the consistency slave controller sends a global ordered target request (“TgtReqGO”) to the consistency master controller via the consistency probe channel of the consistency data texture and begins transmitting response data via the data channel of the consistency data texture.

[0032] As shown in box 512, when the consistency slave controller has completed transmitting response data (which may occur some or all after boxes 512 to 520, depending on the speed of the data channel), the consistency slave controller immediately deals with the entries of the consistency slave data buffer previously allocated for the response data after transmitting the response data, without requiring a source completion message from the selected consistency master controller. In this specific implementation, the deallocation at box 512 occurs in response to determining that a consistency block read command from the selected consistency master controller guarantees that it has only one data response, which is the opposite of the conventional behavior shown in boxes 530 to 546, where the consistency slave controller must wait for a "SrcDone" message, as discussed further below.

[0033] At block 514, the consistency master controller receives the TgtReqGO message and begins receiving response data. The response data is loaded into the allocated entry in the consistency master controller's response data buffer. Also in response to receiving the target request globally ordered message, the consistency master controller executes blocks 516 through 520.

[0034] At box 516, the consistency master controller blocks any consistency probes used for the address associated with the consistency block read command until response data is received via the data channel, forwarded to the requesting client, and acknowledged by the requesting client. At box 518, the consistency master controller reduces the allocation at the response data buffer to a single entry because it is known that no further responses will be received. In some implementations, this is done by incrementing a counter indicating the number of data buffer entries available in the response data buffer (such as, for example, RSPQ buffer counter 406). Figure 4 This is accomplished by [the process described in the original text]. Other specific implementations may directly associate commands with response data buffer entries, in which case the consistency master controller removes the allocation of additional entries to make them available, so that only one entry is allocated to receive response data. At block 520, the consistency master block sends a subsequent memory access command, which, depending on the target address associated with the command, can be sent to the same consistency slave controller to which the consistency block read command was sent, or to another consistency slave controller.

[0035] At block 506, if the consistency slave controller determines that it does not guarantee that the consistent block read command has only one data response, the process proceeds to block 530, where it receives response data when implementing the consistent block read command. At block 532, the consistency slave controller transmits a target complete (“TgtDone”) message to the consistency master controller via the consistency probe channel and begins transmitting the response data of the consistent block read command to the consistent master block via the data channel.

[0036] At box 534, the consistency master controller receives the TgtDone message and begins receiving response data. At box 536, the consistency master controller completes receiving the response data and awaits further responses from the consistency probe (sent at box 504). At box 538, the consistency master controller receives one or more additional responses to the consistency probe, which may include response data or may include an indication that the consistency point does not have response data. Responses may arrive before responses from the consistency slave controllers. Incoming response data is loaded into a second allocated entry in the response data buffer. If response data newer than that sent by the consistency slave controller is received, the consistency master controller will overwrite the older entry with a third or subsequent response (if such a response occurs). When all responses have been received, the consistency master block forwards the correct, most recent data to the requesting client, such as the CPU or GPU, as shown in box 540.

[0037] Then, at box 542, when the client acknowledges receipt of the response data, the consistency master controller dealslocates the response data buffer entry from which it sent data and sends a source complete (“SrcDone”) message to the consistency slave controller. At box 544, the consistency slave controller receives the SrcDone message and, in response, dealslocates the data buffer entry from which data was transmitted. Next, at box 546, the consistency master controller sends a subsequent memory access command, thereby allocating an entry for it in the response data buffer.

[0038] Generally, in this specific implementation, the consistent hypertransport protocol shown in boxes 530-546 is used only when there may be more than one response to the command. The SrcDone message transmitted from the consistent master controller to the consistent slave controller notifies the consistent slave controller that the read response has been made visible to the requesting client, and the consistent slave block is free to move to the next address matching transaction. This process avoids contention for consistent probes for newer transactions to the same address. However, it is anticipated that most cache block reads will not result in consistent probes. Therefore, the SrcDone message required for each cache block read increases the average lifetime of transactions at the consistent slave block beyond the average lifetime achieved by the depicted process. Furthermore, when the consistent protocol uses the read response to the cache block read at the consistent master block to resolve the consistent probe, as is generally more efficient for reads, it must contend for the possibility of two responses with data that may arrive at different times. This possibility adds a design burden to reserve multiple data buffer entries at the consistent master block for each cache block read sent to the consistent slave block.

[0039] Instead of using the slower SrcDone message sequence, the processes in boxes 506 to 520 employ a different message in the probe channel: Globally Ordered Target Request (TgtReqGO). In some implementations, the TgtReqGO message can be implemented as a single bit carried within a conventional Hypertransport Protocol Target Complete (TgtDone) message. In other implementations, it can be a packet used instead of the TgtDone message. TgtReqGO blocks processing of any newer probes to the same address until the previous transaction is fully completed. The advantages are most pronounced when no consistency probes are issued or when a single known external cache is expected to return a probe response with data. When TgtReqGO is issued, significant advantages are provided in data buffer management because the consistency master can release data buffer entries previously held to receive additional probe responses with response information. Furthermore, data buffer entries at the consistency controller are released faster than in the conventional case. As can be understood, this allows for the use of response data buffers (e.g., RSPQ 404) at the consistency master block. Figure 4 ) and consistency from the data buffer at the block level (e.g., CSQ 424, Figure 4 Both have smaller data buffer designs.

[0040] Figure 3 The data texture 320 or any part thereof (such as the coherence master controller 321 and the coherence slave controller 323) may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and is used directly or indirectly for manufacturing integrated circuits. For example, the data structure may be a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes gate sets that also represent the functionality of the hardware comprising the integrated circuit. The netlist can then be placed and routed to produce a dataset describing the geometry to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on a computer-accessible storage medium may be a netlist (with or without a synthesis library), a dataset (as needed), or Graphical Data System (GDS) II data.

[0041] While specific implementations have been described, various modifications to these implementations will be apparent to those skilled in the art. Various techniques for maintaining a low-power state using the probe filters disclosed herein can be used independently or in combination with other techniques. Furthermore, different techniques and circuits can be used to detect the conditions that trigger the entry into the low-power state.

[0042] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A consistent memory texture, the consistent memory texture comprising: Multiple consistency master controllers, each coupled to its own memory access agent capable of initiating memory access requests, and each consistency master controller includes a response data buffer; Transport layer; and A consistency slave controller, coupled to the plurality of consistency master controllers via the transport layer and coupled to a memory controller for responding to memory access requests and providing response data to the consistency slave controller, the consistency slave controller being operable to send a message to the selected consistency master controller and transmit response data in response to determining that a selected consistency block read command from the selected consistency master controller has only one data response, wherein the selected consistency master controller updates the allocation in the response data buffer in response to the message such that only one response data buffer entry is reserved for the selected consistency block read command.

2. The consistent memory texture of claim 1, wherein the selected consistent master controller is operable to block any consistency probes for the address associated with the selected consistent block read command in response to receiving the message, until the reception of the response data is acknowledged by the requesting client.

3. The consistent memory texture of claim 1, wherein the selected consistent master controller transmits subsequent memory access commands to the consistent slave controller immediately after updating the allocation.

4. The consistent memory texture according to claim 1, wherein: The consistency slave controller also includes a consistency slave data buffer; and In response to determining that a selected consistent block read command from the selected consistent master controller has only one data response, the consistent slave controller immediately deals with the entry of the consistent slave data buffer previously allocated for the response data after transmitting the response data, without requiring a source completion message from the selected consistent master controller.

5. The consistent memory texture according to claim 4, wherein: In response to determining that the second selected consistency block read command does not guarantee that it has only one data response, the consistency slave controller transmits a target completion message to the selected consistency master controller, transmits the response data to the selected consistency master controller, and only releases the consistency slave data buffer entry for the response data after receiving a source completion message indicating that the response data has been received from the selected consistency master controller.

6. The consistent memory texture of claim 1, wherein the consistent slave controller determines that the selected consistent block read command has only one data response by performing a probe filter lookup in a probe filter associated with the plurality of consistent master controllers.

7. A method, the method comprising: The consistency master controller transmits a consistency block read command to the consistency slave controller via a consistency data texture. The consistency slave controller is coupled to a memory controller that responds to memory access requests and provides response data to the consistency slave controller. At the consistency controller, it is determined that the consistent block read command has only one data response. The message is sent to the consistency master controller and response data is transmitted, wherein the consistency master controller updates the allocation in the response data buffer in response to the message, such that only one response data buffer entry is reserved for the consistency block read command.

8. The method according to claim 7, further comprising: At the consistency master controller, in response to receiving the message, any consistency probes for the address associated with the consistency block read command are blocked until the response data is received.

9. The method of claim 7, wherein the consistency master controller immediately transmits subsequent memory access commands to the consistency slave controller after updating the allocation.

10. The method of claim 7, wherein the consistency slave controller, in response to determining that the consistency block read command from the selected consistency master controller has only one data response, immediately deals with the entry of the consistency slave data buffer previously allocated for the response data after transmitting the response data, without requiring a source completion message from the selected consistency master controller.

11. The method of claim 7, wherein the consistency slave controller transmits a target completion message to the consistency master controller in response to determining that the second consistency block read command does not guarantee that it has only one data response, transmits second response data to the consistency master controller, and only releases the data buffer entry for the response data after receiving a source completion message from the consistency master controller indicating that the second response data has been received.

12. The method of claim 7, wherein the consistency is initiated from the controller in parallel with sending the message or immediately after sending the message to transmit the response data.

13. The method of claim 7, wherein the consistency slave controller determines that the consistency block read command has only one data response by performing a probe filter lookup in a probe filter associated with a plurality of consistency master controllers.

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