Drive circuit, isolation device and electronic device

Abstract

The application provides a driving circuit, an isolation device and electronic equipment, which are simple in structure. The voltage adjustment module comprises N groups of boosting groups, an integration unit and a driving signal output end, each group of boosting groups comprises a storage unit and a one-way transmission unit; the first end of the one-way transmission unit of the even boosting group, the second end of the one-way transmission unit of the previous boosting group and the first end of the storage unit are coupled to a first node; the first end of the one-way transmission unit of the odd boosting group, the second end of the one-way transmission unit of the previous boosting group and the first end of the storage unit are coupled to a second node; the first end of the one-way transmission unit of the first group of boosting groups receives a power supply signal, the second ends of the storage units of the odd and even boosting groups respectively receive first and second pulse width modulation signals which are the same in frequency and opposite in phase; the second end of the one-way transmission unit of the Nth group of boosting groups and the first end of the storage unit are coupled to a third node; the integration unit is arranged between the third node and the driving signal output end.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, and particularly relates to a driving circuit, an isolation device and an electronic device. BACKGROUND

[0002] When designing a circuit, a Metal Oxide Semiconductor (MOS) field effect transistor (MOS tube for short) is sometimes used to isolate signals, such as power signals, to ensure the reliability and stability of the circuit.

[0003] The conduction and cutoff of the MOS tube are generally driven by a driving chip. However, the existing driving chip has a complex structure and a complex integrated process, which leads to a high cost and is not conducive to reducing the cost of the electronic device. SUMMARY

[0004] To solve the above technical problems, the present application provides a driving circuit, an isolation device and an electronic device. The structure is simple, which is conducive to reducing the cost of the electronic device.

[0005] In a first aspect, the present application provides a driving circuit, which comprises a voltage adjustment module; the voltage adjustment module comprises N groups of boost groups, an integration unit and a driving signal output end, each group of boost groups comprises a storage unit and a unidirectional transmission unit, wherein N is a positive integer greater than or equal to 1; the first end of the unidirectional transmission unit of an even-numbered boost group, the second end of the unidirectional transmission unit of the previous boost group of the even-numbered boost group and the first end of the storage unit of the previous boost group of the even-numbered boost group are coupled to a first node; except for the first group of boost groups, the first end of the unidirectional transmission unit of an odd-numbered boost group, the second end of the unidirectional transmission unit of the previous boost group of the odd-numbered boost group and the first end of the storage unit of the previous boost group of the odd-numbered boost group are coupled to a second node; the first end of the unidirectional transmission unit of the first group of boost groups is used to receive a power signal, the second end of the storage unit of the odd-numbered boost group is used to receive a first pulse width modulation signal, the second end of the storage unit of the even-numbered boost group is used to receive a second pulse width modulation signal, the first pulse width modulation signal and the second pulse width modulation signal have the same frequency and opposite phases; the second end of the unidirectional transmission unit of the Nth group of boost groups and the first end of the storage unit of the Nth group of boost groups are coupled to a third node; the integration unit is arranged between the third node and the driving signal output end.

[0006] Based on the first pulse width modulation signal and the second pulse width modulation signal, the N groups of boost groups sequentially boost the power signal received by the first end of the unidirectional transmission unit of the first group of boost groups through the storage unit to form a high-low square wave signal, and the integral unit integrates the square wave signal to obtain a direct current signal and outputs the direct current signal to the gate of the NMOS tube through the driving signal output end. Without setting a complex boost structure, a higher driving voltage (driving signal for driving the NMOS tube to turn on or off) can be output. That is, the driving circuit provided by the present application has a simple structure, which is beneficial to reducing the cost of electronic equipment.

[0007] For example, the frequency and duty cycle of the first pulse width modulation signal and the second pulse width modulation signal are adjustable. By adjusting the frequency and / or duty cycle of the first pulse width modulation signal and the second pulse width modulation signal, the size of the driving signal output to the gate of the NMOS tube can be changed.

[0008] For example, when N is even, the third node can also be referred to as the second node of the Nth group of boost groups. When N is odd, the third node can also be referred to as the first node of the Nth group of boost groups.

[0009] For example, the driving circuit can be used to drive the NMOS tube, of course, which does not constitute a limitation to the present application.

[0010] According to the first aspect, the driving circuit further comprises an off module, the first end of the off module is electrically connected with the driving signal output end, the second end of the off module is grounded, and the control end of the off module is used to receive a switch control signal; when the off module is turned on according to the received switch control signal, the driving signal output end is grounded.

[0011] That is, the driving circuit not only can turn on the NMOS tube, but also can turn off the NMOS tube, so that the application of the driving circuit is more extensive.

[0012] According to the first aspect, or any one of the implementation manners of the first aspect, the voltage adjustment module comprises a first group of boost groups and a second group of boost groups; the first end of the unidirectional transmission unit of the second group of boost groups, the second end of the unidirectional transmission unit of the first group of boost groups, and the first end of the storage unit of the first group of boost groups are coupled to the first node; the second end of the unidirectional transmission unit of the second group of boost groups and the first end of the storage unit of the second group of boost groups are coupled to the third node; the second end of the storage unit of the first group of boost groups is used to receive the first pulse width modulation signal, and the second end of the storage unit of the second group of boost groups is used to receive the second pulse width modulation signal.

[0013] The boost of the power signal can be realized by two groups of boost groups, which has a simple structure and occupies a small area.

[0014] According to the first aspect, or any one of the implementations of the first aspect, the storage unit comprises a storage capacitor; a first pole of the storage capacitor of the odd voltage boosting group is electrically connected to the first node, and a second pole of the storage capacitor of the odd voltage boosting group is configured to receive the first pulse width modulation signal; a first pole of the storage capacitor of the even voltage boosting group is electrically connected to the second node, and a second pole of the storage capacitor of the even voltage boosting group is configured to receive the second pulse width modulation signal.

[0015] The storage function is realized by one capacitor, the structure of the storage unit is simple, and thus the structure of the driving circuit is simple and the cost is low.

[0016] According to the first aspect, or any one of the implementations of the first aspect, the unidirectional transmission unit comprises a diode; an anode of the diode of the even voltage boosting group, a cathode of the diode of the previous voltage boosting group of the even voltage boosting group, and a first end of the storage unit of the previous voltage boosting group of the even voltage boosting group are coupled to the first node; except for the first voltage boosting group, an anode of the diode of the odd voltage boosting group, a cathode of the diode of the previous voltage boosting group of the odd voltage boosting group, and a first end of the storage unit of the previous voltage boosting group of the odd voltage boosting group are coupled to the second node.

[0017] The unidirectional conduction function is realized by one diode, interference between signals at the first node and the second node is avoided, the structure of the unidirectional transmission unit is simple, and thus the structure of the driving circuit is simple and the cost is low.

[0018] According to the first aspect, or any one of the implementations of the first aspect, the integration unit can comprise a first resistor and an integration capacitor; a first end of the first resistor is electrically connected to the third node, a second end of the first resistor is electrically connected to a first pole of the integration capacitor and the driving signal output end respectively, and a second pole of the integration capacitor is grounded.

[0019] The structure of the integration unit is simple, and thus the structure of the driving circuit is simple and the cost is low.

[0020] According to the first aspect, or any one of the implementations of the first aspect, the driving circuit further comprises a protection module, a first end of the protection module is electrically connected to the driving signal output end, and a second end of the protection module is grounded; the protection module is configured to pull down a signal at the driving signal output end to the ground when the driving circuit does not receive the power signal, the switch control signal, the first pulse width modulation signal, and the second pulse width modulation signal.

[0021] In this way, the problem that the gate of the NMOS transistor is normally turned on due to interference of some other signals or the like can be avoided.

[0022] According to the first aspect, or any one of the implementations of the first aspect, the protection module comprises a second resistor, a first end of the second resistor is electrically connected with the driving signal output end, and a second end of the second resistor is grounded.

[0023] The protection module has a simple structure, and thus the driving circuit has a simple structure and low cost.

[0024] According to the first aspect, or any one of the implementations of the first aspect, the shutdown module comprises a metal oxide semiconductor field effect transistor, and the specific structure of the shutdown module is not limited in the application, as long as the shutdown module can turn off the NMOS transistor when the driving circuit is not powered on, to avoid the problem that the gate of the NMOS transistor is normally turned on due to interference of some other signals or the like.

[0025] According to the first aspect, or any one of the implementations of the first aspect, when the shutdown module is turned on according to the received switch control signal, the duration of the shutdown module being turned on is greater than or equal to a preset duration. In this way, the voltage at the gate of the NMOS transistor can be quickly discharged to the ground, and the voltage on the integration capacitor in the integration circuit can also be quickly discharged to the ground, so that the voltage at the gate of the NMOS transistor quickly becomes 0V, that is, the speed of turning off the NMOS transistor is accelerated.

[0026] For example, the preset duration is 50 microseconds, 60 microseconds, 70 microseconds, 80 microseconds, or the like.

[0027] According to the first aspect, or any one of the implementations of the first aspect, when N is an even number, the highest voltage V max satisfies:

[0028] V max =V0+(N / 2)V P1 +(N / 2)V P2 -NV d ;

[0029] The lowest voltage V min at the third node satisfies:

[0030] V min =V0+(N / 2)V P1 +{(N-2) / 2}V P2 - NV d ;

[0031] When N is an odd number, the highest voltage V max at the third node satisfies:

[0032] V max =V0+{(N+1) / 2}V P1 +{(N-1) / 2}V P2-NV d ;

[0033] The lowest voltage V at the third node min Satisfies:

[0034] V min = V0+{(N-1) / 2}V P1 +{(N-1) / 2}V P2 -NV d ;

[0035] Wherein, V d is the voltage drop of the unidirectional conduction unit, V P1 is the maximum voltage of the first pulse width modulation signal, and V P2 is the maximum voltage of the second pulse width modulation signal.

[0036] It should be noted that the above formula is applicable to the case where the voltage drops of the diodes are the same. For the case where the voltage drops of the diodes are different, the voltage drops of the diodes can be subtracted in turn.

[0037] According to the first aspect, or any one of the implementation forms of the first aspect, the driving circuit further includes a control module, and the control module is configured to output the first pulse width modulation signal and the second pulse width modulation signal.

[0038] The driving circuit can be provided with a control module alone, so that the application range of the driving circuit is wider. Of course, when the driving circuit is applied to an electronic device, the driving circuit can also be provided with the first pulse width modulation signal and the second pulse width modulation signal by other modules in the electronic device, such as a PMU.

[0039] In a second aspect, the application provides an isolation device, which includes an NMOS tube and the driving circuit corresponding to the first aspect and any one of the implementation forms of the first aspect, and the gate of the NMOS tube is electrically connected to the driving signal output end of the driving circuit; the driving circuit is configured to provide a driving signal to the gate of the NMOS tube through the driving signal output end, so as to drive the NMOS tube to be turned on or turned off.

[0040] The second aspect and any one of the implementation forms of the second aspect correspond to the first aspect and any one of the implementation forms of the first aspect respectively. The technical effects corresponding to the second aspect and any one of the implementation forms of the second aspect can be referred to the technical effects corresponding to the first aspect and any one of the implementation forms of the first aspect, which will not be described herein again.

[0041] In a third aspect, the application provides an electronic device, which includes the isolation device according to the second aspect.

[0042] The third aspect and any kind of implementation manner of the third aspect correspond to the second aspect and any kind of implementation manner of the second aspect respectively. The technical effects corresponding to the third aspect and any kind of implementation manner of the third aspect can refer to the technical effects corresponding to the second aspect and any kind of implementation manner of the second aspect, which will not be described herein again.

[0043] According to the third aspect, the electronic device further comprises a power management chip, and the power management chip is configured to output the first pulse width modulation signal and the second pulse width modulation signal.

[0044] That is, the power management chip in the electronic device is directly used to output the first pulse width modulation signal and the second pulse width modulation signal, and a control module does not need to be separately arranged for the driving circuit, so that the structure of the driving circuit is simplified, and the electronic device is facilitated to reduce cost.

[0045] According to the third aspect or any kind of implementation manner of the third aspect, the electronic device comprises a first battery and a second battery; the source of the NMOS tube is electrically connected with the first battery, and the drain of the NMOS tube is electrically connected with the second battery.

[0046] The isolation device is configured to isolate the first battery and the second battery, and when the first battery and the second battery are in communication (for example, one of them charges the other), the isolation device is further configured to perform voltage balancing on the voltages of the first battery and the second battery, so that the voltages of the two batteries connected by the isolation device are balanced, so as to reduce the voltage difference between the two batteries connected by the isolation device, and further limit the mutual charging current between the two batteries connected by the isolation device. When the electronic device is a foldable electronic device, the possibility of burning the distributed traces on the FPC due to large mutual charging current generated between the two batteries connected by the isolation device is reduced, and the safety and reliability of the foldable electronic device are improved.

[0047] According to the third aspect or any kind of implementation manner of the third aspect, the electronic device comprises a battery and a load; the source of the NMOS tube is electrically connected with the battery, and the drain of the NMOS tube is electrically connected with the load.

[0048] The isolation device is configured to isolate the battery and the load, and when the battery and the load are in communication (for example, the battery supplies power to the load), the isolation device is further configured to adjust the voltage provided by the battery to the load, so that the voltages of the battery and the load connected by the isolation device are balanced, so as to reduce the voltage difference between the two batteries connected by the isolation device to meet the power supply requirement.

[0049] Of course, the application of the isolation device in the electronic device is not limited to the above two cases, and the isolation device can be used as long as the devices need to be isolated. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1An output characteristic curve of the NMOS tube;

[0051] Figure 2 A structural schematic diagram of a foldable electronic device provided by an embodiment of the present application;

[0052] Figure 3a A schematic diagram of a foldable mobile phone when folded, provided by an embodiment of the present application;

[0053] Figure 3b Another schematic diagram of a foldable mobile phone when folded, provided by an embodiment of the present application;

[0054] Figure 4 A structural schematic diagram of another foldable electronic device provided by an embodiment of the present application;

[0055] Figure 5 A partial structural schematic diagram of a foldable electronic device provided by an embodiment of the present application;

[0056] Figure 6 A circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0057] Figure 7 Another circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0058] Figure 8 Another circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0059] Figure 9 Another circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0060] Figure 10 Another circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0061] Figure 11 Another circuit diagram of a foldable electronic device provided by an embodiment of the present application;

[0062] Figure 12 A waveform diagram of a first PWM signal and a second PWM signal provided by an embodiment of the present application;

[0063] Figure 13 Another circuit diagram of an isolation circuit provided by an embodiment of the present application;

[0064] Figure 14 A waveform diagram of a signal at a first node and a signal at a second node provided by an embodiment of the present application;

[0065] Figure 15 A voltage waveform diagram after integration of a waveform diagram of a signal at a second node provided by an embodiment of the present application. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be clearly and completely described in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0067] The term "and / or" in the present application is only used to describe the association relationship of the associated objects, and indicates that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone.

[0068] The terms "first" and "second" and the like in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, rather than to describe a specific order of the target objects.

[0069] In the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "exemplary" or "for example" are intended to present the relevant concept in a specific manner.

[0070] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0071] For ease of description, the MOS tube involved in the embodiments of the present application will be briefly introduced first.

[0072] The MOS tube includes PMOS and NMOS, and both PMOS and NMOS include a gate (generally represented by G), a source (generally represented by S), and a drain (generally represented by D). Both PMOS and NMOS have two states, namely, a conduction state and a cutoff state (also referred to as an off state). When the MOS tube changes from the cutoff state to the conduction state, a driving voltage is needed for driving. The relationship between the MOS tube driving voltage and the states is shown in Table 1.

[0073] Table 1 Relationship between MOS tube driving voltage and states

[0074]

[0075] V G V S V D V GS V DS V th V

[0076] From Table 1, for PMOS, when V GS < V th , the PMOS is on; when V GS > V th , the PMOS is off. For NMOS, when V GS > V th , the NMOS is on; when V GS < V th , the NMOS is off.

[0077] In addition, the concept of linear region and saturation region of MOS is introduced, taking NMOS as an example.

[0078] Figure 1 The output characteristic curve of NMOS, where the horizontal axis V DS is the drain-source voltage difference, the vertical axis I D is the drain current, and V GS is the gate-source voltage difference. Referring to Figure 1 , the output characteristic of MOS can be divided into three regions: cutoff region (also off region), constant current region (also saturation region), and variable resistance region (also linear region). When V GS > V th , I D will first show a linear growth with the increase of V DS , and then a flat region. The linear growth stage is called variable resistance region. In this stage, MOS is equivalent to a resistor, and its resistance is the inverse of its slope. When V GS is different, the resistance value will be different, that is, in this region, MOS is equivalent to a resistor with V GSThe controlled variable resistance, that is, when the gate voltage of the MOS tube is adjusted, the resistance value of the MOS tube in the variable resistance region (also the linear region) can be adjusted. It can be understood that when the resistance value changes, the voltage value and current value passing through the MOS tube will change accordingly. The flat stage is called the constant current region (also the saturation region). In this stage, I D does not change with the change of V DS , that is, the current passing through the MOS tube does not change. And because the on-resistance Rds(on) of the MOS tube is very small, the voltage drop after passing through the MOS tube is very small, and the voltages of the source and the drain of the MOS tube are almost equal when the MOS tube is turned on.

[0079] The present application provides an electronic device. The electronic device provided by the embodiments of the present application can be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a television, a smart wearable device, a smart home device, a power bank, a new energy vehicle, and the like. In addition, the electronic device provided by the present application can be a straight type electronic device (such as a straight type mobile phone) or a folding type electronic device (such as a folding type mobile phone), and the specific type and specific form of the electronic device are not limited in the embodiments of the present application. Hereinafter, the electronic device is taken as a folding type mobile phone for example.

[0080] Referring to Figure 2 , Figure 2 , a structural schematic diagram of a folding type electronic device provided by the embodiments of the present application is shown. As shown in Figure 2 , the folding type mobile phone 100 includes a flexible screen (also referred to as a folding screen, etc.) 10.

[0081] The flexible screen 10 is, for example, a display screen with flexibility. The flexible screen 10 includes, for example, an Organic Light Emitting Diode (OLED) display screen. The OLED display screen does not need a backlight module, and the substrate substrate in the OLED display screen can be made of a flexible resin material, for example, Polyethyleneterephthalate (PET), so that the OLED display screen has a bendable characteristic. Of course, the type of the flexible screen 10 includes but is not limited to the OLED display screen, and any display screen that can be bent is within the protection scope of the present application, for example, a Liquid Crystal Display (LCD) screen, an LED display screen (for example, including a Micro-LED display screen and a Mini-LED display screen), and the like.

[0082] Continuing to refer to Figure 2The foldable phone 100 also includes structural components. These components include a first body 20, a second body 30, and a hinge structure 40. The first body 20 and the second body 30 are located on either side of the hinge structure 40, and the hinge structure 40 is connected to both the first body 20 and the second body 30. The first body 20, the hinge structure 40, and the second body 30 can support the flexible screen 10. The first body 20 and the second body 30 can rotate around the axis S0 of the hinge structure 40, thus enabling the flexible screen 10 to fold or unfold, and consequently, the foldable phone 100 to fold or unfold.

[0083] Figure 2 The image shown is a schematic diagram of a foldable phone unfolded. Figure 3a and 3b The diagram shown illustrates a foldable phone when folded. Figure 3a In the case of a foldable phone, when folded, it can face the light-emitting direction of the flexible screen 10. Figure 3a (As indicated by the middle arrow) Folding, that is, the first body 20 and the second body 30 rotate around the axis S0 of the rotating shaft structure 40 in the same direction as the light emission direction of the flexible screen 10. Figure 3b In the middle, when the foldable phone is folded, it can emit light in a direction away from the flexible screen 10. Figure 3b (As indicated by the middle arrow) Folding, that is, the direction in which the first body 20 and the second body 30 rotate around the axis S0 of the rotating shaft structure 40 is opposite to the light emission direction of the flexible screen 10.

[0084] It should be noted that the foldable phone 100 can fold at multiple locations. Correspondingly, the structural components may include multiple hinge structures 40 and multiple bodies. For example, it may include two hinge structures 40 and three bodies, with adjacent bodies connected by a hinge structure 40. Thus, the foldable phone 100 has two folding positions. Therefore, the structural components include at least one hinge structure 40 and at least two bodies, with adjacent bodies connected by a hinge structure 40. For ease of explanation, the embodiments in this application are described using an example where the structural components include one hinge structure 40 and two bodies (i.e., the first body 20 and the second body 30).

[0085] It should also be noted that, such as Figure 2 As shown, the foldable phone 100 can form two screens, left and right, when folded, but this does not constitute a limitation of this application. See other optional embodiments of this application. Figure 4 The foldable phone 100 can also form two screens, one on top and one on the bottom, when folded.

[0086] See also Figure 2The first body 20 includes a first shell 21 and a first middle frame 22, and the flexible screen 10, the first shell 21 and the first middle frame 22 enclose a first accommodating space 23. The second body 30 includes a second shell 31 and a second middle frame 32, and the flexible screen 10, the second shell 31 and the second middle frame 32 enclose a second accommodating space 33.

[0087] It should be noted that the first shell 21 and the second shell 31 can be the outer shell of the folding mobile phone 100; can be display screens for display; or one of the first shell 21 and the second shell 31 is a display screen, and the other is the outer shell of the folding mobile phone 100, and the embodiments of the present application are not limited thereto.

[0088] Referring to Figure 5 , Figure 5 is a partial structural schematic diagram of a folding electronic device provided by the embodiments of the present application. As shown in Figure 5 , the folding mobile phone 100 further includes a first mainboard 50, a second mainboard 60, a flexible printed circuit (FPC) 70 and the like. The first mainboard 50 is located in the first accommodating space 23, and the second mainboard 60 is located in the second accommodating space 33. One end of the flexible printed circuit 70 is electrically connected with the first mainboard 50, and the other end of the flexible printed circuit 70 is electrically connected with the second mainboard 60, so that the first mainboard 50 and the second mainboard 60 are electrically connected through the flexible printed circuit 70.

[0089] It should be noted that the electrical connection between the first mainboard 50 and the second mainboard 60 can be realized by one flexible printed circuit 70; the electrical connection between the first mainboard 50 and the second mainboard 60 can also be realized by multiple (at least two) flexible printed circuits 70, Figure 5 only one flexible printed circuit 71 is taken as an example to realize the electrical connection between the first mainboard 50 and the second mainboard 60.

[0090] It should be further noted that the above example only takes the folding mobile phone 100 including one flexible printed circuit 70 connecting the first mainboard 50 and the second mainboard 60 as an example, and the folding mobile phone 100 further includes other flexible printed circuits to realize the connection between other elements and the first mainboard 50 or the second mainboard 60.

[0091] In order to realize the functions such as battery life of the folding mobile phone 100, referring to Figure 6 , Figure 6 is a circuit diagram of a folding electronic device provided by the embodiments of the present application. As shown in Figure 6As shown, the folding mobile phone 100 further includes a processing module 80, a first battery 81, a second battery 82, a universal serial bus (USB) interface 83, a power management unit (PMU) 84, an isolation circuit 85, and the like.

[0092] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the folding mobile phone 100. In other embodiments of the present application, the folding mobile phone 100 can include more or fewer components than shown, or combine certain components, or change the location of the components. The components shown can be implemented in hardware, software, or a combination of hardware and software.

[0093] The first battery 81 is arranged in the first accommodating space 23, and the second battery 82 is arranged in the second accommodating space 33, i.e., the first battery 81 and the second battery 82 are respectively located on the left and right sides of the shaft structure 40.

[0094] The processing module 80 and the PMU 84 can be arranged on the first mainboard 50 in the first accommodating space 23, and the electrical connection of the processing module 80 and the PMU 84 is realized through the first mainboard 50. The first middle frame 22 of the first body 20 is provided with an opening, and the USB interface 83 is embedded in the opening.

[0095] The processing module 80 can be a MCU (Microcontroller Unit), a SOC (System on Chip), or any device with data processing function, and the embodiments are not limited thereto. For example, when the electronic device is a notebook computer, the processing module 80 can be a MCU, and when the electronic device is a mobile phone, the processing module 80 can be a SOC.

[0096] The processing module 80 can include one or more interfaces, and the connection and signal interaction with other modules are realized through the interfaces. The interfaces can include a GPIO (General-Purpose Input / output) interface and the like.

[0097] The USB interface 83 is an interface conforming to the USB standard specification, and can be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 83 can be used to connect a charger to charge the first battery 81 and / or the second battery 82, and can also be used to transmit data between the folding mobile phone 100 and peripheral devices. It can also be used to connect a headset to play audio through the headset. The interface can also be used to connect other electronic devices, such as AR devices and the like.

[0098] In some embodiments, a first voltage conversion unit (not shown in the figure) is further arranged between the USB interface 83 and the first battery 81, and a second voltage conversion unit is further arranged between the USB interface 83 and the second battery 82.

[0099] The first voltage conversion unit can convert the charging power at the USB interface 83 into the required charging voltage and charging current of the first battery 81. The second voltage conversion unit can convert the charging power at the USB interface 83 into the required charging voltage and charging current of the second battery 82.

[0100] It should be noted that the first voltage conversion unit and the second voltage conversion unit can be arranged separately or integrated in one module, which can be a charging management module, as shown in Figure 7 The charging management module can also be referred to as a Charger IC.

[0101] The isolation circuit 85 can be located on the first mainboard 50 in the first accommodating space 23, or on the second mainboard 60 in the second accommodating space 33. The embodiments of the present application take the isolation circuit 85 located on the second mainboard 60 in the second accommodating space 33 as an example for description. Continue to refer to Figure 7 The isolation circuit 85 is electrically connected with the first battery 81 through the FPC 70 and the first mainboard 50, and is electrically connected with the second battery 82 through the second mainboard 60. The first battery 81 is electrically connected with the PMU 84 through the first mainboard 50, and the second battery 82 is electrically connected with the PMU 84 through the second mainboard 60, the isolation circuit 85 on the second mainboard 60, the FPC 70 and the first mainboard 50; or, referring to Figure 8 The second battery 82 is electrically connected with the PMU 84 through the second mainboard 60 and the FPC 70, and the first battery 81 is electrically connected with the PMU 84 through the first mainboard 50, the FPC 70 and the isolation circuit 85 on the second mainboard 60.

[0102] The isolation circuit 85 is used to isolate the first battery 81 and the second battery 82. When the first battery 81 and the second battery 82 are in communication, the isolation circuit 85 is also used for voltage equalization of the voltage of the first battery 81 and the second battery 82. In this way, the voltage of the two batteries connected by the isolation circuit 85 can be equalized, so as to reduce the voltage difference of the two batteries connected by the isolation circuit, and further limit the mutual charging current between the two batteries connected by the isolation circuit, thereby reducing the possibility of burning the distributed traces on the FPC 70 due to large current mutual charging between the two batteries connected by the isolation circuit, and improving the safety and reliability of the foldable electronic device.

[0103] The PMU 84 can convert the battery voltage provided by the first battery 81 and / or the second battery 82 into a system voltage based on the control of the processing module 80 and provide the system voltage to the processing module 80, the flexible screen 10 and other loads requiring power supply, so as to power the processing module 80, the flexible screen 10 and other loads.

[0104] It should be noted that when the first battery 81 is electrically connected with the PMU 84 and the second battery 82 is electrically connected with the PMU 84 through the isolation circuit 85 (as shown in Figure 7 illustrated), the PMU 84 can be provided with the battery voltage only by the first battery 81, in which case the isolation circuit 85 is closed and the second battery 82 cannot provide the battery voltage for the PMU 84 through the isolation circuit 85; or the PMU 84 can be provided with the battery voltage by the first battery 81 and the second battery 82, in which case the isolation circuit 85 is turned on and the second battery 82 provides the battery voltage for the PMU 84 through the isolation circuit 85. When the second battery 82 is electrically connected with the PMU 84 and the first battery 81 is electrically connected with the PMU 84 through the isolation circuit 85 (as shown in Figure 8 illustrated), the PMU 84 can be provided with the battery voltage only by the second battery 82, in which case the isolation circuit 85 is closed and the first battery 81 cannot provide the battery voltage for the PMU 84 through the isolation circuit 85; or the PMU 84 can be provided with the battery voltage by the first battery 81 and the second battery 82, in which case the isolation circuit 85 is turned on and the first battery 81 provides the battery voltage for the PMU 84 through the isolation circuit 85.

[0105] It can be understood that when the load in the first accommodating space 23 needs to be powered by the second battery 82, the battery voltage provided by the second battery 82 is transmitted to the PMU 84 arranged in the first accommodating space 23 through the power supply traces distributed on the FPC 70 arranged at the rotating shaft structure 40, and the PMU 84 converts the battery voltage provided by the second battery 82 into a system voltage to power the load in the first accommodating space 23. When the load in the second accommodating space 33 needs to be powered by the first battery 81, the battery voltage provided by the first battery 81 is transmitted to the PMU 84, and the PMU 84 converts the battery voltage provided by the first battery 81 into a system voltage, which is transmitted to the load arranged in the second accommodating space 33 through the power supply traces distributed on the FPC 70, so as to power the load in the second accommodating space 33. When the load in the second accommodating space 33 needs to be powered by the second battery 82, the battery voltage provided by the second battery 82 is transmitted to the PMU 84 arranged in the first accommodating space 23 through the power supply traces distributed on the FPC 70 arranged at the rotating shaft structure 40, and the PMU 84 converts the battery voltage provided by the second battery 82 into a system voltage, and the system voltage is transmitted to the load arranged in the second accommodating space 33 through the power supply traces distributed on the FPC 70, so as to power the load in the second accommodating space 33.

[0106] It should be noted that the following description is based on the example that the first battery 81 is electrically connected with the PMU 84, and the second battery 82 is electrically connected with the PMU 84 through the isolation circuit 85.

[0107] Referring to Figure 9 , Figure 9 Another circuit diagram of the folding electronic device provided by the embodiment of the present application is provided. As shown in Figure 9As shown, the isolation circuit 85 includes a PMOS tube 851 and a driving circuit 852, the gate of the PMOS tube 851 is electrically connected with the driving circuit 852, the source of the PMOS tube 851 is electrically connected with the first battery 81, and the drain of the PMOS tube 851 is electrically connected with the second battery 82; or, the source of the PMOS tube 851 is electrically connected with the second battery 82, and the drain of the PMOS tube 851 is electrically connected with the first battery 81. The driving circuit 852 is configured to provide a voltage for the gate of the PMOS tube 851, so that the PMOS tube 851 is turned on or turned off according to the size of the gate voltage. When the PMOS tube 851 is turned on, the resistance value of the PMOS tube 851 can be adjusted by changing the voltage of the gate of the PMOS tube 851. Since I=(V1-V2) / R0, where I is the mutual charging current between the two batteries, V1 is the voltage at the first battery 81, V2 is the voltage at the second battery 82, and R0 is the resistance value of the PMOS tube 851, when the resistance value R0 of the PMOS tube 851 changes, the mutual charging current between the two batteries connected by the isolation circuit 85 changes, which reduces the possibility of burning the distributed lines on the FPC 70 due to the large mutual charging current between the two batteries connected by the isolation circuit 85, and improves the safety and reliability of the foldable electronic device.

[0108] The driving circuit 852 for driving the PMOS tube 851 has a simple structure, and the PMOS tube 851 can be turned on by the driving circuit 852 outputting 0V voltage, and the PMOS tube 851 can be turned off by stopping the output. As known from the foregoing, when the voltage of the gate of the PMOS tube 851 changes (the change of the gate voltage between 0V and the battery voltage), the resistance value of the PMOS tube 851 also changes accordingly.

[0109] However, through research, it is found that the voltage at the source end of the PMOS tube 851 (when the source is electrically connected with the first battery 81, the source voltage is the output voltage of the first battery 81; when the source is electrically connected with the second battery 82, the source voltage is the output voltage of the second battery 82) is real-time changing. When the voltage at the source end of the PMOS tube 851 decreases, under the condition that the gate voltage is constant, the V GS of the PMOS tube 851 will become larger, and the impedance of the PMOS tube 851 will become larger. Thus, when the PMOS tube 851 needs to be completely turned on, the PMOS tube 851 cannot be completely turned on (the minimum voltage output by the driving circuit 852 is 0V, ), but has a certain resistance value, and the resistance value changes with the change of the voltage at the source end of the PMOS tube 851, which cannot realize the stable conduction of the PMOS tube 851.

[0110] Based on this, the embodiment of the present application further provides an isolation circuit. Referring to Figure 10 , Figure 10 Another circuit diagram of the foldable electronic device provided by the embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the isolation circuit 85 includes a PMOS tube 851 and a driving circuit 852, the gate of the PMOS tube 851 is electrically connected with the driving circuit 852, the source of the PMOS tube 851 is electrically connected with the first battery 81, and the drain of the PMOS tube 851 is electrically connected with the second battery 82; or, the source of the PMOS tube 851 is electrically connected with the second battery 82, and the drain of the PMOS tube 851 is electrically connected with the first battery 81. The driving circuit 852 is configured to provide a voltage for the gate of the PMOS tube 851, so that the PMOS tube 851 is turned on or turned off according to the size of the gate voltage. When the PMOS tube 851 is turned on, the resistance value of the PMOS tube 851 can be adjusted by changing the voltage of the gate of the PMOS tube 851. Since I=(V1-V2) / R0, where I is the mutual charging current between the two batteries, V1 is the voltage at the first battery 81, V2 is the voltage at the second battery 82, and R0 is the resistance value of the PMOS tube 851, when the resistance value R0 of the PMOS tube 851 changes, the mutual charging current between the two batteries connected by the isolation circuit 85 changes, which reduces the possibility of burning the distributed lines on the FPC 70 due to the large mutual charging current between the two batteries connected by the isolation circuit 85, and improves the safety and reliability of the foldable electronic device.Figure 10 As shown, the isolation circuit 85 includes an NMOS transistor 853 and a driver chip 854. As mentioned above, for the NMOS transistor 853 to conduct, its gate voltage must be a high-level voltage, i.e., V0. G -V s >V th Only then can the NMOS transistor 853 be turned on, that is, V. G The voltage output by the driver chip 854 must be greater than the sum of the voltage at the source terminal of the NMOS transistor 853 (when the source is electrically connected to the first battery 81, the source voltage is the output voltage of the first battery 81; when the source is electrically connected to the second battery 82, the source voltage is the output voltage of the second battery 82) and the threshold voltage of the NMOS transistor 853. In other words, the stable conduction of the NMOS transistor 853 can be achieved by the voltage output by the driver chip 854 being greater than the sum of the voltage at the source terminal of the NMOS transistor 853 and the threshold voltage of the NMOS transistor 853.

[0111] Although the NMOS transistor 853 and the driver chip 854 work together to achieve stable conduction of the NMOS transistor 853, the structure of the driver chip 854 is quite complex. This is because the highest voltage of electronic devices is the battery voltage, while the output voltage of the driver chip 854 needs to be greater than the sum of the source voltage of the NMOS transistor 853 (which is the battery voltage in this embodiment) and the threshold voltage of the NMOS transistor 853. Therefore, a complex boost circuit needs to be designed. The complex structure and complex integration process of the driver chip 854 result in a high cost, which is not conducive to reducing the cost of electronic devices.

[0112] Based on this, embodiments of this application provide a driving circuit that can drive NMOS transistors and has a simple structure. Compared with driving chips formed through complex structures and complex integration processes, this is beneficial for reducing the cost of electronic devices.

[0113] The following section provides a detailed description of the drive circuit that enables the NMOS transistor to turn on or off.

[0114] See Figure 11 , Figure 11 This is a circuit diagram of an isolation circuit provided in an embodiment of this application. Figure 11As shown, the isolation circuit (also referred to as an isolation device) 85 includes an NMOS tube 853, a driving circuit 855, a protection module 856, and a control module (not shown in the figure). The driving circuit 855 includes a voltage adjustment module 8551 and an off module 8552. The voltage adjustment module 8551 is configured to control the turn-on of the NMOS tube 853 and the adjustment of the resistance when the NMOS tube 853 is turned on, and the off module 8552 is configured to control the turn-off of the NMOS tube 853. The control module is configured to control the driving circuit 855, so that the driving circuit 855 controls the turn-on of the NMOS tube 853 and the adjustment of the resistance when the NMOS tube 853 is turned on, and controls the turn-off of the NMOS tube 853. The protection module 856 is configured to make the NMOS tube 853 in the off state when the control module is not powered on (i.e., the driving circuit 855 is not controlled), so as to avoid the problem that the gate of the NMOS tube 853 is turned on due to interference of some other signals and the like when the control module is not powered on.

[0115] The voltage adjustment module 8551 includes N groups of boosting groups 8551a and an integration unit 8551b, where N is a positive integer greater than or equal to 1. Each group of boosting groups 8551a includes a storage unit 8551a1 and a unidirectional transmission unit 8551a2. The storage unit 8551a1 and the unidirectional transmission unit 8551a2 each include a first end and a second end. The first end of the unidirectional transmission unit 8551a2 of an even-numbered boosting group 8551a, the second end of the unidirectional transmission unit 8551a2 of the previous group of boosting groups 8551a, and the first end of the storage unit 8551a1 of the previous group are coupled to a first node A. Except for the first group of boosting groups 8551a, the first end of the unidirectional transmission unit 8551a2 of an odd-numbered boosting group 8551a, the second end of the unidirectional transmission unit 8551a2 of the previous group of boosting groups 8551a, and the first end of the storage unit 8551a1 of the previous group of boosting groups 8551a are coupled to a second node B. The first end of the unidirectional transmission unit 8551a2 of the first group of boosting groups 8551a is configured to receive a power supply signal V0 (which can be provided by the first battery 81, the second battery 82, or the like, or a signal obtained by boosting or reducing the first battery 81 or the second battery 82). The second end of the storage unit 8551a1 of the odd-numbered boosting group 8551a is configured to receive a first Pulse Width Modulation (PWM) signal, and the second end of the storage unit 8551a1 of the even-numbered boosting group 8551a is configured to receive a second PWM signal. The first PWM signal and the second PWM signal have the same frequency and opposite phases.

[0116] The second end of the unidirectional transmission unit 8551a2 of the Nth group of boost groups 8551a and the first end of the storage unit 8551a1 of the Nth group of boost groups 8551a are coupled to a third node, which can also be referred to as the second node B of the Nth group of boost groups 8551a when N is even, or the first node A of the Nth group of boost groups 8551a when N is odd.

[0117] The second end of the integration unit 8551b is grounded, the third end of the integration unit 8551b, the first end of the protection module 856, the gate of the NMOS tube 853, and the first end of the shutdown module 8552 are coupled to a fifth node E (also referred to as a driving signal output end of a driving signal of a driving NMOS tube), and the second end of the protection module 856 and the second end of the shutdown module 8552 are both grounded. The control end of the shutdown module 8552 is configured to receive a switch control signal GPIO, the shutdown module 8552 is turned on when the control end of the shutdown module 8552 is configured to receive the first switch control signal, and the shutdown module 8552 is turned off when the control end of the shutdown module 8552 is configured to receive the second switch control signal. The source and drain of the NMOS tube 853 are respectively electrically connected to two structures that need to be isolated, such as the first battery 81 and the second battery 82. Of course, this does not constitute a limitation on the present application, and in other optional embodiments of the present application, referring to Figure 10 , the source and drain of the NMOS tube 853 are respectively electrically connected to the power supply module 86 and the load 87, wherein the power supply module 86 can be the first battery 81 or the second battery 82, or a power supply module that can output the required voltage of the load 87 formed by the first battery 81 and some peripheral circuits (such as a boost circuit or a buck circuit), or a power supply module that can output the required voltage of the load 87 formed by the second battery 82 and some peripheral circuits (such as a boost circuit or a buck circuit). The load 87 can be any device that needs to be powered to operate. The isolation circuit 85 arranged between the power supply module 86 and the load 87 can better protect the load 87 and avoid problems such as damage to the load 87 when the power supply module 86 outputs a larger voltage due to damage or other problems.

[0118] For the specific structures of the unidirectional transmission unit 8551a2, the storage unit 8551a1, the integration unit 8551b, the shutdown module 8552, and the protection module 856, the present application does not limit the specific structures of the unidirectional transmission unit 8551a2, the storage unit 8551a1, the integration unit 8551b, the shutdown module 8552, and the protection module 856, and those skilled in the art can set them according to actual conditions.

[0119] In some embodiments, the storage unit 8551a1 can include a device such as a storage capacitor that can store a power supply signal, and the unidirectional transmission unit 8551a2 can include a device such as a diode that can conduct unidirectionally. Continuing to refer to Figure 11 For ease of description, when the storage unit 8551a1 of the odd-numbered boost group 8551a includes a storage capacitor, the storage capacitor is also referred to as a first capacitor C1, and when the unidirectional transmission unit 8551a2 of the odd-numbered boost group 8551a can include a diode, the diode is also referred to as a first diode D1. When the storage unit 8551a1 of the even-numbered boost group 8551a includes a storage capacitor, the storage capacitor is also referred to as a second capacitor C2, and when the unidirectional transmission unit 8551a2 of the even-numbered boost group 8551a can include a diode, the diode is also referred to as a second diode D2.

[0120] The integration unit 8551b can include a first resistor R1 and a third capacitor C3, etc. The turn-off module 8552 can include an NMOS tube Q1, etc. The protection module 856 can include a second resistor R2, etc.

[0121] On this basis, the connection relationship of each structure is that the anode of the second diode D2, the cathode of the first diode D1, and the first pole of the first capacitor C1 are coupled to the first node A, and the second pole of the first capacitor C1 is used to receive a first PWM signal. In addition to the first boost group 8551a, the anode of the first diode D1 of the odd-numbered boost group 8551a, the cathode of the second diode D2 of the previous boost group 8551a of the odd-numbered boost group 8551a, and the first pole of the second capacitor C2 of the previous boost group 8551a of the odd-numbered boost group 8551a are coupled to the second node B. The second pole of the second capacitor C2 is used to receive a second PWM signal, the first PWM signal and the second PWM signal have the same frequency and opposite phases.

[0122] The anode of the first diode D1 of the first boost group 8551a is used to receive a power supply signal (which can be provided by the first battery 81, can be provided by the second battery 82, etc., or can be a signal obtained after the first battery 81 or the second battery 82 is boosted or stepped down, etc.).

[0123] When N is even, the cathode of the second diode D2 of the Nth boost group 8551a and the first pole of the second capacitor C2 of the Nth boost group 8551a are coupled to the second node B with the first end of the integration unit 8551b. When N is odd, the cathode of the first diode D1 of the Nth boost group 8551a and the first pole of the first capacitor C1 of the Nth boost group 8551a are coupled to the first node A with the first end of the integration unit 8551b.

[0124] The second end of the first resistor R1, the first pole of the third capacitor C3, the first end of the second resistor R2 in the protection module 856, the gate of the NMOS tube 853, and the drain of the NMOS tube Q1 are coupled to the fifth node E. The second pole of the third capacitor C3, the second end of the second resistor R2, and the source of the NMOS tube Q1 are all grounded.

[0125] The first PWM signal, the second PWM signal, and the switch control signal GPIO are all provided by a control module. The control module can be a module separately provided in the electronic device, or can be a structure already provided in the electronic device. For example, the PMU 84 in the electronic device is the control module, that is, the PMU 84 not only has the function of converting the battery voltage provided by the battery (the first battery 81 and / or the second battery 82) into a system voltage, but also has the function of outputting the first PWM signal, the second PWM signal, and the switch control signal GPIO. For another example, the processing module 80 in the electronic device is the control module, that is, the processing module 80 not only has the processing function described above, but also has the function of outputting the first PWM signal, the second PWM signal, and the switch control signal GPIO. For another example, the processing module 80 and the PMU 84 in the electronic device are the control modules, the processing module 80 outputs the switch control signal GPIO, and the PMU 84 outputs the first PWM signal and the second PWM signal.

[0126] Based on the above structure, first, the specific working process of driving the NMOS tube to be turned on by the driving circuit 855 is introduced. Among them, combined with Figure 12 , Figure 12 the waveform diagram of the first PWM signal and the second PWM signal provided by the embodiment of the present application, Figure 12 (1) is the waveform diagram of the first PWM signal, Figure 12 (2) is the waveform diagram of the second PWM signal. As Figure 12 shown, the first PWM signal and the second PWM signal each include a plurality of pulse periods T0, each pulse period T0 includes a high-level signal in a first time period T1 and a low-level signal in a second time period T2, the voltage of the high-level signal of the first PWM signal can be V P1 , the voltage of the low-level signal can be 0V, the voltage of the high-level signal of the second PWM signal can be V P2 , and the voltage of the low-level signal can be 0V, Figure 12 V P1 equals V P2For example, the description is carried out. For the convenience of description, in the following content, when the PWM signal is a high level signal, the high level signal can be represented by 1; the PWM signal is a low level signal, and the low level signal can be represented by 0. When the first PWM signal is a high level signal in the first time period T1, the second PWM signal is a low level signal in the first time period T1; when the first PWM signal is a low level signal in the first time period T1, the second PWM signal is a high level signal in the first time period T1.

[0127] At the first time t1, PWM1=0, PWM2=1, GPIO=0. At this time, the NMOS tube Q1 is in the closed state. The power supply signal V0 charges the first capacitor C1 in the first group of boost groups 8551a through the first diode D1, and the voltage of the first capacitor C1 is V0. Correspondingly, the voltage at the first node A is V0, that is, the voltage output by the first group of boost groups 8551a at the first time t1 is V0. That is, the minimum voltage output by the first group of boost groups 8551a is the power supply signal V0.

[0128] At the second time t2, PWM1=1, PWM2=0, GPIO=0. At this time, the NMOS tube Q1 is still in the closed state. The high level signal of PWM1 makes the voltage regulation of the first capacitor C1 of the first group of boost groups 8551a be raised to the sum of the power supply signal V0 and the high level signal of PWM1, and correspondingly, the voltage at the first node A in the first group of boost groups 8551a is raised to the sum of the power supply signal V0 and the high level signal of PWM1. That is, the maximum voltage at the first node A in the first group of boost groups 8551a is the sum of the power supply signal V0 and the high level signal of PWM1. That is, the maximum voltage output by the first group of boost groups 8551a is the sum of the power supply signal V0 and the high level signal of PWM1.

[0129] After the voltage at the first node A in the first group of boost groups 8551a is raised, the voltage at the first node A is charged to the second capacitor C2 through the second diode D2 of the second group of boost groups 8551a. At this time, the voltage of the second capacitor C2 is: the sum of the power supply signal V0 and the high level signal of PWM1, and correspondingly, the voltage at the second node B in the second group of boost groups 8551a is the sum of the power supply signal V0 and the high level signal of PWM1. That is, the voltage output by the second group of boost groups 8551a at the second time t2 is the sum of V0 and the high level signal of PWM1. That is, the minimum voltage output by the second group of boost groups 8551a is the sum of the power supply signal V0 and the high level signal of PWM1.

[0130] At the third moment t3, PWM1=0, PWM2=1, and GPIO=0. At this time, NMOS transistor Q1 is still off. The power supply signal V0 charges the first capacitor C1 through the first diode D1 in the first boost group 8551a. The high-level signal of PWM2 causes the voltage regulation of the second capacitor C2 in the second boost group 8551a to be raised to the sum of the power supply signal V0 plus the high-level signals of PWM1 and PWM2. Correspondingly, the voltage at the second node B in the second boost group 8551a is raised to the sum of the power supply signal V0 plus the high-level signals of PWM1 and PWM2. That is, the highest voltage at the second node B in the second boost group 8551a is the sum of the power supply signal V0 plus the high-level signals of PWM1 and PWM2. In other words, the highest output voltage of the second boost group 8551a is the sum of the power supply signal V0 plus the high-level signals of PWM1 and PWM2.

[0131] After the voltage at the second node B in the second boost group 8551a is raised, the voltage at the second node B simultaneously charges the first capacitor C1 through the first diode D1 in the third boost group 8551a. At this time, the voltage of the first capacitor C1 in the third boost group 8551a is the sum of the power supply signal V0 plus the high-level signal of PWM1 plus the high-level signal of PWM2. Correspondingly, the voltage at the first node A in the third boost group 8551a is the sum of the power supply signal V0 plus the high-level signal of PWM1 plus the high-level signal of PWM2. That is, at the third time t3, the voltage output by the third boost group 8551a is the sum of the power supply signal V0 plus the high-level signal of PWM1 plus the high-level signal of PWM2. In other words, the lowest voltage output by the third boost group 8551a is the sum of the power supply signal V0 plus the high-level signal of PWM1 plus the high-level signal of PWM2.

[0132] At time t4, PWM1=1, PWM2=0, and GPIO=0. At this time, NMOS transistor Q1 is still off. The high-level signal of PWM1 raises the voltage regulation of the first capacitor C1 in the third boost group 8551a to the sum of V0 plus the high-level signals of PWM1, PWM2, and PWM1. Correspondingly, the voltage at the first node A within the third boost group 8551a is raised to the sum of the power supply signal V0 plus the high-level signals of PWM1, PWM2, and PWM1, i.e., the power supply signal V0 plus twice the sum of the high-level signals of PWM1 and PWM2. In other words, the highest voltage at the first node A within the third boost group 8551a is the power supply signal V0 plus twice the sum of the high-level signals of PWM1 and PWM2.

[0133] After the voltage at the first node A in the third group of boost groups 8551a is raised, the voltage at the first node A is simultaneously charged to the second capacitor C2 through the second diode D2 in the fourth group of boost groups 8551a. At this time, the voltage of the second capacitor C2 in the fourth group of boost groups 8551a is: V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2. Correspondingly, the voltage at the second node B in the fourth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2. That is, the lowest voltage output by the fourth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2.

[0134] At the fifth time t5, PWM1=0, PWM2=1, GPIO=0. At this time, the NMOS tube Q1 is still in the closed state. The power signal V0 charges the first capacitor C1 through the first diode D1 in the first group of boost groups 8551a. The high level signal of PWM2 makes the voltage regulation of the second capacitor C2 in the fourth group of boost groups 8551a be raised to: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. Correspondingly, the voltage at the second node B in the fourth group of boost groups 8551a is raised to: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, the highest voltage at the second node B in the fourth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, the highest voltage output by the fourth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2.

[0135] After the voltage at the second node B in the fourth group of boost groups 8551a is raised, the voltage at the second node B is simultaneously charged to the first capacitor C1 through the first diode D1 in the fifth group of boost groups 8551a. At this time, the voltage of the first capacitor C1 in the fifth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. Correspondingly, the voltage at the first node A in the fifth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, at the fifth time t5, the voltage output by the fifth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, the lowest voltage output by the fifth group of boost groups 8551a is: the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2.

[0136] By analogy, when N is even, the highest voltage output by the Nth voltage boosting group 8551a is the sum of the power supply signal V0 and two N / 2 times of the high level signal of PWM1 and two N / 2 times of the high level signal of PWM2; the lowest voltage output by the Nth voltage boosting group 8551a is the sum of the power supply signal V0 and two N / 2 times of the high level signal of PWM1 and two (N-2) / 2 times of the high level signal of PWM2. That is, when N is even, the highest voltage finally output by the N voltage boosting groups 8551a is V max = V0+ (N / 2) V P1 + (N / 2) V P2 ; the lowest voltage finally output by the N voltage boosting groups 8551a is V min = V0+ (N / 2) V P1 + {(N-2) / 2} V P2 .

[0137] When N is odd, the highest voltage output by the Nth voltage boosting group 8551a is the sum of the power supply signal V0 and two (N+1) / 2 times of the high level signal of PWM1 and two (N-1) / 2 times of the high level signal of PWM2; the lowest voltage output by the Nth voltage boosting group 8551a is the sum of the power supply signal V0 and two (N-1) / 2 times of the high level signal of PWM1 and two (N-1) / 2 times of the high level signal of PWM2. That is, when N is odd, the highest voltage finally output by the N voltage boosting groups 8551a is V max = V0+ {(N+1) / 2} V P1 + {(N-1) / 2} V P2 ; the lowest voltage finally output by the N voltage boosting groups 8551a is V min = V0+ {(N-1) / 2} V P1 + {(N-1) / 2} V P2 .

[0138] In addition, in actual scenarios, there is a voltage drop at each diode D1. If the voltage drops of each first diode D1 are the same, such as V d1 ; the voltage drops of each second diode D2 are the same, such as V d2 . Then, when N is even, the highest voltage finally output by the N voltage boosting groups 8551a is V max = V0+ (N / 2) V P1 + (N / 2) V P2 - (N / 2) V d1 - (N / 2) V d2 ; the lowest voltage finally output by the N voltage boosting groups 8551a is V min = V0+ (N / 2) V P1 + {(N-2) / 2} VP2 (N / 2)V d1 (N / 2)V d2 When N is odd, the highest voltage outputted by the N groups of boost groups 8551a is V max =V0+{(N+1) / 2}V P1 +{(N-1) / 2}V P2 -{(N+1) / 2}V d1 -{(N-1) / 2}V d2 ; the lowest voltage outputted by the N groups of boost groups 8551a is V min =V0+{(N-1) / 2}V P1 +{(N-1) / 2}V P2 -{(N+1) / 2}V d1 -{(N-1) / 2}V d2 .

[0139] If the voltages of V P1 and V P2 are equal to the voltage V0 of the power supply signal, and if the voltage drops of the diodes (including the first diode D1 and the second diode D2) are the same, such as V d No matter whether N is odd or even, V max =(N+1)V0-NV d ; V min =N(V0-V d ).

[0140] Therefore, the voltage outputted by the N groups of boost groups 8551a is a square wave signal with high and low changes, wherein the high is the highest voltage outputted by the N groups of boost groups 8551a, which is V max , and the low is the lowest voltage outputted by the N groups of boost groups 8551a, which is V min . After the square wave signal is integrated by the first resistor R1 and the third capacitor C3 in the integration unit 8551b, it becomes a direct current voltage, which can drive the NMOS to be turned on. And the high and low of the direct current voltage can be adjusted by adjusting the frequency and duty cycle of the first PWM signal and the second PWM signal, so as to control whether the NMOS works in the linear region or the saturation region.

[0141] It should be noted that the specific value of N is not limited in the embodiments of the present application, and a person skilled in the art can set the voltage required by the NMOS according to the actual scene. The larger the value of N is, the higher the highest voltage outputted by the N groups of boost groups 8551a is generally.

[0142] For example, referring to Figure 13 , Figure 13 another circuit diagram of the isolation circuit provided by the embodiments of the present application. As shown inFigure 13 As shown, the voltage adjustment module 8551 includes two groups of boost groups 8551a, which include a first group of boost groups 8551a and a second group of boost groups 8551a, and an anode of a first diode D1 of the first group of boost groups 8551a is configured to receive a power supply signal V0. A cathode of the first diode D1 and a first pole of a first capacitor C1 in the first group of boost groups 8551a are coupled to a first node A with an anode of a second diode D2 in the second group of boost groups 8551a, and a second pole of the first capacitor C1 is configured to receive a first PWM signal. A cathode of the second diode D2 and a first pole of a second capacitor C2 in the second group of boost groups 8551a are coupled to a second node B with a first end of a first resistor R1 in an integration unit 8551b, and a second pole of the second capacitor C2 is configured to receive a second PWM signal, the first PWM signal and the second PWM signal have the same frequency and opposite phases. The second end of the first resistor R1, a first pole of a third capacitor C3, a first end of a second resistor R2 in a protection module 856, a gate of an NMOS Q1, and a drain of the NMOS Q1 are coupled to a fifth node E. The second pole of the third capacitor C3, the second end of the second resistor R2, and a source of the NMOS Q1 are all grounded. The voltage V P1 of the high-level signal of the first PWM signal is V P2 , and the voltage V d1 of the high-level signal of the second PWM signal is also V d2 .

[0143] In combination with Figure 14 , Figure 14 FIG. 6 is a waveform diagram of the signals at the first node and the signals at the second node provided by the embodiment of the present application, Figure 14 the dashed line in FIG. 6 represents the voltage signal at the first node A, Figure 14 and the solid line in FIG. 6 represents the voltage signal at the second node B. When the first PWM signal is 0 (low-level signal), the voltage at the first node A is V d1 0-V d1 ; when the first PWM signal is 1 (high-level signal), the voltage at the first node A is 2V d1 0-V d1 . That is, the square wave signal of the voltage at the first node A changes between high and low, where the high is 2V P1 0-V P2 .

[0144] From the foregoing, if the voltages of V P1 and V P2 are both equal to the voltage V0 of the power supply signal, regardless of whether N is odd or even, V max= (N+1) V0-NV d ; V min = N (V0-V d ). Therefore, when the voltage adjustment module 8551 includes two groups of boost groups 8551a, the two groups of boost groups 8551a include a first group of boost groups 8551a and a second group of boost groups 8551a, the highest voltage finally output by the two groups of boost groups 8551a (i.e., the voltage at the second node B) is V max = 3V0-V d1 -V d2 ; the lowest voltage finally output by the two groups of boost groups 8551a is V min = 2V0-V d1 -V d2 . That is, the voltage finally output by the two groups of boost groups 8551a is a square wave signal with high and low changes, wherein the high is the highest voltage finally output by the N groups of boost groups 8551a, which is V max = 3V0-V d1 -V d2 , and the low is the lowest voltage finally output by the N groups of boost groups 8551a, which is V min = 2V0-V d1 -V d2 . After integration by the first resistor R1 and the third capacitor C3 in the integration unit 8551b, the square wave signal becomes a direct current voltage F, as shown in Figure 15 , which can drive the NMOS tube to turn on. And the high and low of the direct current voltage can be adjusted by adjusting the frequency and duty cycle of the first PWM signal and the second PWM signal, thereby controlling whether the NMOS works in the linear region or the saturation region.

[0145] The above describes the specific working process of the driving circuit 855 for driving the NMOS tube to turn on. The following describes the specific working process of the driving circuit 855 for turning off the NMOS tube 853.

[0146] When it is necessary to turn off the NMOS tube 853, PWM1=1, PWM2=1, GPIO=1, and the duration of GPIO=1 is greater than or equal to a preset duration, and then GPIO=0. The preset duration can be 50us, that is, the switch control signal at the gate of the NMOS tube Q1 is a high level signal, and the high level signal lasts for 50us or more, that is, the duration of the conduction of the NMOS tube Q1 is greater than or equal to the preset duration. In this way, the NMOS tube Q1 can be completely turned on, and the time of conduction is relatively long, the voltage at the gate of the NMOS tube 853 is discharged to the ground, and the voltage on the third capacitor C3 can also be quickly discharged to the ground. Further, the voltage at the gate of the NMOS tube 853 is quickly changed to 0V, that is, the speed of turning off the NMOS tube 853 is accelerated.

[0147] The specific working process of driving circuit 855 driving NMOS to turn on and off is introduced above. From the above, it can be seen that the driving circuit 855 provided by the embodiment of the application can realize the output of a larger voltage through a simple structure design of diode and capacitor, for example, the driving circuit 855 can output a voltage greater than the sum of the threshold voltage of the source end of the NMOS 853 (which is the battery voltage in the embodiment of the application) and the threshold voltage of the NMOS 853, and can realize the turn-on and turn-off of the NMOS. When the NMOS is turned on, the frequency and / or duty cycle of the PWM signal can be adjusted to adjust the size of the output voltage of the driving circuit 855, and thus the node at which the NMOS 853 works in the linear region (i.e. the resistance of the NMOS 853). In a specific application scenario, the isolation circuit 85 can isolate the first battery 81 and the second battery 82, and also can perform voltage balancing on the voltages of the first battery 81 and the second battery 82. In this way, the voltages of the two batteries connected by the isolation circuit 85 can be balanced to reduce the voltage difference between the two batteries connected by the isolation circuit, and thus limit the mutual charging current between the two batteries connected by the isolation circuit, thereby reducing the possibility of burning the distributed traces on the FPC 70 due to large mutual charging current between the two batteries connected by the isolation circuit, and improving the safety and reliability of the foldable electronic device.

[0148] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A drive circuit characterized by comprising: The application is applied to an electronic device, and the electronic device comprises a first battery, a second battery, a driving circuit and an NMOS tube, the source of the NMOS tube is electrically connected with the first battery, and the drain of the NMOS tube is electrically connected with the second battery; The driving circuit is used for driving the NMOS tube to be turned on or turned off, and the driving circuit comprises a voltage adjustment module and an off module; the voltage adjustment module comprises N groups of boosting groups, an integration unit and a driving signal output end, each group of boosting groups comprises a storage unit and a unidirectional transmission unit, wherein N is a positive integer greater than or equal to 1; the integration unit comprises a first resistor and an integration capacitor; The first end of the unidirectional transmission unit of the even-numbered boosting group is coupled to a first node, the second end of the unidirectional transmission unit of the previous boosting group of the even-numbered boosting group is coupled to the first node, and the first end of the storage unit of the previous boosting group of the even-numbered boosting group is coupled to the first node; except for the first group of boosting groups, the first end of the unidirectional transmission unit of the odd-numbered boosting group, the second end of the unidirectional transmission unit of the previous boosting group of the odd-numbered boosting group and the first end of the storage unit of the previous boosting group of the odd-numbered boosting group are coupled to a second node; The first end of the unidirectional transmission unit of the first group of boosting groups is used for receiving a power supply signal, the second end of the storage unit of the odd-numbered boosting group is used for receiving a first PWM signal, the second end of the storage unit of the even-numbered boosting group is used for receiving a second PWM signal, the first PWM signal and the second PWM signal have the same frequency and opposite phases; the frequency and the duty cycle of the first PWM signal and the second PWM signal are adjustable, so as to change the size of the driving signal output to the gate of the NMOS tube by the driving signal output end; The second end of the unidirectional transmission unit of the Nth group of boosting groups and the first end of the storage unit of the Nth group of boosting groups are coupled to a third node; the first end of the first resistor is electrically connected with the third node, the second end of the first resistor is electrically connected with the first pole of the integration capacitor and the driving signal output end respectively, and the second pole of the integration capacitor is grounded; the driving signal output end is electrically connected with the gate of the NMOS; The first end of the off module is electrically connected with the driving signal output end, the second end of the off module is grounded, and the control end of the off module is used for receiving a switch control signal; when the off module is turned on according to the received switch control signal, the driving signal output end is grounded; when the off module is turned on according to the received switch control signal, the on duration of the off module is greater than or equal to a preset duration, so that the voltage at the gate of the NMOS and the voltage on the integration capacitor are discharged to the ground.

2. The drive circuit according to claim 1, characterized in that, The voltage adjustment module comprises a first group of boosting groups and a second group of boosting groups; The first end of the unidirectional transmission unit of the second boost group, the second end of the unidirectional transmission unit of the first boost group, and the first end of the storage unit of the first boost group are coupled to the first node; the second end of the unidirectional transmission unit of the second boost group and the first end of the storage unit of the second boost group are coupled to the third node; The second terminal of the storage unit of the first boost group is used to receive the first PWM signal, and the second terminal of the storage unit of the second boost group is used to receive the second PWM signal.

3. The drive circuit according to claim 1 or 2, characterized in that, The storage unit includes a storage capacitor; the first terminal of the storage capacitor of the odd-numbered boost group is electrically connected to the first node, and the second terminal of the storage capacitor of the odd-numbered boost group is used to receive the first PWM signal; The first terminal of the storage capacitor in the even-numbered boost group is electrically connected to the second node, and the second terminal of the storage capacitor in the even-numbered boost group is used to receive the second PWM signal.

4. The drive circuit according to claim 1 or 2, characterized in that, The unidirectional transmission unit includes a diode; the anode of the diode in the even-numbered boost group, the cathode of the diode in the preceding boost group, and the first terminal of the memory cell in the preceding boost group are coupled to a first node; except for the first boost group, the anode of the diode in the odd-numbered boost group, the cathode of the diode in the preceding boost group, and the first terminal of the memory cell in the preceding boost group are coupled to a second node.

5. The drive circuit according to claim 3, characterized by The unidirectional transmission unit includes a diode; the anode of the diode in the even-numbered boost group, the cathode of the diode in the preceding boost group, and the first terminal of the memory cell in the preceding boost group are coupled to a first node; except for the first boost group, the anode of the diode in the odd-numbered boost group, the cathode of the diode in the preceding boost group, and the first terminal of the memory cell in the preceding boost group are coupled to a second node.

6. The drive circuit of claim 1, wherein It also includes a protection module, the first end of which is electrically connected to the drive signal output terminal, and the second end of which is grounded; The protection module is used to pull down the signal at the output terminal of the drive signal to ground when the drive circuit does not receive the power signal, the switch control signal, the first PWM signal and the second PWM signal.

7. The drive circuit according to claim 6, characterized in that, The protection module includes a second resistor, the first end of which is electrically connected to the drive signal output terminal, and the second end of which is grounded.

8. The drive circuit of claim 1, wherein, The shutdown module includes a metal-oxide-semiconductor field-effect transistor.

9. The drive circuit of claim 1, wherein, when N is even, the highest voltage V max satisfies: V max = V0+ (N / 2) V P1 + (N / 2) V P2 - NV d ; the lowest voltage V at the third node min satisfies: V min = V0+ (N / 2) V P1 + {(N-2) / 2} V P2 - NV d ; when N is odd, the highest voltage V max satisfies: V max = V0+ {(N+1) / 2}V P1 + {(N-1) / 2}V P2 -NV d ; the lowest voltage V at the third node min satisfies: V min = V0+{(N-1) / 2}V P1 +{(N-1) / 2}V P2 -NV d ; where V d is the voltage drop of the unidirectional transfer unit, V P1 is the maximum voltage of the first PWM signal, V P2 is the maximum voltage of the second PWM signal.

10. The drive circuit according to any one of claims 1, 2, 6, 7, 8 or 9, characterized in that, The driving circuit also includes a control module, which is used to output the first PWM signal and the second PWM signal.

11. An isolating device, characterized by It includes an NMOS transistor and a driving circuit as described in any one of claims 1-10, wherein the gate of the NMOS transistor is electrically connected to the driving signal output terminal of the driving circuit; The driving circuit is used to provide a driving signal to the gate of the NMOS transistor through the driving signal output terminal, so as to drive the NMOS transistor to turn on or off.

12. An electronic device, comprising: Includes the isolation device as described in claim 11; The electronic device further comprises a first battery and a second battery, or the electronic device further comprises a battery and a load; When the electronic device further comprises a first battery and a second battery, the source of the NMOS tube is electrically connected with the first battery, and the drain of the NMOS tube is electrically connected with the second battery; When the electronic device further comprises a battery and a load, the source of the NMOS tube is electrically connected with the battery, and the drain of the NMOS tube is electrically connected with the load.

13. The electronic device of claim 12, wherein, The electronic device further comprises a power management chip, and the power management chip is configured to output the first PWM signal and the second PWM signal.

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