A DFI protocol analysis system

Abstract

The present application relates to the field of data processing technology, and in particular to a DFI protocol parsing system. The system comprises: a DDR controller, a DFI interface, and a protocol parsing module comprising a signal analysis module and a command parsing module. The signal analysis module analyzes a DFI interface signal sent by the DDR controller to the DFI interface at a first clock frequency at a second clock frequency, and sends sub-signals of multiple phases to the command parsing module in sequence in combination with a count value. The command parsing module then performs parsing processing according to a truth value mapping table. The command parsing module does not need to distinguish the phases of the sub-signals, thereby saving a large amount of logic required for parsing, reducing the amount of code required for parsing, and effectively reducing the cost of DFI protocol parsing. The signal analysis process and the command parsing process are decoupled. When applied to particles of different DDR types, only the command parsing module needs to be modified, thereby improving the versatility of DFI protocol parsing.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a DFI protocol parsing system. Background Art

[0002] DDR PHY Interface (DFI) is a protocol that defines signals, timing parameters, and programmable interface parameters required to transmit command information and data between DDR controller and DDR PHY. In the process of DDR controller IP design, DFI is an important bridge for interaction between controller and PHY. In SOC design and verification, DFI also needs to be parsed to achieve full-process optimization of the data path from software to data flow to hardware storage.

[0003] At present, DFI protocol parsing usually requires analyzing and processing the DFI interface signal, and then parsing the DFI interface signal into the corresponding command type according to the truth value mapping table corresponding to the DDR type. In the frequency ratio system, the DFI interface signal is usually sent in the form of two phases or four phases, which makes the signal analysis and parsing process more complicated. It takes a lot of logic to ensure the real-time analysis, which leads to high parsing costs and is difficult to quickly apply to IP systems of different DDR types. The versatility is poor. Therefore, how to reduce the cost of DFI protocol parsing and improve the versatility of the DFI protocol has become an urgent problem to be solved. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is:

[0005] A DFI protocol analysis system comprises a DDR controller and a DFI interface, and further comprises a protocol analysis module.

[0006] The protocol parsing module is connected to the output side of the DDR controller to receive, at a second clock frequency f2, M DFI interface signals [a1, a2, ..., a3] sent by the DDR controller to the DFI interface at a first clock frequency f1. m , …, a M ], where a m is the mth DFI interface signal, where m is an integer in the range [1, M], and a m =[b m 0, b m 1, …, b m n , …, b m N-1 ], b m nIt is the sub-signal of the n+1th phase in the mth DFI interface signal, the DFI interface signal includes sub-signals of N phases, n is an integer in the range of [0, N-1], and f1 and f2 satisfy the condition: f2=f1×N.

[0007] The protocol analysis module includes a signal analysis submodule and a command analysis submodule. The signal analysis submodule includes a counter. The counter increments the count value i according to f2, and i is initially zero. The signal analysis submodule determines the target subsignal according to i and N, and sends the target subsignal to the command analysis submodule at the time point corresponding to i.

[0008] The command parsing submodule maps the received truth value data corresponding to the target sub-signal into command information according to the truth value mapping table corresponding to the DDR particle to be used, and uses the command information as the DFI protocol parsing result. The truth value mapping table includes the mapping relationship between the truth value data corresponding to the target sub-signal and the command information.

[0009] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the DFI protocol parsing system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0010] The present invention provides a DFI protocol analysis system, the system includes a DDR controller and a DFI interface, the system also includes a protocol analysis module, the protocol analysis module is connected to the output side of the DDR controller, and receives M DFI interface signals [a1, a2, ..., a1] sent by the DDR controller to the DFI interface at a first clock frequency f1 according to a second clock frequency f2. m , …, a M ], where a m is the mth DFI interface signal, where m is an integer in the range [1, M], and a m =[b m 0, b m 1, …, b m n , …, b m N-1 ], b m nis the sub-signal of the n+1th phase in the mth DFI interface signal, the DFI interface signal includes sub-signals of N phases, n is an integer in the range of [0, N-1], f1 and f2 satisfy the condition: f2=f1×N, the protocol parsing module includes a signal analysis sub-module and a command parsing sub-module, the signal analysis sub-module includes a counter, the counter performs a self-increment operation on the count value i according to f2, i is initially zero, the signal analysis sub-module determines the target sub-signal according to i and N, and sends the target sub-signal to the command parsing sub-module at the time point corresponding to i, the command parsing sub-module maps the received truth value data corresponding to the target sub-signal to command information according to the truth value mapping table corresponding to the DDR particle to be used, and uses the command information as the DFI protocol parsing result, and the truth value mapping table includes a mapping relationship between the truth value data corresponding to the target sub-signal and the command information.

[0011] It can be seen that the signal analysis module parses the DFI interface signal sent to the DFI interface by the DDR controller at the first clock frequency at the second clock frequency, and sends the sub-signals of multiple phases to the command parsing module in sequence in combination with the count value, and the command parsing module then performs parsing and processing according to the truth value mapping table. The command parsing module does not need to distinguish the phases of the sub-signals, thereby saving a lot of logic required for parsing, reducing the amount of code required for parsing, and effectively reducing the cost of DFI protocol parsing. In addition, the signal analysis process and the command parsing process are decoupled. When applied to particles of different DDR types, only the command parsing module needs to be modified, thereby improving the versatility of DFI protocol parsing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of the architecture of a DFI protocol parsing system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] This embodiment provides a DFI protocol parsing system. Figure 1 , is a schematic diagram of the architecture of a DFI protocol analysis system provided by an embodiment of the present invention, the system includes a DDR controller and a DFI interface, and the system also includes a protocol analysis module;

[0016] The protocol parsing module is connected to the output side of the DDR controller to receive, at a second clock frequency f2, M DFI interface signals [a1, a2, ..., a3] sent by the DDR controller to the DFI interface at a first clock frequency f1. m , …, a M ], where a m is the mth DFI interface signal, where m is an integer in the range [1, M], and a m =a m =[b m 0, b m 1, …, b m n , …, b m N-1 ], b m n is the sub-signal of the n+1th phase in the mth DFI interface signal, the DFI interface signal includes sub-signals of N phases, n is an integer in the range of [0, N-1], and f1 and f2 satisfy the condition: f2=f1×N;

[0017] The protocol analysis module includes a signal analysis submodule and a command analysis submodule. The signal analysis submodule includes a counter. The counter performs a self-increment operation on a count value i according to f2, i is initially zero. The signal analysis submodule determines a target subsignal according to i and N, and sends the target subsignal to the command analysis submodule at a time point corresponding to i.

[0018] The command parsing submodule maps the received truth value data corresponding to the target sub-signal into command information according to the truth value mapping table corresponding to the DDR particle to be used, and uses the command information as the DFI protocol parsing result. The truth value mapping table includes the mapping relationship between the truth value data corresponding to the target sub-signal and the command information.

[0019] Among them, the DFI protocol parsing system provided in this embodiment can be applied to a frequency ratio system. Usually, in a frequency ratio system, the DDR controller clock frequency and the DDR memory clock frequency are 1:2 or 1:4. Accordingly, when the DFI protocol parsing system is applied to a 1:2 frequency ratio system, the value of N is 2, and when the DFI protocol parsing system is applied to a 1:4 frequency ratio system, the value of N is 4.

[0020] The DDR controller sends M DFI interface signals to the DFI interface at the first clock frequency f1, which may mean that the intervals between the first time points of sending any two adjacent DFI interface signals are the same and are both time intervals corresponding to the first clock frequency f1. Accordingly, a m is the mth DFI interface signal, which can refer to a m It is the DFI interface signal sent at the mth first time point.

[0021] Specifically, the counter performs a self-increment operation on the count value i according to f2, which may mean that the counter performs a self-increment operation on the count value i at each second time point corresponding to f2. The initial value of i is zero. Then at the first second time point, i is updated to 1. At the second second time point, i is updated to 2, ... and so on. The time point corresponding to i is the second time point corresponding to i.

[0022] In a specific implementation, the signal analysis submodule determines the target sub-signal according to i and N, including:

[0023] According to i and N, determine the target signal a p , p = g(i / N), where g() is a rounding function and p is an integer in the range [1, M];

[0024] According to i and N, determine the target signal a p The target sub-signal a in q p , q=(i mod N)⊕1.

[0025] For example, when N is 2 and i increases to 9, according to p=g(i / N), p=5 is obtained, that is, the fifth DFI interface signal a5 is the target signal, mod is the remainder calculation, the calculation result of i mod N is the remainder of i / N, i mod N=1, ⊕ is the XOR operation, q=0, then the target sub-signal is a 0 5.

[0026] In a specific implementation, when the system further includes a physical layer, the clock source of the protocol analysis module is connected to the clock source of the physical layer;

[0027] When the system does not include a physical layer, the clock source of the protocol analysis module is obtained by processing the clock source of the DDR controller through a frequency multiplication circuit, so that the clock domain of the protocol analysis module corresponds to the second clock frequency f2.

[0028] It should be noted that the DDR IP system generally includes a DDR controller, a DFI interface, a physical layer and DDR particles. Since this embodiment is only used for DFI protocol analysis, this embodiment is described by taking the DFI protocol analysis system including a DDR controller and a DFI interface as an example.

[0029] Since in the frequency ratio system, the DDR controller clock frequency and the DDR memory clock frequency are 1:2 or 1:4, and the DDR memory clock frequency is consistent with the physical layer clock frequency, when the system also includes a physical layer, the clock source of the protocol parsing module is connected to the clock source of the physical layer so that the clock domain of the protocol parsing module corresponds to the second clock frequency f2.

[0030] If the system does not include a physical layer, DFI protocol analysis can also be performed. At this time, the clock source of the protocol analysis module is obtained by multiplying the clock source of the DDR controller through a frequency multiplication circuit so that the clock domain of the protocol analysis module corresponds to the second clock frequency f2.

[0031] In this embodiment, a clock source setting method for the protocol parsing module is provided, so that implementers can quickly apply the DFI protocol parsing system provided in this embodiment when switching systems with different frequency ratios or when the system does not include a physical layer, thereby further improving the versatility of DFI protocol parsing.

[0032] In a specific implementation, when the DDR particle to be used is of GDDR6 type, the target sub-signal is 22 bits, and the command parsing submodule maps the received truth value data corresponding to the target sub-signal into command information according to the truth value mapping table corresponding to the DDR particle to be used, including:

[0033] The command parsing submodule uses the high 11 bits of the received target sub-signal as the target rising edge signal, and uses the low 11 bits of the received target sub-signal as the target falling edge signal, and maps the truth value data corresponding to the target rising edge signal to the first sub-command information according to the truth value mapping table corresponding to the GDDR6 type, and maps the truth value data corresponding to the target falling edge signal to the second sub-command information, and the command information is formed by the first sub-command information and the second sub-command information.

[0034] Among them, by sampling the target rising edge signal and the target falling edge signal respectively, the true value data corresponding to the target rising edge signal and the true value data corresponding to the target falling edge signal can be obtained.

[0035] In a specific embodiment, the system also includes a monitor, the command information corresponds to a command type, and the monitor is used to count and display the number of command information of different command types in a unit time period according to the DFI protocol parsing results, and the command type includes at least a read command type and a write command type.

[0036] Among them, the command type can also include activation type, pre-charge type, read command type, write command type, etc. Since the command information is parsed according to the time point, after determining the unit time period, the number of command information of each command type can be counted according to each time point within the unit time period. The unit time period can be set by the implementer. In this embodiment, the unit time period is set to 1 second, and statistics can be achieved through a counter.

[0037] In a specific implementation, the monitor is also used to determine and display the data bandwidth of the DFI interface within the unit time period based on the read data bit width corresponding to the command information of each read command type and the write data bit width corresponding to the command information of each write command type within the unit time period.

[0038] Among them, the command information not only corresponds to the command type, but also corresponds to the command data. According to the data bit width corresponding to the command information, the data bandwidth of the DFI interface is calculated. Compared with the existing method of calculating the data bandwidth at the software level, the convenience of data bandwidth calculation is improved.

[0039] In a specific implementation, the command information includes block information, and the monitor is further used to count the number of accesses to the block information within the unit time period and display the counted information.

[0040] Among them, the number of block information accesses within a unit time period may refer to the number of different memory blocks accessed within a unit time period. The number of accesses can effectively represent the access rate of the system. However, in the existing methods, it is difficult to obtain the accessed memory block information through the software level or the master end of the system-level chip SOC, resulting in the inability to obtain the number of accesses information.

[0041] In a specific implementation, the command information includes row information, column information and block information, and the monitor is further used to convert and display the DFI data stream formed by the command information into an AXI data stream based on the row information, the column information, the block information and mapping information of the DDR controller.

[0042] Among them, the mapping information may include the placement information of the command information. Combined with the row information, column information and block information, the DFI data stream can be converted into an AXI data stream, so that when parity errors, ecc errors, etc. occur, it is convenient to perform data comparison between the software side and the memory side.

[0043] In one embodiment, after obtaining the AXI data stream, the implementer can also evaluate and optimize the AXI address sending method based on the AXI address, combined with the row information, column information, block information, and the number of block information accesses per unit time period displayed in the monitor. Specifically, the prior information of this embodiment is that when data is accessed in memory in units of rows, the memory efficiency is higher, while when accessing on the software side, the access position when accessing the memory is usually not particularly considered. The row information, column information, and block information displayed on the monitor can be used to adjust a more ideal memory access position sequence, thereby providing the software side with a reference for optimizing the AXI address sending method, and the number of block information accesses per unit time period can also be used as one of the criteria for evaluating the AXI address sending method, thereby achieving overall optimization of the SOC and improving system bandwidth.

[0044] In this embodiment, the signal analysis module parses the DFI interface signal sent to the DFI interface by the DDR controller at the first clock frequency at the second clock frequency, and sends the sub-signals of multiple phases to the command parsing module in sequence in combination with the count value, and the command parsing module then performs parsing processing according to the truth value mapping table. The command parsing module does not need to distinguish the phases of the sub-signals, thereby saving a lot of logic required for parsing, reducing the amount of code required for parsing, and effectively reducing the cost of DFI protocol parsing. In addition, the signal analysis process and the command parsing process are decoupled. When applied to particles of different DDR types, only the command parsing module needs to be modified, thereby improving the versatility of DFI protocol parsing.

[0045] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A DFI protocol parsing system, comprising a DDR controller and a DFI interface, characterized in that: The system also includes a protocol parsing module; The protocol parsing module is connected to the output side of the DDR controller to receive, at a second clock frequency f2, M DFI interface signals [a1, a2, ..., a3] sent by the DDR controller to the DFI interface at a first clock frequency f1. m , …, a M ], where a m is the mth DFI interface signal, where m is an integer in the range [1, M], and a m =[b m 0, b m 1, …, b m n , …, b m N-1 ], b m n is the sub-signal of the n+1th phase in the mth DFI interface signal, the DFI interface signal includes sub-signals of N phases, n is an integer in the range of [0, N-1], and f1 and f2 satisfy the condition: f2=f1×N; The protocol analysis module includes a signal analysis submodule and a command analysis submodule. The signal analysis submodule includes a counter. The counter performs a self-increment operation on a count value i according to f2, i is initially zero. The signal analysis submodule determines a target subsignal according to i and N, and sends the target subsignal to the command analysis submodule at a time point corresponding to i. The signal analysis submodule determines the target subsignal according to i and N, including: According to i and N, determine the target signal a p , p = g(i / N), where g() is a rounding function and p is an integer in the range [1, M]; According to i and N, determine the target signal a p The target sub-signal a in q p , q=(i mod N)⊕1; The command parsing submodule maps the received truth value data corresponding to the target sub-signal into command information according to the truth value mapping table corresponding to the DDR particle to be used, and uses the command information as the DFI protocol parsing result. The truth value mapping table includes the mapping relationship between the truth value data corresponding to the target sub-signal and the command information.

2. The DFI protocol analysis system according to claim 1, characterized in that: When the system further includes a physical layer, the clock source of the protocol analysis module is connected to the clock source of the physical layer; When the system does not include a physical layer, the clock source of the protocol analysis module is obtained by processing the clock source of the DDR controller through a frequency multiplication circuit, so that the clock domain of the protocol analysis module corresponds to the second clock frequency f2.

3. The DFI protocol analysis system according to claim 1, characterized in that: When the DDR particle to be used is of GDDR6 type, the target sub-signal is 22 bits, and the command parsing sub-module maps the received truth value data corresponding to the target sub-signal into command information according to the truth value mapping table corresponding to the DDR particle to be used, including: The command parsing submodule uses the high 11 bits of the received target sub-signal as the target rising edge signal, and uses the low 11 bits of the received target sub-signal as the target falling edge signal, and maps the truth value data corresponding to the target rising edge signal to the first sub-command information according to the truth value mapping table corresponding to the GDDR6 type, and maps the truth value data corresponding to the target falling edge signal to the second sub-command information, and the command information is formed by the first sub-command information and the second sub-command information.

4. The DFI protocol analysis system according to claim 1, characterized in that: The system also includes a monitor, the command information corresponds to a command type, and the monitor is used to count and display the number of command information of different command types in a unit time period according to the DFI protocol parsing result, and the command type includes at least a read command type and a write command type.

5. The DFI protocol analysis system according to claim 4, characterized in that: The monitor is further used to determine and display the data bandwidth of the DFI interface within the unit time period according to the read data bit width corresponding to the command information of each read command type and the write data bit width corresponding to the command information of each write command type within the unit time period.

6. The DFI protocol analysis system according to claim 4, characterized in that: The command information includes block information, and the monitor is further used to count the number of accesses to the block information within the unit time period and display the counted number of accesses to the block information.

7. The DFI protocol analysis system according to claim 4, characterized in that: The command information includes row information, column information and block information. The monitor is also used to convert and display the DFI data stream formed by the command information into an AXI data stream according to the row information, the column information, the block information and mapping information of the DDR controller.

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