Negative power supply open circuit detection circuit and driver chip

Abstract

The present invention discloses a negative power supply open circuit detection circuit and a driver chip, wherein the negative power supply open circuit detection circuit comprises a bias circuit module, a comparison circuit module, a sampling circuit module and a filter circuit module; the input end of the bias circuit module is linked to the positive power supply, and the output end of the bias circuit is connected to the comparison circuit module; the comparison circuit module is respectively connected to the bias circuit module, the positive power supply, the negative power supply and the reference ground; the sampling circuit module is connected between the reference ground and the negative power supply; wherein the comparison circuit module is used to detect whether the negative power supply is open circuit. The present invention can detect the negative power supply open circuit through the bias circuit module, the comparison circuit module and the sampling circuit module, thereby not relying on additional reference circuits, sampling circuits and bias circuits, having strong portability and simple structure, and solving the problem of lack of negative power supply detection circuit in the prior art.

Description

Technical Field

[0001] The invention relates to the technical field of detection circuits, and in particular to a negative power supply open circuit detection circuit and a drive chip. Background Art

[0002] With the continuous development of electronic technology, electronic systems are moving towards high power and small size. In high-power systems, power devices such as IGBT (insulated gate bipolar transistor) and SiC MOSFET (metal oxide semiconductor field effect transistor based on silicon carbide material) are an indispensable part. These power devices usually require the system to provide positive and negative power supplies and front drive circuits to achieve reliable on / off. If the positive and negative power supplies of the system fail, it may cause the power device to fail to turn on or mis-turn on, causing damage to the device. Therefore, fault detection circuits for positive and negative power supplies become particularly important.

[0003] Taking the electric drive system as an example, various fault detection circuits are usually implemented by highly integrated driver chips. In driver chips, detection circuits for positive power supplies are already very popular, and there are many mature solutions; but detection circuits for negative power supplies have not received much attention, and there is a lack of detection circuits for negative power supplies in the existing technology.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a negative power open circuit detection circuit and a driver chip to at least solve the problem of lack of negative power detection circuit in the prior art.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] The embodiment of the present invention provides a negative power supply open circuit detection circuit, including a bias circuit module, a comparison circuit module, a sampling circuit module and a filter circuit module;

[0008] The input end of the bias circuit module is linked to the positive power supply, and the output end of the bias circuit is connected to the comparison circuit module; the comparison circuit module is respectively connected to the bias circuit module, the positive power supply, the negative power supply and the reference ground; the sampling circuit module is connected between the reference ground and the negative power supply; wherein the comparison circuit module is used to detect whether the negative power supply is open.

[0009] Furthermore, the bias circuit module includes:

[0010] a first resistor, wherein a first end of the first resistor is connected to the positive power supply;

[0011] a first NMOS transistor, wherein a drain of the first NMOS transistor is respectively connected to the second end of the first resistor and a gate of the first NMOS transistor;

[0012] A second NMOS tube, wherein the drain of the second NMOS tube is respectively connected to the source of the first NMOS tube and the gate of the second NMOS tube, and the source of the second NMOS tube is connected to the negative power supply.

[0013] Furthermore, the comparison circuit module comprises:

[0014] a second resistor, wherein a first end of the second resistor is connected to a negative power supply;

[0015] a third NMOS transistor, wherein a source of the third NMOS transistor is connected to the second end of the second resistor, and a gate of the third NMOS transistor is connected to the bias circuit module;

[0016] a first PMOS tube, wherein a drain of the first PMOS tube is respectively connected to a drain of the third NMOS tube and a gate of the first PMOS tube, and a source of the first PMOS tube is connected to the positive power supply;

[0017] a second PMOS tube, wherein a gate of the second PMOS tube is connected to the gate of the first PMOS tube, and a source of the second PMOS tube is connected to the positive power supply;

[0018] a fourth NMOS tube, wherein a drain of the fourth NMOS tube is connected to a drain of the second PMOS tube, and a gate of the fourth NMOS tube is respectively connected to the bias circuit module and a gate of the third NMOS tube;

[0019] A third resistor, wherein a first end of the third resistor is connected to the source of the fourth NMOS transistor, and a second end of the third resistor is connected to the reference ground.

[0020] Furthermore, the sampling circuit module includes:

[0021] A diode has a cathode connected to the reference ground, and an anode connected to the negative power supply.

[0022] Furthermore, the diode is a parasitic diode or an ESD diode.

[0023] Furthermore, the negative power supply open circuit detection circuit also includes:

[0024] A filter circuit module is connected between the positive power supply and the negative power supply and is connected to the comparison circuit module; and is used to improve the robustness of the negative power supply open circuit detection circuit.

[0025] Furthermore, the filter circuit module includes:

[0026] a third PMOS tube, wherein a source of the third PMOS tube is connected to the positive power supply, and a gate of the third PMOS tube is connected to the comparison circuit module;

[0027] a fourth resistor, a first end of the fourth resistor being connected to the drain of the third PMOS tube;

[0028] a fifth NMOS tube, wherein the drain of the fifth NMOS tube is connected to the second end of the fourth resistor, the gate of the fifth NMOS tube is respectively connected to the comparison circuit module and the drain of the third PMOS tube, and the source of the fifth NMOS tube is connected to a negative power supply;

[0029] A capacitor, two ends of which are connected to the second end of the fourth resistor and the negative power supply respectively;

[0030] A Schmitt trigger, wherein an input end of the Schmitt trigger is connected to the second end of the fourth resistor, and an output end of the Schmitt trigger is connected to an open circuit indication signal.

[0031] An embodiment of the present invention further provides a driver chip, comprising any of the above-mentioned negative power supply open circuit detection circuits.

[0032] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0033] A negative power supply open circuit detection circuit of the present invention can detect the negative power supply open circuit through a bias circuit module, a comparison circuit module and a sampling circuit module, thereby not relying on additional reference circuits, sampling circuits and bias circuits, having strong portability and simple structure, and solving the problem of lack of negative power supply detection circuits in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 The diagram is a circuit diagram of a negative power supply open circuit detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0038] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0039] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0040] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0041] Taking the electric drive system as an example, if the negative power supply VEE of the system is lost or the negative power supply VEE is open, the driver chip cannot turn off the power device with negative voltage. During the switching process of the power device, the large voltage change slope (dV / dt) may be coupled to the gate of the device through the Miller capacitance of the device, causing the power device to be mis-conducted, and then causing the bridge arm to be directly damaged.

[0042] In view of the defects of the prior art, the present application can detect the open circuit of the negative power supply VEE through a bias circuit module, a comparison circuit module and a sampling circuit module, and improve the robustness of the negative power supply open circuit detection circuit through a filtering circuit module to prevent false alarms under harsh working conditions.

[0043] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0044] Example 1

[0045] like Figure 1 As shown, the embodiment of the present application provides a negative power supply open circuit detection circuit, including a bias circuit module 1, a comparison circuit module 2 and a sampling circuit module 3. Among them, the input end of the bias circuit module 1 is connected to the positive power supply VCC, and the output end of the bias circuit module 1 is connected to the negative power supply VEE; the comparison circuit module 2 is respectively connected to the bias circuit module 1, the positive power supply VCC, the negative power supply VEE, and the reference ground GND, for detecting whether the negative power supply VEE is open circuit; the sampling circuit module 3 is connected between the negative power supply VEE and the reference ground GND.

[0046] Furthermore, the bias circuit module 1 includes a first resistor R3, a first NMOS transistor M5, and a second NMOS transistor M6. The first end of the first resistor R3 is connected to the positive power supply VCC; the drain of the first NMOS transistor M5 is respectively connected to the second end of the first resistor R3 and the gate of the first NMOS transistor M5; the drain of the second NMOS transistor M6 is respectively connected to the source of the first NMOS transistor M5 and the gate of the second NMOS transistor M6, and the source of the second NMOS transistor M6 is connected to the negative power supply VEE.

[0047] Furthermore, the comparison circuit module 2 includes a second resistor R1, a third NMOS transistor M1, a first PMOS transistor M3, a second PMOS transistor M4, a fourth NMOS transistor M2 and a third resistor R2. Among them, the first end of the second resistor R1 is connected to the negative power supply VEE; the source of the third NMOS tube M1 is connected to the second end of the second resistor R1, and the gate of the third NMOS tube M1 is connected to the bias circuit module 1; the drain of the first PMOS tube M3 is connected to the drain of the third NMOS tube M1 and the gate of the first PMOS tube M3 respectively, and the source of the first PMOS tube M3 is connected to the positive power supply VCC; the gate of the second PMOS tube M4 is connected to the gate of the first PMOS tube M3, and the source of the second PMOS tube M4 is connected to the positive power supply VCC; the drain of the fourth NMOS tube M2 is connected to the drain of the second PMOS tube M4, and the gate of the fourth NMOS tube M2 is connected to the bias circuit module 1 and the gate of the third NMOS tube M1 respectively; the first end of the third resistor R2 is connected to the source of the fourth NMOS tube M2, and the second end of the third resistor R2 is connected to the reference ground GND.

[0048] Specifically, the gate of the third NMOS transistor M1 is connected to the gate of the first NMOS transistor M5 ; the gate of the fourth NMOS transistor M2 is connected to the gate of the first NMOS transistor M5 .

[0049] Furthermore, the sampling circuit module 3 includes a diode D1 , a cathode of the diode D1 is connected to the reference ground GND, and an anode of the diode D1 is connected to the negative power supply VEE.

[0050] Specifically, the cathode of the diode D1 is connected to the second end of the third resistor R2.

[0051] Furthermore, the diode D1 in the sampling circuit module 3 does not need to be additionally integrated, and it can be a diode D1 in a general circuit, such as a parasitic diode D1 or an ESD diode D1.

[0052] In some of the embodiments, the negative power supply open circuit detection circuit also includes a filter circuit module 4, which is connected between the positive power supply VCC and the negative power supply VEE, and is connected to the comparison circuit module 2, for improving the robustness of the negative power supply open circuit detection circuit.

[0053] Further, the filter circuit module 4 includes a third PMOS tube M7, a fourth resistor R4, a fifth NMOS tube M8, a capacitor C1 and a Schmitt trigger X1. Among them, the source of the third PMOS tube M7 is connected to the positive power supply VCC, and the gate of the third PMOS tube M7 is connected to the comparison circuit module 2; the first end of the fourth resistor R4 is connected to the drain of the third PMOS tube M7; the drain of the fifth NMOS tube M8 is connected to the second end of the fourth resistor R4, the gate of the fifth NMOS tube M8 is connected to the comparison circuit module 2, and the source of the fifth NMOS tube M8 is connected to the negative power supply VEE; the two ends of the capacitor C1 are respectively connected to the second end of the fourth resistor R4 and the negative power supply VEE; the input end of the Schmitt trigger X1 is connected to the second end of the fourth resistor R4, and the output end of the Schmitt trigger X1 is connected to the open circuit indication signal OUT.

[0054] Specifically, the gate of the third PMOS tube M7 is connected to the drain of the second PMOS tube M4; the gate of the fifth NMOS tube M8 is connected to the drain of the second PMOS tube M4.

[0055] The PMOS transistor and the NMOS transistor in this embodiment are both field effect transistors.

[0056] The implementation method of the embodiment of the present invention is as follows:

[0057] One end of the first resistor R3 is connected to the positive power supply VCC, and the other end is connected to the drain of the first NMOS tube M5. The drain of the first NMOS tube M5 is connected to the gate of the first NMOS tube M5, and is connected to the gates of the third NMOS tube M1 and the fourth NMOS tube M2. The source of the first NMOS tube M5 is connected to the drain of the second NMOS tube M6 and the gate of the second NMOS tube M6. The source of the second NMOS tube M6 is connected to the negative power supply VEE. The anode of the diode D1 is connected to the negative power supply VEE, and the cathode is connected to the reference ground GND. One end of the second resistor R1 is connected to the negative power supply VEE, and the other end is connected to the source of the third NMOS tube M1. One end of the third resistor R2 is connected to the reference ground GND, and the other end is connected to the source of the fourth NMOS tube M2. The drain of the third NMOS tube M1 is connected to the drain of the first PMOS tube M3, the gate of the first PMOS tube M3, and the gate of the second PMOS tube M4. The source of the first PMOS tube M3 is connected to the positive power supply VCC. The source of the second PMOS tube M4 is also connected to the positive power supply VCC. The drain of the second PMOS tube M4 is connected to the drain of the fourth NMOS tube M2, and is connected to the gates of the third PMOS tube M7 and the fifth NMOS tube M8. The source of the fourth PMOS tube M7 is connected to the positive power supply VCC, and the drain of the fourth PMOS tube M7 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the drain of the fifth MOS tube M8, one end of the capacitor C1, and the input end of the Schmitt trigger X1. The source of M8 is connected to the negative power supply VEE. The other end of the capacitor C1 is connected to the negative power supply VEE. The output end of the Schmitt trigger X1 is connected to the open circuit indication signal OUT.

[0058] The detection principle of the embodiment of the present invention is as follows:

[0059] Assume first that the second resistor R1 = the third resistor R2, when the positive and negative power sources VEE work normally, the reference ground GND is used as the reference ground (0V), and the voltage of the negative power source VEE is usually lower than the reference ground GND, for example -5V;

[0060] At this time, the current flowing through the second resistor R1 is greater than the current flowing through the third resistor R2, so that the gate of the fifth NMOS transistor M8 is charged to a high level, the filter capacitor C1 is discharged, and the output OUT is a low level, indicating that the negative power supply VEE works normally;

[0061] When an open circuit fault occurs in the negative power supply VEE, under the action of the left bias circuit module 1, current continuously flows into the negative power supply VEE, flows through the diode D1, and finally flows into the reference ground GND. Under the action of this current, the voltage of the negative power supply VEE becomes higher than the voltage of the reference ground GND by a diode D1 drop, and the typical value is about 0.7V. At this time, the current flowing through the second resistor R1 is less than the current through the third resistor R2, so that the gate of the third PMOS tube M7 is put into a low level, the filter capacitor C1 is charged, and the output OUT finally becomes a high level, indicating that the negative power supply VEE has a fault.

[0062] The sampling diode D1 usually does not need to be placed specially. Because in the circuit powered by the positive and negative power supplies VEE, the reference ground GND and the negative power supply VEE are both external pins. The chip will have an ESD electrostatic protection circuit for such pins. A typical ESD circuit includes the diode D1.

[0063] The second resistor R1 and the third resistor R2 can adjust the flip threshold of the comparison circuit. At this time, the voltage of the reference ground GND can be set to 0V, then the flip threshold expression of the negative power supply VEE is as follows:

[0064]

[0065] Among them, V GS6 is the gate-source voltage of the MOS tube M6.

[0066] Considering that when the negative power supply VEE is suspended, the negative power supply VEE voltage is usually equal to a diode D1 voltage drop, about 0.7V, at this time the comparator must be able to detect the fault. When the negative power supply VEE is negative or even 0V, the comparator cannot falsely report a fault. Combining the above two points, the comparator VTH is set at 0.3V for the best state. If V GS6 is 0.9V, then the optimal resistance ratio R1 / R2=2 / 3 can be obtained.

[0067] In the present invention, the function of the filter circuit module 4 is to improve the robustness of the detection circuit and prevent it from false alarms under harsh working conditions. Taking the drive circuit as an example, when the drive circuit applies PWM signal excitation, the output gate-level signal is constantly flipped, and a large transient current may flow into the negative power supply VEE pin of the chip, causing the instantaneous VEE voltage to exceed the GND voltage. If the detection circuit is not provided with a filter circuit, it will be mistakenly flipped under harsh working conditions, resulting in frequent false alarms of the system. After adding the filter circuit, this detection circuit can work stably under various harsh working conditions.

[0068] In summary, the negative power supply open circuit detection circuit proposed by the present invention can effectively improve the fault diagnosis capability of the system. The detection circuit has a simple structure, is easy to implement, has extremely low cost, and has strong robustness, and can be applied to various systems powered by positive and negative power supplies VEE.

[0069] In the existing power supply detection circuit, a sampling circuit is usually used to sample the negative power supply VEE, and then the negative power supply is compared with the voltage reference provided by the reference circuit. That is, a sampling circuit is usually required in the existing power supply detection circuit, and a reference circuit, a bias circuit, a comparison circuit and a filter circuit are also required to be built into the chip to cooperate with the sampling circuit to work. In the present application, no additional sampling circuit, reference circuit, etc. are required to realize the open circuit detection of the negative power supply.

[0070] Therefore, when the present invention is applied to a chip powered by positive and negative power supplies VEE, it can detect the open circuit fault of the negative power supply VEE. The negative power supply open circuit detection circuit of the present invention has a simple structure, is easy to implement, and has low cost. It does not rely on additional bias circuits, reference circuits, and sampling circuits, and has strong portability.

[0071] Example 2

[0072] The embodiment of the present application also provides a driver chip, including the negative power supply open circuit detection circuit described in Embodiment 1.

[0073] The negative power supply open circuit detection circuit of the present invention is simple and reliable, and can realize the detection of negative power supply open circuit faults and be integrated into a driving chip. Since the negative power supply open circuit detection circuit of the present invention has a simple structure and a small area, it almost does not consume additional area and does not require additional circuit coordination, thereby improving the fault diagnosis coverage of the entire system and enhancing the safety performance of the system.

[0074] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0075] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A negative power supply open circuit detection circuit, characterized in that: It includes a bias circuit module, a comparison circuit module, a sampling circuit module and a filter circuit module; The input end of the bias circuit module is connected to the positive power supply, and the output end of the bias circuit is connected to the comparison circuit module; the comparison circuit module is respectively connected to the bias circuit module, the positive power supply, the negative power supply and the reference ground; the sampling circuit module is connected between the reference ground and the negative power supply; wherein the comparison circuit module is used to detect whether the negative power supply is open circuit Wherein, the bias circuit module comprises: a first resistor, wherein a first end of the first resistor is connected to the positive power supply; a first NMOS transistor, wherein a drain of the first NMOS transistor is respectively connected to the second end of the first resistor and a gate of the first NMOS transistor; a second NMOS tube, wherein the drain of the second NMOS tube is respectively connected to the source of the first NMOS tube and the gate of the second NMOS tube, and the source of the second NMOS tube is connected to the negative power supply; The comparison circuit module comprises: a second resistor, wherein a first end of the second resistor is connected to a negative power supply; a third NMOS transistor, wherein a source of the third NMOS transistor is connected to the second end of the second resistor, and a gate of the third NMOS transistor is connected to the bias circuit module; a first PMOS tube, wherein a drain of the first PMOS tube is respectively connected to a drain of the third NMOS tube and a gate of the first PMOS tube, and a source of the first PMOS tube is connected to the positive power supply; a second PMOS tube, wherein a gate of the second PMOS tube is connected to the gate of the first PMOS tube, and a source of the second PMOS tube is connected to the positive power supply; a fourth NMOS tube, wherein a drain of the fourth NMOS tube is connected to a drain of the second PMOS tube, and a gate of the fourth NMOS tube is respectively connected to the bias circuit module and a gate of the third NMOS tube; a third resistor, wherein a first end of the third resistor is connected to the source of the fourth NMOS transistor, and a second end of the third resistor is connected to the reference ground; The sampling circuit module comprises: A diode has a cathode connected to the reference ground, and an anode connected to the negative power supply.

2. The negative power supply open circuit detection circuit according to claim 1, characterized in that: The diode is a parasitic diode or an ESD diode.

3. The negative power supply open circuit detection circuit according to claim 1, characterized in that: Also includes: A filter circuit module, wherein the filter circuit module is connected between the positive power supply and the negative power supply and is connected to the comparison circuit module; Used to improve the robustness of the negative power supply open circuit detection circuit.

4. The negative power supply open circuit detection circuit according to claim 3, characterized in that: The filter circuit module comprises: a third PMOS tube, wherein a source of the third PMOS tube is connected to the positive power supply, and a gate of the third PMOS tube is connected to the comparison circuit module; a fourth resistor, a first end of the fourth resistor being connected to the drain of the third PMOS tube; a fifth NMOS tube, wherein the drain of the fifth NMOS tube is connected to the second end of the fourth resistor, the gate of the fifth NMOS tube is respectively connected to the comparison circuit module and the drain of the third PMOS tube, and the source of the fifth NMOS tube is connected to a negative power supply; A capacitor, two ends of which are connected to the second end of the fourth resistor and the negative power supply respectively; A Schmitt trigger, wherein an input end of the Schmitt trigger is connected to the second end of the fourth resistor, and an output end of the Schmitt trigger is connected to an open circuit indication signal.

5. A driver chip, characterized in that: The invention comprises the negative power supply open circuit detection circuit as described in any one of claims 1 to 4.

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