A high-voltage trench SiC power device and preparation method thereof

Abstract

The present invention discloses a high withstand voltage trench SiC power device and a preparation method, which relates to the field of semiconductor devices, including a first conductive type SiC substrate and an active area arranged in the central area of ​​the SiC substrate, wherein the active area includes a second conductive type shielding layer traversing the active area and a plurality of trench cells distributed in parallel; for any trench cell, a trench gate unit is included above the second conductive type shielding layer, wherein the trench gate unit is isolated from the second conductive type shielding layer; the second conductive type shielding layer is electrically connected to a front first electrode metal for forming a front first electrode above the SiC substrate; the front first electrode metal is insulated and isolated from the trench gate unit; when the power device is reversely turned off, the second conductive type shielding layer is used to shield the electric field at the trench gate unit. The power device has high withstand voltage capability and reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, and in particular to a high-voltage trench SiC power device and a preparation method thereof. Background Art

[0002] In response to the country's call for green and environmentally friendly energy demand, the power electronics industry is vigorously developing and iterating various types of devices to seek high power handling capabilities and low energy loss. Among them, the large bandgap width and critical breakdown electric field strength of silicon carbide materials indicate that this type of material has great application value in voltage applications of 1000V and above.

[0003] At present, silicon carbide-based power devices have occupied a place in the medium and high voltage market due to their advantages such as high voltage level, high switching frequency, low dynamic and static loss, and high thermal conductivity. With the continuous iteration of technology, the critical dimensions of planar gate power devices have been reduced to their limits. If we want to further increase the current density, we can only use trench technology.

[0004] However, the industry has discovered that the gate oxide layer at the bottom of the trench will be subjected to the ultra-high electric field strength brought by the SiC material. This difference from silicon-based materials may lead to long-term reliability degradation of the device at best, or even cause the gate oxide layer to be unable to withstand the operating voltage and break down. Summary of the invention

[0005] In view of the above problems and technical requirements, the inventors have proposed a high withstand voltage trench SiC power device and a preparation method. The technical solution of the present invention is as follows:

[0006] A high withstand voltage trench SiC power device, comprising a first conductive type SiC substrate and an active region arranged in the center of the SiC substrate, wherein the active region comprises a second conductive type shielding layer traversing the active region and a plurality of trench cells arranged in parallel;

[0007] For any trench type cell, a trench gate unit is included which is located above the second conductive type shielding layer, and the trench gate unit is isolated from the second conductive type shielding layer;

[0008] The second conductive type shielding layer is electrically connected to the front first electrode metal for forming the front first electrode above the SiC substrate;

[0009] The front first electrode metal is insulated and isolated from the trench gate unit;

[0010] When the power device is turned off in reverse, the second conductive type shielding layer is used to shield the electric field at the trench gate unit.

[0011] A further technical solution is that a shielding layer lead-out unit is provided between adjacent trench cells in the active area;

[0012] The shielding layer lead-out unit comprises a second conductive type shielding layer lead-out region, and the second conductive type shielding layer lead-out region is in contact with the second conductive type shielding layer;

[0013] The second conductive type shielding layer lead-out region is in ohmic contact with a front first electrode metal on the SiC substrate for forming a front first electrode.

[0014] A further technical solution is that the second conductive type shielding layer lead-out region includes a second conductive type first shielding layer lead-out region and a second conductive type second shielding layer lead-out region, wherein:

[0015] The second conductive type first shielding layer lead-out region and the second conductive type second shielding layer lead-out region are both located in the SiC substrate;

[0016] The second conductive type first shielding layer lead-out region is located below the second conductive type second shielding layer lead-out region and contacts the second conductive type second shielding layer lead-out region;

[0017] In the direction from the active region to the terminal region, the width of the second conductivity type first shielding layer lead-out region is smaller than the width of the second conductivity type second shielding layer lead-out region;

[0018] The second conductive type first shielding layer lead-out region contacts the second conductive type shielding layer.

[0019] A further technical solution is that the shielding layer lead-out unit further includes a shielding layer lead-out groove, and the second conductive type shielding layer lead-out region is formed in the SiC substrate based on the shielding layer lead-out groove, wherein:

[0020] The shielding layer lead-out groove is arranged between adjacent groove-type cells, and includes a first sub-groove and a second sub-groove, wherein:

[0021] The groove width of the first sub-groove is smaller than the groove width of the second sub-groove. The first sub-groove is located below the second sub-groove, and the groove opening of the first sub-groove is connected to the groove bottom of the second sub-groove.

[0022] A further technical solution is that the trench cell further includes a first conductive type doping region located below the trench gate unit, wherein:

[0023] The trench gate unit, the second conductive type shielding layer and the first conductive type doping region are all located in the first conductive type drift region in the SiC substrate, and the doping concentration of the first conductive type doping region is greater than the doping concentration of the first conductive type drift region;

[0024] The first conductive type doping region penetrates the second conductive type shielding layer and contacts the trench gate unit;

[0025] When the power device is forward-conducting, carriers flow from the first conductivity type doped region into the first conductivity type drift region.

[0026] A further technical solution is that the trench gate unit comprises a cell trench, a gate oxide layer formed on the inner wall of the cell trench, and a gate electrode body filled in the cell trench, wherein:

[0027] In the direction from the active area to the terminal area, the width of the cell trench is greater than the width of the first conductive type doping area;

[0028] The gate electrode body is insulated and isolated from the inner wall of the cell trench by a gate oxide layer, and the gate electrode body is in ohmic contact with the front side of the SiC substrate to form a second electrode metal of the front side second electrode.

[0029] A further technical solution is that a second conductive type base region is disposed on both sides of the cell trench, and a first conductive type source region is disposed in each second conductive type base region;

[0030] The second conductive type base region and the first conductive type source region are in contact with corresponding outer side walls of the cell trench;

[0031] The junction depth of the first conductive type source region is not greater than the junction depth of the second conductive type base region;

[0032] The second conductive type base region and the first conductive type source region are both in ohmic contact with the front first electrode metal.

[0033] A method for preparing a high withstand voltage trench SiC power device, used for preparing the above power device, the method for preparing the trench SiC power device comprising:

[0034] A SiC substrate having a first conductivity type is provided, and a front cell process is performed on the front surface of the SiC substrate, wherein:

[0035] When performing a front cell process on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, and a plurality of trench cells connected in parallel are prepared in the active area, as well as a second conductive type shielding layer that traverses the active area;

[0036] For any trench type cell, a trench gate unit is included which is located above the second conductive type shielding layer, and the trench gate unit is isolated from the second conductive type shielding layer;

[0037] The second conductive type shielding layer is electrically connected to the front first electrode metal for forming the front first electrode above the SiC substrate;

[0038] The front first electrode metal is insulated and isolated from the trench gate unit;

[0039] When the power device is turned off in reverse, the second conductive type shielding layer is used to shield the electric field at the trench gate unit.

[0040] A further technical solution is that the front cell process includes preparing a shielding layer lead-out unit in the active area;

[0041] When preparing the shielding layer lead-out unit, a preliminary groove is obtained by etching between adjacent groove-type cells;

[0042] Performing secondary etching on the prepared groove to prepare a first sub-groove, and preparing a second sub-groove above the first sub-groove, wherein the groove width of the first sub-groove is smaller than the groove width of the second sub-groove, and the groove opening of the first sub-groove is connected to the groove bottom of the second sub-groove;

[0043] Performing ion implantation into the SiC substrate through the first sub-groove and the second sub-groove to prepare a second conductive type shielding layer lead-out region, wherein the second conductive type shielding layer lead-out region is in contact with the second conductive type shielding layer;

[0044] Metal deposition is performed on the front side of the SiC substrate to obtain at least a front first electrode metal after the metal deposition, and the front first electrode metal is in ohmic contact with the second conductive type shielding layer lead-out region.

[0045] A further technical solution is to prepare a cell groove in a groove-type cell while preparing a preliminary groove;

[0046] The groove depth of the cellular groove is greater than the groove depth of the preparatory groove, and the groove width of the cellular groove is greater than the groove width of the preparatory groove;

[0047] Before performing secondary etching on the prepared groove, a side wall covering the side wall of the cell groove is prepared in the cell groove, and a first conductive type doping region is prepared below the cell groove by using the side wall;

[0048] The first conductive type doping region penetrates the second conductive type shielding layer and contacts the bottom of the cell trench;

[0049] In a direction from the active region to the terminal region, the width of the cell trench is greater than the width of the first conductive type doping region.

[0050] In the above-mentioned "first conductivity type" and "second conductivity type", for N-type power devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type power devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0051] The beneficial technical effects of the present invention are:

[0052] The present invention improves the withstand voltage of the device by arranging a second conductive type shielding layer that traverses the active region. When the power device is reversely turned off, the second conductive type shielding layer can effectively shield the electric field at the gate oxide layer, so that the electric field strength at the gate oxide layer can be reduced to a reasonable level.

[0053] At the same time, a shielding layer lead-out unit is provided between adjacent groove-type cells for leading out the connection potential of the second conductive type shielding layer. The shielding layer lead-out unit includes a shielding layer lead-out groove and a second conductive type shielding layer lead-out region located in the shielding layer lead-out groove. By setting the shielding layer lead-out groove, the second conductive type shielding layer lead-out region can achieve the lead-out of the second conductive type shielding layer potential when the implantation depth in the SiC substrate is relatively shallow, thereby avoiding the problem of long-term reliability degradation of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a cross-sectional schematic diagram of an embodiment of a high withstand voltage trench SiC power device provided by the present invention.

[0055] Figure 2-Figure 7 1 is a cross-sectional view of a process step of an embodiment of a method for preparing a high withstand voltage trench SiC power device provided by the present invention, wherein:

[0056] Figure 2 It is a cross-sectional view of an embodiment of the present invention after preparing a P-type shielding layer.

[0057] Figure 3 It is a cross-sectional view of an embodiment of the present invention after the preliminary groove is prepared.

[0058] Figure 4 It is a cross-sectional view of an embodiment of the present invention after the side wall is prepared.

[0059] Figure 5 It is a cross-sectional view of an embodiment after the N-type doping region is prepared in the present invention.

[0060] Figure 6 It is a cross-sectional view of an embodiment of the present invention after the P-type shielding layer lead-out region is prepared.

[0061] Figure 7 It is a cross-sectional view of an embodiment after the front metal layer is prepared in the present invention.

[0062] Figure numerals: 1-N-type substrate, 2-N-type drift region, 3-P-type shielding layer, 41-first sub-groove, 42-second sub-groove, 43-P-type shielding layer first lead-out region, 44-P-type shielding layer second lead-out region, 5-N-type doping region, 6-cell trench, 7-gate oxide layer, 8-gate electrode body, 9-P-type base region, 10-N-type source region, 11-insulating dielectric layer, 12-front metal layer, 13-first oxide layer, 14-preparatory groove, 15-etching groove, 151-first side wall, 152-second side wall, 16-second oxide layer. DETAILED DESCRIPTION

[0063] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0064] In order to improve the withstand voltage capability of power devices, the present invention provides a high withstand voltage trench SiC power device. Taking the first conductivity type as N type as an example, in one embodiment of the present invention, it includes an N type SiC substrate and an active area arranged in the center area of ​​the SiC substrate, wherein the active area includes a P type shielding layer 3 that traverses the active area and a plurality of trench cells that are arranged in parallel;

[0065] For any trench type cell, it includes a trench gate unit located above the P-type shielding layer 3, and the trench gate unit is isolated from the P-type shielding layer 3;

[0066] The P-type shielding layer 3 is electrically connected to the front first electrode metal on the SiC substrate for forming the front first electrode;

[0067] The front first electrode metal is insulated and isolated from the trench gate unit;

[0068] When the power device is turned off in reverse direction, the P-type shielding layer 3 is used to shield the electric field at the trench gate unit.

[0069] Specifically, the SiC substrate generally has a front side and a back side corresponding to the front side. For a power device, it generally includes an active area located on the SiC substrate and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art. Generally, the active area includes a plurality of cells distributed in parallel. In one embodiment of the present invention, the cell adopts a groove-type cell, that is, the active area includes a plurality of groove-type cells. In the active area, the groove-type cells can generally adopt the same structural form.

[0070] Generally, a front metal layer 12 is provided on the front of the SiC substrate, and the front metal layer 12 includes a first electrode metal for forming a first electrode, and a second electrode metal for forming a second electrode. A back metal layer is also provided on the back of the SiC substrate, and the back metal layer includes a third electrode metal for forming a third electrode. The trench SiC power device can form a MOSFET type device or an IGBT type device. For a MOSFET type device, the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode; for an IGBT type device, the first electrode is an emitter electrode, the second electrode is a gate electrode, and the third electrode is a collector electrode.

[0071] In one embodiment of the present invention, the SiC substrate includes an N-type substrate 1 and an N-type drift region 2 located on the N-type substrate 1, and the doping concentration of the N-type substrate 1 is greater than the doping concentration of the N-type drift region 2. The trench gate unit and the P-type shielding layer 3 are both located in the N-type drift region 2 in the SiC substrate, and the P-type shielding layer 3 traverses the active region, that is, the P-type shielding layer 3 traverses the N-type drift region 2 in the active region. In addition, the trench gate unit is located above the P-type shielding layer 3, and the trench gate unit is isolated from the P-type shielding layer 3, that is, the trench gate unit does not contact the P-type shielding layer 3, and the trench gate unit and the P-type shielding layer 3 are isolated by the N-type drift region 2 above the P-type shielding layer 3.

[0072] The P-type shielding layer 3 is electrically connected to the front first electrode metal on the SiC substrate for forming the front first electrode. When the power device is reversely turned off, the P-type shielding layer 3 is used to shield the electric field at the trench gate unit to reduce the electric field strength at the trench gate unit. The specific structure of the trench gate unit and the specific method of electrically connecting the P-type shielding layer 3 to the front first electrode metal can be referred to the following description.

[0073] Furthermore, a shielding layer lead-out unit is provided between adjacent trench cells in the active region;

[0074] The shielding layer lead-out unit comprises a P-type shielding layer lead-out region, and the P-type shielding layer lead-out region is in contact with the P-type shielding layer 3;

[0075] The P-type shielding layer lead-out region is in ohmic contact with the front first electrode metal on the SiC substrate for forming the front first electrode.

[0076] Specifically, the doping concentration of the P-type shielding layer lead-out region is greater than the doping concentration of the P-type shielding layer 3, the P-type shielding layer lead-out region is located in the N-type drift region 2, and one end of the P-type shielding layer lead-out region away from the front surface of the SiC substrate is located in the P-type shielding layer 3. The P-type shielding layer lead-out region is in ohmic contact with the front first electrode metal for forming the front first electrode above the SiC substrate, and the P-type shielding layer 3 is electrically connected to the front first electrode metal through the P-type shielding layer lead-out region, effectively avoiding the problems of turning on the parasitic device formed based on the P-type shielding 3 and abnormal increase in device loss.

[0077] Furthermore, the P-type shielding layer lead-out region includes a P-type first shielding layer lead-out region 43 and a P-type second shielding layer lead-out region 44, wherein:

[0078] The P-type first shielding layer lead-out region 43 and the P-type second shielding layer lead-out region 44 are both located in the SiC substrate;

[0079] The P-type first shielding layer lead-out region 43 is located below the P-type second shielding layer lead-out region 44 and contacts the P-type second shielding layer lead-out region 44;

[0080] In the direction from the active area to the terminal area, the width of the P-type first shielding layer lead-out area 43 is smaller than the width of the P-type second shielding layer lead-out area 44;

[0081] The P-type first shielding layer lead-out region 43 contacts the P-type shielding layer 3 .

[0082] Specifically, the P-type first shielding layer lead-out region 43 and the P-type second shielding layer lead-out region 44 are both located in the N-type drift region 2 in the SiC substrate, and the P-type second shielding layer lead-out region 44 is isolated from the P-type shielding layer 3 by the N-type drift region 2. The P-type first shielding layer lead-out region 43 and the P-type second shielding layer lead-out region 44 are both in ohmic contact with the front first electrode metal for forming the front first electrode above the SiC substrate.

[0083] Furthermore, the shielding layer lead-out unit further includes a shielding layer lead-out groove, and the P-type shielding layer lead-out region is formed in the SiC substrate based on the shielding layer lead-out groove, wherein:

[0084] The shielding layer lead-out groove is disposed between adjacent groove-type cells, and includes a first sub-groove 41 and a second sub-groove 42, wherein:

[0085] The groove width of the first sub-groove 41 is smaller than that of the second sub-groove 42 . The first sub-groove 41 is located below the second sub-groove 42 , and the groove opening of the first sub-groove 41 is connected to the groove bottom of the second sub-groove 42 .

[0086] Specifically, in order to effectively control the injection depth of the P-type shielding layer lead-out region in the N-type drift region 2 and avoid problems such as long-term reliability degradation of the device caused by excessive injection depth of the P-type shielding layer lead-out region, a shielding layer lead-out groove is set between adjacent trench-type cells, and the shielding layer lead-out groove is used to inject P-type impurities into the N-type drift region 2 of the SiC substrate to form a P-type shielding layer lead-out region.

[0087] Preferably, when the P-type shielding layer lead-out region includes a P-type first shielding layer lead-out region 43 and a P-type second shielding layer lead-out region 44, the shielding layer lead-out groove adopts a double-stage stepped groove, that is, the shielding layer lead-out groove includes a first sub-groove 41 and a second sub-groove 42. Figure 1 As shown, the first sub-groove 41 is located below the second sub-groove 42, and the groove width of the first sub-groove 41 is smaller than the groove width of the second sub-groove 42, the groove opening of the first sub-groove 41 is connected to the groove bottom of the second sub-groove 42, and a groove step can be formed at the connection between the groove opening of the first sub-groove 41 and the groove bottom of the second sub-groove 42. At this time, P-type impurities are injected into the N-type drift region 2 of the SiC substrate by the shielding layer lead-out groove, and a P-type shielding layer lead-out region shaped like a step-type groove can be formed accordingly, namely the above-mentioned P-type first shielding layer lead-out region 43 and the P-type second shielding layer lead-out region 44.

[0088] The bottom of the first sub-groove 41 is located in the N-type drift region 2 above the P-type shielding layer 3. Since the width of the first sub-groove 41 is small, the diffusion range of the P-type first shielding layer lead-out region 43 formed by ion implantation from the first sub-groove 41 to the N-type drift region 2 is small, thereby further controlling the implantation depth of the P-type shielding layer lead-out region. In addition, the stepped shielding layer lead-out groove can also optimize the electric field distribution at the shielding layer lead-out groove, further improving the withstand voltage capability of the power device.

[0089] Furthermore, the trench gate unit comprises a cell trench 6, a gate oxide layer 7 formed on the inner wall of the cell trench 6, and a gate electrode body 8 filled in the cell trench 6, wherein:

[0090] The gate electrode body 8 is insulated and isolated from the inner wall of the cell trench 6 by the gate oxide layer 7, and the gate electrode body 8 is in ohmic contact with the front side of the SiC substrate to form a second electrode metal of the front side second electrode.

[0091] Specifically, the cell groove 6 has a width greater than the width of the first sub-groove 41, and the cell groove 6 extends vertically from the front side of the SiC substrate to the N-type drift region 2, the bottom of the cell groove 6 is located above the P-type shielding layer 3, the gate oxide layer 7 covers the inner wall of the cell groove 6, and the gate electrode body 8 is insulated and isolated from the inner wall of the cell groove 6 by the gate oxide layer 7. When the power device is reversely turned off, the P-type shielding layer 3 is used to shield the electric field at the trench gate unit, which specifically means that when the power device is reversely turned off, the electric field strength loaded to the N-type doping region 5 is reduced by the pressure-bearing effect of the P-type shielding layer 3 located on both sides of the N-type doping region 5, thereby reducing the voltage borne by the gate oxide layer 7 in the trench gate unit, and avoiding the gate oxide layer 7 from being broken down and affecting the normal operation of the device. Optionally, the material of the gate electrode body 8 can be selected from metal or polysilicon. In specific implementation, the material of the gate electrode body 8 can be selected according to actual needs.

[0092] Furthermore, the trench cell further includes an N-type doping region 5 located below the trench gate unit, wherein the

[0093] The trench gate unit, the P-type shielding layer 3 and the N-type doping region 5 are all located in the N-type drift region 2 in the SiC substrate;

[0094] The N-type doping region 5 penetrates the P-type shielding layer 3 and contacts the trench gate unit;

[0095] When the power device is forward-conducting, carriers flow from the N-type doped region 5 into the N-type drift region 2 .

[0096] Specifically, the doping concentration of the N-type doping region 5 is greater than the doping concentration of the N-type drift region 2, one end of the N-type doping region 5 contacts the gate oxide layer 7 located at the bottom of the cell trench 6, and the N-type doping region 5 vertically extends from the bottom of the cell trench 6 to the back of the SiC substrate in the N-type drift region 2, penetrating the P-type shielding layer 3. The side of the N-type doping region 5 contacts the N-type drift region 2 and the P-type shielding layer 3, and one end of the N-type doping region 5 close to the back of the SiC substrate contacts the N-type drift region 2 located below the P-type shielding layer 3. When the power device is forward-conducted, carriers flow into the N-type doping region 5 along the channel region formed at the edge of the gate oxide layer, and flow from the N-type doping region 5 into the N-type drift region 2 below the P-type shielding layer 3.

[0097] Preferably, along the direction from the active area to the terminal area, the width of the cell trench 6 is greater than the width of the N-type doping area 5, so as to ensure the shielding effect of the P-type shielding layer 3 when the device is turned off.

[0098] Furthermore, P-type base regions 9 are disposed on both sides of the cell trench 6, and an N-type source region 10 is disposed in each P-type base region 9;

[0099] The P-type base region 9 and the N-type source region 10 are in contact with the corresponding outer side walls of the cell trench 6;

[0100] The junction depth of the N-type source region 10 is not greater than the junction depth of the P-type base region 9;

[0101] The P-type base region 9 and the N-type source region 10 are both in ohmic contact with the front first electrode metal.

[0102] Specifically, the P-type base region 9 and the N-type source region 10 are both located in the N-type drift region 2 above the P-type shielding layer 3, the P-type base region 9 vertically extends from the front of the SiC substrate to the N-type drift region 2, and the N-type source region 10 also vertically extends from the front of the SiC substrate to the N-type drift region 2. The junction depth of the N-type source region 10 is less than or equal to the junction depth of the P-type base region 9, and the junction depth of the P-type base region 9 is less than the groove depth of the cell trench 6. In general, the doping concentration of the N-type source region 10 is greater than the doping concentration of the N-type drift region 2, and the doping concentration of the P-type base region 9 is less than the doping concentration of the P-type shielding layer lead-out region.

[0103] One side of the cell trench 6 is defined as the first side, and the other side opposite to the first side is defined as the second side. The P-type base region 9 and the N-type source region 10 are in contact with the corresponding outer side walls of the cell trench 6, that is, the P-type base region 9 and the N-type source region 10 located on the first side of the cell trench 6 are in contact with the outer side wall of the first side of the cell trench 6, and the P-type base region 9 and the N-type source region 10 located on the second side of the cell trench 6 are in contact with the outer side wall of the second side of the cell trench 6.

[0104] For the above-mentioned high withstand voltage trench SiC power device, the present invention provides a method for preparing the high withstand voltage trench SiC power device, and the method for preparing the high withstand voltage trench SiC power device comprises:

[0105] A SiC substrate having a first conductivity type is provided, and a front cell process is performed on the front surface of the SiC substrate, wherein:

[0106] When performing a front cell process on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, and a plurality of trench cells connected in parallel are prepared in the active area, as well as a second conductive type shielding layer that traverses the active area;

[0107] For any trench type cell, it includes a trench gate unit located above the P-type shielding layer 3, and the trench gate unit is isolated from the P-type shielding layer 3;

[0108] The P-type shielding layer 3 is electrically connected to the front first electrode metal on the SiC substrate for forming the front first electrode;

[0109] The front first electrode metal is insulated and isolated from the trench gate unit;

[0110] When the power device is turned off in reverse direction, the P-type shielding layer 3 is used to shield the electric field at the trench gate unit.

[0111] Specifically, the front cell process includes preparing a shielding layer lead-out unit in the active area;

[0112] When preparing the shielding layer lead-out unit, a preliminary groove 14 is etched between adjacent groove-type cells;

[0113] The preliminary groove 14 is etched twice to obtain a first sub-groove 41, and a second sub-groove 42 is obtained above the first sub-groove 41, wherein the groove width of the first sub-groove 41 is smaller than the groove width of the second sub-groove 42, and the groove opening of the first sub-groove 41 is connected to the groove bottom of the second sub-groove 42;

[0114] Ion implantation is performed into the SiC substrate through the first sub-groove 41 and the second sub-groove 42 to prepare a P-type shielding layer lead-out region, wherein the P-type shielding layer lead-out region is in contact with the P-type shielding layer 3;

[0115] Metal deposition is performed on the front side of the SiC substrate to obtain at least a front first electrode metal after the metal deposition, and the front first electrode metal is in ohmic contact with the P-type shielding layer lead-out region.

[0116] In one embodiment of the present invention, before preparing the preliminary groove 14, a first oxide layer 13 is first deposited on the front side of the SiC substrate, and the first oxide layer 13 and the front side of the SiC substrate are etched to prepare the preliminary groove 14 on the front side of the SiC substrate. Moreover, while preparing the preliminary groove 14, a cellular groove 6 is prepared in the groove-type cell, and the groove depth of the preliminary groove 14 is smaller than the groove depth of the cellular groove 6, and the groove width of the preliminary groove 14 is smaller than the groove width of the cellular groove 6. At the same time, the groove depth of the preliminary groove 14 is also smaller than the groove depth of the first sub-groove 41 and the second sub-groove 42. The purpose of preparing the preliminary groove 14 is to form the above-mentioned stepped shielding layer lead-out groove on the basis of the preliminary groove 14. When the P-type impurities are injected into the SiC substrate using the groove steps formed by the stepped groove, the loss of invalid conductive area caused by the P-type impurity injection for leading out the P-type shielding layer 3 can be fully reduced. At the same time, metal can also be deposited in the stepped groove, thereby facilitating the lead-out of the connection potential of the P-type shielding layer 3.

[0117] Furthermore, before the secondary etching of the prepared trench 14, a sidewall covering the sidewall of the cell trench 6 is prepared in the cell trench 6, and the N-type doping region 5 is prepared below the cell trench 6 by using the sidewall;

[0118] The N-type doping region 5 penetrates the P-type shielding layer 3 and contacts the bottom of the cell trench 6;

[0119] In the direction from the active region to the terminal region, the width of the cell trench 6 is greater than the width of the N-type doping region 5 .

[0120] In one embodiment of the present invention, oxide is first filled in the cell trench 6, and then the filled oxide is etched to form a sidewall on the sidewall of the cell trench 6, the sidewall covers the inner sidewall of the cell trench 6 and part of the bottom of the cell trench 6, the bottom of the cell trench 6 not covered by the sidewall is used as an injection window for N-type impurities, and the injection window is used to inject N-type impurities into the N-type drift region 2 and the P-type shielding layer 3 to form an N-type doped region 5. Since the sidewall covers part of the bottom of the cell trench 6, the length of the injection window formed by the sidewall is smaller than the width of the cell trench 6, so the width of the N-type doped region 5 formed by the injection window is smaller than the width of the cell trench 6 in the direction from the active region to the terminal region.

[0121] Furthermore, the method for preparing the high-voltage trench SiC power device also includes performing a back side process on the back side of the SiC substrate. Depending on the back side process, a MOSFET type device or an IGBT type device can be formed. Generally, the front side cell process is performed first and then the back side cell process.

[0122] Figure 2-Figure 7 Taking MOSFET type device as an example, an embodiment of the process steps for preparing the above-mentioned high withstand voltage trench SiC power device is shown. Figure 2-Figure 7 The process of specific process steps is described in detail.

[0123] like Figure 2 As shown, a SiC substrate is provided, the SiC substrate includes an N-type substrate 1 and an N-type drift region 2 disposed on the N-type substrate 1, P-type impurities are implanted in the N-type drift region 2 of the SiC substrate to obtain a P-type shielding layer 3 that traverses the active region, and the doping concentration of the N-type drift region 2 is less than the doping concentration of the N-type substrate 1. Of course, the provided SiC substrate may also include only the N-type substrate 1. When the SiC substrate includes only the N-type substrate 1, a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer are sequentially formed on the N-type substrate 1, the P-type epitaxial layer is used as the P-type shielding layer 3, and the first N-type epitaxial layer and the second N-type epitaxial layer are used as the N-type drift region 2 traversed by the P-type shielding layer 3.

[0124] like Figure 3As shown, a P-type base region 9 is prepared in the N-type drift region 2 by ion implantation and high-temperature push-junction process, and the P-type base region 9 extends vertically downward from the front side of the SiC substrate. An N-type source region 10 is prepared in the above-mentioned P-type base region 9 by ion implantation and high-temperature push-junction process, and the junction depth of the N-type source region 10 is not greater than the junction depth of the P-type base region 9, and the doping concentration of the N-type source region 10 is greater than the doping concentration of the N-type drift region 2. In specific implementation, the process conditions of the ion implantation and high-temperature push-junction process can be selected according to actual needs, specifically to meet the preparation of the N-type source region 10 and the P-type base region 9.

[0125] A first oxide layer 13 of a preset thickness is deposited on the front of the SiC substrate, and the first oxide layer 13 and the front of the SiC substrate are etched, and a cell groove 6 is prepared in the groove-type cell, and a preliminary groove 14 is prepared between adjacent groove-type cells, wherein the groove depth of the preliminary groove 14 is less than the groove depth of the cell groove 6, and the groove width of the preliminary groove 14 is less than the groove width of the cell groove 6. The bottom of the cell groove 6 is located in the N-type drift region 2 above the P-type shielding layer 3, and the groove depth of the preliminary groove 14 is the same as the junction depth of the P-type base region 9. When etching the first oxide layer 13 and the front of the SiC substrate, a common process used by those skilled in the art, such as wet etching, etc., can be adopted. In specific implementation, the preset thickness of the first oxide layer 13 can be selected according to actual needs.

[0126] like Figure 4 As shown, oxide is deposited on the front side of the SiC substrate to fill the preliminary groove 14 and the cell groove 6, and the oxide filled in the cell groove 6 is etched to prepare an etched groove 15. The sidewall of the etched groove 15 does not contact the sidewall of the cell groove 6, the groove width of the etched groove 15 is smaller than the groove width of the cell groove 6, and the groove depth of the etched groove 15 is the same as the groove depth of the cell groove 6. The unetched oxide in the cell groove 6 is used to form a sidewall, that is, a first sidewall 151 is formed between the first outer sidewall of the etched groove 15 and the first inner sidewall of the cell groove, and a second sidewall 152 is formed between the second outer sidewall of the etched groove 15 and the second inner sidewall of the cell groove.

[0127] like Figure 5 As shown, the bottom of the cell trench 6 not covered by the first side wall 151 and the second side wall 152 is used as an injection window for N-type impurities, and the injection window is used to inject N-type impurities into the N-type drift region 2 and the P-type shielding layer 3 to form an N-type doping region 5. The N-type doping region 5 extends vertically from the bottom of the cell trench 6 to the back of the SiC substrate, penetrating the P-type shielding layer 3. The side of the N-type doping region 5 is in contact with the N-type drift region 2 and the P-type shielding layer 3, and one end of the N-type doping region 5 close to the back of the SiC substrate is in contact with the N-type drift region 2 located below the P-type shielding layer 3. The doping concentration of the N-type doping region 5 is greater than the doping concentration of the N-type drift region 2.

[0128] like Figure 6 As shown, after removing the first oxide layer 13 on the front side of the SiC substrate, oxide is deposited again on the front side of the SiC substrate, and the oxide fills the cell groove 6 and forms a second oxide layer 16 of a preset thickness on the front side of the SiC substrate. Etching is performed on the first oxide layer 16 and the front side of the SiC substrate to increase the depth of the preliminary groove 14, so as to prepare a first sub-groove 41 on the basis of the preliminary groove, and prepare a second sub-groove 42 above the first sub-groove 41, wherein the groove width of the first sub-groove 41 is smaller than the groove width of the second sub-groove 42, and the notch of the first sub-groove 41 is connected to the groove bottom of the second sub-groove 42.

[0129] P-type impurities are injected into the N-type drift region 2 through the first sub-groove 41 and the second sub-groove 42 to prepare a P-type shielding layer lead-out region, wherein the P-type shielding layer lead-out region includes a P-type first shielding layer lead-out region 43 and a P-type second shielding layer lead-out region 44. The end of the P-type first shielding layer lead-out region 43 away from the front of the SiC substrate contacts the P-type shielding layer 3, and the P-type second shielding layer lead-out region 44 contacts the P-type first shielding layer lead-out region 43, the P-type base region 9, and the N-type drift region 2 above the P-type shielding layer 3. The doping concentration of the P-type shielding layer lead-out region is greater than the doping concentration of the P-type shielding layer 3.

[0130] like Figure 7 As shown, the second oxide layer 16 on the front side of the SiC substrate is removed, and the oxide in the cell groove 6 is etched to a preset thickness to form a gate oxide layer 7. The gate electrode body 8 is filled in the cell groove 6 where the gate oxide layer 7 is formed, and the gate electrode body 8 is insulated and isolated from the inner wall of the cell groove 6 by the gate oxide layer 7. An insulating dielectric of a preset thickness is deposited on the front side of the SiC substrate and etched to prepare an insulating dielectric layer 11, which covers the notch of the cell groove 6 and partially overlaps with the N-type source region 10 distributed on both sides of the cell groove 6. The partial overlap between the insulating dielectric layer 11 and the N-type source region 10 specifically refers to the projection of the insulating dielectric layer 11 onto the N-type source region 10 distributed on both sides of the cell groove 6, and the projection of the insulating dielectric layer 11 overlaps with the N-type source region 10 on each side of the cell groove 6. In specific implementation, the material and thickness of the insulating dielectric layer 11 can be selected according to actual needs.

[0131] Metal is deposited on the front of the SiC substrate to form a front metal layer 13, and the front metal layer 13 includes a first electrode metal for forming a first electrode, and a second electrode metal for forming a second electrode. The first electrode metal is also deposited in the first sub-groove 41 and the second sub-groove 42, and the P-type shielding layer lead-out region is in ohmic contact with the first electrode metal through the first electrode metal deposited in the first sub-groove 41 and the second sub-groove 42, and the P-type shielding layer 3 is electrically connected to the first electrode metal through the P-type shielding layer lead-out region. The first electrode metal is in ohmic contact with the N-type source region 10 and the P-type base region 9 to form a first electrode. The second electrode metal is in ohmic contact with the gate electrode body 8 to form a second electrode.

[0132] A backside process is performed on the backside of the SiC substrate, that is, a backside metal layer is deposited on the backside of the SiC substrate. The backside metal layer includes a third electrode metal for forming a third electrode. The third electrode metal is in ohmic contact with the N-type substrate 1 .

[0133] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A high withstand voltage trench SiC power device, characterized in that: It comprises a first conductive type SiC substrate and an active area arranged in the central area of ​​the SiC substrate, wherein the active area comprises a second conductive type shielding layer traversing the active area and a plurality of trench-type cells distributed in parallel; for any trench-type cell, it comprises a trench gate unit located above the second conductive type shielding layer, wherein the trench gate unit is isolated from the second conductive type shielding layer; the second conductive type shielding layer is electrically connected to a front first electrode metal for forming a front first electrode above the SiC substrate; the front first electrode metal is insulated and isolated from the trench gate unit; when the power device is reversely turned off, the second conductive type shielding layer is used to shield the electric field at the trench gate unit; A shielding layer lead-out unit is provided between adjacent trench cells in the active area; the shielding layer lead-out unit includes a second conductive type shielding layer lead-out region, the second conductive type shielding layer lead-out region is in contact with the second conductive type shielding layer; the second conductive type shielding layer lead-out region is in ohmic contact with a front first electrode metal for forming a front first electrode above the SiC substrate; The second conductive type shielding layer lead-out region comprises a second conductive type first shielding layer lead-out region and a second conductive type second shielding layer lead-out region, wherein the second conductive type first shielding layer lead-out region and the second conductive type second shielding layer lead-out region are both located in the SiC substrate; the second conductive type first shielding layer lead-out region is located below the second conductive type second shielding layer lead-out region and contacts the second conductive type second shielding layer lead-out region; in a direction from the active region to the terminal region, a width of the second conductive type first shielding layer lead-out region is smaller than a width of the second conductive type second shielding layer lead-out region; the second conductive type first shielding layer lead-out region contacts the second conductive type shielding layer; The trench cell also includes a first conductive type doped region located below the trench gate unit, wherein the trench gate unit, the second conductive type shielding layer and the first conductive type doped region are all located in the first conductive type drift region in the SiC substrate, and the doping concentration of the first conductive type doped region is greater than the doping concentration of the first conductive type drift region; the first conductive type doped region penetrates the second conductive type shielding layer and contacts the trench gate unit; the trench gate unit and the second conductive type shielding layer are isolated by the first conductive type drift region above the second conductive type shielding layer; when the power device is forward-conducted, carriers flow from the first conductive type doped region into the first conductive type drift region.

2. The high withstand voltage trench SiC power device according to claim 1, characterized in that: The shielding layer lead-out unit further includes a shielding layer lead-out groove, and the second conductive type shielding layer lead-out region is formed in the SiC substrate based on the shielding layer lead-out groove, wherein: The shielding layer lead-out groove is arranged between adjacent groove-type cells, and includes a first sub-groove and a second sub-groove, wherein: The groove width of the first sub-groove is smaller than the groove width of the second sub-groove. The first sub-groove is located below the second sub-groove, and the groove opening of the first sub-groove is connected to the groove bottom of the second sub-groove.

3. The high withstand voltage trench SiC power device according to claim 1, characterized in that: The trench gate unit comprises a cell trench, a gate oxide layer formed on the inner wall of the cell trench, and a gate electrode body filled in the cell trench, wherein: In the direction from the active area to the terminal area, the width of the cell trench is greater than the width of the first conductive type doping area; The gate electrode body is insulated and isolated from the inner wall of the cell trench by a gate oxide layer, and the gate electrode body is in ohmic contact with the front side of the SiC substrate to form a second electrode metal of the front side second electrode.

4. The high withstand voltage trench SiC power device according to claim 3, characterized in that: The second conductive type base regions are arranged on both sides of the cell trench, and the first conductive type source region is arranged in each second conductive type base region; The second conductive type base region and the first conductive type source region are in contact with corresponding outer side walls of the cell trench; The junction depth of the first conductive type source region is not greater than the junction depth of the second conductive type base region; The second conductive type base region and the first conductive type source region are both in ohmic contact with the front first electrode metal.

5. A method for preparing a high withstand voltage trench SiC power device, characterized in that: For preparing a power device according to any one of claims 1 to 4, the method for preparing the trench SiC power device comprises: A SiC substrate having a first conductivity type is provided, and a front cell process is performed on the front surface of the SiC substrate, wherein: When performing a front cell process on the front side of the SiC substrate, an active area is prepared in the central area of ​​the SiC substrate, and a plurality of trench cells connected in parallel are prepared in the active area, as well as a second conductive type shielding layer that traverses the active area; For any trench type cell, a trench gate unit is included which is located above the second conductive type shielding layer, and the trench gate unit is isolated from the second conductive type shielding layer; The second conductive type shielding layer is electrically connected to the front first electrode metal for forming the front first electrode above the SiC substrate; The front first electrode metal is insulated and isolated from the trench gate unit; When the power device is turned off in reverse, the second conductive type shielding layer is used to shield the electric field at the trench gate unit.

6. The method for preparing a high withstand voltage trench SiC power device according to claim 5, characterized in that: The front cell process includes preparing a shielding layer lead-out unit in the active area; When preparing the shielding layer lead-out unit, a preliminary groove is obtained by etching between adjacent groove-type cells; Performing secondary etching on the prepared groove to prepare a first sub-groove, and preparing a second sub-groove above the first sub-groove, wherein the groove width of the first sub-groove is smaller than the groove width of the second sub-groove, and the groove opening of the first sub-groove is connected to the groove bottom of the second sub-groove; Performing ion implantation into the SiC substrate through the first sub-groove and the second sub-groove to prepare a second conductive type shielding layer lead-out region, wherein the second conductive type shielding layer lead-out region is in contact with the second conductive type shielding layer; Metal deposition is performed on the front side of the SiC substrate to obtain at least a front first electrode metal after the metal deposition, and the front first electrode metal is in ohmic contact with the second conductive type shielding layer lead-out region.

7. The method for preparing a high withstand voltage trench SiC power device according to claim 6, characterized in that: While preparing the preliminary groove, a cell groove is prepared in the groove-type cell; The groove depth of the cellular groove is greater than the groove depth of the preparatory groove, and the groove width of the cellular groove is greater than the groove width of the preparatory groove; Before performing secondary etching on the prepared groove, a side wall covering the side wall of the cell groove is prepared in the cell groove, and a first conductive type doping region is prepared below the cell groove by using the side wall; The first conductive type doping region penetrates the second conductive type shielding layer and contacts the bottom of the cell trench; In a direction from the active region to the terminal region, the width of the cell trench is greater than the width of the first conductive type doping region.

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