A DBC substrate and power module

Abstract

The present invention discloses a DBC substrate and a power module, which relates to the field of semiconductor packaging, and includes an insulator, wherein the insulator includes an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer; an upper connecting layer is prepared on the upper insulating layer, and a lower connecting layer is prepared on the lower insulating layer, and the upper connecting layer and / or the lower connecting layer are used to package a chip. Using the DBC substrate to package a power module can improve the power density and heat dissipation capacity of the power module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, in particular to a DBC substrate and a power module. Background Art

[0002] With the rapid development of social economy and the continuous advancement of technology and processes, emerging application fields such as new energy vehicles and charging piles, intelligent equipment manufacturing, the Internet of Things, new energy power generation, and rail transit have gradually become important application markets for power semiconductors, driving the rapid growth of demand for power semiconductors. At the same time, it also puts forward higher requirements for power modules such as low loss, high power density, high heat dissipation, and high reliability.

[0003] Existing power modules usually include a copper-clad ceramic board (DBC, Direct Bonding Copper) and a power chip encapsulated on the copper-clad ceramic board. The traditional copper-clad ceramic board includes a front side and a back side corresponding to the front side. Generally, the front side of the traditional copper-clad ceramic board is used to encapsulate the chip, and the back side is used to fix the copper-clad ceramic board to the external structure. This makes the power density of the traditional copper-clad ceramic board low and the heat dissipation path single, which seriously limits the power density and heat dissipation capacity of the power module. At the same time, it also causes the parasitic parameters such as parasitic resistance and parasitic inductance of the power module to be large, which increases the loss of the power module and affects the normal operation of the power chip. In summary, the existing copper-clad ceramic board structure cannot meet the requirements of high power density, high heat dissipation and high reliability of the power module. Summary of the invention

[0004] In view of the above problems and technical requirements, the inventors have proposed a DBC substrate and a power module. The technical solution of the present invention is as follows:

[0005] A DBC substrate comprises an insulator, wherein the insulator comprises an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer;

[0006] An upper connection layer is prepared on the upper insulating layer, and a lower connection layer is prepared on the lower insulating layer. The upper connection layer and / or the lower connection layer are used for packaging chips.

[0007] A further technical solution is that the DBC substrate further includes a connection structure, which surrounds the upper insulating layer and the lower insulating layer and is fixedly connected to the upper insulating layer and the lower insulating layer;

[0008] After the connection structure is fixedly connected to the upper insulating layer and the lower insulating layer, a cavity is formed between the upper insulating layer and the lower insulating layer, and the cavity is filled with a cooling medium.

[0009] A further technical solution is that the upper connection layer includes an upper first electrode region, and the lower connection layer includes a lower third electrode region, wherein:

[0010] The upper first electrode region penetrates the upper insulating layer and the lower insulating layer, and is connected to the lower third electrode region as a whole.

[0011] A further technical solution is that the upper connection layer further includes an upper second electrode region and an upper third electrode region, wherein the upper first electrode region, the upper second electrode region and the upper third electrode region are insulated and isolated by an upper insulating layer, and the upper first electrode region and the upper second electrode region are located at the same end of the upper connection layer;

[0012] The lower connection layer also includes a lower first electrode region and a lower second electrode region, wherein the lower first electrode region, the lower second electrode region and the lower third electrode region are insulated and isolated by a lower insulating layer, and the lower first electrode region and the lower second electrode region are located at the same end of the lower connection layer.

[0013] A further technical solution is that the upper first electrode region and the upper second electrode region overlap with the lower third electrode region;

[0014] The upper third electrode region overlaps with the lower first electrode region and the lower second electrode region, and the upper third electrode region partially overlaps with the lower third electrode region.

[0015] A further technical solution is that the area of ​​the third electrode region of the upper layer is larger than the area of ​​the first electrode region of the upper layer, and the area of ​​the first electrode region of the upper layer is larger than the area of ​​the second electrode region of the upper layer;

[0016] And / or the area of ​​the lower third electrode region is larger than the area of ​​the lower first electrode region, and the area of ​​the lower first electrode region is larger than the area of ​​the lower second electrode region.

[0017] A further technical solution is that the upper insulating layer is provided with a first through hole and a second through hole communicating with the cavity;

[0018] When the cooling medium is a cooling liquid, the cooling medium is injected into the cavity from the first through hole and / or the second through hole, and the cooling medium is stationary in the cavity or flows from the first through hole to the second through hole in the cavity.

[0019] A power module, characterized by comprising the above-mentioned DBC substrate, and an upper chip group and a lower chip group arranged on the DBC substrate, wherein the upper chip group is electrically connected to the lower chip group.

[0020] A further technical solution is that the upper chip set and the lower chip set both include a plurality of chips, wherein:

[0021] The welding surface of the chip in the upper chip group is welded to the upper third electrode area of ​​the connection layer on the DBC substrate by solder;

[0022] The welding surfaces of the chips in the lower chip group are welded to the lower third electrode area of ​​the lower connection layer of the DBC substrate through solder.

[0023] A further technical solution thereof is that it also includes an upper signal terminal group and a lower signal terminal group, wherein:

[0024] The upper signal terminal group includes an upper first signal terminal welded to the upper first electrode area, an upper second signal terminal welded to the upper second electrode area, a module power positive power terminal welded to the upper third electrode area, and a module power output terminal welded to the upper third electrode area;

[0025] The lower signal terminal group includes a lower first signal terminal welded to the lower first electrode region, a lower second signal terminal welded to the lower second electrode region, and a module power supply negative power terminal welded to the lower first electrode region.

[0026] The beneficial technical effects of the present invention are:

[0027] The DBC substrate provided by the present invention includes an upper connection layer prepared on an upper insulating layer and a lower connection layer prepared on a lower insulating layer. When the DBC substrate is used to encapsulate a power module, both the upper connection layer and the lower connection layer can encapsulate power chips, thereby improving the power density of the power module. At the same time, a heat sink can be installed on all four sides of the power module, thereby improving the heat dissipation capacity of the power module. In addition, the DBC substrate provided by the present invention is also provided with a cavity filled with a cooling medium between the upper insulating layer and the lower insulating layer, thereby further increasing the heat dissipation path of the DBC substrate, thereby ensuring that the power module works normally under high power density.

[0028] In addition, the DBC substrate provided by the present invention connects the upper first electrode area in the upper connection layer and the lower third electrode area in the lower connection layer into one, omitting the bonding wire connecting the upper first electrode area and the lower third electrode area, thereby reducing the parasitic resistance and parasitic inductance of the power module formed by packaging using the DBC substrate, so that the power module has lower loss while reducing the packaging cost, and improving the packaging yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a front schematic diagram of an embodiment of a DBC substrate provided by the present invention.

[0030] Figure 2 It is a schematic back view of an embodiment of a DBC substrate provided by the present invention.

[0031] Figure 3 It is a cross-sectional view of a DBC substrate at AA' in an embodiment provided by the present invention.

[0032] Figure 4 It is a cross-sectional view of a DBC substrate at BB' in an embodiment provided by the present invention.

[0033] Figure 5 It is a cross-sectional view of a DBC substrate at CC' in an embodiment provided by the present invention.

[0034] Figure 6 It is a front schematic diagram of an embodiment of a power module provided by the present invention.

[0035] Figure 7 It is a schematic back view of an embodiment of a power module provided by the present invention.

[0036] Figure markings: 1-upper IGBT chip, 2-upper FRD chip, 3-first connecting strip, 4-second connecting strip, 5-first connecting line, 6-lower first signal terminal, 7-module power positive power terminal, 8-lower second signal terminal, 9-upper first signal terminal, 10-connection structure, 11-module power output terminal, 12-upper second signal terminal, 13-outer copper frame, 14-module power negative power terminal, 15-lower IGBT chip, 16-lower FRD chip, 17-third connecting strip, 18-fourth connecting strip, 19-second connecting line, 101-upper insulating layer, 102-lower insulating layer, 111-upper first electrode area, 112-upper second electrode area, 113-upper third electrode area, 121-lower first electrode area, 122-lower second electrode area, 123-lower third electrode area, 131-first through hole, 132-second through hole. DETAILED DESCRIPTION

[0037] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0038] In order to improve the power density and heat dissipation capacity of the DBC substrate, the present invention proposes a DBC substrate, comprising an insulator, wherein the insulator comprises an upper insulating layer 101 and a lower insulating layer 102 corresponding to the upper insulating layer 101;

[0039] An upper connection layer is prepared on the upper insulating layer 101 , and a lower connection layer is prepared on the lower insulating layer 102 . The upper connection layer and / or the lower connection layer are used to package chips.

[0040] like Figure 1 and Figure 2As shown, the DBC substrate provided by the present invention includes a front side and a back side corresponding to the front side. Optionally, the upper insulating layer 101 and the upper connection layer prepared on the upper insulating layer 101 correspond to the front side of the DBC substrate. In this case, the lower insulating layer 102 and the lower connection layer prepared on the lower insulating layer 102 correspond to the back side of the DBC substrate. The upper insulating layer 101 corresponds to the lower insulating layer 102. Preferably, the upper insulating layer 101 and the lower insulating layer 102 are completely overlapped, that is, when projecting from the upper insulating layer 101 to the lower insulating layer 102, the projection of the upper insulating layer 101 and the projection of the lower insulating layer 102 are completely overlapped. Generally, the area of ​​the upper connection layer is not larger than the area of ​​the upper insulating layer 101, and the area of ​​the lower connection layer is not larger than the area of ​​the lower insulating layer 102. Specifically, the upper connection layer can be prepared on the upper insulating layer 101 and the lower connection layer can be prepared on the lower insulating layer 102 by using the common process in the DBC preparation process, which will not be repeated here.

[0041] Optionally, the material of the upper insulating layer 101 and the lower insulating layer 102 may be Al2O3, AlN, Si3N4, etc. The material of the upper connection layer and the lower connection layer may be Cu. In specific implementation, the materials of the upper insulating layer 101, the lower insulating layer 102, the upper connection layer, and the lower connection layer may be selected according to actual needs.

[0042] Preferably, the front and back sides of the DBC substrate are used to package power chips at the same time, that is, the upper connection layer and the lower connection layer are used to package power chips at the same time, and the specific method of packaging chips in the upper connection layer and the lower connection layer can refer to the following description. Compared with the traditional DBC that can only package chips on one side, the DBC substrate provided by the present invention can package more chips in the same area, thereby improving the power density of the power module formed after packaging.

[0043] Furthermore, the DBC substrate further includes a connection structure 10, which surrounds the upper insulating layer 101 and the lower insulating layer 102 and is fixedly connected to the upper insulating layer 101 and the lower insulating layer 102;

[0044] After the connection structure is fixedly connected to the upper insulating layer and the lower insulating layer, a cavity 100 is formed between the upper insulating layer 101 and the lower insulating layer 102 , and the cavity 100 is filled with a cooling medium.

[0045] As can be seen from the background technology, in a traditional DBC, the DBC is fixed to an external structure through a connection layer on the back of the DBC. However, since the front and back of the DBC substrate provided in the present invention are both used to package chips, the DBC cannot be fixed to an external structure using the back of the DBC. Therefore, the connection structure 10 is arranged around the DBC substrate, that is, around the upper insulating layer 101 and the lower insulating layer 102, and the DBC substrate is fixed to the external structure using the connection structure 10. In a specific implementation, the material of the connection structure 10 can be selected from Cu. Different from the traditional power module that can only install a heat sink on one side, when a power module is formed based on the DBC substrate provided by the present invention, a heat sink can be installed on all four sides of the power module. Adequate heat dissipation of the power module can be achieved through multiple heat sinks, thereby improving the heat dissipation capacity of the power module. The manner of forming a power module based on the DBC substrate provided by the present invention, as well as the specific form of installing a heat sink on the four sides of the power module can refer to the following description.

[0046] In order to further improve the heat dissipation capacity of the DBC substrate, a cooling medium is built into the DBC substrate, that is, a cavity 100 is formed between the upper insulating layer 101 and the lower insulating layer 102, and a cooling medium is filled in the cavity 100, and the cooling medium may be a coolant. By building a cooling medium into the DBC substrate, the heat dissipation path of the DBC substrate can be increased, thereby improving the heat dissipation performance of the DBC substrate. When the DBC substrate is used to form a power module, the normal operation of the power module under high frequency and high power density can be guaranteed.

[0047] In order to increase the contact area between the cooling medium and the upper insulating layer 101 and the lower insulating layer 102, in one embodiment of the present invention, the upper insulating layer 101 is isolated from the lower insulating layer 102 to form a gap of a preset thickness, and the cavity 100 is formed by surrounding the gap with the connection structure 10. Figure 4 As shown, at this time, the cooling medium in the cavity 100 can cover the side of the upper insulating layer 101 away from the upper connecting layer, and the side of the lower insulating layer 102 away from the lower connecting layer. The cooling medium has a large contact area with the upper insulating layer 101 and the lower insulating layer 102, which improves the heat exchange efficiency, thereby improving the heat dissipation performance of the DBC substrate.

[0048] Furthermore, the upper insulating layer 101 is provided with a first through hole 131 and a second through hole 132 communicating with the cavity 100;

[0049] When the cooling medium is a cooling liquid, the cooling medium is injected into the cavity 100 through the first through hole 131 and / or the second through hole 132 , and the cooling medium is stationary in the cavity 100 or flows from the first through hole 131 to the second through hole 132 in the cavity 100 .

[0050] like Figure 1As shown, in this embodiment, the first through hole 131 and the second through hole 132 are respectively arranged on the upper insulating layer 101 on both sides of the upper connection layer, and the centers of the first through hole 131 and the second through hole 132 are both located on the central axis of the length direction of the DBC substrate. Figure 3 FIG. 4 shows a cross-sectional view of the DBC substrate along the longitudinal center axis, that is, a cross-sectional view of the DBC substrate at AA'. Figure 3 As shown, the first through hole 131 and the second through hole 132 vertically extend from the surface of the upper insulating layer 101 to the cavity 100 and communicate with the cavity 100 .

[0051] Preferably, when the cooling medium is a coolant, the first through hole 131 is used as a liquid inlet hole, and the second through hole 132 is used as a liquid outlet hole, so that the cooling medium flows from the first through hole 131 to the second through hole 132 in the cavity 100. The flowing coolant can more efficiently take away the heat dissipated by the power chip packaged on the DBC substrate, so that the packaged power module has better heat dissipation and cooling performance, thereby being suitable for the application of power modules with higher power requirements.

[0052] Furthermore, the upper connection layer includes an upper first electrode region 111, and the lower connection layer includes a lower third electrode region 123, wherein:

[0053] The upper first electrode region 111 penetrates the upper insulating layer 101 and the lower insulating layer 102 , and is connected to the lower third electrode region 123 as a whole.

[0054] Specifically, Figure 1 As shown, the upper connection layer is divided into an upper first electrode region 111, an upper second electrode region 112 and an upper third electrode region 113, and the upper first electrode region 111, the upper second electrode region 112 and the upper third electrode region 113 are insulated and isolated by an upper insulating layer 101. Figure 2 As shown, the lower connection layer is divided into a lower first electrode region 121 , a lower second electrode region 122 and a lower third electrode region 123 , and the lower first electrode region 121 , the lower second electrode region 122 and the lower third electrode region 123 are insulated and isolated by the lower insulating layer 102 .

[0055] like Figure 3 and Figure 5As shown, when a cavity 100 is provided between the upper insulating layer 101 and the lower insulating layer 102, the upper first electrode region 111 penetrates the upper insulating layer 101, the cavity 100 and the lower insulating layer 102, and is connected to the lower third electrode region 123 as a whole. When the upper first electrode region 111 and the lower third electrode region 123 are connected as a whole and the power module is formed using the DBC substrate, the bonding wire connecting the upper first electrode region 111 and the lower third electrode region 123 can be omitted, and the parasitic resistance and parasitic inductance of the power module can be reduced, so that the power module has lower loss while reducing the packaging cost. At the same time, the problem of the bonding wire connecting the upper first electrode region 111 and the lower third electrode region 123 breaking and failing is avoided, and the packaging yield and reliability of the power module are improved.

[0056] Furthermore, the upper first electrode region 111 and the upper second electrode region 112 overlap with the lower third electrode region 123;

[0057] The upper third electrode region 113 overlaps with the lower first electrode region 121 and the lower second electrode region 122 , and the upper third electrode region 113 partially overlaps with the lower third electrode region 123 .

[0058] like Figure 1 As shown, the DBC substrate is rectangular as a whole, and the upper first electrode area 111, the upper second electrode area 112 and the upper third electrode area 113 in the upper connection layer are also rectangular, and the upper first electrode area 111 and the upper second electrode area 112 are located at the same end. The end where the upper third electrode area 113 is located is used as the first end of the DBC substrate, and the end where the upper first electrode area 111 and the upper second electrode area 112 are located is used as the second end of the DBC substrate.

[0059] like Figure 2 As shown, the lower first electrode region 121, the lower second electrode region 122 and the lower third electrode region 123 in the lower connection layer are all rectangular, and the lower first electrode region 121 and the lower second electrode region 122 are both located at the first end of the DBC substrate, and the lower third electrode region 123 is located at the second end of the DBC substrate.

[0060] like Figure 3 As shown, the upper first electrode region 111 and the upper second electrode region 112 overlap with the lower third electrode region 123, specifically, when the upper first electrode region 111 and the upper second electrode region 112 are projected onto the lower third electrode region 123, the projections of the upper first electrode region 111 and the upper second electrode region 112 overlap with the lower third electrode region 123. When the upper first electrode region 111 overlaps with the lower third electrode region 123, the upper first electrode region 111 extends vertically to the lower third electrode region 123 and is connected as a whole.

[0061] The upper third electrode area 113 overlaps with the lower first electrode area 121 and the lower second electrode area 122, and the upper third electrode area 113 partially overlaps with the lower third electrode area 123, specifically, when the upper third electrode area 113 is projected onto the lower first electrode area 121, the lower second electrode area 122 and the lower third electrode area 123, the projection of the upper third electrode area 113 overlaps with the lower first electrode area 121 and the lower second electrode area 122, and the projection of the upper third electrode area 113 partially overlaps with the lower third electrode area 123.

[0062] Further, the area of ​​the upper third electrode region 113 is greater than the area of ​​the upper first electrode region 111, and the area of ​​the upper first electrode region 111 is greater than the area of ​​the upper second electrode region 112;

[0063] And / or the area of ​​the lower third electrode region 123 is larger than the area of ​​the lower first electrode region 121 , and the area of ​​the lower first electrode region 121 is larger than the area of ​​the lower second electrode region 122 .

[0064] Specifically, when the DBC substrate package provided by the present invention is used to form a power module, the upper third electrode area 113 in the upper connection layer and the lower third electrode area 123 in the lower connection layer are used to package the chip. Therefore, preferably, the area of ​​the upper third electrode area 113 in the upper connection layer is larger than the areas of the upper first electrode area 111 and the upper second electrode area 112; and the area of ​​the lower third electrode area 123 in the lower connection layer is larger than the areas of the lower first electrode area 121 and the lower second electrode area 122, so as to facilitate chip packaging.

[0065] Furthermore, when the power module is formed by utilizing the above-mentioned DBC substrate package, the upper first electrode region 111 in the upper connection layer and the lower first electrode region 121 in the lower connection layer are required to connect more signal terminals. Therefore, in this embodiment, the area of ​​the upper first electrode region 111 is made larger than the area of ​​the upper second electrode region 112, and the area of ​​the lower first electrode region 121 is made larger than the area of ​​the lower second electrode region 122.

[0066] Preferably, to facilitate the preparation of the DBC substrate, the area of ​​the upper first electrode region 111 is equal to the area of ​​the lower first electrode region 121, the area of ​​the upper second electrode region 112 is equal to the area of ​​the lower second electrode region 122, and the area of ​​the upper third electrode region 113 is equal to the area of ​​the lower third electrode region 123. At the same time, the distribution of each electrode region in the upper connection layer and the lower connection layer is made centrally symmetrical, that is, each electrode region in the lower connection layer is rotated 180° with the center of the DBC substrate as the rotation center and then projected onto the upper connection layer, at which time the projections of the lower first electrode region 121, the lower second electrode region 122 and the lower third electrode region 123 in the lower connection layer overlap with the upper first electrode region 111, the upper second electrode region 112 and the upper third electrode region 113 in the upper connection layer, respectively.

[0067] The present invention further provides a power module, comprising the above-mentioned DBC substrate, and an upper chip group and a lower chip group arranged on the DBC substrate, wherein the upper chip group is electrically connected to the lower chip group.

[0068] Specifically, the power module is packaged using the above-mentioned DBC substrate. From the above description, it can be seen that the upper first electrode area 111 and the lower third electrode area 123 of the DBC substrate are connected as a whole, and the upper chip group is electrically connected to the lower third electrode area 123 through the upper first electrode area 111, thereby achieving electrical connection with the lower chip group.

[0069] Furthermore, the upper chip set and the lower chip set each include a plurality of chips, wherein:

[0070] The welding surface of the chip in the upper chip group is welded to the upper third electrode area 113 of the connection layer on the DBC substrate by solder;

[0071] The welding surfaces of the chips in the lower chip group are welded to the lower third electrode region 123 of the lower connection layer of the DBC substrate by solder.

[0072] Optionally, the solder includes but is not limited to Sn, Ag, etc. In specific implementation, the type, quantity and connection method of the chips in the upper chipset and the lower chipset can be determined according to the circuit topology of the required power module, and the material of the solder can also be selected according to actual needs.

[0073] In one embodiment of the present invention, the power module is a half-bridge module. Figure 6 and Figure 7 , taking a half-bridge module as an example, the structure of a power module formed by the above-mentioned DBC substrate package is described:

[0074] The circuit topology of the half-bridge module is consistent with the prior art and will not be described in detail here. When the power module is a half-bridge module, the upper chipset includes an upper IGBT chip 1 and an upper FRD chip 2 connected in anti-parallel with the upper IGBT chip 1, and the lower chipset includes a lower IGBT chip 15 and a lower FRD chip 16 connected in anti-parallel with the lower IGBT chip 15. Both the IGBT chip and the FRD chip include a front side and a back side corresponding to the front side. Generally, a collector is provided on the back side of the IGBT chip, and an emitter and a base are provided on the front side of the IGBT chip. A cathode is provided on the back side of the FRD chip, and an anode is provided on the front side of the FRD chip. In this embodiment, the back sides of the IGBT chip and the FRD chip are used as welding surfaces.

[0075] like Figure 6 As shown, the welding surfaces of the upper IGBT chip 1 and the upper FRD chip 2 are welded in parallel to the upper third electrode area 113 through solder, and the emitter of the upper IGBT chip 1 is connected to the anode of the upper FRD chip 2 through the first connecting strip 3. The emitter of the upper IGBT chip 1 is also connected to the upper first electrode area 111 through the second connecting strip 4, and the base of the upper IGBT chip 1 is connected to the upper second electrode area 112 through the first connecting wire 5.

[0076] like Figure 7 As shown, the welding surfaces of the lower IGBT chip 15 and the lower FRD chip 16 are welded in parallel to the lower third electrode area 123 through solder, and the emitter of the lower IGBT chip 15 is connected to the anode of the lower FRD chip 16 through the third connecting strip 17. The emitter of the lower IGBT chip 15 is also connected to the lower first electrode area 121 through the fourth connecting strip 18, and the base of the lower IGBT chip 15 is connected to the lower second electrode area 122 through the second connecting wire 19. Since the upper first electrode area 111 and the lower third electrode area 123 are connected as one, the emitter of the upper IGBT chip 1 is connected to the collector of the lower IGBT chip 15. The materials of the first connecting strip 3, the second connecting strip 4, the first connecting wire 5, the third connecting strip 17, the fourth connecting strip 18 and the second connecting wire 19 can all be Cu.

[0077] Furthermore, the power module further comprises an upper signal terminal group and a lower signal terminal group, wherein:

[0078] The upper signal terminal group includes an upper first signal terminal 9 welded to the upper first electrode area 111, an upper second signal terminal 12 welded to the upper second electrode area 112, a module power positive power terminal 7 welded to the upper third electrode area 113, and a module power output terminal 11 welded to the upper third electrode area 113;

[0079] The lower signal terminal group includes a lower first signal terminal 6 welded to the lower first electrode region 121 , a lower second signal terminal 8 welded to the lower second electrode region 122 , and a module power negative power terminal 14 welded to the lower first electrode region 121 .

[0080] From the above description, it can be seen that during the packaging of the traditional DBC, the DBC is fixed to the external structure through the connection layer on the back of the DBC. Generally, the external structure mostly uses a copper substrate, which can provide mechanical support and a thermal conduction path for the DBC. At the same time, a heat sink can be provided on the side of the copper substrate where the DBC is not fixed to further dissipate heat for the DBC.

[0081] However, since both the front and back sides of the DBC substrate provided by the present invention are used to package chips, a connection structure 10 is required to replace the connection layer on the back side of the traditional DBC to fix the DBC to the external structure. In order to adapt to the connection structure 10, in one embodiment of the present invention, the external structure adopts an outer copper frame 13 that surrounds and is fixed to the outside of the connection structure 10. The outer copper frame 13 is used to replace the copper substrate in the traditional DBC package to provide mechanical support and a heat conduction path for the DBC substrate. In addition, compared with a copper substrate that can only be provided with a heat sink on one side, the four outer sides of the outer copper frame 13 can be installed with a heat sink, which can further improve the heat dissipation capacity of the DBC substrate.

[0082] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front", "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0083] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A DBC substrate, characterized in that: An insulator is included, wherein the insulator includes an upper insulating layer and a lower insulating layer corresponding to the upper insulating layer; An upper connection layer is prepared on the upper insulating layer, and a lower connection layer is prepared on the lower insulating layer, and the upper connection layer and / or the lower connection layer are used for packaging chips; The DBC substrate further includes a connection structure, which surrounds the upper insulating layer and the lower insulating layer and is fixedly connected to the upper insulating layer and the lower insulating layer; After the connection structure is fixedly connected to the upper insulating layer and the lower insulating layer, a cavity is formed between the upper insulating layer and the lower insulating layer, and the cavity is filled with a cooling medium; The DBC substrate is fixed to an external structure using the connection structure, wherein the external structure includes an outer copper frame surrounding and fixed to the outside of the connection structure; The upper connection layer includes an upper first electrode region, and the lower connection layer includes a lower third electrode region, wherein the upper first electrode region penetrates the upper insulating layer and the lower insulating layer and is connected to the lower third electrode region as a whole.

2. The DBC substrate according to claim 1, characterized in that: The upper connection layer further includes an upper second electrode region and an upper third electrode region, wherein the upper first electrode region, the upper second electrode region and the upper third electrode region are insulated and isolated by an upper insulating layer, and the upper first electrode region and the upper second electrode region are located at the same end of the upper connection layer; The lower connection layer also includes a lower first electrode region and a lower second electrode region, wherein the lower first electrode region, the lower second electrode region and the lower third electrode region are insulated and isolated by a lower insulating layer, and the lower first electrode region and the lower second electrode region are located at the same end of the lower connection layer.

3. The DBC substrate according to claim 2, characterized in that: The upper first electrode region and the upper second electrode region both overlap with the lower third electrode region; The upper third electrode region overlaps with the lower first electrode region and the lower second electrode region, and the upper third electrode region partially overlaps with the lower third electrode region.

4. The DBC substrate according to claim 3, characterized in that: The area of ​​the third electrode region of the upper layer is larger than the area of ​​the first electrode region of the upper layer, and the area of ​​the first electrode region of the upper layer is larger than the area of ​​the second electrode region of the upper layer; And / or the area of ​​the lower third electrode region is larger than the area of ​​the lower first electrode region, and the area of ​​the lower first electrode region is larger than the area of ​​the lower second electrode region.

5. The DBC substrate according to claim 1, characterized in that: The upper insulating layer is provided with a first through hole and a second through hole communicating with the cavity; When the cooling medium is a cooling liquid, the cooling medium is injected into the cavity from the first through hole and / or the second through hole, and the cooling medium is stationary in the cavity or flows from the first through hole to the second through hole in the cavity.

6. A power module, characterized in that: It comprises the DBC substrate according to any one of claims 1 to 5, and an upper chip group and a lower chip group arranged on the DBC substrate, wherein the upper chip group is electrically connected to the lower chip group.

7. The power module according to claim 6, characterized in that: The upper chip set and the lower chip set both include a plurality of chips, wherein: The welding surface of the chip in the upper chip group is welded to the upper third electrode area of ​​the connection layer on the DBC substrate by solder; The welding surfaces of the chips in the lower chip group are welded to the lower third electrode area of ​​the lower connection layer of the DBC substrate through solder.

8. The power module according to claim 7, characterized in that: It also includes an upper signal terminal group and a lower signal terminal group, wherein: The upper signal terminal group includes an upper first signal terminal welded to the upper first electrode area, an upper second signal terminal welded to the upper second electrode area, a module power positive power terminal welded to the upper third electrode area, and a module power output terminal welded to the upper third electrode area; The lower signal terminal group includes a lower first signal terminal welded to the lower first electrode region, a lower second signal terminal welded to the lower second electrode region, and a module power supply negative power terminal welded to the lower first electrode region.

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