Coding method, device and equipment for controlling memristor array

Abstract

The present invention relates to the field of storage and computing technology, and discloses a coding method, device and equipment for controlling a memristor array, the method comprising: applying an initial stable voltage to the memristor array; performing a read operation on the memristor array based on the initial stable voltage to determine the initial resistance value of the memristor array; determining the excitation behavior of the memristor array based on the initial resistance value and calculation parameters; generating a coding protocol packet according to the excitation behavior; sending the coding protocol packet to a field programmable gate array FPGA connected to the memristor array, and controlling the memristor array through the FPGA. The present invention solves the problems of low efficiency, insufficient precision, poor stability, etc. in the traditional method of controlling a memristor array.

Description

Technical Field

[0001] The present invention relates to the field of storage and computing technology, and in particular to a coding method, device and equipment for controlling a memristor array. Background Art

[0002] With the rapid development of information technology, the demand for data storage and computing has exploded. Although traditional memory and computing units, such as flash memory, hard disks, and central processing units, have been continuously optimized and improved, they are still inadequate when processing large-scale, highly complex data. In addition, these traditional devices often have high energy consumption and are difficult to integrate and miniaturize, which limits their application in certain specific scenarios.

[0003] In recent years, the emergence of a new type of electronic component, memristor, has brought revolutionary changes to the fields of storage and computing. Memristors have nonlinear resistance characteristics and state memory capabilities. Their resistance value can change according to the history of applied voltage or current and maintain this changed state. This feature makes memristors show great potential in storage and computing. By constructing a memristor array, high-density, low-power data storage and computing can be achieved.

[0004] However, despite the many advantages of memristor arrays, they still face some challenges in practical applications. One of the most important issues is how to achieve precise control of memristor arrays. Since the resistance value of a memristor is affected by many factors, such as the magnitude, timing, and frequency of the applied voltage, the signal applied to the memristor array must be precisely controlled to achieve accurate storage and reading of data. However, existing control methods often have problems such as insufficient precision and poor stability, which affects the accuracy of data storage and calculation.

[0005] In addition, as data processing tasks become increasingly complex, the performance requirements for memristor arrays are also getting higher and higher. How to improve computing speed and energy efficiency while ensuring accuracy has become a hot topic and difficulty in current research.

[0006] Therefore, developing a coding method and device that can achieve precise control of the memristor array has important theoretical significance and application value. Summary of the invention

[0007] The present invention provides a coding method, device and equipment for controlling a memristor array, which solves the problems of low efficiency, insufficient precision and poor stability in traditional methods for controlling a memristor array.

[0008] A coding method for controlling a memristor array, comprising:

[0009] applying an initial stable voltage to the memristor array;

[0010] Performing a read operation on the memristor array based on the initial stable voltage to determine an initial resistance value of the memristor array;

[0011] Determining a stimulus behavior for the memristor array based on the initial resistance value and the calculation parameter;

[0012] generating a coding protocol package according to the incentive behavior;

[0013] The encoding protocol packet is sent to a field programmable gate array FPGA connected to the memristor array, and the memristor array is controlled by the FPGA.

[0014] In one embodiment of the present invention, applying an initial stable voltage to the memristor array specifically includes: converting the type and characteristics of input information into a digital signal; mapping the digital signal into a corresponding initial stable voltage according to a preset conversion method; and applying the initial stable voltage to the memristor array.

[0015] In one embodiment of the present invention, the determination of the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters specifically includes: obtaining an initial stable voltage applied to the memristor array; applying a voltage pulse to the memristor array based on the initial stable voltage; determining a change in voltage on the memristor array by adjusting properties of the voltage pulse; the properties of the voltage pulse include amplitude, width, frequency, sequence and / or timing; based on the initial resistance value, determining a change in resistance of the memristor array according to a change in the voltage, thereby simulating different types of biological neural synaptic behaviors.

[0016] In one embodiment of the present invention, generating a coding protocol packet according to the incentive behavior specifically includes: generating a corresponding coding signal according to the incentive behavior; based on a preset coding protocol, determining a coding protocol packet according to the coding signal; wherein the coding protocol packet includes an uplink protocol packet and a downlink protocol packet.

[0017] In one embodiment of the present invention, the encoding protocol packet is sent to a field programmable gate array FPGA connected to a memristor array, and the memristor array is controlled through the FPGA, specifically including: sending the encoding protocol packet to the FPGA, the FPGA parsing the encoding protocol packet to obtain a digital signal for controlling the memristor array; converting the digital signal into an analog signal and sending it to the memristor array, thereby achieving control of the memristor array.

[0018] In one embodiment of the present invention, in the process of sending the encoded protocol packet to the FPGA, the host communicates through the Ethernet or PCIe interface on the FPGA; in the process of converting the digital signal into an analog signal and sending it to the memristor array, the FPGA communicates with the memristor array through a digital-to-analog converter DAC and an analog-to-digital converter ADC.

[0019] In one embodiment of the present invention, the uplink protocol packet includes an inference result packet; the downlink protocol packet includes an initialization packet, a training data packet, an erasure process packet, and an inference process packet; the encoding protocol in the encoding protocol packet includes: a packet flag, an X-axis selection of a memristor array, a Y-axis selection of a memristor array, a Burst burst length, a write selection of the X-axis is a pulse input or an amplitude, a write selection of the Y-axis is a pulse input or an amplitude, and a cyclic redundancy check CRC.

[0020] A coding device for controlling a memristor array, comprising:

[0021] An initialization module, used for applying an initial stable voltage to the memristor array; performing a read operation on the memristor array based on the initial stable voltage to determine an initial resistance value of the memristor array;

[0022] A behavior simulation module, used for determining the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters;

[0023] An encoding module, used to generate an encoding protocol package according to the incentive behavior;

[0024] The control module is used to send the encoding protocol packet to a field programmable gate array FPGA connected to the memristor array, and control the memristor array through the FPGA.

[0025] A coding device for controlling a memristor array, comprising:

[0026] at least one processor; and,

[0027] A memory connected to the at least one processor via a bus; wherein,

[0028] The memory stores instructions executable by the at least one processor, and the instructions are executed to implement the method described in any one of the above embodiments.

[0029] A non-volatile storage medium stores computer executable instructions, wherein the computer executable instructions are executed by a processor to implement the method described in any one of the above embodiments.

[0030] The present invention provides a coding method, device and equipment for controlling a memristor array, which at least includes the following beneficial effects: by accurately controlling the voltage, current and timing parameters applied to the memristor array, accurate storage and reading of data are achieved, which can not only improve the accuracy of data processing and avoid errors and distortions caused by insufficient control accuracy, but also optimize computing performance and improve the speed and efficiency of data processing. The control process of the memristor array is realized by downlinking the encoding protocol packet through the host, without the need for complex algorithm support, and has high practicality and scalability. By accurately controlling the signal parameters applied to the memristor array, unnecessary energy consumption can be reduced and the energy efficiency ratio can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0032] Figure 1 A schematic diagram of steps of an encoding method for controlling a memristor array provided by an embodiment of the present invention;

[0033] Figure 2 A memristor array encoding protocol provided by an embodiment of the present invention;

[0034] Figure 3 A conversion relationship diagram of an input digital signal and an input analog signal voltage provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the hardware connection of a memristor array provided in an embodiment of the present invention;

[0036] Figure 5 A flow chart of initializing a memristor array provided in an embodiment of the present invention;

[0037] Figure 6 A flow chart of memristor array training / erasing provided by an embodiment of the present invention;

[0038] Figure 7 A flow chart of reasoning for a single channel of a memristor array provided by an embodiment of the present invention;

[0039] Figure 8 A flow chart of continuous multi-channel reasoning of a memristor array provided by an embodiment of the present invention;

[0040] Fig. 9 A schematic diagram of an encoding device for controlling a memristor array provided by an embodiment of the present invention;

[0041] Fig.10 A schematic diagram of an encoding device for controlling a memristor array provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be described clearly and completely in conjunction with the specific embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that it is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present invention can be combined with other embodiments without conflict. Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be the usual meanings understood by people with ordinary skills in the technical field to which the present invention belongs. The words "one", "a", "a", "the" and the like involved in the present invention do not indicate a quantitative limitation and may represent the singular or plural. The terms "including", "comprising", "having" and any of their variations involved in the present invention are intended to cover non-exclusive inclusions; the terms "first", "second", "third", etc. involved in the present invention are merely to distinguish similar objects and do not represent a specific ordering of objects.

[0044] Some concepts involved in the present invention are explained below.

[0045] ADC (Analog-to-Digital Converter) is a device that converts continuous analog signals into discrete digital signals.

[0046] DAC (Digital-to-Analog Converter) is a device that converts discrete digital signals into continuous analog signals.

[0047] FPGA (Field Programmable Gate Array) is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0048] IO (Iuput / Output) is divided into two parts: IO device and IO interface. This article mainly refers to IO interface, which is a kind of connection method.

[0049] PCIe (Peripheral Component Interconnect Express) is a high-speed serial bus standard that is widely used for communication between components inside a computer.

[0050] CRC (Cyclic Redundancy Check), also known as polynomial code, works by generating a redundant code at the sending end, appending it to the information bit and sending it to the receiving end. The receiving end checks the information received by the sending end using the same algorithm as the cyclic redundancy code. If an error is found, the sending end is notified to resend.

[0051] Ethernet interface is a physical interface used to connect computer devices. It is a standardized technology and is usually used in Local Area Network (LAN). Ethernet interface usually uses RJ-45 jack connection to connect computers, routers, switches and other devices together through cables.

[0052] The present invention proposes a coding method, device and equipment for controlling a memristor array, and proposes a coding method based on precise control of a memristor array, aiming to solve the problems existing in the existing memristor array control method. The host communicates with an FPGA board embedded with a memristor array, and controls devices such as ADC and DAC connected through IO on the FPGA, thereby accurately controlling the voltage, current and timing parameters applied to the memristor array, realizing accurate storage and reading of data, and optimizing computing performance. The present invention not only helps to promote the further development of memristor array technology, but also provides new ideas and methods for solving large-scale, high-complexity data processing problems.

[0053] The specific instructions are given below.

[0054] The present invention is based on the design of an FPGA board with a memristor array embedded therein. Since the signals sent and received by the memristor array are both analog signals, and the input and output signals of the FPGA are both digital signals, the conversion between the input and output digital signals and analog signals is realized between the FPGA and the memristor array through ADC and DAC devices.

[0055] Figure 1 A schematic diagram of the steps of a coding method for controlling a memristor array provided by an embodiment of the present invention, Figure 1The coding method for controlling a memristor array shown can be executed by a coding device for controlling a memristor array, and the coding device for controlling a memristor array can be set on a server. For example, the server can be a physical server including an independent host, a virtual server carried by a host cluster, a cloud server, etc., which is not limited in the embodiment of the present invention. The coding method for controlling a memristor array can include the following steps:

[0056] S110: applying an initial stable voltage to the memristor array; and performing a read operation on the memristor array based on the initial stable voltage to determine an initial resistance value of the memristor array.

[0057] In one embodiment of the present invention, applying an initial stable voltage to the memristor array specifically includes: converting the type and characteristics of input information into a digital signal; mapping the digital signal into a corresponding initial stable voltage according to a preset conversion method; and applying the initial stable voltage to the memristor array.

[0058] Specifically, in order to determine the initial resistance value of the memristor array, a read operation can be performed on the memristor array in a stable voltage environment. The initial stable voltage varies according to the characteristics of the memristor array, and the initial stable voltage is used to provide an environment for subsequent training and reasoning operations of the memristor array.

[0059] In order to improve the mapping accuracy, it can be improved by refining the voltage control. First, upgrade the voltage control device and select a power supply device that can provide high-precision voltage output to ensure the accuracy of the output at the hardware level. At the same time, at the software level, add a fine adjustment function for the output voltage, such as improving the accuracy of the DAC to achieve a smaller voltage step. In this way, higher mapping accuracy can be achieved, thereby reducing errors and improving system performance.

[0060] By using high-performance voltage control equipment to ensure the accuracy and stability of voltage pulses, after applying a voltage pulse, the change in resistance can be determined based on the change in voltage on the memristor array, and the input information can be effectively mapped to the resistance of the memristor array, thereby simulating different types of biological neural synaptic behaviors.

[0061] S120: Determine the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters.

[0062] In one embodiment of the present invention, the excitation behavior of the memristor array is determined based on the initial resistance value and the calculation parameters, specifically including: obtaining an initial stable voltage applied to the memristor array; applying a voltage pulse to the memristor array based on the initial stable voltage; determining the change of the voltage on the memristor array by adjusting the properties of the voltage pulse; the properties of the voltage pulse include amplitude, width, frequency, sequence and / or timing; based on the initial resistance value, determining the change of the resistance value of the memristor array according to the change of the voltage, thereby simulating different types of biological neural synaptic behaviors.

[0063] Specifically, in the process of simulating synaptic behavior, the present invention uses a voltage pulse to stimulate the memristor array. A voltage pulse is a short-term voltage change. By adjusting the amplitude, width and frequency of the voltage pulse, different types of biological neural synaptic behaviors can be simulated. For example, a higher voltage pulse can simulate the excitation process of the synapse, resulting in a decrease in the resistance of the memristor array; while a lower voltage pulse can simulate the inhibition process of the synapse, resulting in an increase in resistance.

[0064] At the same time, the sequence and timing of voltage pulses will also affect the resistance of the memristor array. By carefully designing the sequence and timing of voltage pulses, more complex synaptic behavior patterns can be simulated. In order to accurately control the properties of voltage pulses to simulate different types of biological neural synaptic behaviors, the present invention establishes a mathematical model to describe the relationship between the properties of voltage pulses and synaptic behavior to accurately predict the impact of different voltage pulse properties on the behavior of the memristor array. This mathematical model can be used to accurately calculate the properties of the voltage pulses that need to be applied to achieve the desired synaptic behavior. By adjusting the properties of the voltage pulses in real time, based on the results predicted by the model, the desired synaptic behavior can be more accurately achieved. This approach not only simplifies the complex voltage pulse control process, but also improves the response speed and accuracy of the system.

[0065] Alternatively, the optimal voltage pulse properties can be determined experimentally. Specifically, a series of experiments can be performed, each with a different voltage pulse property, and the response of the memristor array can be observed. In this way, the optimal voltage pulse properties that achieve the desired synaptic behavior can be found.

[0066] S130: Generate a coding protocol package according to the incentive behavior.

[0067] In one embodiment of the present invention, generating a coding protocol packet according to an incentive behavior specifically includes: generating a corresponding coding signal according to the incentive behavior; based on a preset coding protocol, determining the coding protocol packet according to the coding signal; wherein the coding protocol packet includes an uplink protocol packet and a downlink protocol packet.

[0068] In one embodiment of the present invention, the uplink protocol packet includes an inference result packet; the downlink protocol packet includes an initialization packet, a training data packet, an erasure process packet, and an inference process packet; the encoding protocol in the encoding protocol packet includes: a packet flag, an X-axis selection of the memristor array, a Y-axis selection of the memristor array, a Burst burst length, a write selection of the X-axis is a pulse input or an amplitude, a write selection of the Y-axis is a pulse input or an amplitude, and a cyclic redundancy check CRC.

[0069] Specifically, after the synaptic behavior to be simulated is set, a corresponding coding signal is generated according to the behavior. According to the initialization requirements of the memristor array and the requirements of the memristor array running algorithm, the present invention mainly sets four downlink protocol packets of the coding protocol packet, namely, initialization packet, training data packet, erasure process packet, and reasoning packet. Then, according to the uplink requirements of the calculation results of the memristor array, the uplink protocol packet of the coding protocol packet is set as the reasoning result packet. The coding protocol packet is as follows: Figure 2 As shown, each protocol is analyzed as follows:

[0070] RW: Located at position [124:122] in the protocol packet, occupying 3 bits.

[0071] When RW is 3'b (binary) 001, it indicates that the current protocol packet is a memristor array initialization packet, which is a downlink protocol packet;

[0072] When RW is 3'b010, it indicates that the current protocol packet is a training data packet, and the packet is a downlink protocol packet;

[0073] When RW is 3'b011, it indicates that the current protocol packet is an inference process packet, the packet is a downlink protocol packet, and the Data_1 data in the packet is invalid;

[0074] When RW is 3'b100, it indicates that the current protocol packet is an erase process packet, and the packet is a downlink protocol packet;

[0075] When RW is 3'b111, it indicates that the current protocol packet is the inference result packet of the FPGA uplink. This packet is an uplink protocol packet. The inference result in this packet is stored in the Data_1 position. At the same time, ADDR_CX and ADDR_CY in this packet are valid to identify the source of the inference result. The Burst Length protocol is invalid in this packet.

[0076] ADDR_CX: Located at [107:98] in the protocol packet, occupies 10 bits. ADDR_CX is the X-axis selection of the memristor array, and the addressable range is 0-1023.

[0077] ADDR_CY: Located at [97:88] in the protocol packet, occupies 10 bits. ADDR_CY is the Y-axis selection of the memristor array, and the addressable range is 0-1023.

[0078] Burst Length: Located at [87:78] in the protocol packet, occupies 10 bits. The length of continuous read. The base address of continuous read starts from ADDR_CY in the protocol. The maximum Burst Length is 1024.

[0079] When the burst length value is 0, it is a single channel (ch for short) read, and only the value of 1 ch whose Y-axis coordinate of the memristor array is ADDR_CY is read. When the burst length is greater than 0, it is a burst read, that is, a continuous read mode, and the ch including ADDR_CY on the Y-axis coordinate of the memristor array will be read, starting from ADDR_CY ch and ending at (ADDR_CY+burst length) ch, with a total of burst length+1 ch values.

[0080] X_PA_Flag: Located at position

[77] in the protocol packet, occupies 1 bit. It marks whether the write selection of the X-axis is pulse input or amplitude, 1 bit, 1 represents pulse, 0 represents amplitude.

[0081] Y_PA_Flag: Located at position

[76] in the protocol packet, occupies 1 bit. It marks whether the Y-axis write selection is pulse input or amplitude, 1 bit, 1 indicates pulse, 0 indicates amplitude.

[0082] Data_0: Located at position [59:38] in the protocol packet, occupying 22 bits.

[0083] Data_1: Located at position [37:16] in the protocol packet, occupying 22 bits.

[0084] When the downlink protocol packet is a training data packet or an erase process packet, the Data_0 position is the input data of the X-axis coordinate of the memristor array, and the Data_1 position is the input data of the Y-axis coordinate of the memristor array.

[0085] When the downlink protocol packet is an inference process packet, Data_0 is the input data 0 of the X-axis coordinate of the memristor array, and Data_1 is the input data 1 of the X-axis coordinate of the memristor array. During the inference process, multiple configurable square wave or pulse voltage inputs are supported for the X-axis coordinates of the memristor array, that is, the voltage marked by Data_0 and the voltage marked by Data_1 are input alternately, and the retention time of different voltages and the number of alternating voltage inputs can be configured.

[0086] When the uplink protocol packet is an inference result packet, the lower 12 bits of the Data_1 position (ie, the [27:16] position in the protocol packet) are the inference result.

[0087] CRC: Located at [15:0] in the protocol packet, it occupies 16 bits. CRC is a cyclic redundancy check, which is a fast algorithm that generates a short fixed-bit check code based on network data packets or computer files. It is mainly used to detect or check errors that may occur after data transmission or storage.

[0088] The specific content of the coding protocol includes information such as packet flags and axis selection to ensure accurate data transmission and parsing. Cyclic redundancy check (CRC) is a widely used checksum algorithm for detecting errors during data transmission. Based on the above protocol and actual needs, a coding protocol packet is generated.

[0089] By converting the simulated synaptic behavior into a coded protocol packet, it is easy to transmit and process in the system. This coding method ensures the accuracy and integrity of the data while improving the efficiency of internal communication in the system.

[0090] In order to improve the efficiency of encoding and decoding, the size of the encoded protocol packet is reduced by using data compression technology, such as lossless compression algorithm, so as to improve the transmission efficiency. By cutting or merging unnecessary fields in the existing protocol, using fixed-length fields to simplify the parsing process and maintain the scalability of the protocol, the load of data transmission will be significantly reduced and the overall efficiency of the system will be improved.

[0091] S140: Send the encoded protocol packet to a field programmable gate array FPGA connected to the memristor array, and control the memristor array through the FPGA.

[0092] In one embodiment of the present invention, a coding protocol packet is sent to a field programmable gate array FPGA connected to a memristor array, and the memristor array is controlled by the FPGA, specifically including: sending the coding protocol packet to the FPGA, the FPGA parsing the coding protocol packet to obtain a digital signal for controlling the memristor array; converting the digital signal into an analog signal and sending it to the memristor array, thereby achieving control of the memristor array.

[0093] In one embodiment of the present invention, the input voltage applied to the memristor array is converted according to the binary value of the digital signal carried in the coding protocol packet; the digital signal is a discrete, discontinuous signal; the digital signal will be passed through Figure 3 The conversion method shown is used to realize the control of the analog signal of the input voltage applied to the memristor array.

[0094] like Figure 4 A schematic diagram of the hardware connection of a memristor array provided in an embodiment of the present invention.

[0095] The X-axis and Y-axis of the memristor array are as follows Figure 4As shown, the input and output signals of the FPGA are both digital signals, and the memristor array involved in the present invention is an analog circuit element, so a DAC device is required between the FPGA and the memristor array to complete the conversion from digital signals to analog signals, and an ADC device is required to complete the conversion from analog signals to digital signals.

[0096] When the FPGA receives the initialization configuration package, training data package, and erase process package, voltage needs to be applied to both the X-axis and Y-axis of the memristor array. Therefore, DAC devices are connected to both the X-axis and Y-axis of the memristor array, and the DAC devices are then connected to the FPGA.

[0097] When the FPGA receives the inference process package, it needs to apply voltage to the X-axis of the memristor array and read the current on the Y-axis of the memristor array. Therefore, an ADC device is also connected to the Y-axis of the memristor array, and the ADC device is connected to the FPGA.

[0098] Since only one of applying voltage or reading current can be selected on the Y axis of the memristor array at the same time, a SWITCH switching element is added to enable flexible switching of the elements connected to the Y axis of the memristor array when the FPGA receives different protocol packets at different times. The FPGA controls the switching state of the SWITCH switching element through the IIC protocol bus. Figure 4 As shown, when SWITCH is 0, the Y-axis of the memristor array is connected to the ADC device; when SWITCH is 1, the Y-axis of the memristor array is connected to the DAC device.

[0099] In one embodiment of the present invention, in the process of sending the encoded protocol packet to the FPGA, the host communicates through the Ethernet or PCIe interface on the FPGA; in the process of converting the digital signal into an analog signal and sending it to the memristor array, the FPGA communicates with the memristor array through the digital-to-analog converter DAC and the analog-to-digital converter ADC.

[0100] Specifically, the encoding protocol packet generated on the host is downloaded to the FPGA through the Ethernet or PCIe interface on the FPGA to achieve control of the memristor array. By utilizing the parallel processing capability of the FPGA, the encoding protocol packet can be quickly and accurately parsed and the memristor array can be controlled. This control method not only improves the response speed, but also ensures the accuracy of control.

[0101] Furthermore, in the embodiment of the present invention, the logic function module of the FPGA indirectly realizes the control behavior of the memristor array by controlling devices such as ADC and DAC. The FPGA also provides interfaces such as Ethernet and PCIe, and the host can communicate with the FPGA through these interfaces. After receiving the encoding protocol packet from the host, the FPGA will parse the content information of the encoding protocol packet, thereby controlling devices such as ADC and DAC to perform corresponding behaviors, and the ADC and DAC will then control the memristor array.

[0102] Communicating with the host through the Ethernet or PCIe interface, and communicating with the memristor array through DAC and ADC, ensures the speed and accuracy of data transmission, making real-time, large-scale data processing possible.

[0103] In order to enhance the reliability of hardware interface and communication, a communication method with stronger anti-interference ability, such as differential signal transmission technology, is adopted to improve the stability of the signal during transmission. At the same time, the error detection and correction mechanism of the CRC checksum in the coding protocol package can ensure the integrity of the data. This will greatly improve the reliability of communication and reduce errors in data transmission.

[0104] like Figure 5 Shown is the memristor array initialization process.

[0105] The FPGA relies on the memristor array controller to control the memristor array accordingly. After power-on, the memristor array controller is in the INIT IDLE state. In this state, the memristor array controller will only respond to the downstream memristor array initialization packet. Before receiving the memristor array initialization packet, even if the memristor array controller receives other protocol packets, such as training data packets, it will consider the training data packets as invalid packets and will not respond because the memristor array has not been initialized.

[0106] After receiving the memristor array initialization package, the memristor array controller will initialize the configuration of the memristor array. Since the Y-axis of the memristor array requires both DAC as voltage input and ADC to read current, the Y-axis of the memristor array is connected with a SWITCH (switching switch). The memristor array controller needs to control the SWITCH to switch to DAC through the IIC bus protocol. It is necessary to first write 'h (hexadecimal) 00 to the register address 6 and address 7 of the IIC bus, set the pin to OUTPUT (output), and then set 'hFF to the register address 2 and address 3 of the IIC bus, so that the Y-axis of the memristor array is the DAC voltage input. Then configure the DAC device connected to the X-axis and Y-axis of the memristor array to input the initial stable voltage.

[0107] After completing the above operations, the memristor array controller will be in the WORK IDLE state. When in the WORK IDLE state, the memristor array controller can respond to various downstream protocol packets, including the memristor array initialization packet, and can re-initialize the memristor array.

[0108] like Figure 6 Shown is the training / erasing process of the memristor array.

[0109] When the memristor array controller is in the WORK IDLE state, if it receives a training data packet or an erase process packet, it will apply voltage to the coordinate channels corresponding to the X-axis and Y-axis of the memristor array for a certain period of time through the DAC device. The applied voltage value is converted according to Data_0 and Data_1 in the received training data packet or erase process packet. Then, the voltage applied to the coordinate channels corresponding to the X-axis and Y-axis of the memristor array is restored to the initial stable voltage.

[0110] After completing the above operations, the memristor array controller will return to the WORK IDLE state.

[0111] like Figure 7 Shown is the inference flow of a single channel of a memristor array.

[0112] When the memristor array controller is in the WORK IDLE state, if it receives an inference process packet, and the value of the Burst Length in the inference process packet is 0, the memristor array controller will perform inference control of a single channel of the memristor array.

[0113] The memristor array controller first controls SWITCH through the IIC protocol bus to connect the Y-axis channel of the corresponding memristor array to the ADC device. Then it controls the input voltage of the DAC device connected to the X-axis of the memristor array, and reads the current value of the Y-axis coordinate channel of the memristor array through the ADC device connected to the Y-axis of the memristor array.

[0114] After the inference result is obtained, the inference result will be packaged and uploaded in the inference result uplink device on the FPGA. The memristor array controller will restore the voltage of the X-axis coordinate channel of the memristor array to the initial stable voltage through the DAC device connected to the X-axis of the memristor array. Then, the SWITCH is controlled through the IIC protocol bus to reconnect the Y-axis channel of the memristor array to the DAC device.

[0115] After completing the above operations, the memristor array controller will return to the WORK IDLE state.

[0116] like Figure 8 The figure shows the reasoning process of continuous multi-channel memristor array reasoning.

[0117] When the memristor array controller is in the WORK IDLE state, if it receives an inference process packet and the value of the Burst Length in the inference process packet is not 0, the memristor array controller will perform continuous multi-channel inference control of the memristor array.

[0118] The memristor array controller first controls SWITCH through the IIC protocol bus to connect the corresponding multiple Y-axis channels of the memristor array to the ADC device. On the Y-axis of the memristor array, starting from the ADDR_CY channel in the inference process package and ending at the (ADDR_CY+Burst Length) channel, including the start channel and the end channel, there are a total of Burst Length+1 channels.

[0119] Then, the input voltage of the DAC device connected to the X-axis of the memristor array is controlled, and at the same time, the current values ​​of multiple consecutive Y-axis coordinate channels corresponding to the memristor array are read through the ADC device connected to the Y-axis of the memristor array.

[0120] After the inference result is obtained, the inference result will be packaged and uploaded in the inference result uplink device on the FPGA. The memristor array controller will restore the voltage of the X-axis coordinate channel of the memristor array to the initial stable voltage through the DAC device connected to the X-axis of the memristor array. Then, the SWITCH is controlled through the IIC protocol bus to reconnect the multiple Y-axis channels of the memristor array to the DAC device.

[0121] After completing the above operations, the memristor array controller will return to the WORK IDLE state.

[0122] Through the above steps, the present invention utilizes the special properties of the memristor array to achieve effective encoding of input information. This method and device improves the accuracy and efficiency of encoding and provides new ideas and methods for the development of artificial intelligence and neural network fields.

[0123] First, by precisely controlling the voltage, current, and timing parameters applied to the memristor array, accurate storage and reading of data is achieved. This not only improves the accuracy of data processing and avoids errors and distortions caused by insufficient control precision, but also optimizes computing performance and improves the speed and efficiency of data processing. In fields such as big data and artificial intelligence that require the processing of massive amounts of data, this ability to precisely control is particularly important and can greatly improve the overall performance and stability of the system.

[0124] Secondly, the device structure proposed in the present invention is relatively simple and easy to implement. The encoding method of the present invention only needs to downlink the encoding protocol packet through the host to realize the control process of the memristor array, without the need for complex algorithm support, so it has high practicality and generalizability. This makes it easy to integrate into various computing and storage systems in practical applications, improving the integration and reliability of the system. At the same time, since the design of the device takes into account the need to adjust the control parameters in real time, the control strategy can be flexibly adjusted according to the needs of the actual application scenario to further optimize the performance of the memristor array.

[0125] In addition, the present invention can also reduce the overall power consumption of the system by selecting low-power hardware components and optimizing power management strategies, such as using sleep mode and dynamically adjusting the operating frequency. By accurately controlling the voltage, current, timing and other parameters applied to the memristor array, it is also helpful to reduce energy consumption in the data processing process. By accurately controlling the signal parameters applied to the memristor array, unnecessary energy consumption can be reduced and the energy efficiency ratio can be improved. In today's increasingly tight energy and increasingly stringent environmental protection requirements, this low-energy consumption feature has important practical significance and helps promote green computing and sustainable development.

[0126] Finally, the invention is also helpful to promote the further development of memristor array technology. By solving the problems existing in the existing control methods and improving the performance and stability of memristor arrays, more researchers and enterprises can be attracted to invest in the research and development and application of memristor technology, forming a virtuous circle and promoting the progress of the entire field.

[0127] In summary, the present invention is based on the non-volatile storage and variable resistance characteristics of the memristor, changes the resistance of the memristor by precisely controlling the voltage or current, thereby simulating the synaptic weights in the biological neural network, and performs real-time control and data processing through FPGA, thereby improving the response speed and accuracy of the system. The beneficial effects of the present invention are not only reflected in improving the accuracy and speed of data processing, reducing energy consumption, etc., but also in promoting technological development and application expansion. The coding method of the present invention is simple and easy to implement, and has good application prospects and promotion value. With the implementation and promotion of the present invention, it is foreseeable that it will bring new breakthroughs and opportunities for the development of the field of information technology.

[0128] The above is a coding method for controlling a memristor array provided by an embodiment of the present invention. Based on the same inventive idea, an embodiment of the present invention also provides a corresponding coding device for controlling a memristor array, such as Fig. 9 As shown, including:

[0129] Initialization module 910, used to apply an initial stable voltage to the memristor array; perform a read operation on the memristor array based on the initial stable voltage to determine an initial resistance value of the memristor array;

[0130] A behavior simulation module 920, used to determine the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters;

[0131] Coding module 930, used to generate a coding protocol package according to the incentive behavior;

[0132] The control module 940 is used to send the encoding protocol packet to a field programmable gate array FPGA connected to the memristor array, and control the memristor array through the FPGA.

[0133] The embodiment of the present invention also provides a corresponding encoding device for controlling a memristor array, such as Fig.10 As shown, including:

[0134] At least one processor 1002 (processor), a communication interface 1004 (Communications Interface), a memory 1006 (memory) and a communication bus 1008; wherein the processor 1002, the communication interface 1004, and the memory 1006 communicate with each other via the communication bus 1008; the processor 1002 can call the logic instructions stored in the memory 1006 to enable at least one processor 1002 to execute the steps of the above-mentioned embodiments.

[0135] Based on the same idea, some embodiments of the present invention also provide a medium corresponding to the above method.

[0136] Some embodiments of the present invention provide a storage medium storing computer executable instructions, and the computer executable instructions are executed by a processor to implement the steps of the above embodiments.

[0137] On the other hand, an embodiment of the present application also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the steps of a coding method for controlling a memristor array provided in the above embodiments.

[0138] Each embodiment of the present invention is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, medium and program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0139] The devices, media, and program products provided in the embodiments of the present invention correspond one-to-one to the methods. Therefore, the devices, media, and program products also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices, media, and program products will not be repeated here.

[0140] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or method including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or method. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or method including the elements.

[0141] The above are only embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail above with general descriptions and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made on the basis of the present invention. Therefore, these modifications or improvements made on the basis of not departing from the spirit of the present invention all belong to the scope of protection claimed in the present invention.

Claims

1. A coding method for controlling a memristor array, characterized in that: include: Applying an initial stable voltage to the memristor array includes: converting the type and characteristics of input information into a digital signal; mapping the digital signal into a corresponding initial stable voltage according to a preset conversion method; and applying the initial stable voltage to the memristor array; Performing a read operation on the memristor array based on the initial stable voltage to determine an initial resistance value of the memristor array; Determining the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters, including: obtaining an initial stable voltage applied to the memristor array; applying a voltage pulse to the memristor array based on the initial stable voltage; determining the change of the voltage on the memristor array by adjusting the properties of the voltage pulse; the properties of the voltage pulse include amplitude, width, frequency, sequence and / or timing; based on the initial resistance value, determining the change of the resistance value of the memristor array according to the change of the voltage, so as to simulate different types of biological neural synaptic behaviors; generating a coding protocol package according to the incentive behavior; The encoding protocol packet is sent to a field programmable gate array FPGA connected to the memristor array, and the memristor array is controlled by the FPGA.

2. The encoding method for controlling a memristor array according to claim 1, characterized in that: The generating of the coding protocol package according to the incentive behavior specifically includes: generating a corresponding coded signal according to the incentive behavior; Based on a preset coding protocol, determining a coding protocol package according to the coding signal; The coding protocol packet includes an uplink protocol packet and a downlink protocol packet.

3. The encoding method for controlling a memristor array according to claim 1, characterized in that: The step of sending the encoding protocol packet to a field programmable gate array FPGA connected to a memristor array and controlling the memristor array through the FPGA specifically includes: The coding protocol packet is sent to the FPGA, and the FPGA parses the coding protocol packet to obtain a digital signal for controlling the memristor array; The digital signal is converted into an analog signal and sent to the memristor array, thereby realizing control over the memristor array.

4. The encoding method for controlling a memristor array according to claim 3, characterized in that: In the process of sending the coded protocol packet to the FPGA, the host communicates via an Ethernet or PCIe interface on the FPGA; In the process of converting the digital signal into an analog signal and sending it to the memristor array, the FPGA communicates with the memristor array through a digital-to-analog converter DAC and an analog-to-digital converter ADC.

5. The encoding method for controlling a memristor array according to claim 2, characterized in that: The uplink protocol packet includes an inference result packet; The downlink protocol packet includes an initialization packet, a training data packet, an erasure process packet, and an inference process packet; The coding protocol in the coding protocol package includes: a package flag, an X-axis selection of a memristor array, a Y-axis selection of a memristor array, a Burst burst length, a write selection of the X-axis, whether it is a pulse input or an amplitude, a write selection of the Y-axis, whether it is a pulse input or an amplitude, and a cyclic redundancy check CRC.

6. A coding device for controlling a memristor array, characterized in that: include: An initialization module, used for applying an initial stable voltage to the memristor array, including: converting the type and characteristics of input information into a digital signal; mapping the digital signal into a corresponding initial stable voltage according to a preset conversion method; applying the initial stable voltage to the memristor array; performing a read operation on the memristor array based on the initial stable voltage to determine the initial resistance value of the memristor array; A behavior simulation module, used to determine the excitation behavior of the memristor array based on the initial resistance value and the calculation parameters, including: obtaining an initial stable voltage applied to the memristor array; applying a voltage pulse to the memristor array based on the initial stable voltage; determining the change of the voltage on the memristor array by adjusting the properties of the voltage pulse; the properties of the voltage pulse include amplitude, width, frequency, sequence and / or timing; based on the initial resistance value, determining the change of the resistance value of the memristor array according to the change of the voltage, thereby simulating different types of biological neural synaptic behaviors; An encoding module, used to generate an encoding protocol package according to the incentive behavior; The control module is used to send the encoding protocol packet to a field programmable gate array FPGA connected to the memristor array, and control the memristor array through the FPGA.

7. An encoding device for controlling a memristor array, characterized in that: include: at least one processor; as well as, A memory connected to the at least one processor via a bus; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed to implement the encoding method for controlling a memristor array according to any one of claims 1 to 5.

8. A non-volatile storage medium storing computer executable instructions, characterized in that: The computer executable instructions are executed by a processor to implement the encoding method for controlling a memristor array according to any one of claims 1 to 5.

Images